drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20 #include "trace.h"
  21
  22 /**
  23  * Theory of operation:
  24  *
  25  * There is ISR pseudo-cause register,
  26  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  27  * Its bits represents OR'ed bits from 3 real ISR registers:
  28  * TX, RX, and MISC.
  29  *
  30  * Registers may be configured to either "write 1 to clear" or
  31  * "clear on read" mode
  32  *
  33  * When handling interrupt, one have to mask/unmask interrupts for the
  34  * real ISR registers, or hardware may malfunction.
  35  *
  36  */
  37
  38 #define WIL6210_IRQ_DISABLE     (0xFFFFFFFFUL)
  39 #define WIL6210_IMC_RX          (BIT_DMA_EP_RX_ICR_RX_DONE | \
  40                                  BIT_DMA_EP_RX_ICR_RX_HTRSH)
  41 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  42                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  43 #define WIL6210_IMC_MISC        (ISR_MISC_FW_READY | \
  44                                  ISR_MISC_MBOX_EVT | \
  45                                  ISR_MISC_FW_ERROR)
  46
  47 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  48                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  49                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  50
  51 #if defined(CONFIG_WIL6210_ISR_COR)
  52 /* configure to Clear-On-Read mode */
  53 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  54
  55 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  56 {
  57 }
  58 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  59 /* configure to Write-1-to-Clear mode */
  60 #define WIL_ICR_ICC_VALUE       (0UL)
  61
  62 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  63 {
  64         iowrite32(x, addr);
  65 }
  66 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  67
  68 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  69 {
  70         u32 x = ioread32(addr);
  71
  72         wil_icr_clear(x, addr);
  73
  74         return x;
  75 }
  76
  77 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  78 {
  79         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  80                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
  81                   offsetof(struct RGF_ICR, IMS));
  82 }
  83
  84 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  85 {
  86         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  87                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
  88                   offsetof(struct RGF_ICR, IMS));
  89 }
  90
  91 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
  92 {
  93         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  94                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
  95                   offsetof(struct RGF_ICR, IMS));
  96 }
  97
  98 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
  99 {
 100         wil_dbg_irq(wil, "%s()\n", __func__);
 101
 102         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
 103                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 104
 105         clear_bit(wil_status_irqen, wil->status);
 106 }
 107
 108 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 109 {
 110         iowrite32(WIL6210_IMC_TX, wil->csr +
 111                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
 112                   offsetof(struct RGF_ICR, IMC));
 113 }
 114
 115 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 116 {
 117         iowrite32(WIL6210_IMC_RX, wil->csr +
 118                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
 119                   offsetof(struct RGF_ICR, IMC));
 120 }
 121
 122 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
 123 {
 124         iowrite32(WIL6210_IMC_MISC, wil->csr +
 125                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 126                   offsetof(struct RGF_ICR, IMC));
 127 }
 128
 129 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 130 {
 131         wil_dbg_irq(wil, "%s()\n", __func__);
 132
 133         set_bit(wil_status_irqen, wil->status);
 134
 135         iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
 136                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 137 }
 138
 139 void wil_mask_irq(struct wil6210_priv *wil)
 140 {
 141         wil_dbg_irq(wil, "%s()\n", __func__);
 142
 143         wil6210_mask_irq_tx(wil);
 144         wil6210_mask_irq_rx(wil);
 145         wil6210_mask_irq_misc(wil);
 146         wil6210_mask_irq_pseudo(wil);
 147 }
 148
 149 void wil_unmask_irq(struct wil6210_priv *wil)
 150 {
 151         wil_dbg_irq(wil, "%s()\n", __func__);
 152
 153         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 154                   offsetof(struct RGF_ICR, ICC));
 155         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 156                   offsetof(struct RGF_ICR, ICC));
 157         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 158                   offsetof(struct RGF_ICR, ICC));
 159
 160         wil6210_unmask_irq_pseudo(wil);
 161         wil6210_unmask_irq_tx(wil);
 162         wil6210_unmask_irq_rx(wil);
 163         wil6210_unmask_irq_misc(wil);
 164 }
 165
 166 /* target write operation */
 167 #define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
 168
 169 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
 170 {
 171         wil_dbg_irq(wil, "%s()\n", __func__);
 172
 173         /* disable interrupt moderation for monitor
 174          * to get better timestamp precision
 175          */
 176         if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
 177                 return;
 178
 179         /* Disable and clear tx counter before (re)configuration */
 180         W(RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
 181         W(RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
 182         wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
 183                  wil->tx_max_burst_duration);
 184         /* Configure TX max burst duration timer to use usec units */
 185         W(RGF_DMA_ITR_TX_CNT_CTL,
 186           BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
 187
 188         /* Disable and clear tx idle counter before (re)configuration */
 189         W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
 190         W(RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
 191         wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
 192                  wil->tx_interframe_timeout);
 193         /* Configure TX max burst duration timer to use usec units */
 194         W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
 195                                       BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
 196
 197         /* Disable and clear rx counter before (re)configuration */
 198         W(RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
 199         W(RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
 200         wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
 201                  wil->rx_max_burst_duration);
 202         /* Configure TX max burst duration timer to use usec units */
 203         W(RGF_DMA_ITR_RX_CNT_CTL,
 204           BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
 205
 206         /* Disable and clear rx idle counter before (re)configuration */
 207         W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
 208         W(RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
 209         wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
 210                  wil->rx_interframe_timeout);
 211         /* Configure TX max burst duration timer to use usec units */
 212         W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
 213                                       BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
 214 }
 215
 216 #undef W
 217
 218 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 219 {
 220         struct wil6210_priv *wil = cookie;
 221         u32 isr = wil_ioread32_and_clear(wil->csr +
 222                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 223                                          offsetof(struct RGF_ICR, ICR));
 224         bool need_unmask = true;
 225
 226         trace_wil6210_irq_rx(isr);
 227         wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
 228
 229         if (!isr) {
 230                 wil_err(wil, "spurious IRQ: RX\n");
 231                 return IRQ_NONE;
 232         }
 233
 234         wil6210_mask_irq_rx(wil);
 235
 236         /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
 237          * moderation is not used. Interrupt moderation may cause RX
 238          * buffer overflow while RX_DONE is delayed. The required
 239          * action is always the same - should empty the accumulated
 240          * packets from the RX ring.
 241          */
 242         if (isr & (BIT_DMA_EP_RX_ICR_RX_DONE | BIT_DMA_EP_RX_ICR_RX_HTRSH)) {
 243                 wil_dbg_irq(wil, "RX done\n");
 244
 245                 if (isr & BIT_DMA_EP_RX_ICR_RX_HTRSH)
 246                         wil_err_ratelimited(wil,
 247                                             "Received \"Rx buffer is in risk of overflow\" interrupt\n");
 248
 249                 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
 250                          BIT_DMA_EP_RX_ICR_RX_HTRSH);
 251                 if (test_bit(wil_status_reset_done, wil->status)) {
 252                         if (test_bit(wil_status_napi_en, wil->status)) {
 253                                 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
 254                                 need_unmask = false;
 255                                 napi_schedule(&wil->napi_rx);
 256                         } else {
 257                                 wil_err(wil,
 258                                         "Got Rx interrupt while stopping interface\n");
 259                         }
 260                 } else {
 261                         wil_err(wil, "Got Rx interrupt while in reset\n");
 262                 }
 263         }
 264
 265         if (isr)
 266                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 267
 268         /* Rx IRQ will be enabled when NAPI processing finished */
 269
 270         atomic_inc(&wil->isr_count_rx);
 271
 272         if (unlikely(need_unmask))
 273                 wil6210_unmask_irq_rx(wil);
 274
 275         return IRQ_HANDLED;
 276 }
 277
 278 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 279 {
 280         struct wil6210_priv *wil = cookie;
 281         u32 isr = wil_ioread32_and_clear(wil->csr +
 282                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 283                                          offsetof(struct RGF_ICR, ICR));
 284         bool need_unmask = true;
 285
 286         trace_wil6210_irq_tx(isr);
 287         wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
 288
 289         if (!isr) {
 290                 wil_err(wil, "spurious IRQ: TX\n");
 291                 return IRQ_NONE;
 292         }
 293
 294         wil6210_mask_irq_tx(wil);
 295
 296         if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
 297                 wil_dbg_irq(wil, "TX done\n");
 298                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 299                 /* clear also all VRING interrupts */
 300                 isr &= ~(BIT(25) - 1UL);
 301                 if (test_bit(wil_status_reset_done, wil->status)) {
 302                         wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
 303                         need_unmask = false;
 304                         napi_schedule(&wil->napi_tx);
 305                 } else {
 306                         wil_err(wil, "Got Tx interrupt while in reset\n");
 307                 }
 308         }
 309
 310         if (isr)
 311                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 312
 313         /* Tx IRQ will be enabled when NAPI processing finished */
 314
 315         atomic_inc(&wil->isr_count_tx);
 316
 317         if (unlikely(need_unmask))
 318                 wil6210_unmask_irq_tx(wil);
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323 static void wil_notify_fw_error(struct wil6210_priv *wil)
 324 {
 325         struct device *dev = &wil_to_ndev(wil)->dev;
 326         char *envp[3] = {
 327                 [0] = "SOURCE=wil6210",
 328                 [1] = "EVENT=FW_ERROR",
 329                 [2] = NULL,
 330         };
 331         wil_err(wil, "Notify about firmware error\n");
 332         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 333 }
 334
 335 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
 336 {
 337         /* make shadow copy of registers that should not change on run time */
 338         wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
 339                              sizeof(struct wil6210_mbox_ctl));
 340         wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
 341         wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
 342 }
 343
 344 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 345 {
 346         struct wil6210_priv *wil = cookie;
 347         u32 isr = wil_ioread32_and_clear(wil->csr +
 348                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 349                                          offsetof(struct RGF_ICR, ICR));
 350
 351         trace_wil6210_irq_misc(isr);
 352         wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
 353
 354         if (!isr) {
 355                 wil_err(wil, "spurious IRQ: MISC\n");
 356                 return IRQ_NONE;
 357         }
 358
 359         wil6210_mask_irq_misc(wil);
 360
 361         if (isr & ISR_MISC_FW_ERROR) {
 362                 wil_err(wil, "Firmware error detected\n");
 363                 clear_bit(wil_status_fwready, wil->status);
 364                 /*
 365                  * do not clear @isr here - we do 2-nd part in thread
 366                  * there, user space get notified, and it should be done
 367                  * in non-atomic context
 368                  */
 369         }
 370
 371         if (isr & ISR_MISC_FW_READY) {
 372                 wil_dbg_irq(wil, "IRQ: FW ready\n");
 373                 wil_cache_mbox_regs(wil);
 374                 set_bit(wil_status_reset_done, wil->status);
 375                 /**
 376                  * Actual FW ready indicated by the
 377                  * WMI_FW_READY_EVENTID
 378                  */
 379                 isr &= ~ISR_MISC_FW_READY;
 380         }
 381
 382         wil->isr_misc = isr;
 383
 384         if (isr) {
 385                 return IRQ_WAKE_THREAD;
 386         } else {
 387                 wil6210_unmask_irq_misc(wil);
 388                 return IRQ_HANDLED;
 389         }
 390 }
 391
 392 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 393 {
 394         struct wil6210_priv *wil = cookie;
 395         u32 isr = wil->isr_misc;
 396
 397         trace_wil6210_irq_misc_thread(isr);
 398         wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
 399
 400         if (isr & ISR_MISC_FW_ERROR) {
 401                 wil_notify_fw_error(wil);
 402                 isr &= ~ISR_MISC_FW_ERROR;
 403                 wil_fw_error_recovery(wil);
 404         }
 405
 406         if (isr & ISR_MISC_MBOX_EVT) {
 407                 wil_dbg_irq(wil, "MBOX event\n");
 408                 wmi_recv_cmd(wil);
 409                 isr &= ~ISR_MISC_MBOX_EVT;
 410         }
 411
 412         if (isr)
 413                 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 414
 415         wil->isr_misc = 0;
 416
 417         wil6210_unmask_irq_misc(wil);
 418
 419         return IRQ_HANDLED;
 420 }
 421
 422 /**
 423  * thread IRQ handler
 424  */
 425 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 426 {
 427         struct wil6210_priv *wil = cookie;
 428
 429         wil_dbg_irq(wil, "Thread IRQ\n");
 430         /* Discover real IRQ cause */
 431         if (wil->isr_misc)
 432                 wil6210_irq_misc_thread(irq, cookie);
 433
 434         wil6210_unmask_irq_pseudo(wil);
 435
 436         return IRQ_HANDLED;
 437 }
 438
 439 /* DEBUG
 440  * There is subtle bug in hardware that causes IRQ to raise when it should be
 441  * masked. It is quite rare and hard to debug.
 442  *
 443  * Catch irq issue if it happens and print all I can.
 444  */
 445 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 446 {
 447         if (!test_bit(wil_status_irqen, wil->status)) {
 448                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 449                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 450                                 offsetof(struct RGF_ICR, ICM));
 451                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 452                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 453                                 offsetof(struct RGF_ICR, ICR));
 454                 u32 imv_rx = ioread32(wil->csr +
 455                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 456                                 offsetof(struct RGF_ICR, IMV));
 457                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 458                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 459                                 offsetof(struct RGF_ICR, ICM));
 460                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 461                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 462                                 offsetof(struct RGF_ICR, ICR));
 463                 u32 imv_tx = ioread32(wil->csr +
 464                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 465                                 offsetof(struct RGF_ICR, IMV));
 466                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 467                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 468                                 offsetof(struct RGF_ICR, ICM));
 469                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 470                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 471                                 offsetof(struct RGF_ICR, ICR));
 472                 u32 imv_misc = ioread32(wil->csr +
 473                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 474                                 offsetof(struct RGF_ICR, IMV));
 475                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 476                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 477                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 478                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 479                                 pseudo_cause,
 480                                 icm_rx, icr_rx, imv_rx,
 481                                 icm_tx, icr_tx, imv_tx,
 482                                 icm_misc, icr_misc, imv_misc);
 483
 484                 return -EINVAL;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 491 {
 492         irqreturn_t rc = IRQ_HANDLED;
 493         struct wil6210_priv *wil = cookie;
 494         u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
 495
 496         /**
 497          * pseudo_cause is Clear-On-Read, no need to ACK
 498          */
 499         if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
 500                 return IRQ_NONE;
 501
 502         /* FIXME: IRQ mask debug */
 503         if (wil6210_debug_irq_mask(wil, pseudo_cause))
 504                 return IRQ_NONE;
 505
 506         trace_wil6210_irq_pseudo(pseudo_cause);
 507         wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
 508
 509         wil6210_mask_irq_pseudo(wil);
 510
 511         /* Discover real IRQ cause
 512          * There are 2 possible phases for every IRQ:
 513          * - hard IRQ handler called right here
 514          * - threaded handler called later
 515          *
 516          * Hard IRQ handler reads and clears ISR.
 517          *
 518          * If threaded handler requested, hard IRQ handler
 519          * returns IRQ_WAKE_THREAD and saves ISR register value
 520          * for the threaded handler use.
 521          *
 522          * voting for wake thread - need at least 1 vote
 523          */
 524         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 525             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 526                 rc = IRQ_WAKE_THREAD;
 527
 528         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 529             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 530                 rc = IRQ_WAKE_THREAD;
 531
 532         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 533             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 534                 rc = IRQ_WAKE_THREAD;
 535
 536         /* if thread is requested, it will unmask IRQ */
 537         if (rc != IRQ_WAKE_THREAD)
 538                 wil6210_unmask_irq_pseudo(wil);
 539
 540         return rc;
 541 }
 542
 543 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
 544 {
 545         int rc;
 546         /*
 547          * IRQ's are in the following order:
 548          * - Tx
 549          * - Rx
 550          * - Misc
 551          */
 552
 553         rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
 554                          WIL_NAME"_tx", wil);
 555         if (rc)
 556                 return rc;
 557
 558         rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
 559                          WIL_NAME"_rx", wil);
 560         if (rc)
 561                 goto free0;
 562
 563         rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
 564                                   wil6210_irq_misc_thread,
 565                                   IRQF_SHARED, WIL_NAME"_misc", wil);
 566         if (rc)
 567                 goto free1;
 568
 569         return 0;
 570         /* error branch */
 571 free1:
 572         free_irq(irq + 1, wil);
 573 free0:
 574         free_irq(irq, wil);
 575
 576         return rc;
 577 }
 578
 579 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
 580 static inline void wil_clear32(void __iomem *addr)
 581 {
 582         u32 x = ioread32(addr);
 583
 584         iowrite32(x, addr);
 585 }
 586
 587 void wil6210_clear_irq(struct wil6210_priv *wil)
 588 {
 589         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 590                     offsetof(struct RGF_ICR, ICR));
 591         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 592                     offsetof(struct RGF_ICR, ICR));
 593         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 594                     offsetof(struct RGF_ICR, ICR));
 595         wmb(); /* make sure write completed */
 596 }
 597
 598 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
 599 {
 600         int rc;
 601
 602         wil_dbg_misc(wil, "%s() n_msi=%d\n", __func__, wil->n_msi);
 603
 604         if (wil->n_msi == 3)
 605                 rc = wil6210_request_3msi(wil, irq);
 606         else
 607                 rc = request_threaded_irq(irq, wil6210_hardirq,
 608                                           wil6210_thread_irq,
 609                                           wil->n_msi ? 0 : IRQF_SHARED,
 610                                           WIL_NAME, wil);
 611         return rc;
 612 }
 613
 614 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 615 {
 616         wil_dbg_misc(wil, "%s()\n", __func__);
 617
 618         wil_mask_irq(wil);
 619         free_irq(irq, wil);
 620         if (wil->n_msi == 3) {
 621                 free_irq(irq + 1, wil);
 622                 free_irq(irq + 2, wil);
 623         }
 624 }