2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/interrupt.h>
23 * Theory of operation:
25 * There is ISR pseudo-cause register,
26 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
27 * Its bits represents OR'ed bits from 3 real ISR registers:
30 * Registers may be configured to either "write 1 to clear" or
31 * "clear on read" mode
33 * When handling interrupt, one have to mask/unmask interrupts for the
34 * real ISR registers, or hardware may malfunction.
38 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
39 #define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
40 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
41 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
42 #define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
46 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
47 BIT_DMA_PSEUDO_CAUSE_TX | \
48 BIT_DMA_PSEUDO_CAUSE_MISC))
50 #if defined(CONFIG_WIL6210_ISR_COR)
51 /* configure to Clear-On-Read mode */
52 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
54 static inline void wil_icr_clear(u32 x, void __iomem *addr)
57 #else /* defined(CONFIG_WIL6210_ISR_COR) */
58 /* configure to Write-1-to-Clear mode */
59 #define WIL_ICR_ICC_VALUE (0UL)
61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
65 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
67 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
69 u32 x = ioread32(addr);
71 wil_icr_clear(x, addr);
76 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
78 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
79 HOSTADDR(RGF_DMA_EP_TX_ICR) +
80 offsetof(struct RGF_ICR, IMS));
83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
85 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
86 HOSTADDR(RGF_DMA_EP_RX_ICR) +
87 offsetof(struct RGF_ICR, IMS));
90 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
92 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
93 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
94 offsetof(struct RGF_ICR, IMS));
97 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
99 wil_dbg_irq(wil, "%s()\n", __func__);
101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
102 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
104 clear_bit(wil_status_irqen, &wil->status);
107 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
109 iowrite32(WIL6210_IMC_TX, wil->csr +
110 HOSTADDR(RGF_DMA_EP_TX_ICR) +
111 offsetof(struct RGF_ICR, IMC));
114 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
116 iowrite32(WIL6210_IMC_RX, wil->csr +
117 HOSTADDR(RGF_DMA_EP_RX_ICR) +
118 offsetof(struct RGF_ICR, IMC));
121 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
123 iowrite32(WIL6210_IMC_MISC, wil->csr +
124 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
125 offsetof(struct RGF_ICR, IMC));
128 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
130 wil_dbg_irq(wil, "%s()\n", __func__);
132 set_bit(wil_status_irqen, &wil->status);
134 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
135 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
138 void wil6210_disable_irq(struct wil6210_priv *wil)
140 wil_dbg_irq(wil, "%s()\n", __func__);
142 wil6210_mask_irq_tx(wil);
143 wil6210_mask_irq_rx(wil);
144 wil6210_mask_irq_misc(wil);
145 wil6210_mask_irq_pseudo(wil);
148 void wil6210_enable_irq(struct wil6210_priv *wil)
150 wil_dbg_irq(wil, "%s()\n", __func__);
152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
153 offsetof(struct RGF_ICR, ICC));
154 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
155 offsetof(struct RGF_ICR, ICC));
156 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
157 offsetof(struct RGF_ICR, ICC));
159 /* interrupt moderation parameters */
160 if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
161 /* disable interrupt moderation for monitor
162 * to get better timestamp precision
164 iowrite32(0, wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
166 iowrite32(WIL6210_ITR_TRSH,
167 wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
168 iowrite32(BIT_DMA_ITR_CNT_CRL_EN,
169 wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
172 wil6210_unmask_irq_pseudo(wil);
173 wil6210_unmask_irq_tx(wil);
174 wil6210_unmask_irq_rx(wil);
175 wil6210_unmask_irq_misc(wil);
178 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
180 struct wil6210_priv *wil = cookie;
181 u32 isr = wil_ioread32_and_clear(wil->csr +
182 HOSTADDR(RGF_DMA_EP_RX_ICR) +
183 offsetof(struct RGF_ICR, ICR));
185 trace_wil6210_irq_rx(isr);
186 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
189 wil_err(wil, "spurious IRQ: RX\n");
193 wil6210_mask_irq_rx(wil);
195 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
196 wil_dbg_irq(wil, "RX done\n");
197 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
198 if (test_bit(wil_status_reset_done, &wil->status)) {
199 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
200 napi_schedule(&wil->napi_rx);
202 wil_err(wil, "Got Rx interrupt while in reset\n");
207 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
209 /* Rx IRQ will be enabled when NAPI processing finished */
211 atomic_inc(&wil->isr_count_rx);
215 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
217 struct wil6210_priv *wil = cookie;
218 u32 isr = wil_ioread32_and_clear(wil->csr +
219 HOSTADDR(RGF_DMA_EP_TX_ICR) +
220 offsetof(struct RGF_ICR, ICR));
222 trace_wil6210_irq_tx(isr);
223 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
226 wil_err(wil, "spurious IRQ: TX\n");
230 wil6210_mask_irq_tx(wil);
232 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
233 wil_dbg_irq(wil, "TX done\n");
234 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
235 /* clear also all VRING interrupts */
236 isr &= ~(BIT(25) - 1UL);
237 if (test_bit(wil_status_reset_done, &wil->status)) {
238 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
239 napi_schedule(&wil->napi_tx);
241 wil_err(wil, "Got Tx interrupt while in reset\n");
246 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
248 /* Tx IRQ will be enabled when NAPI processing finished */
250 atomic_inc(&wil->isr_count_tx);
254 static void wil_notify_fw_error(struct wil6210_priv *wil)
256 struct device *dev = &wil_to_ndev(wil)->dev;
258 [0] = "SOURCE=wil6210",
259 [1] = "EVENT=FW_ERROR",
262 wil_err(wil, "Notify about firmware error\n");
263 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
266 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
268 /* make shadow copy of registers that should not change on run time */
269 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
270 sizeof(struct wil6210_mbox_ctl));
271 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
272 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
275 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
277 struct wil6210_priv *wil = cookie;
278 u32 isr = wil_ioread32_and_clear(wil->csr +
279 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
280 offsetof(struct RGF_ICR, ICR));
282 trace_wil6210_irq_misc(isr);
283 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
286 wil_err(wil, "spurious IRQ: MISC\n");
290 wil6210_mask_irq_misc(wil);
292 if (isr & ISR_MISC_FW_ERROR) {
293 wil_err(wil, "Firmware error detected\n");
294 clear_bit(wil_status_fwready, &wil->status);
296 * do not clear @isr here - we do 2-nd part in thread
297 * there, user space get notified, and it should be done
298 * in non-atomic context
302 if (isr & ISR_MISC_FW_READY) {
303 wil_dbg_irq(wil, "IRQ: FW ready\n");
304 wil_cache_mbox_regs(wil);
305 set_bit(wil_status_reset_done, &wil->status);
307 * Actual FW ready indicated by the
308 * WMI_FW_READY_EVENTID
310 isr &= ~ISR_MISC_FW_READY;
316 return IRQ_WAKE_THREAD;
318 wil6210_unmask_irq_misc(wil);
323 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
325 struct wil6210_priv *wil = cookie;
326 u32 isr = wil->isr_misc;
328 trace_wil6210_irq_misc_thread(isr);
329 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
331 if (isr & ISR_MISC_FW_ERROR) {
332 wil_notify_fw_error(wil);
333 isr &= ~ISR_MISC_FW_ERROR;
334 wil_fw_error_recovery(wil);
337 if (isr & ISR_MISC_MBOX_EVT) {
338 wil_dbg_irq(wil, "MBOX event\n");
340 isr &= ~ISR_MISC_MBOX_EVT;
344 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
348 wil6210_unmask_irq_misc(wil);
356 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
358 struct wil6210_priv *wil = cookie;
360 wil_dbg_irq(wil, "Thread IRQ\n");
361 /* Discover real IRQ cause */
363 wil6210_irq_misc_thread(irq, cookie);
365 wil6210_unmask_irq_pseudo(wil);
371 * There is subtle bug in hardware that causes IRQ to raise when it should be
372 * masked. It is quite rare and hard to debug.
374 * Catch irq issue if it happens and print all I can.
376 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
378 if (!test_bit(wil_status_irqen, &wil->status)) {
379 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
380 HOSTADDR(RGF_DMA_EP_RX_ICR) +
381 offsetof(struct RGF_ICR, ICM));
382 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
383 HOSTADDR(RGF_DMA_EP_RX_ICR) +
384 offsetof(struct RGF_ICR, ICR));
385 u32 imv_rx = ioread32(wil->csr +
386 HOSTADDR(RGF_DMA_EP_RX_ICR) +
387 offsetof(struct RGF_ICR, IMV));
388 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
389 HOSTADDR(RGF_DMA_EP_TX_ICR) +
390 offsetof(struct RGF_ICR, ICM));
391 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
392 HOSTADDR(RGF_DMA_EP_TX_ICR) +
393 offsetof(struct RGF_ICR, ICR));
394 u32 imv_tx = ioread32(wil->csr +
395 HOSTADDR(RGF_DMA_EP_TX_ICR) +
396 offsetof(struct RGF_ICR, IMV));
397 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
398 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
399 offsetof(struct RGF_ICR, ICM));
400 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
401 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
402 offsetof(struct RGF_ICR, ICR));
403 u32 imv_misc = ioread32(wil->csr +
404 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
405 offsetof(struct RGF_ICR, IMV));
406 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
407 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
408 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
409 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
411 icm_rx, icr_rx, imv_rx,
412 icm_tx, icr_tx, imv_tx,
413 icm_misc, icr_misc, imv_misc);
421 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
423 irqreturn_t rc = IRQ_HANDLED;
424 struct wil6210_priv *wil = cookie;
425 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
428 * pseudo_cause is Clear-On-Read, no need to ACK
430 if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
433 /* FIXME: IRQ mask debug */
434 if (wil6210_debug_irq_mask(wil, pseudo_cause))
437 trace_wil6210_irq_pseudo(pseudo_cause);
438 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
440 wil6210_mask_irq_pseudo(wil);
442 /* Discover real IRQ cause
443 * There are 2 possible phases for every IRQ:
444 * - hard IRQ handler called right here
445 * - threaded handler called later
447 * Hard IRQ handler reads and clears ISR.
449 * If threaded handler requested, hard IRQ handler
450 * returns IRQ_WAKE_THREAD and saves ISR register value
451 * for the threaded handler use.
453 * voting for wake thread - need at least 1 vote
455 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
456 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
457 rc = IRQ_WAKE_THREAD;
459 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
460 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
461 rc = IRQ_WAKE_THREAD;
463 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
464 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
465 rc = IRQ_WAKE_THREAD;
467 /* if thread is requested, it will unmask IRQ */
468 if (rc != IRQ_WAKE_THREAD)
469 wil6210_unmask_irq_pseudo(wil);
474 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
478 * IRQ's are in the following order:
484 rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
489 rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
494 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
495 wil6210_irq_misc_thread,
496 IRQF_SHARED, WIL_NAME"_misc", wil);
503 free_irq(irq + 1, wil);
509 /* can't use wil_ioread32_and_clear because ICC value is not ser yet */
510 static inline void wil_clear32(void __iomem *addr)
512 u32 x = ioread32(addr);
517 void wil6210_clear_irq(struct wil6210_priv *wil)
519 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
520 offsetof(struct RGF_ICR, ICR));
521 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
522 offsetof(struct RGF_ICR, ICR));
523 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
524 offsetof(struct RGF_ICR, ICR));
527 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
531 rc = wil6210_request_3msi(wil, irq);
533 rc = request_threaded_irq(irq, wil6210_hardirq,
535 wil->n_msi ? 0 : IRQF_SHARED,
540 wil6210_enable_irq(wil);
545 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
547 wil6210_disable_irq(wil);
549 if (wil->n_msi == 3) {
550 free_irq(irq + 1, wil);
551 free_irq(irq + 2, wil);