2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/interrupt.h>
22 * Theory of operation:
24 * There is ISR pseudo-cause register,
25 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
26 * Its bits represents OR'ed bits from 3 real ISR registers:
29 * Registers may be configured to either "write 1 to clear" or
30 * "clear on read" mode
32 * When handling interrupt, one have to mask/unmask interrupts for the
33 * real ISR registers, or hardware may malfunction.
37 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
38 #define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
39 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
40 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
41 #define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
45 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
46 BIT_DMA_PSEUDO_CAUSE_TX | \
47 BIT_DMA_PSEUDO_CAUSE_MISC))
49 #if defined(CONFIG_WIL6210_ISR_COR)
50 /* configure to Clear-On-Read mode */
51 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
53 static inline void wil_icr_clear(u32 x, void __iomem *addr)
56 #else /* defined(CONFIG_WIL6210_ISR_COR) */
57 /* configure to Write-1-to-Clear mode */
58 #define WIL_ICR_ICC_VALUE (0UL)
60 static inline void wil_icr_clear(u32 x, void __iomem *addr)
64 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
66 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
68 u32 x = ioread32(addr);
70 wil_icr_clear(x, addr);
75 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
77 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
78 HOSTADDR(RGF_DMA_EP_TX_ICR) +
79 offsetof(struct RGF_ICR, IMS));
82 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
84 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
85 HOSTADDR(RGF_DMA_EP_RX_ICR) +
86 offsetof(struct RGF_ICR, IMS));
89 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
91 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
92 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
93 offsetof(struct RGF_ICR, IMS));
96 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
98 wil_dbg_irq(wil, "%s()\n", __func__);
100 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
101 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
103 clear_bit(wil_status_irqen, &wil->status);
106 static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
108 iowrite32(WIL6210_IMC_TX, wil->csr +
109 HOSTADDR(RGF_DMA_EP_TX_ICR) +
110 offsetof(struct RGF_ICR, IMC));
113 static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
115 iowrite32(WIL6210_IMC_RX, wil->csr +
116 HOSTADDR(RGF_DMA_EP_RX_ICR) +
117 offsetof(struct RGF_ICR, IMC));
120 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
122 iowrite32(WIL6210_IMC_MISC, wil->csr +
123 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
124 offsetof(struct RGF_ICR, IMC));
127 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
129 wil_dbg_irq(wil, "%s()\n", __func__);
131 set_bit(wil_status_irqen, &wil->status);
133 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
134 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
137 void wil6210_disable_irq(struct wil6210_priv *wil)
139 wil_dbg_irq(wil, "%s()\n", __func__);
141 wil6210_mask_irq_tx(wil);
142 wil6210_mask_irq_rx(wil);
143 wil6210_mask_irq_misc(wil);
144 wil6210_mask_irq_pseudo(wil);
147 void wil6210_enable_irq(struct wil6210_priv *wil)
149 wil_dbg_irq(wil, "%s()\n", __func__);
151 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
152 offsetof(struct RGF_ICR, ICC));
153 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
154 offsetof(struct RGF_ICR, ICC));
155 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
156 offsetof(struct RGF_ICR, ICC));
158 wil6210_unmask_irq_pseudo(wil);
159 wil6210_unmask_irq_tx(wil);
160 wil6210_unmask_irq_rx(wil);
161 wil6210_unmask_irq_misc(wil);
164 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
166 struct wil6210_priv *wil = cookie;
167 u32 isr = wil_ioread32_and_clear(wil->csr +
168 HOSTADDR(RGF_DMA_EP_RX_ICR) +
169 offsetof(struct RGF_ICR, ICR));
171 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
174 wil_err(wil, "spurious IRQ: RX\n");
178 wil6210_mask_irq_rx(wil);
180 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
181 wil_dbg_irq(wil, "RX done\n");
182 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
187 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
189 wil6210_unmask_irq_rx(wil);
194 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
196 struct wil6210_priv *wil = cookie;
197 u32 isr = wil_ioread32_and_clear(wil->csr +
198 HOSTADDR(RGF_DMA_EP_TX_ICR) +
199 offsetof(struct RGF_ICR, ICR));
201 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
204 wil_err(wil, "spurious IRQ: TX\n");
208 wil6210_mask_irq_tx(wil);
210 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
212 wil_dbg_irq(wil, "TX done\n");
213 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
214 for (i = 0; i < 24; i++) {
215 u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
218 wil_dbg_irq(wil, "TX done(%i)\n", i);
219 wil_tx_complete(wil, i);
225 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
227 wil6210_unmask_irq_tx(wil);
232 static void wil_notify_fw_error(struct wil6210_priv *wil)
234 struct device *dev = &wil_to_ndev(wil)->dev;
236 [0] = "SOURCE=wil6210",
237 [1] = "EVENT=FW_ERROR",
240 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
243 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
245 /* make shadow copy of registers that should not change on run time */
246 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
247 sizeof(struct wil6210_mbox_ctl));
248 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
249 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
252 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
254 struct wil6210_priv *wil = cookie;
255 u32 isr = wil_ioread32_and_clear(wil->csr +
256 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
257 offsetof(struct RGF_ICR, ICR));
259 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
262 wil_err(wil, "spurious IRQ: MISC\n");
266 wil6210_mask_irq_misc(wil);
268 if (isr & ISR_MISC_FW_ERROR) {
269 wil_err(wil, "Firmware error detected\n");
270 clear_bit(wil_status_fwready, &wil->status);
272 * do not clear @isr here - we do 2-nd part in thread
273 * there, user space get notified, and it should be done
274 * in non-atomic context
278 if (isr & ISR_MISC_FW_READY) {
279 wil_dbg_irq(wil, "IRQ: FW ready\n");
280 wil_cache_mbox_regs(wil);
281 set_bit(wil_status_reset_done, &wil->status);
283 * Actual FW ready indicated by the
284 * WMI_FW_READY_EVENTID
286 isr &= ~ISR_MISC_FW_READY;
292 return IRQ_WAKE_THREAD;
294 wil6210_unmask_irq_misc(wil);
299 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
301 struct wil6210_priv *wil = cookie;
302 u32 isr = wil->isr_misc;
304 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
306 if (isr & ISR_MISC_FW_ERROR) {
307 wil_notify_fw_error(wil);
308 isr &= ~ISR_MISC_FW_ERROR;
311 if (isr & ISR_MISC_MBOX_EVT) {
312 wil_dbg_irq(wil, "MBOX event\n");
314 isr &= ~ISR_MISC_MBOX_EVT;
318 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
322 wil6210_unmask_irq_misc(wil);
330 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
332 struct wil6210_priv *wil = cookie;
334 wil_dbg_irq(wil, "Thread IRQ\n");
335 /* Discover real IRQ cause */
337 wil6210_irq_misc_thread(irq, cookie);
339 wil6210_unmask_irq_pseudo(wil);
345 * There is subtle bug in hardware that causes IRQ to raise when it should be
346 * masked. It is quite rare and hard to debug.
348 * Catch irq issue if it happens and print all I can.
350 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
352 if (!test_bit(wil_status_irqen, &wil->status)) {
353 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
354 HOSTADDR(RGF_DMA_EP_RX_ICR) +
355 offsetof(struct RGF_ICR, ICM));
356 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
357 HOSTADDR(RGF_DMA_EP_RX_ICR) +
358 offsetof(struct RGF_ICR, ICR));
359 u32 imv_rx = ioread32(wil->csr +
360 HOSTADDR(RGF_DMA_EP_RX_ICR) +
361 offsetof(struct RGF_ICR, IMV));
362 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
363 HOSTADDR(RGF_DMA_EP_TX_ICR) +
364 offsetof(struct RGF_ICR, ICM));
365 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
366 HOSTADDR(RGF_DMA_EP_TX_ICR) +
367 offsetof(struct RGF_ICR, ICR));
368 u32 imv_tx = ioread32(wil->csr +
369 HOSTADDR(RGF_DMA_EP_TX_ICR) +
370 offsetof(struct RGF_ICR, IMV));
371 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
372 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
373 offsetof(struct RGF_ICR, ICM));
374 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
375 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
376 offsetof(struct RGF_ICR, ICR));
377 u32 imv_misc = ioread32(wil->csr +
378 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
379 offsetof(struct RGF_ICR, IMV));
380 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
381 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
382 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
383 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
385 icm_rx, icr_rx, imv_rx,
386 icm_tx, icr_tx, imv_tx,
387 icm_misc, icr_misc, imv_misc);
395 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
397 irqreturn_t rc = IRQ_HANDLED;
398 struct wil6210_priv *wil = cookie;
399 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
402 * pseudo_cause is Clear-On-Read, no need to ACK
404 if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
407 /* FIXME: IRQ mask debug */
408 if (wil6210_debug_irq_mask(wil, pseudo_cause))
411 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
413 wil6210_mask_irq_pseudo(wil);
415 /* Discover real IRQ cause
416 * There are 2 possible phases for every IRQ:
417 * - hard IRQ handler called right here
418 * - threaded handler called later
420 * Hard IRQ handler reads and clears ISR.
422 * If threaded handler requested, hard IRQ handler
423 * returns IRQ_WAKE_THREAD and saves ISR register value
424 * for the threaded handler use.
426 * voting for wake thread - need at least 1 vote
428 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
429 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
430 rc = IRQ_WAKE_THREAD;
432 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
433 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
434 rc = IRQ_WAKE_THREAD;
436 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
437 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
438 rc = IRQ_WAKE_THREAD;
440 /* if thread is requested, it will unmask IRQ */
441 if (rc != IRQ_WAKE_THREAD)
442 wil6210_unmask_irq_pseudo(wil);
447 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
451 * IRQ's are in the following order:
457 rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
462 rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
467 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
468 wil6210_irq_misc_thread,
469 IRQF_SHARED, WIL_NAME"_misc", wil);
476 free_irq(irq + 1, wil);
483 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
487 rc = wil6210_request_3msi(wil, irq);
489 rc = request_threaded_irq(irq, wil6210_hardirq,
491 wil->n_msi ? 0 : IRQF_SHARED,
496 wil6210_enable_irq(wil);
501 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
503 wil6210_disable_irq(wil);
505 if (wil->n_msi == 3) {
506 free_irq(irq + 1, wil);
507 free_irq(irq + 2, wil);