2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
54 /* Macro to expand scalars to 64-bit objects */
56 #define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
61 (((unsigned long long int)(x)) & 0xffffffff) : \
62 (unsigned long long int)(x))
64 /* increment with wrap-around */
65 #define INCR(_l, _sz) do { \
67 (_l) &= ((_sz) - 1); \
70 /* decrement with wrap-around */
71 #define DECR(_l, _sz) do { \
73 (_l) &= ((_sz) - 1); \
76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
78 #define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
84 #define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
87 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
89 static inline unsigned long get_timestamp(void)
91 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
94 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
101 ATH_DBG_RESET = 0x00000001,
102 ATH_DBG_PHY_IO = 0x00000002,
103 ATH_DBG_REG_IO = 0x00000004,
104 ATH_DBG_QUEUE = 0x00000008,
105 ATH_DBG_EEPROM = 0x00000010,
106 ATH_DBG_NF_CAL = 0x00000020,
107 ATH_DBG_CALIBRATE = 0x00000040,
108 ATH_DBG_CHANNEL = 0x00000080,
109 ATH_DBG_INTERRUPT = 0x00000100,
110 ATH_DBG_REGULATORY = 0x00000200,
111 ATH_DBG_ANI = 0x00000400,
112 ATH_DBG_POWER_MGMT = 0x00000800,
113 ATH_DBG_XMIT = 0x00001000,
114 ATH_DBG_BEACON = 0x00002000,
115 ATH_DBG_RATE = 0x00004000,
116 ATH_DBG_CONFIG = 0x00008000,
117 ATH_DBG_KEYCACHE = 0x00010000,
118 ATH_DBG_AGGR = 0x00020000,
119 ATH_DBG_FATAL = 0x00040000,
120 ATH_DBG_ANY = 0xffffffff
123 #define DBG_DEFAULT (ATH_DBG_FATAL)
125 #define DPRINTF(sc, _m, _fmt, ...) do { \
126 if (sc->sc_debug & (_m)) \
127 printk(_fmt , ##__VA_ARGS__); \
130 /***************************/
131 /* Load-time Configuration */
132 /***************************/
134 /* Per-instance load-time (note: NOT run-time) configurations
135 * for Atheros Device */
139 u16 txpowlimit_override;
140 u8 cabqReadytime; /* Cabq Readytime % */
141 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
144 /***********************/
145 /* Chainmask Selection */
146 /***********************/
148 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
149 /* Default - Number of last RSSI values that is used for
150 * chainmask selection */
151 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
152 /* Means use 3x3 chainmask instead of configured chainmask */
153 #define ATH_CHAINMASK_SEL_3X3 7
154 /* Default - Rssi threshold below which we have to switch to 3x3 */
155 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
156 /* Default - Rssi threshold above which we have to switch to
157 * user configured values */
158 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
159 /* Struct to store the chainmask select related info */
160 struct ath_chainmask_sel {
161 struct timer_list timer;
162 int cur_tx_mask; /* user configured or 3x3 */
163 int cur_rx_mask; /* user configured or 3x3 */
165 u8 switch_allowed:1, /* timer will set this */
169 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
170 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
172 /*************************/
173 /* Descriptor Management */
174 /*************************/
176 #define ATH_TXBUF_RESET(_bf) do { \
177 (_bf)->bf_status = 0; \
178 (_bf)->bf_lastbf = NULL; \
179 (_bf)->bf_lastfrm = NULL; \
180 (_bf)->bf_next = NULL; \
181 memset(&((_bf)->bf_state), 0, \
182 sizeof(struct ath_buf_state)); \
192 BUF_SHORT_PREAMBLE = BIT(6),
195 BUF_AGGR_BURST = BIT(9),
196 BUF_CALC_AIRTIME = BIT(10),
199 struct ath_buf_state {
200 int bfs_nframes; /* # frames in aggregate */
201 u16 bfs_al; /* length of aggregate */
202 u16 bfs_frmlen; /* length of frame */
203 int bfs_seqno; /* sequence number */
204 int bfs_tidno; /* tid of this frame */
205 int bfs_retries; /* current retries */
206 u32 bf_type; /* BUF_* (enum buffer_type) */
207 /* key type use to encrypt this frame */
209 enum ath9k_key_type bfs_keytype;
212 #define bf_nframes bf_state.bfs_nframes
213 #define bf_al bf_state.bfs_al
214 #define bf_frmlen bf_state.bfs_frmlen
215 #define bf_retries bf_state.bfs_retries
216 #define bf_seqno bf_state.bfs_seqno
217 #define bf_tidno bf_state.bfs_tidno
218 #define bf_rcs bf_state.bfs_rcs
219 #define bf_keyix bf_state.bfs_keyix
220 #define bf_keytype bf_state.bfs_keytype
221 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
222 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
223 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
224 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
225 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
226 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
227 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
228 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
229 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
230 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
233 * Abstraction of a contiguous buffer to transmit/receive. There is only
234 * a single hw descriptor encapsulated here.
237 struct list_head list;
238 struct list_head *last;
239 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
241 struct ath_buf *bf_lastfrm; /* last buf of this frame */
242 struct ath_buf *bf_next; /* next subframe in the aggregate */
243 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
244 void *bf_mpdu; /* enclosing frame structure */
245 struct ath_desc *bf_desc; /* virtual addr of desc */
246 dma_addr_t bf_daddr; /* physical addr of desc */
247 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
249 u16 bf_flags; /* tx descriptor flags */
250 struct ath_buf_state bf_state; /* buffer state */
251 dma_addr_t bf_dmacontext;
255 * reset the rx buffer.
256 * any new fields added to the athbuf and require
257 * reset need to be added to this macro.
258 * currently bf_status is the only one requires that
261 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
263 /* hw processing complete, desc processed by hal */
264 #define ATH_BUFSTATUS_DONE 0x00000001
265 /* hw processing complete, desc hold for hw */
266 #define ATH_BUFSTATUS_STALE 0x00000002
267 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
268 #define ATH_BUFSTATUS_FREE 0x00000004
270 /* DMA state for tx/rx descriptors */
274 struct ath_desc *dd_desc; /* descriptors */
275 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
276 u32 dd_desc_len; /* size of dd_desc */
277 struct ath_buf *dd_bufptr; /* associated buffers */
278 dma_addr_t dd_dmacontext;
281 int ath_descdma_setup(struct ath_softc *sc,
282 struct ath_descdma *dd,
283 struct list_head *head,
287 int ath_desc_alloc(struct ath_softc *sc);
288 void ath_desc_free(struct ath_softc *sc);
289 void ath_descdma_cleanup(struct ath_softc *sc,
290 struct ath_descdma *dd,
291 struct list_head *head);
297 #define ATH_MAX_ANTENNA 3
298 #define ATH_RXBUF 512
299 #define WME_NUM_TID 16
301 int ath_startrecv(struct ath_softc *sc);
302 bool ath_stoprecv(struct ath_softc *sc);
303 void ath_flushrecv(struct ath_softc *sc);
304 u32 ath_calcrxfilter(struct ath_softc *sc);
305 int ath_rx_init(struct ath_softc *sc, int nbufs);
306 void ath_rx_cleanup(struct ath_softc *sc);
307 int ath_rx_tasklet(struct ath_softc *sc, int flush);
309 #define ATH_TXBUF 512
310 /* max number of transmit attempts (tries) */
311 #define ATH_TXMAXTRY 13
312 /* max number of 11n transmit attempts (tries) */
313 #define ATH_11N_TXMAXTRY 10
314 /* max number of tries for management and control frames */
315 #define ATH_MGT_TXMAXTRY 4
316 #define WME_BA_BMP_SIZE 64
317 #define WME_MAX_BA WME_BA_BMP_SIZE
318 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
319 #define TID_TO_WME_AC(_tid) \
320 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
321 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
322 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
326 /* Wireless Multimedia Extension Defines */
327 #define WME_AC_BE 0 /* best effort */
328 #define WME_AC_BK 1 /* background */
329 #define WME_AC_VI 2 /* video */
330 #define WME_AC_VO 3 /* voice */
334 * Data transmit queue state. One of these exists for each
335 * hardware transmit queue. Packets sent to us from above
336 * are assigned to queues based on their priority. Not all
337 * devices support a complete set of hardware transmit queues.
338 * For those devices the array sc_ac2q will map multiple
339 * priorities to fewer hardware queues (typically all to one
343 u32 axq_qnum; /* hardware q number */
344 u32 *axq_link; /* link ptr in last TX desc */
345 struct list_head axq_q; /* transmit queue */
347 unsigned long axq_lockflags; /* intr state when must cli */
348 u32 axq_depth; /* queue depth */
349 u8 axq_aggr_depth; /* aggregates queued */
350 u32 axq_totalqueued; /* total ever queued */
352 bool stopped; /* Is mac80211 queue stopped ? */
353 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
355 /* first desc of the last descriptor that contains CTS */
356 struct ath_desc *axq_lastdsWithCTS;
358 /* final desc of the gating desc that determines whether
359 lastdsWithCTS has been DMA'ed or not */
360 struct ath_desc *axq_gatingds;
362 struct list_head axq_acq;
365 #define AGGR_CLEANUP BIT(1)
366 #define AGGR_ADDBA_COMPLETE BIT(2)
367 #define AGGR_ADDBA_PROGRESS BIT(3)
369 /* per TID aggregate tx state for a destination */
371 struct list_head list; /* round-robin tid entry */
372 struct list_head buf_q; /* pending buffers */
374 struct ath_atx_ac *ac;
375 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
380 int baw_head; /* first un-acked tx buffer */
381 int baw_tail; /* next unused tx buffer slot */
385 int addba_exchangeattempts;
388 /* per access-category aggregate tx state for a destination */
390 int sched; /* dest-ac is scheduled */
391 int qnum; /* H/W queue number associated
393 struct list_head list; /* round-robin txq entry */
394 struct list_head tid_q; /* queue of TIDs with buffers */
397 /* per dest tx state */
399 struct ath_atx_tid tid[WME_NUM_TID];
400 struct ath_atx_ac ac[WME_NUM_AC];
403 /* per-frame tx control block */
404 struct ath_tx_control {
409 /* per frame tx status block */
410 struct ath_xmit_status {
411 int retries; /* number of retries to successufully
412 transmit this frame */
413 int flags; /* status of transmit */
414 #define ATH_TX_ERROR 0x01
415 #define ATH_TX_XRETRY 0x02
416 #define ATH_TX_BAR 0x04
420 int rssi; /* RSSI (noise floor ajusted) */
421 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
422 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
423 int rateieee; /* data rate xmitted (IEEE rate code) */
424 int rateKbps; /* data rate xmitted (Kbps) */
425 int ratecode; /* phy rate code */
426 int flags; /* validity flags */
427 /* if any of ctl,extn chain rssis are valid */
428 #define ATH_TX_CHAIN_RSSI_VALID 0x01
429 /* if extn chain rssis are valid */
430 #define ATH_TX_RSSI_EXTN_VALID 0x02
431 u32 airtime; /* time on air per final tx rate */
434 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
435 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
436 int ath_tx_setup(struct ath_softc *sc, int haltype);
437 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
438 void ath_tx_draintxq(struct ath_softc *sc,
439 struct ath_txq *txq, bool retry_tx);
440 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
441 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
442 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
443 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
444 int ath_tx_init(struct ath_softc *sc, int nbufs);
445 int ath_tx_cleanup(struct ath_softc *sc);
446 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
447 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
448 int ath_txq_update(struct ath_softc *sc, int qnum,
449 struct ath9k_tx_queue_info *q);
450 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
451 struct ath_tx_control *txctl);
452 void ath_tx_tasklet(struct ath_softc *sc);
453 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
454 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
455 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
456 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
457 struct ath_xmit_status *tx_status);
458 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
460 /**********************/
461 /* Node / Aggregation */
462 /**********************/
464 #define ADDBA_EXCHANGE_ATTEMPTS 10
465 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
466 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
467 /* number of delimiters for encryption padding */
468 #define ATH_AGGR_ENCRYPTDELIM 10
469 /* minimum h/w qdepth to be sustained to maximize aggregation */
470 #define ATH_AGGR_MIN_QDEPTH 2
471 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
472 #define IEEE80211_SEQ_SEQ_SHIFT 4
473 #define IEEE80211_SEQ_MAX 4096
474 #define IEEE80211_MIN_AMPDU_BUF 0x8
475 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
477 /* return whether a bit at index _n in bitmap _bm is set
478 * _sz is the size of the bitmap */
479 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
480 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
482 /* return block-ack bitmap index given sequence and starting sequence */
483 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
485 /* returns delimiter padding required given the packet length */
486 #define ATH_AGGR_GET_NDELIM(_len) \
487 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
488 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
490 #define BAW_WITHIN(_start, _bawsz, _seqno) \
491 ((((_seqno) - (_start)) & 4095) < (_bawsz))
493 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
494 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
495 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
496 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
498 enum ATH_AGGR_STATUS {
506 struct aggr_rifs_param {
507 int param_max_frames;
511 struct ath_rc_series *param_rcs;
514 /* Per-node aggregation state */
515 struct ath_node_aggr {
516 struct ath_atx tx; /* node transmit state */
519 /* driver-specific node state */
521 struct ath_softc *an_sc;
522 struct ath_chainmask_sel an_chainmask_sel;
523 struct ath_node_aggr an_aggr;
528 void ath_tx_resume_tid(struct ath_softc *sc,
529 struct ath_atx_tid *tid);
530 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
531 void ath_tx_aggr_teardown(struct ath_softc *sc,
532 struct ath_node *an, u8 tidno);
533 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
535 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
536 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
537 void ath_newassoc(struct ath_softc *sc,
538 struct ath_node *node, int isnew, int isuapsd);
539 void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta);
540 void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
547 * Define the scheme that we select MAC address for multiple
548 * BSS on the same radio. The very first VAP will just use the MAC
549 * address from the EEPROM. For the next 3 VAPs, we set the
550 * U/L bit (bit 1) in MAC address, and use the next two bits as the
554 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
555 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
557 /* driver-specific vap state */
559 int av_bslot; /* beacon slot index */
560 enum ath9k_opmode av_opmode; /* VAP operational mode */
561 struct ath_buf *av_bcbuf; /* beacon buffer */
562 struct ath_tx_control av_btxctl; /* txctl information for beacon */
565 /*******************/
566 /* Beacon Handling */
567 /*******************/
570 * Regardless of the number of beacons we stagger, (i.e. regardless of the
571 * number of BSSIDs) if a given beacon does not go out even after waiting this
572 * number of beacon intervals, the game's up.
574 #define BSTUCK_THRESH (9 * ATH_BCBUF)
575 #define ATH_BCBUF 4 /* number of beacon buffers */
576 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
577 #define ATH_DEFAULT_BMISS_LIMIT 10
578 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
580 /* beacon configuration */
581 struct ath_beacon_config {
591 } u; /* last received beacon/probe response timestamp of this BSS. */
594 void ath9k_beacon_tasklet(unsigned long data);
595 void ath_beacon_config(struct ath_softc *sc, int if_id);
596 int ath_beaconq_setup(struct ath_hal *ah);
597 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
598 void ath_bstuck_process(struct ath_softc *sc);
599 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
600 void ath_beacon_sync(struct ath_softc *sc, int if_id);
601 void ath_get_beaconconfig(struct ath_softc *sc,
603 struct ath_beacon_config *conf);
604 /*********************/
605 /* Antenna diversity */
606 /*********************/
608 #define ATH_ANT_DIV_MAX_CFG 2
609 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
610 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
612 enum ATH_ANT_DIV_STATE{
614 ATH_ANT_DIV_SCAN, /* evaluating antenna */
618 struct ath_softc *antdiv_sc;
620 enum ATH_ANT_DIV_STATE antdiv_state;
621 u8 antdiv_num_antcfg;
624 int32_t antdivf_rssitrig;
625 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
626 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
627 u64 antdiv_laststatetsf;
628 u8 antdiv_bssid[ETH_ALEN];
631 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
632 struct ath_softc *sc, int32_t rssitrig);
633 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
636 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
637 void ath_slow_ant_div(struct ath_antdiv *antdiv,
638 struct ieee80211_hdr *wh,
639 struct ath_rx_status *rx_stats);
640 void ath_setdefantenna(void *sc, u32 antenna);
646 /* ANI values for STA only.
647 FIXME: Add appropriate values for AP later */
649 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
650 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
651 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
652 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
656 int16_t sc_noise_floor;
657 unsigned int sc_longcal_timer;
658 unsigned int sc_shortcal_timer;
659 unsigned int sc_resetcal_timer;
660 unsigned int sc_checkani_timer;
661 struct timer_list timer;
664 /********************/
666 /********************/
668 #define ATH_LED_PIN 1
678 struct ath_softc *sc;
679 struct led_classdev led_cdev;
680 enum ath_led_type led_type;
686 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
689 struct rfkill *rfkill;
690 struct delayed_work rfkill_poll;
691 char rfkill_name[32];
694 /********************/
695 /* Main driver core */
696 /********************/
699 * Default cache line size, in bytes.
700 * Used when PCI device not fully initialized by bootrom/BIOS
702 #define DEFAULT_CACHELINE 32
703 #define ATH_DEFAULT_NOISE_FLOOR -95
704 #define ATH_REGCLASSIDS_MAX 10
705 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
706 #define ATH_MAX_SW_RETRIES 10
707 #define ATH_CHAN_MAX 255
708 #define IEEE80211_WEP_NKID 4 /* number of key ids */
709 #define IEEE80211_RATE_VAL 0x7f
711 * The key cache is used for h/w cipher state and also for
712 * tracking station state such as the current tx antenna.
713 * We also setup a mapping table between key cache slot indices
714 * and station state to short-circuit node lookups on rx.
715 * Different parts have different size key caches. We handle
716 * up to ATH_KEYMAX entries (could dynamically allocate state).
718 #define ATH_KEYMAX 128 /* max key cache size we handle */
720 #define ATH_IF_ID_ANY 0xff
721 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
723 #define RSSI_LPF_THRESHOLD -20
724 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
725 #define ATH_RATE_DUMMY_MARKER 0
726 #define ATH_RSSI_LPF_LEN 10
727 #define ATH_RSSI_DUMMY_MARKER 0x127
729 #define ATH_EP_MUL(x, mul) ((x) * (mul))
730 #define ATH_EP_RND(x, mul) \
731 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
732 #define ATH_RSSI_OUT(x) \
733 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
734 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
735 #define ATH_RSSI_IN(x) \
736 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
737 #define ATH_LPF_RSSI(x, y, len) \
738 ((x != ATH_RSSI_DUMMY_MARKER) ? \
739 (((x) * ((len) - 1) + (y)) / (len)) : (y))
740 #define ATH_RSSI_LPF(x, y) do { \
741 if ((y) >= RSSI_LPF_THRESHOLD) \
742 x = ATH_LPF_RSSI((x), \
743 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
760 enum ath9k_ht_macmode tx_chan_width;
764 #define SC_OP_INVALID BIT(0)
765 #define SC_OP_BEACONS BIT(1)
766 #define SC_OP_RXAGGR BIT(2)
767 #define SC_OP_TXAGGR BIT(3)
768 #define SC_OP_CHAINMASK_UPDATE BIT(4)
769 #define SC_OP_FULL_RESET BIT(5)
770 #define SC_OP_NO_RESET BIT(6)
771 #define SC_OP_PREAMBLE_SHORT BIT(7)
772 #define SC_OP_PROTECT_ENABLE BIT(8)
773 #define SC_OP_RXFLUSH BIT(9)
774 #define SC_OP_LED_ASSOCIATED BIT(10)
775 #define SC_OP_RFKILL_REGISTERED BIT(11)
776 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
777 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
780 struct ieee80211_hw *hw;
781 struct pci_dev *pdev;
782 struct tasklet_struct intr_tq;
783 struct tasklet_struct bcon_tasklet;
784 struct ath_config sc_config;
785 struct ath_hal *sc_ah;
788 u8 sc_curbssid[ETH_ALEN];
789 u8 sc_myaddr[ETH_ALEN];
790 u8 sc_bssidmask[ETH_ALEN];
794 u32 sc_flags; /* SC_OP_* */
795 unsigned int rx_filter;
799 int sc_slotupdate; /* slot to next advance fsm */
801 int sc_bslot[ATH_BCBUF];
804 enum ath9k_int sc_imask;
805 enum wireless_mode sc_curmode; /* current phy mode */
806 enum PROT_MODE sc_protmode;
808 u8 sc_nbcnvaps; /* # of vaps sending beacons */
809 u16 sc_nvaps; /* # of active virtual ap's */
810 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
813 u8 sc_defant; /* current default antenna */
814 u8 sc_rxotherant; /* rx's on non-default antenna */
816 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
817 struct ath_ht_info sc_ht_info;
818 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
820 #ifdef CONFIG_SLOW_ANT_DIV
821 struct ath_antdiv sc_antdiv;
824 OK, /* no change needed */
825 UPDATE, /* update pending */
826 COMMIT /* beacon sent, commit change */
827 } sc_updateslot; /* slot time update fsm */
830 u32 sc_keymax; /* size of key cache */
831 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
832 u8 sc_splitmic; /* split TKIP MIC keys */
835 struct list_head sc_rxbuf;
836 struct ath_descdma sc_rxdma;
837 int sc_rxbufsize; /* rx size based on mtu */
838 u32 *sc_rxlink; /* link ptr in last RX desc */
841 struct list_head sc_txbuf;
842 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
843 struct ath_descdma sc_txdma;
845 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
846 u16 seq_no; /* TX sequence number */
849 struct ath9k_tx_queue_info sc_beacon_qi;
850 struct ath_descdma sc_bdma;
851 struct ath_txq *sc_cabq;
852 struct list_head sc_bbuf;
855 u32 ast_be_xmit; /* beacons transmitted */
859 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
860 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
861 const struct ath9k_rate_table *sc_currates;
862 u8 sc_protrix; /* protection rate index */
864 u32 rateKbps; /* transfer rate in kbs */
865 u8 ieeerate; /* IEEE rate */
866 } sc_hwmap[256]; /* h/w rate ix mappings */
869 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
870 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
873 spinlock_t sc_rxflushlock;
874 spinlock_t sc_rxbuflock;
875 spinlock_t sc_txbuflock;
876 spinlock_t sc_resetlock;
879 struct ath_led radio_led;
880 struct ath_led assoc_led;
881 struct ath_led tx_led;
882 struct ath_led rx_led;
885 struct ath_rfkill rf_kill;
888 struct ath_ani sc_ani;
891 int ath_init(u16 devid, struct ath_softc *sc);
892 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
893 void ath_stop(struct ath_softc *sc);
894 irqreturn_t ath_isr(int irq, void *dev);
895 int ath_reset(struct ath_softc *sc, bool retry_tx);
896 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
898 /*********************/
899 /* Utility Functions */
900 /*********************/
902 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
903 int ath_keyset(struct ath_softc *sc,
905 struct ath9k_keyval *hk,
906 const u8 mac[ETH_ALEN]);
907 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
908 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
909 void ath_setslottime(struct ath_softc *sc);
910 void ath_update_txpow(struct ath_softc *sc);
911 int ath_cabq_update(struct ath_softc *);
912 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);