2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
54 /* Macro to expand scalars to 64-bit objects */
56 #define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
61 (((unsigned long long int)(x)) & 0xffffffff) : \
62 (unsigned long long int)(x))
64 /* increment with wrap-around */
65 #define INCR(_l, _sz) do { \
67 (_l) &= ((_sz) - 1); \
70 /* decrement with wrap-around */
71 #define DECR(_l, _sz) do { \
73 (_l) &= ((_sz) - 1); \
76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
78 #define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
84 #define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
87 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
89 static inline unsigned long get_timestamp(void)
91 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
94 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
101 ATH_DBG_RESET = 0x00000001,
102 ATH_DBG_PHY_IO = 0x00000002,
103 ATH_DBG_REG_IO = 0x00000004,
104 ATH_DBG_QUEUE = 0x00000008,
105 ATH_DBG_EEPROM = 0x00000010,
106 ATH_DBG_NF_CAL = 0x00000020,
107 ATH_DBG_CALIBRATE = 0x00000040,
108 ATH_DBG_CHANNEL = 0x00000080,
109 ATH_DBG_INTERRUPT = 0x00000100,
110 ATH_DBG_REGULATORY = 0x00000200,
111 ATH_DBG_ANI = 0x00000400,
112 ATH_DBG_POWER_MGMT = 0x00000800,
113 ATH_DBG_XMIT = 0x00001000,
114 ATH_DBG_BEACON = 0x00002000,
115 ATH_DBG_RATE = 0x00004000,
116 ATH_DBG_CONFIG = 0x00008000,
117 ATH_DBG_KEYCACHE = 0x00010000,
118 ATH_DBG_AGGR = 0x00020000,
119 ATH_DBG_FATAL = 0x00040000,
120 ATH_DBG_ANY = 0xffffffff
123 #define DBG_DEFAULT (ATH_DBG_FATAL)
125 #define DPRINTF(sc, _m, _fmt, ...) do { \
126 if (sc->sc_debug & (_m)) \
127 printk(_fmt , ##__VA_ARGS__); \
130 /***************************/
131 /* Load-time Configuration */
132 /***************************/
134 /* Per-instance load-time (note: NOT run-time) configurations
135 * for Atheros Device */
139 u16 txpowlimit_override;
140 u8 cabqReadytime; /* Cabq Readytime % */
141 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
144 /***********************/
145 /* Chainmask Selection */
146 /***********************/
148 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
149 /* Default - Number of last RSSI values that is used for
150 * chainmask selection */
151 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
152 /* Means use 3x3 chainmask instead of configured chainmask */
153 #define ATH_CHAINMASK_SEL_3X3 7
154 /* Default - Rssi threshold below which we have to switch to 3x3 */
155 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
156 /* Default - Rssi threshold above which we have to switch to
157 * user configured values */
158 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
159 /* Struct to store the chainmask select related info */
160 struct ath_chainmask_sel {
161 struct timer_list timer;
162 int cur_tx_mask; /* user configured or 3x3 */
163 int cur_rx_mask; /* user configured or 3x3 */
165 u8 switch_allowed:1, /* timer will set this */
169 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
170 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
172 /*************************/
173 /* Descriptor Management */
174 /*************************/
176 #define ATH_TXBUF_RESET(_bf) do { \
177 (_bf)->bf_status = 0; \
178 (_bf)->bf_lastbf = NULL; \
179 (_bf)->bf_lastfrm = NULL; \
180 (_bf)->bf_next = NULL; \
181 memset(&((_bf)->bf_state), 0, \
182 sizeof(struct ath_buf_state)); \
192 BUF_SHORT_PREAMBLE = BIT(6),
195 BUF_AGGR_BURST = BIT(9),
196 BUF_CALC_AIRTIME = BIT(10),
199 struct ath_buf_state {
200 int bfs_nframes; /* # frames in aggregate */
201 u16 bfs_al; /* length of aggregate */
202 u16 bfs_frmlen; /* length of frame */
203 int bfs_seqno; /* sequence number */
204 int bfs_tidno; /* tid of this frame */
205 int bfs_retries; /* current retries */
206 struct ath_rc_series bfs_rcs[4]; /* rate series */
207 u32 bf_type; /* BUF_* (enum buffer_type) */
208 /* key type use to encrypt this frame */
210 enum ath9k_key_type bfs_keytype;
213 #define bf_nframes bf_state.bfs_nframes
214 #define bf_al bf_state.bfs_al
215 #define bf_frmlen bf_state.bfs_frmlen
216 #define bf_retries bf_state.bfs_retries
217 #define bf_seqno bf_state.bfs_seqno
218 #define bf_tidno bf_state.bfs_tidno
219 #define bf_rcs bf_state.bfs_rcs
220 #define bf_keyix bf_state.bfs_keyix
221 #define bf_keytype bf_state.bfs_keytype
222 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
223 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
224 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
225 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
226 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
227 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
228 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
229 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
230 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
231 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
234 * Abstraction of a contiguous buffer to transmit/receive. There is only
235 * a single hw descriptor encapsulated here.
238 struct list_head list;
239 struct list_head *last;
240 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
242 struct ath_buf *bf_lastfrm; /* last buf of this frame */
243 struct ath_buf *bf_next; /* next subframe in the aggregate */
244 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
245 void *bf_mpdu; /* enclosing frame structure */
246 struct ath_desc *bf_desc; /* virtual addr of desc */
247 dma_addr_t bf_daddr; /* physical addr of desc */
248 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
250 u16 bf_flags; /* tx descriptor flags */
251 struct ath_buf_state bf_state; /* buffer state */
252 dma_addr_t bf_dmacontext;
256 * reset the rx buffer.
257 * any new fields added to the athbuf and require
258 * reset need to be added to this macro.
259 * currently bf_status is the only one requires that
262 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
264 /* hw processing complete, desc processed by hal */
265 #define ATH_BUFSTATUS_DONE 0x00000001
266 /* hw processing complete, desc hold for hw */
267 #define ATH_BUFSTATUS_STALE 0x00000002
268 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
269 #define ATH_BUFSTATUS_FREE 0x00000004
271 /* DMA state for tx/rx descriptors */
275 struct ath_desc *dd_desc; /* descriptors */
276 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
277 u32 dd_desc_len; /* size of dd_desc */
278 struct ath_buf *dd_bufptr; /* associated buffers */
279 dma_addr_t dd_dmacontext;
282 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
284 struct ath_rx_context {
285 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
287 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
289 int ath_descdma_setup(struct ath_softc *sc,
290 struct ath_descdma *dd,
291 struct list_head *head,
295 int ath_desc_alloc(struct ath_softc *sc);
296 void ath_desc_free(struct ath_softc *sc);
297 void ath_descdma_cleanup(struct ath_softc *sc,
298 struct ath_descdma *dd,
299 struct list_head *head);
305 #define ATH_MAX_ANTENNA 3
306 #define ATH_RXBUF 512
307 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
308 #define WME_NUM_TID 16
309 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
310 #define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */
313 ATH_RX_NON_CONSUMED = 0,
317 /* per frame rx status block */
318 struct ath_recv_status {
319 u64 tsf; /* mac tsf */
320 int8_t rssi; /* RSSI (noise floor ajusted) */
321 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
322 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
323 int8_t abs_rssi; /* absolute RSSI */
324 u8 rateieee; /* data rate received (IEEE rate code) */
325 u8 ratecode; /* phy rate code */
326 int rateKbps; /* data rate received (Kbps) */
327 int antenna; /* rx antenna */
328 int flags; /* status of associated skb */
329 #define ATH_RX_FCS_ERROR 0x01
330 #define ATH_RX_MIC_ERROR 0x02
331 #define ATH_RX_DECRYPT_ERROR 0x04
332 #define ATH_RX_RSSI_VALID 0x08
333 /* if any of ctl,extn chainrssis are valid */
334 #define ATH_RX_CHAIN_RSSI_VALID 0x10
335 /* if extn chain rssis are valid */
336 #define ATH_RX_RSSI_EXTN_VALID 0x20
337 /* set if 40Mhz, clear if 20Mhz */
338 #define ATH_RX_40MHZ 0x40
339 /* set if short GI, clear if full GI */
340 #define ATH_RX_SHORT_GI 0x80
344 struct sk_buff *rx_wbuf;
345 unsigned long rx_time; /* system time when received */
346 struct ath_recv_status rx_status; /* cached rx status */
349 /* Per-TID aggregate receiver state for a node */
352 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
353 struct timer_list timer;
355 int baw_head; /* seq_next at head */
356 int baw_tail; /* tail of block-ack window */
357 int seq_reset; /* need to reset start sequence */
358 int addba_exchangecomplete;
359 u16 seq_next; /* next expected sequence */
360 u16 baw_size; /* block-ack window size */
363 /* Per-node receiver aggregate state */
365 struct ath_arx_tid tid[WME_NUM_TID];
368 int ath_startrecv(struct ath_softc *sc);
369 bool ath_stoprecv(struct ath_softc *sc);
370 void ath_flushrecv(struct ath_softc *sc);
371 u32 ath_calcrxfilter(struct ath_softc *sc);
372 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
373 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
374 void ath_handle_rx_intr(struct ath_softc *sc);
375 int ath_rx_init(struct ath_softc *sc, int nbufs);
376 void ath_rx_cleanup(struct ath_softc *sc);
377 int ath_rx_tasklet(struct ath_softc *sc, int flush);
378 int ath_rx_input(struct ath_softc *sc,
379 struct ath_node *node,
381 struct ath_recv_status *rx_status,
382 enum ATH_RX_TYPE *status);
383 int _ath_rx_indicate(struct ath_softc *sc,
385 struct ath_recv_status *status,
387 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
388 struct ath_recv_status *status);
394 #define ATH_TXBUF 512
395 /* max number of transmit attempts (tries) */
396 #define ATH_TXMAXTRY 13
397 /* max number of 11n transmit attempts (tries) */
398 #define ATH_11N_TXMAXTRY 10
399 /* max number of tries for management and control frames */
400 #define ATH_MGT_TXMAXTRY 4
401 #define WME_BA_BMP_SIZE 64
402 #define WME_MAX_BA WME_BA_BMP_SIZE
403 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
404 #define TID_TO_WME_AC(_tid) \
405 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
406 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
407 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
411 /* Wireless Multimedia Extension Defines */
412 #define WME_AC_BE 0 /* best effort */
413 #define WME_AC_BK 1 /* background */
414 #define WME_AC_VI 2 /* video */
415 #define WME_AC_VO 3 /* voice */
419 * Data transmit queue state. One of these exists for each
420 * hardware transmit queue. Packets sent to us from above
421 * are assigned to queues based on their priority. Not all
422 * devices support a complete set of hardware transmit queues.
423 * For those devices the array sc_ac2q will map multiple
424 * priorities to fewer hardware queues (typically all to one
428 u32 axq_qnum; /* hardware q number */
429 u32 *axq_link; /* link ptr in last TX desc */
430 struct list_head axq_q; /* transmit queue */
432 unsigned long axq_lockflags; /* intr state when must cli */
433 u32 axq_depth; /* queue depth */
434 u8 axq_aggr_depth; /* aggregates queued */
435 u32 axq_totalqueued; /* total ever queued */
437 bool stopped; /* Is mac80211 queue stopped ? */
438 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
440 /* first desc of the last descriptor that contains CTS */
441 struct ath_desc *axq_lastdsWithCTS;
443 /* final desc of the gating desc that determines whether
444 lastdsWithCTS has been DMA'ed or not */
445 struct ath_desc *axq_gatingds;
447 struct list_head axq_acq;
450 #define AGGR_CLEANUP BIT(1)
451 #define AGGR_ADDBA_COMPLETE BIT(2)
452 #define AGGR_ADDBA_PROGRESS BIT(3)
454 /* per TID aggregate tx state for a destination */
456 struct list_head list; /* round-robin tid entry */
457 struct list_head buf_q; /* pending buffers */
459 struct ath_atx_ac *ac;
460 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
465 int baw_head; /* first un-acked tx buffer */
466 int baw_tail; /* next unused tx buffer slot */
470 int addba_exchangeattempts;
473 /* per access-category aggregate tx state for a destination */
475 int sched; /* dest-ac is scheduled */
476 int qnum; /* H/W queue number associated
478 struct list_head list; /* round-robin txq entry */
479 struct list_head tid_q; /* queue of TIDs with buffers */
482 /* per dest tx state */
484 struct ath_atx_tid tid[WME_NUM_TID];
485 struct ath_atx_ac ac[WME_NUM_AC];
488 /* per-frame tx control block */
489 struct ath_tx_control {
494 /* per frame tx status block */
495 struct ath_xmit_status {
496 int retries; /* number of retries to successufully
497 transmit this frame */
498 int flags; /* status of transmit */
499 #define ATH_TX_ERROR 0x01
500 #define ATH_TX_XRETRY 0x02
501 #define ATH_TX_BAR 0x04
505 int rssi; /* RSSI (noise floor ajusted) */
506 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
507 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
508 int rateieee; /* data rate xmitted (IEEE rate code) */
509 int rateKbps; /* data rate xmitted (Kbps) */
510 int ratecode; /* phy rate code */
511 int flags; /* validity flags */
512 /* if any of ctl,extn chain rssis are valid */
513 #define ATH_TX_CHAIN_RSSI_VALID 0x01
514 /* if extn chain rssis are valid */
515 #define ATH_TX_RSSI_EXTN_VALID 0x02
516 u32 airtime; /* time on air per final tx rate */
519 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
520 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
521 int ath_tx_setup(struct ath_softc *sc, int haltype);
522 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
523 void ath_tx_draintxq(struct ath_softc *sc,
524 struct ath_txq *txq, bool retry_tx);
525 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
526 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
527 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
528 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
529 int ath_tx_init(struct ath_softc *sc, int nbufs);
530 int ath_tx_cleanup(struct ath_softc *sc);
531 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
532 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
533 int ath_txq_update(struct ath_softc *sc, int qnum,
534 struct ath9k_tx_queue_info *q);
535 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
536 struct ath_tx_control *txctl);
537 void ath_tx_tasklet(struct ath_softc *sc);
538 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
539 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
540 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
541 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
542 struct ath_xmit_status *tx_status);
543 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
545 /**********************/
546 /* Node / Aggregation */
547 /**********************/
549 #define ADDBA_EXCHANGE_ATTEMPTS 10
550 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
551 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
552 /* number of delimiters for encryption padding */
553 #define ATH_AGGR_ENCRYPTDELIM 10
554 /* minimum h/w qdepth to be sustained to maximize aggregation */
555 #define ATH_AGGR_MIN_QDEPTH 2
556 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
557 #define IEEE80211_SEQ_SEQ_SHIFT 4
558 #define IEEE80211_SEQ_MAX 4096
559 #define IEEE80211_MIN_AMPDU_BUF 0x8
560 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
562 /* return whether a bit at index _n in bitmap _bm is set
563 * _sz is the size of the bitmap */
564 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
565 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
567 /* return block-ack bitmap index given sequence and starting sequence */
568 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
570 /* returns delimiter padding required given the packet length */
571 #define ATH_AGGR_GET_NDELIM(_len) \
572 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
573 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
575 #define BAW_WITHIN(_start, _bawsz, _seqno) \
576 ((((_seqno) - (_start)) & 4095) < (_bawsz))
578 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
579 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
580 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
581 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
583 enum ATH_AGGR_STATUS {
591 enum ATH_AGGR_CHECK {
594 AGGR_CLEANUP_PROGRESS,
595 AGGR_EXCHANGE_PROGRESS,
599 struct aggr_rifs_param {
600 int param_max_frames;
604 struct ath_rc_series *param_rcs;
607 /* Per-node aggregation state */
608 struct ath_node_aggr {
609 struct ath_atx tx; /* node transmit state */
610 struct ath_arx rx; /* node receive state */
613 /* driver-specific node state */
615 struct ath_softc *an_sc;
616 struct ath_chainmask_sel an_chainmask_sel;
617 struct ath_node_aggr an_aggr;
622 void ath_tx_resume_tid(struct ath_softc *sc,
623 struct ath_atx_tid *tid);
624 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
625 struct ath_node *an, u8 tidno);
626 void ath_tx_aggr_teardown(struct ath_softc *sc,
627 struct ath_node *an, u8 tidno);
628 void ath_rx_aggr_teardown(struct ath_softc *sc,
629 struct ath_node *an, u8 tidno);
630 int ath_rx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
632 int ath_rx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
633 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
635 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
636 void ath_newassoc(struct ath_softc *sc,
637 struct ath_node *node, int isnew, int isuapsd);
638 void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta);
639 void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
641 /*******************/
642 /* Beacon Handling */
643 /*******************/
646 * Regardless of the number of beacons we stagger, (i.e. regardless of the
647 * number of BSSIDs) if a given beacon does not go out even after waiting this
648 * number of beacon intervals, the game's up.
650 #define BSTUCK_THRESH (9 * ATH_BCBUF)
651 #define ATH_BCBUF 4 /* number of beacon buffers */
652 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
653 #define ATH_DEFAULT_BMISS_LIMIT 10
654 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
656 /* beacon configuration */
657 struct ath_beacon_config {
667 } u; /* last received beacon/probe response timestamp of this BSS. */
670 void ath9k_beacon_tasklet(unsigned long data);
671 void ath_beacon_config(struct ath_softc *sc, int if_id);
672 int ath_beaconq_setup(struct ath_hal *ah);
673 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
674 void ath_bstuck_process(struct ath_softc *sc);
675 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
676 void ath_beacon_sync(struct ath_softc *sc, int if_id);
677 void ath_get_beaconconfig(struct ath_softc *sc,
679 struct ath_beacon_config *conf);
685 * Define the scheme that we select MAC address for multiple
686 * BSS on the same radio. The very first VAP will just use the MAC
687 * address from the EEPROM. For the next 3 VAPs, we set the
688 * U/L bit (bit 1) in MAC address, and use the next two bits as the
692 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
693 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
695 /* VAP configuration (from protocol layer) */
696 struct ath_vap_config {
697 u32 av_fixed_rateset;
698 u32 av_fixed_retryset;
701 /* driver-specific vap state */
703 int av_bslot; /* beacon slot index */
704 enum ath9k_opmode av_opmode; /* VAP operational mode */
705 struct ath_buf *av_bcbuf; /* beacon buffer */
706 struct ath_tx_control av_btxctl; /* txctl information for beacon */
707 struct ath_vap_config av_config;/* vap configuration parameters*/
708 struct ath_rate_node *rc_node;
711 /*********************/
712 /* Antenna diversity */
713 /*********************/
715 #define ATH_ANT_DIV_MAX_CFG 2
716 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
717 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
719 enum ATH_ANT_DIV_STATE{
721 ATH_ANT_DIV_SCAN, /* evaluating antenna */
725 struct ath_softc *antdiv_sc;
727 enum ATH_ANT_DIV_STATE antdiv_state;
728 u8 antdiv_num_antcfg;
731 int32_t antdivf_rssitrig;
732 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
733 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
734 u64 antdiv_laststatetsf;
735 u8 antdiv_bssid[ETH_ALEN];
738 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
739 struct ath_softc *sc, int32_t rssitrig);
740 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
743 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
744 void ath_slow_ant_div(struct ath_antdiv *antdiv,
745 struct ieee80211_hdr *wh,
746 struct ath_rx_status *rx_stats);
747 void ath_setdefantenna(void *sc, u32 antenna);
753 /* ANI values for STA only.
754 FIXME: Add appropriate values for AP later */
756 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
757 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
758 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
759 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
763 int16_t sc_noise_floor;
764 unsigned int sc_longcal_timer;
765 unsigned int sc_shortcal_timer;
766 unsigned int sc_resetcal_timer;
767 unsigned int sc_checkani_timer;
768 struct timer_list timer;
771 /********************/
773 /********************/
775 #define ATH_LED_PIN 1
785 struct ath_softc *sc;
786 struct led_classdev led_cdev;
787 enum ath_led_type led_type;
793 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
796 struct rfkill *rfkill;
797 struct delayed_work rfkill_poll;
798 char rfkill_name[32];
801 /********************/
802 /* Main driver core */
803 /********************/
806 * Default cache line size, in bytes.
807 * Used when PCI device not fully initialized by bootrom/BIOS
809 #define DEFAULT_CACHELINE 32
810 #define ATH_DEFAULT_NOISE_FLOOR -95
811 #define ATH_REGCLASSIDS_MAX 10
812 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
813 #define ATH_MAX_SW_RETRIES 10
814 #define ATH_CHAN_MAX 255
815 #define IEEE80211_WEP_NKID 4 /* number of key ids */
816 #define IEEE80211_RATE_VAL 0x7f
818 * The key cache is used for h/w cipher state and also for
819 * tracking station state such as the current tx antenna.
820 * We also setup a mapping table between key cache slot indices
821 * and station state to short-circuit node lookups on rx.
822 * Different parts have different size key caches. We handle
823 * up to ATH_KEYMAX entries (could dynamically allocate state).
825 #define ATH_KEYMAX 128 /* max key cache size we handle */
827 #define ATH_IF_ID_ANY 0xff
828 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
830 #define RSSI_LPF_THRESHOLD -20
831 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
832 #define ATH_RATE_DUMMY_MARKER 0
833 #define ATH_RSSI_LPF_LEN 10
834 #define ATH_RSSI_DUMMY_MARKER 0x127
836 #define ATH_EP_MUL(x, mul) ((x) * (mul))
837 #define ATH_EP_RND(x, mul) \
838 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
839 #define ATH_RSSI_OUT(x) \
840 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
841 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
842 #define ATH_RSSI_IN(x) \
843 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
844 #define ATH_LPF_RSSI(x, y, len) \
845 ((x != ATH_RSSI_DUMMY_MARKER) ? \
846 (((x) * ((len) - 1) + (y)) / (len)) : (y))
847 #define ATH_RSSI_LPF(x, y) do { \
848 if ((y) >= RSSI_LPF_THRESHOLD) \
849 x = ATH_LPF_RSSI((x), \
850 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
867 enum ath9k_ht_macmode tx_chan_width;
871 #define SC_OP_INVALID BIT(0)
872 #define SC_OP_BEACONS BIT(1)
873 #define SC_OP_RXAGGR BIT(2)
874 #define SC_OP_TXAGGR BIT(3)
875 #define SC_OP_CHAINMASK_UPDATE BIT(4)
876 #define SC_OP_FULL_RESET BIT(5)
877 #define SC_OP_NO_RESET BIT(6)
878 #define SC_OP_PREAMBLE_SHORT BIT(7)
879 #define SC_OP_PROTECT_ENABLE BIT(8)
880 #define SC_OP_RXFLUSH BIT(9)
881 #define SC_OP_LED_ASSOCIATED BIT(10)
882 #define SC_OP_RFKILL_REGISTERED BIT(11)
883 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
884 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
887 struct ieee80211_hw *hw;
888 struct pci_dev *pdev;
889 struct tasklet_struct intr_tq;
890 struct tasklet_struct bcon_tasklet;
891 struct ath_config sc_config;
892 struct ath_hal *sc_ah;
893 struct ath_rate_softc *sc_rc;
896 u8 sc_curbssid[ETH_ALEN];
897 u8 sc_myaddr[ETH_ALEN];
898 u8 sc_bssidmask[ETH_ALEN];
902 u32 sc_flags; /* SC_OP_* */
903 unsigned int rx_filter;
907 int sc_slotupdate; /* slot to next advance fsm */
909 int sc_bslot[ATH_BCBUF];
912 enum ath9k_int sc_imask;
913 enum wireless_mode sc_curmode; /* current phy mode */
914 enum PROT_MODE sc_protmode;
916 u8 sc_nbcnvaps; /* # of vaps sending beacons */
917 u16 sc_nvaps; /* # of active virtual ap's */
918 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
921 u8 sc_defant; /* current default antenna */
922 u8 sc_rxotherant; /* rx's on non-default antenna */
924 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
925 struct ath_ht_info sc_ht_info;
926 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
928 #ifdef CONFIG_SLOW_ANT_DIV
929 struct ath_antdiv sc_antdiv;
932 OK, /* no change needed */
933 UPDATE, /* update pending */
934 COMMIT /* beacon sent, commit change */
935 } sc_updateslot; /* slot time update fsm */
938 u32 sc_keymax; /* size of key cache */
939 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
940 u8 sc_splitmic; /* split TKIP MIC keys */
943 struct list_head sc_rxbuf;
944 struct ath_descdma sc_rxdma;
945 int sc_rxbufsize; /* rx size based on mtu */
946 u32 *sc_rxlink; /* link ptr in last RX desc */
949 struct list_head sc_txbuf;
950 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
951 struct ath_descdma sc_txdma;
953 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
954 u16 seq_no; /* TX sequence number */
957 struct ath9k_tx_queue_info sc_beacon_qi;
958 struct ath_descdma sc_bdma;
959 struct ath_txq *sc_cabq;
960 struct list_head sc_bbuf;
963 u32 ast_be_xmit; /* beacons transmitted */
967 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
968 const struct ath9k_rate_table *sc_currates;
969 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
970 u8 sc_protrix; /* protection rate index */
972 u32 rateKbps; /* transfer rate in kbs */
973 u8 ieeerate; /* IEEE rate */
974 } sc_hwmap[256]; /* h/w rate ix mappings */
977 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
978 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
981 spinlock_t sc_rxflushlock;
982 spinlock_t sc_rxbuflock;
983 spinlock_t sc_txbuflock;
984 spinlock_t sc_resetlock;
987 struct ath_led radio_led;
988 struct ath_led assoc_led;
989 struct ath_led tx_led;
990 struct ath_led rx_led;
993 struct ath_rfkill rf_kill;
996 struct ath_ani sc_ani;
999 int ath_init(u16 devid, struct ath_softc *sc);
1000 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1001 void ath_stop(struct ath_softc *sc);
1002 irqreturn_t ath_isr(int irq, void *dev);
1003 int ath_reset(struct ath_softc *sc, bool retry_tx);
1004 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
1006 /*********************/
1007 /* Utility Functions */
1008 /*********************/
1010 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1011 int ath_keyset(struct ath_softc *sc,
1013 struct ath9k_keyval *hk,
1014 const u8 mac[ETH_ALEN]);
1015 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1016 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1017 void ath_setslottime(struct ath_softc *sc);
1018 void ath_update_txpow(struct ath_softc *sc);
1019 int ath_cabq_update(struct ath_softc *);
1020 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);