drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   SDIO support
  12   Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
  13
  14   Some parts of the code in this file are derived from the ipw2200
  15   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  16
  17   This program is free software; you can redistribute it and/or modify
  18   it under the terms of the GNU General Public License as published by
  19   the Free Software Foundation; either version 2 of the License, or
  20   (at your option) any later version.
  21
  22   This program is distributed in the hope that it will be useful,
  23   but WITHOUT ANY WARRANTY; without even the implied warranty of
  24   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25   GNU General Public License for more details.
  26
  27   You should have received a copy of the GNU General Public License
  28   along with this program; see the file COPYING.  If not, write to
  29   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  30   Boston, MA 02110-1301, USA.
  31
  32 */
  33
  34 #include <linux/delay.h>
  35 #include <linux/init.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/if_arp.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/firmware.h>
  40 #include <linux/wireless.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/io.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/slab.h>
  46 #include <asm/unaligned.h>
  47
  48 #include "b43.h"
  49 #include "main.h"
  50 #include "debugfs.h"
  51 #include "phy_common.h"
  52 #include "phy_g.h"
  53 #include "phy_n.h"
  54 #include "dma.h"
  55 #include "pio.h"
  56 #include "sysfs.h"
  57 #include "xmit.h"
  58 #include "lo.h"
  59 #include "pcmcia.h"
  60 #include "sdio.h"
  61 #include <linux/mmc/sdio_func.h>
  62
  63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  64 MODULE_AUTHOR("Martin Langer");
  65 MODULE_AUTHOR("Stefano Brivio");
  66 MODULE_AUTHOR("Michael Buesch");
  67 MODULE_AUTHOR("Gábor Stefanik");
  68 MODULE_LICENSE("GPL");
  69
  70 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
  71 MODULE_FIRMWARE("b43/ucode11.fw");
  72 MODULE_FIRMWARE("b43/ucode13.fw");
  73 MODULE_FIRMWARE("b43/ucode14.fw");
  74 MODULE_FIRMWARE("b43/ucode15.fw");
  75 MODULE_FIRMWARE("b43/ucode5.fw");
  76 MODULE_FIRMWARE("b43/ucode9.fw");
  77
  78 static int modparam_bad_frames_preempt;
  79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  80 MODULE_PARM_DESC(bad_frames_preempt,
  81                  "enable(1) / disable(0) Bad Frames Preemption");
  82
  83 static char modparam_fwpostfix[16];
  84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  85 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  86
  87 static int modparam_hwpctl;
  88 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  89 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  90
  91 static int modparam_nohwcrypt;
  92 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  93 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  94
  95 static int modparam_hwtkip;
  96 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
  97 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
  98
  99 static int modparam_qos = 1;
 100 module_param_named(qos, modparam_qos, int, 0444);
 101 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
 102
 103 static int modparam_btcoex = 1;
 104 module_param_named(btcoex, modparam_btcoex, int, 0444);
 105 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
 106
 107 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
 108 module_param_named(verbose, b43_modparam_verbose, int, 0644);
 109 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
 110
 111 static int b43_modparam_pio = B43_PIO_DEFAULT;
 112 module_param_named(pio, b43_modparam_pio, int, 0644);
 113 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
 114
 115 static const struct ssb_device_id b43_ssb_tbl[] = {
 116         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
 117         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
 118         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
 119         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
 120         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
 121         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
 122         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
 123         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
 124         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
 125         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
 126         SSB_DEVTABLE_END
 127 };
 128
 129 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 130
 131 /* Channel and ratetables are shared for all devices.
 132  * They can't be const, because ieee80211 puts some precalculated
 133  * data in there. This data is the same for all devices, so we don't
 134  * get concurrency issues */
 135 #define RATETAB_ENT(_rateid, _flags) \
 136         {                                                               \
 137                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
 138                 .hw_value       = (_rateid),                            \
 139                 .flags          = (_flags),                             \
 140         }
 141
 142 /*
 143  * NOTE: When changing this, sync with xmit.c's
 144  *       b43_plcp_get_bitrate_idx_* functions!
 145  */
 146 static struct ieee80211_rate __b43_ratetable[] = {
 147         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
 148         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 149         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 150         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 151         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
 152         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
 153         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
 154         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
 155         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
 156         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
 157         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
 158         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
 159 };
 160
 161 #define b43_a_ratetable         (__b43_ratetable + 4)
 162 #define b43_a_ratetable_size    8
 163 #define b43_b_ratetable         (__b43_ratetable + 0)
 164 #define b43_b_ratetable_size    4
 165 #define b43_g_ratetable         (__b43_ratetable + 0)
 166 #define b43_g_ratetable_size    12
 167
 168 #define CHAN4G(_channel, _freq, _flags) {                       \
 169         .band                   = IEEE80211_BAND_2GHZ,          \
 170         .center_freq            = (_freq),                      \
 171         .hw_value               = (_channel),                   \
 172         .flags                  = (_flags),                     \
 173         .max_antenna_gain       = 0,                            \
 174         .max_power              = 30,                           \
 175 }
 176 static struct ieee80211_channel b43_2ghz_chantable[] = {
 177         CHAN4G(1, 2412, 0),
 178         CHAN4G(2, 2417, 0),
 179         CHAN4G(3, 2422, 0),
 180         CHAN4G(4, 2427, 0),
 181         CHAN4G(5, 2432, 0),
 182         CHAN4G(6, 2437, 0),
 183         CHAN4G(7, 2442, 0),
 184         CHAN4G(8, 2447, 0),
 185         CHAN4G(9, 2452, 0),
 186         CHAN4G(10, 2457, 0),
 187         CHAN4G(11, 2462, 0),
 188         CHAN4G(12, 2467, 0),
 189         CHAN4G(13, 2472, 0),
 190         CHAN4G(14, 2484, 0),
 191 };
 192 #undef CHAN4G
 193
 194 #define CHAN5G(_channel, _flags) {                              \
 195         .band                   = IEEE80211_BAND_5GHZ,          \
 196         .center_freq            = 5000 + (5 * (_channel)),      \
 197         .hw_value               = (_channel),                   \
 198         .flags                  = (_flags),                     \
 199         .max_antenna_gain       = 0,                            \
 200         .max_power              = 30,                           \
 201 }
 202 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
 203         CHAN5G(32, 0),          CHAN5G(34, 0),
 204         CHAN5G(36, 0),          CHAN5G(38, 0),
 205         CHAN5G(40, 0),          CHAN5G(42, 0),
 206         CHAN5G(44, 0),          CHAN5G(46, 0),
 207         CHAN5G(48, 0),          CHAN5G(50, 0),
 208         CHAN5G(52, 0),          CHAN5G(54, 0),
 209         CHAN5G(56, 0),          CHAN5G(58, 0),
 210         CHAN5G(60, 0),          CHAN5G(62, 0),
 211         CHAN5G(64, 0),          CHAN5G(66, 0),
 212         CHAN5G(68, 0),          CHAN5G(70, 0),
 213         CHAN5G(72, 0),          CHAN5G(74, 0),
 214         CHAN5G(76, 0),          CHAN5G(78, 0),
 215         CHAN5G(80, 0),          CHAN5G(82, 0),
 216         CHAN5G(84, 0),          CHAN5G(86, 0),
 217         CHAN5G(88, 0),          CHAN5G(90, 0),
 218         CHAN5G(92, 0),          CHAN5G(94, 0),
 219         CHAN5G(96, 0),          CHAN5G(98, 0),
 220         CHAN5G(100, 0),         CHAN5G(102, 0),
 221         CHAN5G(104, 0),         CHAN5G(106, 0),
 222         CHAN5G(108, 0),         CHAN5G(110, 0),
 223         CHAN5G(112, 0),         CHAN5G(114, 0),
 224         CHAN5G(116, 0),         CHAN5G(118, 0),
 225         CHAN5G(120, 0),         CHAN5G(122, 0),
 226         CHAN5G(124, 0),         CHAN5G(126, 0),
 227         CHAN5G(128, 0),         CHAN5G(130, 0),
 228         CHAN5G(132, 0),         CHAN5G(134, 0),
 229         CHAN5G(136, 0),         CHAN5G(138, 0),
 230         CHAN5G(140, 0),         CHAN5G(142, 0),
 231         CHAN5G(144, 0),         CHAN5G(145, 0),
 232         CHAN5G(146, 0),         CHAN5G(147, 0),
 233         CHAN5G(148, 0),         CHAN5G(149, 0),
 234         CHAN5G(150, 0),         CHAN5G(151, 0),
 235         CHAN5G(152, 0),         CHAN5G(153, 0),
 236         CHAN5G(154, 0),         CHAN5G(155, 0),
 237         CHAN5G(156, 0),         CHAN5G(157, 0),
 238         CHAN5G(158, 0),         CHAN5G(159, 0),
 239         CHAN5G(160, 0),         CHAN5G(161, 0),
 240         CHAN5G(162, 0),         CHAN5G(163, 0),
 241         CHAN5G(164, 0),         CHAN5G(165, 0),
 242         CHAN5G(166, 0),         CHAN5G(168, 0),
 243         CHAN5G(170, 0),         CHAN5G(172, 0),
 244         CHAN5G(174, 0),         CHAN5G(176, 0),
 245         CHAN5G(178, 0),         CHAN5G(180, 0),
 246         CHAN5G(182, 0),         CHAN5G(184, 0),
 247         CHAN5G(186, 0),         CHAN5G(188, 0),
 248         CHAN5G(190, 0),         CHAN5G(192, 0),
 249         CHAN5G(194, 0),         CHAN5G(196, 0),
 250         CHAN5G(198, 0),         CHAN5G(200, 0),
 251         CHAN5G(202, 0),         CHAN5G(204, 0),
 252         CHAN5G(206, 0),         CHAN5G(208, 0),
 253         CHAN5G(210, 0),         CHAN5G(212, 0),
 254         CHAN5G(214, 0),         CHAN5G(216, 0),
 255         CHAN5G(218, 0),         CHAN5G(220, 0),
 256         CHAN5G(222, 0),         CHAN5G(224, 0),
 257         CHAN5G(226, 0),         CHAN5G(228, 0),
 258 };
 259
 260 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
 261         CHAN5G(34, 0),          CHAN5G(36, 0),
 262         CHAN5G(38, 0),          CHAN5G(40, 0),
 263         CHAN5G(42, 0),          CHAN5G(44, 0),
 264         CHAN5G(46, 0),          CHAN5G(48, 0),
 265         CHAN5G(52, 0),          CHAN5G(56, 0),
 266         CHAN5G(60, 0),          CHAN5G(64, 0),
 267         CHAN5G(100, 0),         CHAN5G(104, 0),
 268         CHAN5G(108, 0),         CHAN5G(112, 0),
 269         CHAN5G(116, 0),         CHAN5G(120, 0),
 270         CHAN5G(124, 0),         CHAN5G(128, 0),
 271         CHAN5G(132, 0),         CHAN5G(136, 0),
 272         CHAN5G(140, 0),         CHAN5G(149, 0),
 273         CHAN5G(153, 0),         CHAN5G(157, 0),
 274         CHAN5G(161, 0),         CHAN5G(165, 0),
 275         CHAN5G(184, 0),         CHAN5G(188, 0),
 276         CHAN5G(192, 0),         CHAN5G(196, 0),
 277         CHAN5G(200, 0),         CHAN5G(204, 0),
 278         CHAN5G(208, 0),         CHAN5G(212, 0),
 279         CHAN5G(216, 0),
 280 };
 281 #undef CHAN5G
 282
 283 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
 284         .band           = IEEE80211_BAND_5GHZ,
 285         .channels       = b43_5ghz_nphy_chantable,
 286         .n_channels     = ARRAY_SIZE(b43_5ghz_nphy_chantable),
 287         .bitrates       = b43_a_ratetable,
 288         .n_bitrates     = b43_a_ratetable_size,
 289 };
 290
 291 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
 292         .band           = IEEE80211_BAND_5GHZ,
 293         .channels       = b43_5ghz_aphy_chantable,
 294         .n_channels     = ARRAY_SIZE(b43_5ghz_aphy_chantable),
 295         .bitrates       = b43_a_ratetable,
 296         .n_bitrates     = b43_a_ratetable_size,
 297 };
 298
 299 static struct ieee80211_supported_band b43_band_2GHz = {
 300         .band           = IEEE80211_BAND_2GHZ,
 301         .channels       = b43_2ghz_chantable,
 302         .n_channels     = ARRAY_SIZE(b43_2ghz_chantable),
 303         .bitrates       = b43_g_ratetable,
 304         .n_bitrates     = b43_g_ratetable_size,
 305 };
 306
 307 static void b43_wireless_core_exit(struct b43_wldev *dev);
 308 static int b43_wireless_core_init(struct b43_wldev *dev);
 309 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
 310 static int b43_wireless_core_start(struct b43_wldev *dev);
 311
 312 static int b43_ratelimit(struct b43_wl *wl)
 313 {
 314         if (!wl || !wl->current_dev)
 315                 return 1;
 316         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 317                 return 1;
 318         /* We are up and running.
 319          * Ratelimit the messages to avoid DoS over the net. */
 320         return net_ratelimit();
 321 }
 322
 323 void b43info(struct b43_wl *wl, const char *fmt, ...)
 324 {
 325         struct va_format vaf;
 326         va_list args;
 327
 328         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
 329                 return;
 330         if (!b43_ratelimit(wl))
 331                 return;
 332
 333         va_start(args, fmt);
 334
 335         vaf.fmt = fmt;
 336         vaf.va = &args;
 337
 338         printk(KERN_INFO "b43-%s: %pV",
 339                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 340
 341         va_end(args);
 342 }
 343
 344 void b43err(struct b43_wl *wl, const char *fmt, ...)
 345 {
 346         struct va_format vaf;
 347         va_list args;
 348
 349         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
 350                 return;
 351         if (!b43_ratelimit(wl))
 352                 return;
 353
 354         va_start(args, fmt);
 355
 356         vaf.fmt = fmt;
 357         vaf.va = &args;
 358
 359         printk(KERN_ERR "b43-%s ERROR: %pV",
 360                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 361
 362         va_end(args);
 363 }
 364
 365 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 366 {
 367         struct va_format vaf;
 368         va_list args;
 369
 370         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
 371                 return;
 372         if (!b43_ratelimit(wl))
 373                 return;
 374
 375         va_start(args, fmt);
 376
 377         vaf.fmt = fmt;
 378         vaf.va = &args;
 379
 380         printk(KERN_WARNING "b43-%s warning: %pV",
 381                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 382
 383         va_end(args);
 384 }
 385
 386 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 387 {
 388         struct va_format vaf;
 389         va_list args;
 390
 391         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
 392                 return;
 393
 394         va_start(args, fmt);
 395
 396         vaf.fmt = fmt;
 397         vaf.va = &args;
 398
 399         printk(KERN_DEBUG "b43-%s debug: %pV",
 400                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 401
 402         va_end(args);
 403 }
 404
 405 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 406 {
 407         u32 macctl;
 408
 409         B43_WARN_ON(offset % 4 != 0);
 410
 411         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 412         if (macctl & B43_MACCTL_BE)
 413                 val = swab32(val);
 414
 415         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 416         mmiowb();
 417         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 418 }
 419
 420 static inline void b43_shm_control_word(struct b43_wldev *dev,
 421                                         u16 routing, u16 offset)
 422 {
 423         u32 control;
 424
 425         /* "offset" is the WORD offset. */
 426         control = routing;
 427         control <<= 16;
 428         control |= offset;
 429         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 430 }
 431
 432 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 433 {
 434         u32 ret;
 435
 436         if (routing == B43_SHM_SHARED) {
 437                 B43_WARN_ON(offset & 0x0001);
 438                 if (offset & 0x0003) {
 439                         /* Unaligned access */
 440                         b43_shm_control_word(dev, routing, offset >> 2);
 441                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 442                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 443                         ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
 444
 445                         goto out;
 446                 }
 447                 offset >>= 2;
 448         }
 449         b43_shm_control_word(dev, routing, offset);
 450         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 451 out:
 452         return ret;
 453 }
 454
 455 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
 456 {
 457         u16 ret;
 458
 459         if (routing == B43_SHM_SHARED) {
 460                 B43_WARN_ON(offset & 0x0001);
 461                 if (offset & 0x0003) {
 462                         /* Unaligned access */
 463                         b43_shm_control_word(dev, routing, offset >> 2);
 464                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 465
 466                         goto out;
 467                 }
 468                 offset >>= 2;
 469         }
 470         b43_shm_control_word(dev, routing, offset);
 471         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 472 out:
 473         return ret;
 474 }
 475
 476 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 477 {
 478         if (routing == B43_SHM_SHARED) {
 479                 B43_WARN_ON(offset & 0x0001);
 480                 if (offset & 0x0003) {
 481                         /* Unaligned access */
 482                         b43_shm_control_word(dev, routing, offset >> 2);
 483                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 484                                     value & 0xFFFF);
 485                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 486                         b43_write16(dev, B43_MMIO_SHM_DATA,
 487                                     (value >> 16) & 0xFFFF);
 488                         return;
 489                 }
 490                 offset >>= 2;
 491         }
 492         b43_shm_control_word(dev, routing, offset);
 493         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 494 }
 495
 496 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 497 {
 498         if (routing == B43_SHM_SHARED) {
 499                 B43_WARN_ON(offset & 0x0001);
 500                 if (offset & 0x0003) {
 501                         /* Unaligned access */
 502                         b43_shm_control_word(dev, routing, offset >> 2);
 503                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 504                         return;
 505                 }
 506                 offset >>= 2;
 507         }
 508         b43_shm_control_word(dev, routing, offset);
 509         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 510 }
 511
 512 /* Read HostFlags */
 513 u64 b43_hf_read(struct b43_wldev *dev)
 514 {
 515         u64 ret;
 516
 517         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 518         ret <<= 16;
 519         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
 520         ret <<= 16;
 521         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 522
 523         return ret;
 524 }
 525
 526 /* Write HostFlags */
 527 void b43_hf_write(struct b43_wldev *dev, u64 value)
 528 {
 529         u16 lo, mi, hi;
 530
 531         lo = (value & 0x00000000FFFFULL);
 532         mi = (value & 0x0000FFFF0000ULL) >> 16;
 533         hi = (value & 0xFFFF00000000ULL) >> 32;
 534         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
 535         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
 536         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
 537 }
 538
 539 /* Read the firmware capabilities bitmask (Opensource firmware only) */
 540 static u16 b43_fwcapa_read(struct b43_wldev *dev)
 541 {
 542         B43_WARN_ON(!dev->fw.opensource);
 543         return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
 544 }
 545
 546 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
 547 {
 548         u32 low, high;
 549
 550         B43_WARN_ON(dev->dev->id.revision < 3);
 551
 552         /* The hardware guarantees us an atomic read, if we
 553          * read the low register first. */
 554         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 555         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 556
 557         *tsf = high;
 558         *tsf <<= 32;
 559         *tsf |= low;
 560 }
 561
 562 static void b43_time_lock(struct b43_wldev *dev)
 563 {
 564         u32 macctl;
 565
 566         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 567         macctl |= B43_MACCTL_TBTTHOLD;
 568         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 569         /* Commit the write */
 570         b43_read32(dev, B43_MMIO_MACCTL);
 571 }
 572
 573 static void b43_time_unlock(struct b43_wldev *dev)
 574 {
 575         u32 macctl;
 576
 577         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 578         macctl &= ~B43_MACCTL_TBTTHOLD;
 579         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 580         /* Commit the write */
 581         b43_read32(dev, B43_MMIO_MACCTL);
 582 }
 583
 584 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 585 {
 586         u32 low, high;
 587
 588         B43_WARN_ON(dev->dev->id.revision < 3);
 589
 590         low = tsf;
 591         high = (tsf >> 32);
 592         /* The hardware guarantees us an atomic write, if we
 593          * write the low register first. */
 594         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
 595         mmiowb();
 596         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
 597         mmiowb();
 598 }
 599
 600 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 601 {
 602         b43_time_lock(dev);
 603         b43_tsf_write_locked(dev, tsf);
 604         b43_time_unlock(dev);
 605 }
 606
 607 static
 608 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
 609 {
 610         static const u8 zero_addr[ETH_ALEN] = { 0 };
 611         u16 data;
 612
 613         if (!mac)
 614                 mac = zero_addr;
 615
 616         offset |= 0x0020;
 617         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 618
 619         data = mac[0];
 620         data |= mac[1] << 8;
 621         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 622         data = mac[2];
 623         data |= mac[3] << 8;
 624         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 625         data = mac[4];
 626         data |= mac[5] << 8;
 627         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 628 }
 629
 630 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 631 {
 632         const u8 *mac;
 633         const u8 *bssid;
 634         u8 mac_bssid[ETH_ALEN * 2];
 635         int i;
 636         u32 tmp;
 637
 638         bssid = dev->wl->bssid;
 639         mac = dev->wl->mac_addr;
 640
 641         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 642
 643         memcpy(mac_bssid, mac, ETH_ALEN);
 644         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 645
 646         /* Write our MAC address and BSSID to template ram */
 647         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 648                 tmp = (u32) (mac_bssid[i + 0]);
 649                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 650                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 651                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 652                 b43_ram_write(dev, 0x20 + i, tmp);
 653         }
 654 }
 655
 656 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 657 {
 658         b43_write_mac_bssid_templates(dev);
 659         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 660 }
 661
 662 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 663 {
 664         /* slot_time is in usec. */
 665         /* This test used to exit for all but a G PHY. */
 666         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 667                 return;
 668         b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
 669         /* Shared memory location 0x0010 is the slot time and should be
 670          * set to slot_time; however, this register is initially 0 and changing
 671          * the value adversely affects the transmit rate for BCM4311
 672          * devices. Until this behavior is unterstood, delete this step
 673          *
 674          * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 675          */
 676 }
 677
 678 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 679 {
 680         b43_set_slot_time(dev, 9);
 681 }
 682
 683 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 684 {
 685         b43_set_slot_time(dev, 20);
 686 }
 687
 688 /* DummyTransmission function, as documented on
 689  * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
 690  */
 691 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
 692 {
 693         struct b43_phy *phy = &dev->phy;
 694         unsigned int i, max_loop;
 695         u16 value;
 696         u32 buffer[5] = {
 697                 0x00000000,
 698                 0x00D40000,
 699                 0x00000000,
 700                 0x01000000,
 701                 0x00000000,
 702         };
 703
 704         if (ofdm) {
 705                 max_loop = 0x1E;
 706                 buffer[0] = 0x000201CC;
 707         } else {
 708                 max_loop = 0xFA;
 709                 buffer[0] = 0x000B846E;
 710         }
 711
 712         for (i = 0; i < 5; i++)
 713                 b43_ram_write(dev, i * 4, buffer[i]);
 714
 715         b43_write16(dev, 0x0568, 0x0000);
 716         if (dev->dev->id.revision < 11)
 717                 b43_write16(dev, 0x07C0, 0x0000);
 718         else
 719                 b43_write16(dev, 0x07C0, 0x0100);
 720         value = (ofdm ? 0x41 : 0x40);
 721         b43_write16(dev, 0x050C, value);
 722         if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
 723                 b43_write16(dev, 0x0514, 0x1A02);
 724         b43_write16(dev, 0x0508, 0x0000);
 725         b43_write16(dev, 0x050A, 0x0000);
 726         b43_write16(dev, 0x054C, 0x0000);
 727         b43_write16(dev, 0x056A, 0x0014);
 728         b43_write16(dev, 0x0568, 0x0826);
 729         b43_write16(dev, 0x0500, 0x0000);
 730         if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
 731                 //SPEC TODO
 732         }
 733
 734         switch (phy->type) {
 735         case B43_PHYTYPE_N:
 736                 b43_write16(dev, 0x0502, 0x00D0);
 737                 break;
 738         case B43_PHYTYPE_LP:
 739                 b43_write16(dev, 0x0502, 0x0050);
 740                 break;
 741         default:
 742                 b43_write16(dev, 0x0502, 0x0030);
 743         }
 744
 745         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 746                 b43_radio_write16(dev, 0x0051, 0x0017);
 747         for (i = 0x00; i < max_loop; i++) {
 748                 value = b43_read16(dev, 0x050E);
 749                 if (value & 0x0080)
 750                         break;
 751                 udelay(10);
 752         }
 753         for (i = 0x00; i < 0x0A; i++) {
 754                 value = b43_read16(dev, 0x050E);
 755                 if (value & 0x0400)
 756                         break;
 757                 udelay(10);
 758         }
 759         for (i = 0x00; i < 0x19; i++) {
 760                 value = b43_read16(dev, 0x0690);
 761                 if (!(value & 0x0100))
 762                         break;
 763                 udelay(10);
 764         }
 765         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 766                 b43_radio_write16(dev, 0x0051, 0x0037);
 767 }
 768
 769 static void key_write(struct b43_wldev *dev,
 770                       u8 index, u8 algorithm, const u8 *key)
 771 {
 772         unsigned int i;
 773         u32 offset;
 774         u16 value;
 775         u16 kidx;
 776
 777         /* Key index/algo block */
 778         kidx = b43_kidx_to_fw(dev, index);
 779         value = ((kidx << 4) | algorithm);
 780         b43_shm_write16(dev, B43_SHM_SHARED,
 781                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 782
 783         /* Write the key to the Key Table Pointer offset */
 784         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 785         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 786                 value = key[i];
 787                 value |= (u16) (key[i + 1]) << 8;
 788                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 789         }
 790 }
 791
 792 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
 793 {
 794         u32 addrtmp[2] = { 0, 0, };
 795         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 796
 797         if (b43_new_kidx_api(dev))
 798                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 799
 800         B43_WARN_ON(index < pairwise_keys_start);
 801         /* We have four default TX keys and possibly four default RX keys.
 802          * Physical mac 0 is mapped to physical key 4 or 8, depending
 803          * on the firmware version.
 804          * So we must adjust the index here.
 805          */
 806         index -= pairwise_keys_start;
 807         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
 808
 809         if (addr) {
 810                 addrtmp[0] = addr[0];
 811                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 812                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 813                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 814                 addrtmp[1] = addr[4];
 815                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 816         }
 817
 818         /* Receive match transmitter address (RCMTA) mechanism */
 819         b43_shm_write32(dev, B43_SHM_RCMTA,
 820                         (index * 2) + 0, addrtmp[0]);
 821         b43_shm_write16(dev, B43_SHM_RCMTA,
 822                         (index * 2) + 1, addrtmp[1]);
 823 }
 824
 825 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
 826  * When a packet is received, the iv32 is checked.
 827  * - if it doesn't the packet is returned without modification (and software
 828  *   decryption can be done). That's what happen when iv16 wrap.
 829  * - if it does, the rc4 key is computed, and decryption is tried.
 830  *   Either it will success and B43_RX_MAC_DEC is returned,
 831  *   either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
 832  *   and the packet is not usable (it got modified by the ucode).
 833  * So in order to never have B43_RX_MAC_DECERR, we should provide
 834  * a iv32 and phase1key that match. Because we drop packets in case of
 835  * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
 836  * packets will be lost without higher layer knowing (ie no resync possible
 837  * until next wrap).
 838  *
 839  * NOTE : this should support 50 key like RCMTA because
 840  * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
 841  */
 842 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
 843                 u16 *phase1key)
 844 {
 845         unsigned int i;
 846         u32 offset;
 847         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 848
 849         if (!modparam_hwtkip)
 850                 return;
 851
 852         if (b43_new_kidx_api(dev))
 853                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 854
 855         B43_WARN_ON(index < pairwise_keys_start);
 856         /* We have four default TX keys and possibly four default RX keys.
 857          * Physical mac 0 is mapped to physical key 4 or 8, depending
 858          * on the firmware version.
 859          * So we must adjust the index here.
 860          */
 861         index -= pairwise_keys_start;
 862         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
 863
 864         if (b43_debug(dev, B43_DBG_KEYS)) {
 865                 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
 866                                 index, iv32);
 867         }
 868         /* Write the key to the  RX tkip shared mem */
 869         offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
 870         for (i = 0; i < 10; i += 2) {
 871                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
 872                                 phase1key ? phase1key[i / 2] : 0);
 873         }
 874         b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
 875         b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
 876 }
 877
 878 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
 879                                    struct ieee80211_vif *vif,
 880                                    struct ieee80211_key_conf *keyconf,
 881                                    struct ieee80211_sta *sta,
 882                                    u32 iv32, u16 *phase1key)
 883 {
 884         struct b43_wl *wl = hw_to_b43_wl(hw);
 885         struct b43_wldev *dev;
 886         int index = keyconf->hw_key_idx;
 887
 888         if (B43_WARN_ON(!modparam_hwtkip))
 889                 return;
 890
 891         /* This is only called from the RX path through mac80211, where
 892          * our mutex is already locked. */
 893         B43_WARN_ON(!mutex_is_locked(&wl->mutex));
 894         dev = wl->current_dev;
 895         B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
 896
 897         keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
 898
 899         rx_tkip_phase1_write(dev, index, iv32, phase1key);
 900         /* only pairwise TKIP keys are supported right now */
 901         if (WARN_ON(!sta))
 902                 return;
 903         keymac_write(dev, index, sta->addr);
 904 }
 905
 906 static void do_key_write(struct b43_wldev *dev,
 907                          u8 index, u8 algorithm,
 908                          const u8 *key, size_t key_len, const u8 *mac_addr)
 909 {
 910         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 911         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 912
 913         if (b43_new_kidx_api(dev))
 914                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 915
 916         B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
 917         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 918
 919         if (index >= pairwise_keys_start)
 920                 keymac_write(dev, index, NULL); /* First zero out mac. */
 921         if (algorithm == B43_SEC_ALGO_TKIP) {
 922                 /*
 923                  * We should provide an initial iv32, phase1key pair.
 924                  * We could start with iv32=0 and compute the corresponding
 925                  * phase1key, but this means calling ieee80211_get_tkip_key
 926                  * with a fake skb (or export other tkip function).
 927                  * Because we are lazy we hope iv32 won't start with
 928                  * 0xffffffff and let's b43_op_update_tkip_key provide a
 929                  * correct pair.
 930                  */
 931                 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
 932         } else if (index >= pairwise_keys_start) /* clear it */
 933                 rx_tkip_phase1_write(dev, index, 0, NULL);
 934         if (key)
 935                 memcpy(buf, key, key_len);
 936         key_write(dev, index, algorithm, buf);
 937         if (index >= pairwise_keys_start)
 938                 keymac_write(dev, index, mac_addr);
 939
 940         dev->key[index].algorithm = algorithm;
 941 }
 942
 943 static int b43_key_write(struct b43_wldev *dev,
 944                          int index, u8 algorithm,
 945                          const u8 *key, size_t key_len,
 946                          const u8 *mac_addr,
 947                          struct ieee80211_key_conf *keyconf)
 948 {
 949         int i;
 950         int pairwise_keys_start;
 951
 952         /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
 953          *      - Temporal Encryption Key (128 bits)
 954          *      - Temporal Authenticator Tx MIC Key (64 bits)
 955          *      - Temporal Authenticator Rx MIC Key (64 bits)
 956          *
 957          *      Hardware only store TEK
 958          */
 959         if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
 960                 key_len = 16;
 961         if (key_len > B43_SEC_KEYSIZE)
 962                 return -EINVAL;
 963         for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
 964                 /* Check that we don't already have this key. */
 965                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 966         }
 967         if (index < 0) {
 968                 /* Pairwise key. Get an empty slot for the key. */
 969                 if (b43_new_kidx_api(dev))
 970                         pairwise_keys_start = B43_NR_GROUP_KEYS;
 971                 else
 972                         pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 973                 for (i = pairwise_keys_start;
 974                      i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
 975                      i++) {
 976                         B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
 977                         if (!dev->key[i].keyconf) {
 978                                 /* found empty */
 979                                 index = i;
 980                                 break;
 981                         }
 982                 }
 983                 if (index < 0) {
 984                         b43warn(dev->wl, "Out of hardware key memory\n");
 985                         return -ENOSPC;
 986                 }
 987         } else
 988                 B43_WARN_ON(index > 3);
 989
 990         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 991         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 992                 /* Default RX key */
 993                 B43_WARN_ON(mac_addr);
 994                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 995         }
 996         keyconf->hw_key_idx = index;
 997         dev->key[index].keyconf = keyconf;
 998
 999         return 0;
1000 }
1001
1002 static int b43_key_clear(struct b43_wldev *dev, int index)
1003 {
1004         if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1005                 return -EINVAL;
1006         do_key_write(dev, index, B43_SEC_ALGO_NONE,
1007                      NULL, B43_SEC_KEYSIZE, NULL);
1008         if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1010                              NULL, B43_SEC_KEYSIZE, NULL);
1011         }
1012         dev->key[index].keyconf = NULL;
1013
1014         return 0;
1015 }
1016
1017 static void b43_clear_keys(struct b43_wldev *dev)
1018 {
1019         int i, count;
1020
1021         if (b43_new_kidx_api(dev))
1022                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1023         else
1024                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1025         for (i = 0; i < count; i++)
1026                 b43_key_clear(dev, i);
1027 }
1028
1029 static void b43_dump_keymemory(struct b43_wldev *dev)
1030 {
1031         unsigned int i, index, count, offset, pairwise_keys_start;
1032         u8 mac[ETH_ALEN];
1033         u16 algo;
1034         u32 rcmta0;
1035         u16 rcmta1;
1036         u64 hf;
1037         struct b43_key *key;
1038
1039         if (!b43_debug(dev, B43_DBG_KEYS))
1040                 return;
1041
1042         hf = b43_hf_read(dev);
1043         b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
1044                !!(hf & B43_HF_USEDEFKEYS));
1045         if (b43_new_kidx_api(dev)) {
1046                 pairwise_keys_start = B43_NR_GROUP_KEYS;
1047                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1048         } else {
1049                 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1050                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1051         }
1052         for (index = 0; index < count; index++) {
1053                 key = &(dev->key[index]);
1054                 printk(KERN_DEBUG "Key slot %02u: %s",
1055                        index, (key->keyconf == NULL) ? " " : "*");
1056                 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1057                 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1058                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1059                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1060                 }
1061
1062                 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1063                                       B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1064                 printk("   Algo: %04X/%02X", algo, key->algorithm);
1065
1066                 if (index >= pairwise_keys_start) {
1067                         if (key->algorithm == B43_SEC_ALGO_TKIP) {
1068                                 printk("   TKIP: ");
1069                                 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1070                                 for (i = 0; i < 14; i += 2) {
1071                                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1072                                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1073                                 }
1074                         }
1075                         rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1076                                                 ((index - pairwise_keys_start) * 2) + 0);
1077                         rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1078                                                 ((index - pairwise_keys_start) * 2) + 1);
1079                         *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1080                         *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1081                         printk("   MAC: %pM", mac);
1082                 } else
1083                         printk("   DEFAULT KEY");
1084                 printk("\n");
1085         }
1086 }
1087
1088 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1089 {
1090         u32 macctl;
1091         u16 ucstat;
1092         bool hwps;
1093         bool awake;
1094         int i;
1095
1096         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1097                     (ps_flags & B43_PS_DISABLED));
1098         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1099
1100         if (ps_flags & B43_PS_ENABLED) {
1101                 hwps = 1;
1102         } else if (ps_flags & B43_PS_DISABLED) {
1103                 hwps = 0;
1104         } else {
1105                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1106                 //      and thus is not an AP and we are associated, set bit 25
1107         }
1108         if (ps_flags & B43_PS_AWAKE) {
1109                 awake = 1;
1110         } else if (ps_flags & B43_PS_ASLEEP) {
1111                 awake = 0;
1112         } else {
1113                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1114                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
1115                 //      successful, set bit26
1116         }
1117
1118 /* FIXME: For now we force awake-on and hwps-off */
1119         hwps = 0;
1120         awake = 1;
1121
1122         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1123         if (hwps)
1124                 macctl |= B43_MACCTL_HWPS;
1125         else
1126                 macctl &= ~B43_MACCTL_HWPS;
1127         if (awake)
1128                 macctl |= B43_MACCTL_AWAKE;
1129         else
1130                 macctl &= ~B43_MACCTL_AWAKE;
1131         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1132         /* Commit write */
1133         b43_read32(dev, B43_MMIO_MACCTL);
1134         if (awake && dev->dev->id.revision >= 5) {
1135                 /* Wait for the microcode to wake up. */
1136                 for (i = 0; i < 100; i++) {
1137                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1138                                                 B43_SHM_SH_UCODESTAT);
1139                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1140                                 break;
1141                         udelay(10);
1142                 }
1143         }
1144 }
1145
1146 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1147 {
1148         u32 tmslow;
1149         u32 macctl;
1150
1151         flags |= B43_TMSLOW_PHYCLKEN;
1152         flags |= B43_TMSLOW_PHYRESET;
1153         if (dev->phy.type == B43_PHYTYPE_N)
1154                 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1155         ssb_device_enable(dev->dev, flags);
1156         msleep(2);              /* Wait for the PLL to turn on. */
1157
1158         /* Now take the PHY out of Reset again */
1159         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1160         tmslow |= SSB_TMSLOW_FGC;
1161         tmslow &= ~B43_TMSLOW_PHYRESET;
1162         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1163         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1164         msleep(1);
1165         tmslow &= ~SSB_TMSLOW_FGC;
1166         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1167         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1168         msleep(1);
1169
1170         /* Turn Analog ON, but only if we already know the PHY-type.
1171          * This protects against very early setup where we don't know the
1172          * PHY-type, yet. wireless_core_reset will be called once again later,
1173          * when we know the PHY-type. */
1174         if (dev->phy.ops)
1175                 dev->phy.ops->switch_analog(dev, 1);
1176
1177         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1178         macctl &= ~B43_MACCTL_GMODE;
1179         if (flags & B43_TMSLOW_GMODE)
1180                 macctl |= B43_MACCTL_GMODE;
1181         macctl |= B43_MACCTL_IHR_ENABLED;
1182         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1183 }
1184
1185 static void handle_irq_transmit_status(struct b43_wldev *dev)
1186 {
1187         u32 v0, v1;
1188         u16 tmp;
1189         struct b43_txstatus stat;
1190
1191         while (1) {
1192                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1193                 if (!(v0 & 0x00000001))
1194                         break;
1195                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1196
1197                 stat.cookie = (v0 >> 16);
1198                 stat.seq = (v1 & 0x0000FFFF);
1199                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1200                 tmp = (v0 & 0x0000FFFF);
1201                 stat.frame_count = ((tmp & 0xF000) >> 12);
1202                 stat.rts_count = ((tmp & 0x0F00) >> 8);
1203                 stat.supp_reason = ((tmp & 0x001C) >> 2);
1204                 stat.pm_indicated = !!(tmp & 0x0080);
1205                 stat.intermediate = !!(tmp & 0x0040);
1206                 stat.for_ampdu = !!(tmp & 0x0020);
1207                 stat.acked = !!(tmp & 0x0002);
1208
1209                 b43_handle_txstatus(dev, &stat);
1210         }
1211 }
1212
1213 static void drain_txstatus_queue(struct b43_wldev *dev)
1214 {
1215         u32 dummy;
1216
1217         if (dev->dev->id.revision < 5)
1218                 return;
1219         /* Read all entries from the microcode TXstatus FIFO
1220          * and throw them away.
1221          */
1222         while (1) {
1223                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1224                 if (!(dummy & 0x00000001))
1225                         break;
1226                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1227         }
1228 }
1229
1230 static u32 b43_jssi_read(struct b43_wldev *dev)
1231 {
1232         u32 val = 0;
1233
1234         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1235         val <<= 16;
1236         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1237
1238         return val;
1239 }
1240
1241 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1242 {
1243         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1244         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1245 }
1246
1247 static void b43_generate_noise_sample(struct b43_wldev *dev)
1248 {
1249         b43_jssi_write(dev, 0x7F7F7F7F);
1250         b43_write32(dev, B43_MMIO_MACCMD,
1251                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1252 }
1253
1254 static void b43_calculate_link_quality(struct b43_wldev *dev)
1255 {
1256         /* Top half of Link Quality calculation. */
1257
1258         if (dev->phy.type != B43_PHYTYPE_G)
1259                 return;
1260         if (dev->noisecalc.calculation_running)
1261                 return;
1262         dev->noisecalc.calculation_running = 1;
1263         dev->noisecalc.nr_samples = 0;
1264
1265         b43_generate_noise_sample(dev);
1266 }
1267
1268 static void handle_irq_noise(struct b43_wldev *dev)
1269 {
1270         struct b43_phy_g *phy = dev->phy.g;
1271         u16 tmp;
1272         u8 noise[4];
1273         u8 i, j;
1274         s32 average;
1275
1276         /* Bottom half of Link Quality calculation. */
1277
1278         if (dev->phy.type != B43_PHYTYPE_G)
1279                 return;
1280
1281         /* Possible race condition: It might be possible that the user
1282          * changed to a different channel in the meantime since we
1283          * started the calculation. We ignore that fact, since it's
1284          * not really that much of a problem. The background noise is
1285          * an estimation only anyway. Slightly wrong results will get damped
1286          * by the averaging of the 8 sample rounds. Additionally the
1287          * value is shortlived. So it will be replaced by the next noise
1288          * calculation round soon. */
1289
1290         B43_WARN_ON(!dev->noisecalc.calculation_running);
1291         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1292         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1293             noise[2] == 0x7F || noise[3] == 0x7F)
1294                 goto generate_new;
1295
1296         /* Get the noise samples. */
1297         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1298         i = dev->noisecalc.nr_samples;
1299         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1300         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1301         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1302         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1303         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1304         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1305         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1306         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1307         dev->noisecalc.nr_samples++;
1308         if (dev->noisecalc.nr_samples == 8) {
1309                 /* Calculate the Link Quality by the noise samples. */
1310                 average = 0;
1311                 for (i = 0; i < 8; i++) {
1312                         for (j = 0; j < 4; j++)
1313                                 average += dev->noisecalc.samples[i][j];
1314                 }
1315                 average /= (8 * 4);
1316                 average *= 125;
1317                 average += 64;
1318                 average /= 128;
1319                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1320                 tmp = (tmp / 128) & 0x1F;
1321                 if (tmp >= 8)
1322                         average += 2;
1323                 else
1324                         average -= 25;
1325                 if (tmp == 8)
1326                         average -= 72;
1327                 else
1328                         average -= 48;
1329
1330                 dev->stats.link_noise = average;
1331                 dev->noisecalc.calculation_running = 0;
1332                 return;
1333         }
1334 generate_new:
1335         b43_generate_noise_sample(dev);
1336 }
1337
1338 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1339 {
1340         if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1341                 ///TODO: PS TBTT
1342         } else {
1343                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1344                         b43_power_saving_ctl_bits(dev, 0);
1345         }
1346         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1347                 dev->dfq_valid = 1;
1348 }
1349
1350 static void handle_irq_atim_end(struct b43_wldev *dev)
1351 {
1352         if (dev->dfq_valid) {
1353                 b43_write32(dev, B43_MMIO_MACCMD,
1354                             b43_read32(dev, B43_MMIO_MACCMD)
1355                             | B43_MACCMD_DFQ_VALID);
1356                 dev->dfq_valid = 0;
1357         }
1358 }
1359
1360 static void handle_irq_pmq(struct b43_wldev *dev)
1361 {
1362         u32 tmp;
1363
1364         //TODO: AP mode.
1365
1366         while (1) {
1367                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1368                 if (!(tmp & 0x00000008))
1369                         break;
1370         }
1371         /* 16bit write is odd, but correct. */
1372         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1373 }
1374
1375 static void b43_write_template_common(struct b43_wldev *dev,
1376                                       const u8 *data, u16 size,
1377                                       u16 ram_offset,
1378                                       u16 shm_size_offset, u8 rate)
1379 {
1380         u32 i, tmp;
1381         struct b43_plcp_hdr4 plcp;
1382
1383         plcp.data = 0;
1384         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1385         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1386         ram_offset += sizeof(u32);
1387         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1388          * So leave the first two bytes of the next write blank.
1389          */
1390         tmp = (u32) (data[0]) << 16;
1391         tmp |= (u32) (data[1]) << 24;
1392         b43_ram_write(dev, ram_offset, tmp);
1393         ram_offset += sizeof(u32);
1394         for (i = 2; i < size; i += sizeof(u32)) {
1395                 tmp = (u32) (data[i + 0]);
1396                 if (i + 1 < size)
1397                         tmp |= (u32) (data[i + 1]) << 8;
1398                 if (i + 2 < size)
1399                         tmp |= (u32) (data[i + 2]) << 16;
1400                 if (i + 3 < size)
1401                         tmp |= (u32) (data[i + 3]) << 24;
1402                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1403         }
1404         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1405                         size + sizeof(struct b43_plcp_hdr6));
1406 }
1407
1408 /* Check if the use of the antenna that ieee80211 told us to
1409  * use is possible. This will fall back to DEFAULT.
1410  * "antenna_nr" is the antenna identifier we got from ieee80211. */
1411 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1412                                   u8 antenna_nr)
1413 {
1414         u8 antenna_mask;
1415
1416         if (antenna_nr == 0) {
1417                 /* Zero means "use default antenna". That's always OK. */
1418                 return 0;
1419         }
1420
1421         /* Get the mask of available antennas. */
1422         if (dev->phy.gmode)
1423                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1424         else
1425                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1426
1427         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1428                 /* This antenna is not available. Fall back to default. */
1429                 return 0;
1430         }
1431
1432         return antenna_nr;
1433 }
1434
1435 /* Convert a b43 antenna number value to the PHY TX control value. */
1436 static u16 b43_antenna_to_phyctl(int antenna)
1437 {
1438         switch (antenna) {
1439         case B43_ANTENNA0:
1440                 return B43_TXH_PHY_ANT0;
1441         case B43_ANTENNA1:
1442                 return B43_TXH_PHY_ANT1;
1443         case B43_ANTENNA2:
1444                 return B43_TXH_PHY_ANT2;
1445         case B43_ANTENNA3:
1446                 return B43_TXH_PHY_ANT3;
1447         case B43_ANTENNA_AUTO0:
1448         case B43_ANTENNA_AUTO1:
1449                 return B43_TXH_PHY_ANT01AUTO;
1450         }
1451         B43_WARN_ON(1);
1452         return 0;
1453 }
1454
1455 static void b43_write_beacon_template(struct b43_wldev *dev,
1456                                       u16 ram_offset,
1457                                       u16 shm_size_offset)
1458 {
1459         unsigned int i, len, variable_len;
1460         const struct ieee80211_mgmt *bcn;
1461         const u8 *ie;
1462         bool tim_found = 0;
1463         unsigned int rate;
1464         u16 ctl;
1465         int antenna;
1466         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1467
1468         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1469         len = min((size_t) dev->wl->current_beacon->len,
1470                   0x200 - sizeof(struct b43_plcp_hdr6));
1471         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1472
1473         b43_write_template_common(dev, (const u8 *)bcn,
1474                                   len, ram_offset, shm_size_offset, rate);
1475
1476         /* Write the PHY TX control parameters. */
1477         antenna = B43_ANTENNA_DEFAULT;
1478         antenna = b43_antenna_to_phyctl(antenna);
1479         ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1480         /* We can't send beacons with short preamble. Would get PHY errors. */
1481         ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1482         ctl &= ~B43_TXH_PHY_ANT;
1483         ctl &= ~B43_TXH_PHY_ENC;
1484         ctl |= antenna;
1485         if (b43_is_cck_rate(rate))
1486                 ctl |= B43_TXH_PHY_ENC_CCK;
1487         else
1488                 ctl |= B43_TXH_PHY_ENC_OFDM;
1489         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1490
1491         /* Find the position of the TIM and the DTIM_period value
1492          * and write them to SHM. */
1493         ie = bcn->u.beacon.variable;
1494         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1495         for (i = 0; i < variable_len - 2; ) {
1496                 uint8_t ie_id, ie_len;
1497
1498                 ie_id = ie[i];
1499                 ie_len = ie[i + 1];
1500                 if (ie_id == 5) {
1501                         u16 tim_position;
1502                         u16 dtim_period;
1503                         /* This is the TIM Information Element */
1504
1505                         /* Check whether the ie_len is in the beacon data range. */
1506                         if (variable_len < ie_len + 2 + i)
1507                                 break;
1508                         /* A valid TIM is at least 4 bytes long. */
1509                         if (ie_len < 4)
1510                                 break;
1511                         tim_found = 1;
1512
1513                         tim_position = sizeof(struct b43_plcp_hdr6);
1514                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1515                         tim_position += i;
1516
1517                         dtim_period = ie[i + 3];
1518
1519                         b43_shm_write16(dev, B43_SHM_SHARED,
1520                                         B43_SHM_SH_TIMBPOS, tim_position);
1521                         b43_shm_write16(dev, B43_SHM_SHARED,
1522                                         B43_SHM_SH_DTIMPER, dtim_period);
1523                         break;
1524                 }
1525                 i += ie_len + 2;
1526         }
1527         if (!tim_found) {
1528                 /*
1529                  * If ucode wants to modify TIM do it behind the beacon, this
1530                  * will happen, for example, when doing mesh networking.
1531                  */
1532                 b43_shm_write16(dev, B43_SHM_SHARED,
1533                                 B43_SHM_SH_TIMBPOS,
1534                                 len + sizeof(struct b43_plcp_hdr6));
1535                 b43_shm_write16(dev, B43_SHM_SHARED,
1536                                 B43_SHM_SH_DTIMPER, 0);
1537         }
1538         b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1539 }
1540
1541 static void b43_upload_beacon0(struct b43_wldev *dev)
1542 {
1543         struct b43_wl *wl = dev->wl;
1544
1545         if (wl->beacon0_uploaded)
1546                 return;
1547         b43_write_beacon_template(dev, 0x68, 0x18);
1548         wl->beacon0_uploaded = 1;
1549 }
1550
1551 static void b43_upload_beacon1(struct b43_wldev *dev)
1552 {
1553         struct b43_wl *wl = dev->wl;
1554
1555         if (wl->beacon1_uploaded)
1556                 return;
1557         b43_write_beacon_template(dev, 0x468, 0x1A);
1558         wl->beacon1_uploaded = 1;
1559 }
1560
1561 static void handle_irq_beacon(struct b43_wldev *dev)
1562 {
1563         struct b43_wl *wl = dev->wl;
1564         u32 cmd, beacon0_valid, beacon1_valid;
1565
1566         if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1567             !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1568                 return;
1569
1570         /* This is the bottom half of the asynchronous beacon update. */
1571
1572         /* Ignore interrupt in the future. */
1573         dev->irq_mask &= ~B43_IRQ_BEACON;
1574
1575         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1576         beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1577         beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1578
1579         /* Schedule interrupt manually, if busy. */
1580         if (beacon0_valid && beacon1_valid) {
1581                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1582                 dev->irq_mask |= B43_IRQ_BEACON;
1583                 return;
1584         }
1585
1586         if (unlikely(wl->beacon_templates_virgin)) {
1587                 /* We never uploaded a beacon before.
1588                  * Upload both templates now, but only mark one valid. */
1589                 wl->beacon_templates_virgin = 0;
1590                 b43_upload_beacon0(dev);
1591                 b43_upload_beacon1(dev);
1592                 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1593                 cmd |= B43_MACCMD_BEACON0_VALID;
1594                 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1595         } else {
1596                 if (!beacon0_valid) {
1597                         b43_upload_beacon0(dev);
1598                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1599                         cmd |= B43_MACCMD_BEACON0_VALID;
1600                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1601                 } else if (!beacon1_valid) {
1602                         b43_upload_beacon1(dev);
1603                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1604                         cmd |= B43_MACCMD_BEACON1_VALID;
1605                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1606                 }
1607         }
1608 }
1609
1610 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1611 {
1612         u32 old_irq_mask = dev->irq_mask;
1613
1614         /* update beacon right away or defer to irq */
1615         handle_irq_beacon(dev);
1616         if (old_irq_mask != dev->irq_mask) {
1617                 /* The handler updated the IRQ mask. */
1618                 B43_WARN_ON(!dev->irq_mask);
1619                 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1620                         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1621                 } else {
1622                         /* Device interrupts are currently disabled. That means
1623                          * we just ran the hardirq handler and scheduled the
1624                          * IRQ thread. The thread will write the IRQ mask when
1625                          * it finished, so there's nothing to do here. Writing
1626                          * the mask _here_ would incorrectly re-enable IRQs. */
1627                 }
1628         }
1629 }
1630
1631 static void b43_beacon_update_trigger_work(struct work_struct *work)
1632 {
1633         struct b43_wl *wl = container_of(work, struct b43_wl,
1634                                          beacon_update_trigger);
1635         struct b43_wldev *dev;
1636
1637         mutex_lock(&wl->mutex);
1638         dev = wl->current_dev;
1639         if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1640                 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1641                         /* wl->mutex is enough. */
1642                         b43_do_beacon_update_trigger_work(dev);
1643                         mmiowb();
1644                 } else {
1645                         spin_lock_irq(&wl->hardirq_lock);
1646                         b43_do_beacon_update_trigger_work(dev);
1647                         mmiowb();
1648                         spin_unlock_irq(&wl->hardirq_lock);
1649                 }
1650         }
1651         mutex_unlock(&wl->mutex);
1652 }
1653
1654 /* Asynchronously update the packet templates in template RAM.
1655  * Locking: Requires wl->mutex to be locked. */
1656 static void b43_update_templates(struct b43_wl *wl)
1657 {
1658         struct sk_buff *beacon;
1659
1660         /* This is the top half of the ansynchronous beacon update.
1661          * The bottom half is the beacon IRQ.
1662          * Beacon update must be asynchronous to avoid sending an
1663          * invalid beacon. This can happen for example, if the firmware
1664          * transmits a beacon while we are updating it. */
1665
1666         /* We could modify the existing beacon and set the aid bit in
1667          * the TIM field, but that would probably require resizing and
1668          * moving of data within the beacon template.
1669          * Simply request a new beacon and let mac80211 do the hard work. */
1670         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1671         if (unlikely(!beacon))
1672                 return;
1673
1674         if (wl->current_beacon)
1675                 dev_kfree_skb_any(wl->current_beacon);
1676         wl->current_beacon = beacon;
1677         wl->beacon0_uploaded = 0;
1678         wl->beacon1_uploaded = 0;
1679         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1680 }
1681
1682 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1683 {
1684         b43_time_lock(dev);
1685         if (dev->dev->id.revision >= 3) {
1686                 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1687                 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1688         } else {
1689                 b43_write16(dev, 0x606, (beacon_int >> 6));
1690                 b43_write16(dev, 0x610, beacon_int);
1691         }
1692         b43_time_unlock(dev);
1693         b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1694 }
1695
1696 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1697 {
1698         u16 reason;
1699
1700         /* Read the register that contains the reason code for the panic. */
1701         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1702         b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1703
1704         switch (reason) {
1705         default:
1706                 b43dbg(dev->wl, "The panic reason is unknown.\n");
1707                 /* fallthrough */
1708         case B43_FWPANIC_DIE:
1709                 /* Do not restart the controller or firmware.
1710                  * The device is nonfunctional from now on.
1711                  * Restarting would result in this panic to trigger again,
1712                  * so we avoid that recursion. */
1713                 break;
1714         case B43_FWPANIC_RESTART:
1715                 b43_controller_restart(dev, "Microcode panic");
1716                 break;
1717         }
1718 }
1719
1720 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1721 {
1722         unsigned int i, cnt;
1723         u16 reason, marker_id, marker_line;
1724         __le16 *buf;
1725
1726         /* The proprietary firmware doesn't have this IRQ. */
1727         if (!dev->fw.opensource)
1728                 return;
1729
1730         /* Read the register that contains the reason code for this IRQ. */
1731         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1732
1733         switch (reason) {
1734         case B43_DEBUGIRQ_PANIC:
1735                 b43_handle_firmware_panic(dev);
1736                 break;
1737         case B43_DEBUGIRQ_DUMP_SHM:
1738                 if (!B43_DEBUG)
1739                         break; /* Only with driver debugging enabled. */
1740                 buf = kmalloc(4096, GFP_ATOMIC);
1741                 if (!buf) {
1742                         b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1743                         goto out;
1744                 }
1745                 for (i = 0; i < 4096; i += 2) {
1746                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1747                         buf[i / 2] = cpu_to_le16(tmp);
1748                 }
1749                 b43info(dev->wl, "Shared memory dump:\n");
1750                 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1751                                16, 2, buf, 4096, 1);
1752                 kfree(buf);
1753                 break;
1754         case B43_DEBUGIRQ_DUMP_REGS:
1755                 if (!B43_DEBUG)
1756                         break; /* Only with driver debugging enabled. */
1757                 b43info(dev->wl, "Microcode register dump:\n");
1758                 for (i = 0, cnt = 0; i < 64; i++) {
1759                         u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1760                         if (cnt == 0)
1761                                 printk(KERN_INFO);
1762                         printk("r%02u: 0x%04X  ", i, tmp);
1763                         cnt++;
1764                         if (cnt == 6) {
1765                                 printk("\n");
1766                                 cnt = 0;
1767                         }
1768                 }
1769                 printk("\n");
1770                 break;
1771         case B43_DEBUGIRQ_MARKER:
1772                 if (!B43_DEBUG)
1773                         break; /* Only with driver debugging enabled. */
1774                 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1775                                            B43_MARKER_ID_REG);
1776                 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1777                                              B43_MARKER_LINE_REG);
1778                 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1779                         "at line number %u\n",
1780                         marker_id, marker_line);
1781                 break;
1782         default:
1783                 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1784                        reason);
1785         }
1786 out:
1787         /* Acknowledge the debug-IRQ, so the firmware can continue. */
1788         b43_shm_write16(dev, B43_SHM_SCRATCH,
1789                         B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1790 }
1791
1792 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1793 {
1794         u32 reason;
1795         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1796         u32 merged_dma_reason = 0;
1797         int i;
1798
1799         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1800                 return;
1801
1802         reason = dev->irq_reason;
1803         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1804                 dma_reason[i] = dev->dma_reason[i];
1805                 merged_dma_reason |= dma_reason[i];
1806         }
1807
1808         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1809                 b43err(dev->wl, "MAC transmission error\n");
1810
1811         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1812                 b43err(dev->wl, "PHY transmission error\n");
1813                 rmb();
1814                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1815                         atomic_set(&dev->phy.txerr_cnt,
1816                                    B43_PHY_TX_BADNESS_LIMIT);
1817                         b43err(dev->wl, "Too many PHY TX errors, "
1818                                         "restarting the controller\n");
1819                         b43_controller_restart(dev, "PHY TX errors");
1820                 }
1821         }
1822
1823         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1824                                           B43_DMAIRQ_NONFATALMASK))) {
1825                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1826                         b43err(dev->wl, "Fatal DMA error: "
1827                                "0x%08X, 0x%08X, 0x%08X, "
1828                                "0x%08X, 0x%08X, 0x%08X\n",
1829                                dma_reason[0], dma_reason[1],
1830                                dma_reason[2], dma_reason[3],
1831                                dma_reason[4], dma_reason[5]);
1832                         b43err(dev->wl, "This device does not support DMA "
1833                                "on your system. It will now be switched to PIO.\n");
1834                         /* Fall back to PIO transfers if we get fatal DMA errors! */
1835                         dev->use_pio = 1;
1836                         b43_controller_restart(dev, "DMA error");
1837                         return;
1838                 }
1839                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1840                         b43err(dev->wl, "DMA error: "
1841                                "0x%08X, 0x%08X, 0x%08X, "
1842                                "0x%08X, 0x%08X, 0x%08X\n",
1843                                dma_reason[0], dma_reason[1],
1844                                dma_reason[2], dma_reason[3],
1845                                dma_reason[4], dma_reason[5]);
1846                 }
1847         }
1848
1849         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1850                 handle_irq_ucode_debug(dev);
1851         if (reason & B43_IRQ_TBTT_INDI)
1852                 handle_irq_tbtt_indication(dev);
1853         if (reason & B43_IRQ_ATIM_END)
1854                 handle_irq_atim_end(dev);
1855         if (reason & B43_IRQ_BEACON)
1856                 handle_irq_beacon(dev);
1857         if (reason & B43_IRQ_PMQ)
1858                 handle_irq_pmq(dev);
1859         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1860                 ;/* TODO */
1861         if (reason & B43_IRQ_NOISESAMPLE_OK)
1862                 handle_irq_noise(dev);
1863
1864         /* Check the DMA reason registers for received data. */
1865         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1866                 if (b43_using_pio_transfers(dev))
1867                         b43_pio_rx(dev->pio.rx_queue);
1868                 else
1869                         b43_dma_rx(dev->dma.rx_ring);
1870         }
1871         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1872         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1873         B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1874         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1875         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1876
1877         if (reason & B43_IRQ_TX_OK)
1878                 handle_irq_transmit_status(dev);
1879
1880         /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1881         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1882
1883 #if B43_DEBUG
1884         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1885                 dev->irq_count++;
1886                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1887                         if (reason & (1 << i))
1888                                 dev->irq_bit_count[i]++;
1889                 }
1890         }
1891 #endif
1892 }
1893
1894 /* Interrupt thread handler. Handles device interrupts in thread context. */
1895 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1896 {
1897         struct b43_wldev *dev = dev_id;
1898
1899         mutex_lock(&dev->wl->mutex);
1900         b43_do_interrupt_thread(dev);
1901         mmiowb();
1902         mutex_unlock(&dev->wl->mutex);
1903
1904         return IRQ_HANDLED;
1905 }
1906
1907 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1908 {
1909         u32 reason;
1910
1911         /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1912          * On SDIO, this runs under wl->mutex. */
1913
1914         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1915         if (reason == 0xffffffff)       /* shared IRQ */
1916                 return IRQ_NONE;
1917         reason &= dev->irq_mask;
1918         if (!reason)
1919                 return IRQ_HANDLED;
1920
1921         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1922             & 0x0001DC00;
1923         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1924             & 0x0000DC00;
1925         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1926             & 0x0000DC00;
1927         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1928             & 0x0001DC00;
1929         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1930             & 0x0000DC00;
1931 /* Unused ring
1932         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1933             & 0x0000DC00;
1934 */
1935
1936         /* ACK the interrupt. */
1937         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1938         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1939         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1940         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1941         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1942         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1943 /* Unused ring
1944         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1945 */
1946
1947         /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1948         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1949         /* Save the reason bitmasks for the IRQ thread handler. */
1950         dev->irq_reason = reason;
1951
1952         return IRQ_WAKE_THREAD;
1953 }
1954
1955 /* Interrupt handler top-half. This runs with interrupts disabled. */
1956 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1957 {
1958         struct b43_wldev *dev = dev_id;
1959         irqreturn_t ret;
1960
1961         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1962                 return IRQ_NONE;
1963
1964         spin_lock(&dev->wl->hardirq_lock);
1965         ret = b43_do_interrupt(dev);
1966         mmiowb();
1967         spin_unlock(&dev->wl->hardirq_lock);
1968
1969         return ret;
1970 }
1971
1972 /* SDIO interrupt handler. This runs in process context. */
1973 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1974 {
1975         struct b43_wl *wl = dev->wl;
1976         irqreturn_t ret;
1977
1978         mutex_lock(&wl->mutex);
1979
1980         ret = b43_do_interrupt(dev);
1981         if (ret == IRQ_WAKE_THREAD)
1982                 b43_do_interrupt_thread(dev);
1983
1984         mutex_unlock(&wl->mutex);
1985 }
1986
1987 void b43_do_release_fw(struct b43_firmware_file *fw)
1988 {
1989         release_firmware(fw->data);
1990         fw->data = NULL;
1991         fw->filename = NULL;
1992 }
1993
1994 static void b43_release_firmware(struct b43_wldev *dev)
1995 {
1996         b43_do_release_fw(&dev->fw.ucode);
1997         b43_do_release_fw(&dev->fw.pcm);
1998         b43_do_release_fw(&dev->fw.initvals);
1999         b43_do_release_fw(&dev->fw.initvals_band);
2000 }
2001
2002 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2003 {
2004         const char text[] =
2005                 "You must go to " \
2006                 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2007                 "and download the correct firmware for this driver version. " \
2008                 "Please carefully read all instructions on this website.\n";
2009
2010         if (error)
2011                 b43err(wl, text);
2012         else
2013                 b43warn(wl, text);
2014 }
2015
2016 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2017                       const char *name,
2018                       struct b43_firmware_file *fw)
2019 {
2020         const struct firmware *blob;
2021         struct b43_fw_header *hdr;
2022         u32 size;
2023         int err;
2024
2025         if (!name) {
2026                 /* Don't fetch anything. Free possibly cached firmware. */
2027                 /* FIXME: We should probably keep it anyway, to save some headache
2028                  * on suspend/resume with multiband devices. */
2029                 b43_do_release_fw(fw);
2030                 return 0;
2031         }
2032         if (fw->filename) {
2033                 if ((fw->type == ctx->req_type) &&
2034                     (strcmp(fw->filename, name) == 0))
2035                         return 0; /* Already have this fw. */
2036                 /* Free the cached firmware first. */
2037                 /* FIXME: We should probably do this later after we successfully
2038                  * got the new fw. This could reduce headache with multiband devices.
2039                  * We could also redesign this to cache the firmware for all possible
2040                  * bands all the time. */
2041                 b43_do_release_fw(fw);
2042         }
2043
2044         switch (ctx->req_type) {
2045         case B43_FWTYPE_PROPRIETARY:
2046                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2047                          "b43%s/%s.fw",
2048                          modparam_fwpostfix, name);
2049                 break;
2050         case B43_FWTYPE_OPENSOURCE:
2051                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2052                          "b43-open%s/%s.fw",
2053                          modparam_fwpostfix, name);
2054                 break;
2055         default:
2056                 B43_WARN_ON(1);
2057                 return -ENOSYS;
2058         }
2059         err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2060         if (err == -ENOENT) {
2061                 snprintf(ctx->errors[ctx->req_type],
2062                          sizeof(ctx->errors[ctx->req_type]),
2063                          "Firmware file \"%s\" not found\n", ctx->fwname);
2064                 return err;
2065         } else if (err) {
2066                 snprintf(ctx->errors[ctx->req_type],
2067                          sizeof(ctx->errors[ctx->req_type]),
2068                          "Firmware file \"%s\" request failed (err=%d)\n",
2069                          ctx->fwname, err);
2070                 return err;
2071         }
2072         if (blob->size < sizeof(struct b43_fw_header))
2073                 goto err_format;
2074         hdr = (struct b43_fw_header *)(blob->data);
2075         switch (hdr->type) {
2076         case B43_FW_TYPE_UCODE:
2077         case B43_FW_TYPE_PCM:
2078                 size = be32_to_cpu(hdr->size);
2079                 if (size != blob->size - sizeof(struct b43_fw_header))
2080                         goto err_format;
2081                 /* fallthrough */
2082         case B43_FW_TYPE_IV:
2083                 if (hdr->ver != 1)
2084                         goto err_format;
2085                 break;
2086         default:
2087                 goto err_format;
2088         }
2089
2090         fw->data = blob;
2091         fw->filename = name;
2092         fw->type = ctx->req_type;
2093
2094         return 0;
2095
2096 err_format:
2097         snprintf(ctx->errors[ctx->req_type],
2098                  sizeof(ctx->errors[ctx->req_type]),
2099                  "Firmware file \"%s\" format error.\n", ctx->fwname);
2100         release_firmware(blob);
2101
2102         return -EPROTO;
2103 }
2104
2105 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2106 {
2107         struct b43_wldev *dev = ctx->dev;
2108         struct b43_firmware *fw = &ctx->dev->fw;
2109         const u8 rev = ctx->dev->dev->id.revision;
2110         const char *filename;
2111         u32 tmshigh;
2112         int err;
2113
2114         /* Get microcode */
2115         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2116         if ((rev >= 5) && (rev <= 10))
2117                 filename = "ucode5";
2118         else if ((rev >= 11) && (rev <= 12))
2119                 filename = "ucode11";
2120         else if (rev == 13)
2121                 filename = "ucode13";
2122         else if (rev == 14)
2123                 filename = "ucode14";
2124         else if (rev >= 15)
2125                 filename = "ucode15";
2126         else
2127                 goto err_no_ucode;
2128         err = b43_do_request_fw(ctx, filename, &fw->ucode);
2129         if (err)
2130                 goto err_load;
2131
2132         /* Get PCM code */
2133         if ((rev >= 5) && (rev <= 10))
2134                 filename = "pcm5";
2135         else if (rev >= 11)
2136                 filename = NULL;
2137         else
2138                 goto err_no_pcm;
2139         fw->pcm_request_failed = 0;
2140         err = b43_do_request_fw(ctx, filename, &fw->pcm);
2141         if (err == -ENOENT) {
2142                 /* We did not find a PCM file? Not fatal, but
2143                  * core rev <= 10 must do without hwcrypto then. */
2144                 fw->pcm_request_failed = 1;
2145         } else if (err)
2146                 goto err_load;
2147
2148         /* Get initvals */
2149         switch (dev->phy.type) {
2150         case B43_PHYTYPE_A:
2151                 if ((rev >= 5) && (rev <= 10)) {
2152                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2153                                 filename = "a0g1initvals5";
2154                         else
2155                                 filename = "a0g0initvals5";
2156                 } else
2157                         goto err_no_initvals;
2158                 break;
2159         case B43_PHYTYPE_G:
2160                 if ((rev >= 5) && (rev <= 10))
2161                         filename = "b0g0initvals5";
2162                 else if (rev >= 13)
2163                         filename = "b0g0initvals13";
2164                 else
2165                         goto err_no_initvals;
2166                 break;
2167         case B43_PHYTYPE_N:
2168                 if ((rev >= 11) && (rev <= 12))
2169                         filename = "n0initvals11";
2170                 else
2171                         goto err_no_initvals;
2172                 break;
2173         case B43_PHYTYPE_LP:
2174                 if (rev == 13)
2175                         filename = "lp0initvals13";
2176                 else if (rev == 14)
2177                         filename = "lp0initvals14";
2178                 else if (rev >= 15)
2179                         filename = "lp0initvals15";
2180                 else
2181                         goto err_no_initvals;
2182                 break;
2183         default:
2184                 goto err_no_initvals;
2185         }
2186         err = b43_do_request_fw(ctx, filename, &fw->initvals);
2187         if (err)
2188                 goto err_load;
2189
2190         /* Get bandswitch initvals */
2191         switch (dev->phy.type) {
2192         case B43_PHYTYPE_A:
2193                 if ((rev >= 5) && (rev <= 10)) {
2194                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2195                                 filename = "a0g1bsinitvals5";
2196                         else
2197                                 filename = "a0g0bsinitvals5";
2198                 } else if (rev >= 11)
2199                         filename = NULL;
2200                 else
2201                         goto err_no_initvals;
2202                 break;
2203         case B43_PHYTYPE_G:
2204                 if ((rev >= 5) && (rev <= 10))
2205                         filename = "b0g0bsinitvals5";
2206                 else if (rev >= 11)
2207                         filename = NULL;
2208                 else
2209                         goto err_no_initvals;
2210                 break;
2211         case B43_PHYTYPE_N:
2212                 if ((rev >= 11) && (rev <= 12))
2213                         filename = "n0bsinitvals11";
2214                 else
2215                         goto err_no_initvals;
2216                 break;
2217         case B43_PHYTYPE_LP:
2218                 if (rev == 13)
2219                         filename = "lp0bsinitvals13";
2220                 else if (rev == 14)
2221                         filename = "lp0bsinitvals14";
2222                 else if (rev >= 15)
2223                         filename = "lp0bsinitvals15";
2224                 else
2225                         goto err_no_initvals;
2226                 break;
2227         default:
2228                 goto err_no_initvals;
2229         }
2230         err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2231         if (err)
2232                 goto err_load;
2233
2234         return 0;
2235
2236 err_no_ucode:
2237         err = ctx->fatal_failure = -EOPNOTSUPP;
2238         b43err(dev->wl, "The driver does not know which firmware (ucode) "
2239                "is required for your device (wl-core rev %u)\n", rev);
2240         goto error;
2241
2242 err_no_pcm:
2243         err = ctx->fatal_failure = -EOPNOTSUPP;
2244         b43err(dev->wl, "The driver does not know which firmware (PCM) "
2245                "is required for your device (wl-core rev %u)\n", rev);
2246         goto error;
2247
2248 err_no_initvals:
2249         err = ctx->fatal_failure = -EOPNOTSUPP;
2250         b43err(dev->wl, "The driver does not know which firmware (initvals) "
2251                "is required for your device (wl-core rev %u)\n", rev);
2252         goto error;
2253
2254 err_load:
2255         /* We failed to load this firmware image. The error message
2256          * already is in ctx->errors. Return and let our caller decide
2257          * what to do. */
2258         goto error;
2259
2260 error:
2261         b43_release_firmware(dev);
2262         return err;
2263 }
2264
2265 static int b43_request_firmware(struct b43_wldev *dev)
2266 {
2267         struct b43_request_fw_context *ctx;
2268         unsigned int i;
2269         int err;
2270         const char *errmsg;
2271
2272         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2273         if (!ctx)
2274                 return -ENOMEM;
2275         ctx->dev = dev;
2276
2277         ctx->req_type = B43_FWTYPE_PROPRIETARY;
2278         err = b43_try_request_fw(ctx);
2279         if (!err)
2280                 goto out; /* Successfully loaded it. */
2281         err = ctx->fatal_failure;
2282         if (err)
2283                 goto out;
2284
2285         ctx->req_type = B43_FWTYPE_OPENSOURCE;
2286         err = b43_try_request_fw(ctx);
2287         if (!err)
2288                 goto out; /* Successfully loaded it. */
2289         err = ctx->fatal_failure;
2290         if (err)
2291                 goto out;
2292
2293         /* Could not find a usable firmware. Print the errors. */
2294         for (i = 0; i < B43_NR_FWTYPES; i++) {
2295                 errmsg = ctx->errors[i];
2296                 if (strlen(errmsg))
2297                         b43err(dev->wl, errmsg);
2298         }
2299         b43_print_fw_helptext(dev->wl, 1);
2300         err = -ENOENT;
2301
2302 out:
2303         kfree(ctx);
2304         return err;
2305 }
2306
2307 static int b43_upload_microcode(struct b43_wldev *dev)
2308 {
2309         struct wiphy *wiphy = dev->wl->hw->wiphy;
2310         const size_t hdr_len = sizeof(struct b43_fw_header);
2311         const __be32 *data;
2312         unsigned int i, len;
2313         u16 fwrev, fwpatch, fwdate, fwtime;
2314         u32 tmp, macctl;
2315         int err = 0;
2316
2317         /* Jump the microcode PSM to offset 0 */
2318         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2319         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2320         macctl |= B43_MACCTL_PSM_JMP0;
2321         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2322         /* Zero out all microcode PSM registers and shared memory. */
2323         for (i = 0; i < 64; i++)
2324                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2325         for (i = 0; i < 4096; i += 2)
2326                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2327
2328         /* Upload Microcode. */
2329         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2330         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2331         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2332         for (i = 0; i < len; i++) {
2333                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2334                 udelay(10);
2335         }
2336
2337         if (dev->fw.pcm.data) {
2338                 /* Upload PCM data. */
2339                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2340                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2341                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2342                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2343                 /* No need for autoinc bit in SHM_HW */
2344                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2345                 for (i = 0; i < len; i++) {
2346                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2347                         udelay(10);
2348                 }
2349         }
2350
2351         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2352
2353         /* Start the microcode PSM */
2354         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2355         macctl &= ~B43_MACCTL_PSM_JMP0;
2356         macctl |= B43_MACCTL_PSM_RUN;
2357         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2358
2359         /* Wait for the microcode to load and respond */
2360         i = 0;
2361         while (1) {
2362                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2363                 if (tmp == B43_IRQ_MAC_SUSPENDED)
2364                         break;
2365                 i++;
2366                 if (i >= 20) {
2367                         b43err(dev->wl, "Microcode not responding\n");
2368                         b43_print_fw_helptext(dev->wl, 1);
2369                         err = -ENODEV;
2370                         goto error;
2371                 }
2372                 msleep(50);
2373         }
2374         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
2375
2376         /* Get and check the revisions. */
2377         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2378         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2379         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2380         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2381
2382         if (fwrev <= 0x128) {
2383                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2384                        "binary drivers older than version 4.x is unsupported. "
2385                        "You must upgrade your firmware files.\n");
2386                 b43_print_fw_helptext(dev->wl, 1);
2387                 err = -EOPNOTSUPP;
2388                 goto error;
2389         }
2390         dev->fw.rev = fwrev;
2391         dev->fw.patch = fwpatch;
2392         dev->fw.opensource = (fwdate == 0xFFFF);
2393
2394         /* Default to use-all-queues. */
2395         dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2396         dev->qos_enabled = !!modparam_qos;
2397         /* Default to firmware/hardware crypto acceleration. */
2398         dev->hwcrypto_enabled = 1;
2399
2400         if (dev->fw.opensource) {
2401                 u16 fwcapa;
2402
2403                 /* Patchlevel info is encoded in the "time" field. */
2404                 dev->fw.patch = fwtime;
2405                 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2406                         dev->fw.rev, dev->fw.patch);
2407
2408                 fwcapa = b43_fwcapa_read(dev);
2409                 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2410                         b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2411                         /* Disable hardware crypto and fall back to software crypto. */
2412                         dev->hwcrypto_enabled = 0;
2413                 }
2414                 if (!(fwcapa & B43_FWCAPA_QOS)) {
2415                         b43info(dev->wl, "QoS not supported by firmware\n");
2416                         /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2417                          * ieee80211_unregister to make sure the networking core can
2418                          * properly free possible resources. */
2419                         dev->wl->hw->queues = 1;
2420                         dev->qos_enabled = 0;
2421                 }
2422         } else {
2423                 b43info(dev->wl, "Loading firmware version %u.%u "
2424                         "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2425                         fwrev, fwpatch,
2426                         (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2427                         (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2428                 if (dev->fw.pcm_request_failed) {
2429                         b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2430                                 "Hardware accelerated cryptography is disabled.\n");
2431                         b43_print_fw_helptext(dev->wl, 0);
2432                 }
2433         }
2434
2435         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2436                         dev->fw.rev, dev->fw.patch);
2437         wiphy->hw_version = dev->dev->id.coreid;
2438
2439         if (b43_is_old_txhdr_format(dev)) {
2440                 /* We're over the deadline, but we keep support for old fw
2441                  * until it turns out to be in major conflict with something new. */
2442                 b43warn(dev->wl, "You are using an old firmware image. "
2443                         "Support for old firmware will be removed soon "
2444                         "(official deadline was July 2008).\n");
2445                 b43_print_fw_helptext(dev->wl, 0);
2446         }
2447
2448         return 0;
2449
2450 error:
2451         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2452         macctl &= ~B43_MACCTL_PSM_RUN;
2453         macctl |= B43_MACCTL_PSM_JMP0;
2454         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2455
2456         return err;
2457 }
2458
2459 static int b43_write_initvals(struct b43_wldev *dev,
2460                               const struct b43_iv *ivals,
2461                               size_t count,
2462                               size_t array_size)
2463 {
2464         const struct b43_iv *iv;
2465         u16 offset;
2466         size_t i;
2467         bool bit32;
2468
2469         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2470         iv = ivals;
2471         for (i = 0; i < count; i++) {
2472                 if (array_size < sizeof(iv->offset_size))
2473                         goto err_format;
2474                 array_size -= sizeof(iv->offset_size);
2475                 offset = be16_to_cpu(iv->offset_size);
2476                 bit32 = !!(offset & B43_IV_32BIT);
2477                 offset &= B43_IV_OFFSET_MASK;
2478                 if (offset >= 0x1000)
2479                         goto err_format;
2480                 if (bit32) {
2481                         u32 value;
2482
2483                         if (array_size < sizeof(iv->data.d32))
2484                                 goto err_format;
2485                         array_size -= sizeof(iv->data.d32);
2486
2487                         value = get_unaligned_be32(&iv->data.d32);
2488                         b43_write32(dev, offset, value);
2489
2490                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2491                                                         sizeof(__be16) +
2492                                                         sizeof(__be32));
2493                 } else {
2494                         u16 value;
2495
2496                         if (array_size < sizeof(iv->data.d16))
2497                                 goto err_format;
2498                         array_size -= sizeof(iv->data.d16);
2499
2500                         value = be16_to_cpu(iv->data.d16);
2501                         b43_write16(dev, offset, value);
2502
2503                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2504                                                         sizeof(__be16) +
2505                                                         sizeof(__be16));
2506                 }
2507         }
2508         if (array_size)
2509                 goto err_format;
2510
2511         return 0;
2512
2513 err_format:
2514         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2515         b43_print_fw_helptext(dev->wl, 1);
2516
2517         return -EPROTO;
2518 }
2519
2520 static int b43_upload_initvals(struct b43_wldev *dev)
2521 {
2522         const size_t hdr_len = sizeof(struct b43_fw_header);
2523         const struct b43_fw_header *hdr;
2524         struct b43_firmware *fw = &dev->fw;
2525         const struct b43_iv *ivals;
2526         size_t count;
2527         int err;
2528
2529         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2530         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2531         count = be32_to_cpu(hdr->size);
2532         err = b43_write_initvals(dev, ivals, count,
2533                                  fw->initvals.data->size - hdr_len);
2534         if (err)
2535                 goto out;
2536         if (fw->initvals_band.data) {
2537                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2538                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2539                 count = be32_to_cpu(hdr->size);
2540                 err = b43_write_initvals(dev, ivals, count,
2541                                          fw->initvals_band.data->size - hdr_len);
2542                 if (err)
2543                         goto out;
2544         }
2545 out:
2546
2547         return err;
2548 }
2549
2550 /* Initialize the GPIOs
2551  * http://bcm-specs.sipsolutions.net/GPIO
2552  */
2553 static int b43_gpio_init(struct b43_wldev *dev)
2554 {
2555         struct ssb_bus *bus = dev->dev->bus;
2556         struct ssb_device *gpiodev, *pcidev = NULL;
2557         u32 mask, set;
2558
2559         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2560                     & ~B43_MACCTL_GPOUTSMSK);
2561
2562         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2563                     | 0x000F);
2564
2565         mask = 0x0000001F;
2566         set = 0x0000000F;
2567         if (dev->dev->bus->chip_id == 0x4301) {
2568                 mask |= 0x0060;
2569                 set |= 0x0060;
2570         }
2571         if (0 /* FIXME: conditional unknown */ ) {
2572                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2573                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2574                             | 0x0100);
2575                 mask |= 0x0180;
2576                 set |= 0x0180;
2577         }
2578         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2579                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2580                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2581                             | 0x0200);
2582                 mask |= 0x0200;
2583                 set |= 0x0200;
2584         }
2585         if (dev->dev->id.revision >= 2)
2586                 mask |= 0x0010; /* FIXME: This is redundant. */
2587
2588 #ifdef CONFIG_SSB_DRIVER_PCICORE
2589         pcidev = bus->pcicore.dev;
2590 #endif
2591         gpiodev = bus->chipco.dev ? : pcidev;
2592         if (!gpiodev)
2593                 return 0;
2594         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2595                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2596                      & mask) | set);
2597
2598         return 0;
2599 }
2600
2601 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2602 static void b43_gpio_cleanup(struct b43_wldev *dev)
2603 {
2604         struct ssb_bus *bus = dev->dev->bus;
2605         struct ssb_device *gpiodev, *pcidev = NULL;
2606
2607 #ifdef CONFIG_SSB_DRIVER_PCICORE
2608         pcidev = bus->pcicore.dev;
2609 #endif
2610         gpiodev = bus->chipco.dev ? : pcidev;
2611         if (!gpiodev)
2612                 return;
2613         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2614 }
2615
2616 /* http://bcm-specs.sipsolutions.net/EnableMac */
2617 void b43_mac_enable(struct b43_wldev *dev)
2618 {
2619         if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2620                 u16 fwstate;
2621
2622                 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2623                                          B43_SHM_SH_UCODESTAT);
2624                 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2625                     (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2626                         b43err(dev->wl, "b43_mac_enable(): The firmware "
2627                                "should be suspended, but current state is %u\n",
2628                                fwstate);
2629                 }
2630         }
2631
2632         dev->mac_suspended--;
2633         B43_WARN_ON(dev->mac_suspended < 0);
2634         if (dev->mac_suspended == 0) {
2635                 b43_write32(dev, B43_MMIO_MACCTL,
2636                             b43_read32(dev, B43_MMIO_MACCTL)
2637                             | B43_MACCTL_ENABLED);
2638                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2639                             B43_IRQ_MAC_SUSPENDED);
2640                 /* Commit writes */
2641                 b43_read32(dev, B43_MMIO_MACCTL);
2642                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2643                 b43_power_saving_ctl_bits(dev, 0);
2644         }
2645 }
2646
2647 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2648 void b43_mac_suspend(struct b43_wldev *dev)
2649 {
2650         int i;
2651         u32 tmp;
2652
2653         might_sleep();
2654         B43_WARN_ON(dev->mac_suspended < 0);
2655
2656         if (dev->mac_suspended == 0) {
2657                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2658                 b43_write32(dev, B43_MMIO_MACCTL,
2659                             b43_read32(dev, B43_MMIO_MACCTL)
2660                             & ~B43_MACCTL_ENABLED);
2661                 /* force pci to flush the write */
2662                 b43_read32(dev, B43_MMIO_MACCTL);
2663                 for (i = 35; i; i--) {
2664                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2665                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2666                                 goto out;
2667                         udelay(10);
2668                 }
2669                 /* Hm, it seems this will take some time. Use msleep(). */
2670                 for (i = 40; i; i--) {
2671                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2672                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2673                                 goto out;
2674                         msleep(1);
2675                 }
2676                 b43err(dev->wl, "MAC suspend failed\n");
2677         }
2678 out:
2679         dev->mac_suspended++;
2680 }
2681
2682 static void b43_adjust_opmode(struct b43_wldev *dev)
2683 {
2684         struct b43_wl *wl = dev->wl;
2685         u32 ctl;
2686         u16 cfp_pretbtt;
2687
2688         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2689         /* Reset status to STA infrastructure mode. */
2690         ctl &= ~B43_MACCTL_AP;
2691         ctl &= ~B43_MACCTL_KEEP_CTL;
2692         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2693         ctl &= ~B43_MACCTL_KEEP_BAD;
2694         ctl &= ~B43_MACCTL_PROMISC;
2695         ctl &= ~B43_MACCTL_BEACPROMISC;
2696         ctl |= B43_MACCTL_INFRA;
2697
2698         if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2699             b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2700                 ctl |= B43_MACCTL_AP;
2701         else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2702                 ctl &= ~B43_MACCTL_INFRA;
2703
2704         if (wl->filter_flags & FIF_CONTROL)
2705                 ctl |= B43_MACCTL_KEEP_CTL;
2706         if (wl->filter_flags & FIF_FCSFAIL)
2707                 ctl |= B43_MACCTL_KEEP_BAD;
2708         if (wl->filter_flags & FIF_PLCPFAIL)
2709                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2710         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2711                 ctl |= B43_MACCTL_PROMISC;
2712         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2713                 ctl |= B43_MACCTL_BEACPROMISC;
2714
2715         /* Workaround: On old hardware the HW-MAC-address-filter
2716          * doesn't work properly, so always run promisc in filter
2717          * it in software. */
2718         if (dev->dev->id.revision <= 4)
2719                 ctl |= B43_MACCTL_PROMISC;
2720
2721         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2722
2723         cfp_pretbtt = 2;
2724         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2725                 if (dev->dev->bus->chip_id == 0x4306 &&
2726                     dev->dev->bus->chip_rev == 3)
2727                         cfp_pretbtt = 100;
2728                 else
2729                         cfp_pretbtt = 50;
2730         }
2731         b43_write16(dev, 0x612, cfp_pretbtt);
2732
2733         /* FIXME: We don't currently implement the PMQ mechanism,
2734          *        so always disable it. If we want to implement PMQ,
2735          *        we need to enable it here (clear DISCPMQ) in AP mode.
2736          */
2737         if (0  /* ctl & B43_MACCTL_AP */) {
2738                 b43_write32(dev, B43_MMIO_MACCTL,
2739                             b43_read32(dev, B43_MMIO_MACCTL)
2740                             & ~B43_MACCTL_DISCPMQ);
2741         } else {
2742                 b43_write32(dev, B43_MMIO_MACCTL,
2743                             b43_read32(dev, B43_MMIO_MACCTL)
2744                             | B43_MACCTL_DISCPMQ);
2745         }
2746 }
2747
2748 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2749 {
2750         u16 offset;
2751
2752         if (is_ofdm) {
2753                 offset = 0x480;
2754                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2755         } else {
2756                 offset = 0x4C0;
2757                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2758         }
2759         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2760                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2761 }
2762
2763 static void b43_rate_memory_init(struct b43_wldev *dev)
2764 {
2765         switch (dev->phy.type) {
2766         case B43_PHYTYPE_A:
2767         case B43_PHYTYPE_G:
2768         case B43_PHYTYPE_N:
2769         case B43_PHYTYPE_LP:
2770                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2771                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2772                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2773                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2774                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2775                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2776                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2777                 if (dev->phy.type == B43_PHYTYPE_A)
2778                         break;
2779                 /* fallthrough */
2780         case B43_PHYTYPE_B:
2781                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2782                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2783                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2784                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2785                 break;
2786         default:
2787                 B43_WARN_ON(1);
2788         }
2789 }
2790
2791 /* Set the default values for the PHY TX Control Words. */
2792 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2793 {
2794         u16 ctl = 0;
2795
2796         ctl |= B43_TXH_PHY_ENC_CCK;
2797         ctl |= B43_TXH_PHY_ANT01AUTO;
2798         ctl |= B43_TXH_PHY_TXPWR;
2799
2800         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2801         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2802         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2803 }
2804
2805 /* Set the TX-Antenna for management frames sent by firmware. */
2806 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2807 {
2808         u16 ant;
2809         u16 tmp;
2810
2811         ant = b43_antenna_to_phyctl(antenna);
2812
2813         /* For ACK/CTS */
2814         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2815         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2816         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2817         /* For Probe Resposes */
2818         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2819         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2820         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2821 }
2822
2823 /* This is the opposite of b43_chip_init() */
2824 static void b43_chip_exit(struct b43_wldev *dev)
2825 {
2826         b43_phy_exit(dev);
2827         b43_gpio_cleanup(dev);
2828         /* firmware is released later */
2829 }
2830
2831 /* Initialize the chip
2832  * http://bcm-specs.sipsolutions.net/ChipInit
2833  */
2834 static int b43_chip_init(struct b43_wldev *dev)
2835 {
2836         struct b43_phy *phy = &dev->phy;
2837         int err;
2838         u32 value32, macctl;
2839         u16 value16;
2840
2841         /* Initialize the MAC control */
2842         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2843         if (dev->phy.gmode)
2844                 macctl |= B43_MACCTL_GMODE;
2845         macctl |= B43_MACCTL_INFRA;
2846         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2847
2848         err = b43_request_firmware(dev);
2849         if (err)
2850                 goto out;
2851         err = b43_upload_microcode(dev);
2852         if (err)
2853                 goto out;       /* firmware is released later */
2854
2855         err = b43_gpio_init(dev);
2856         if (err)
2857                 goto out;       /* firmware is released later */
2858
2859         err = b43_upload_initvals(dev);
2860         if (err)
2861                 goto err_gpio_clean;
2862
2863         /* Turn the Analog on and initialize the PHY. */
2864         phy->ops->switch_analog(dev, 1);
2865         err = b43_phy_init(dev);
2866         if (err)
2867                 goto err_gpio_clean;
2868
2869         /* Disable Interference Mitigation. */
2870         if (phy->ops->interf_mitigation)
2871                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2872
2873         /* Select the antennae */
2874         if (phy->ops->set_rx_antenna)
2875                 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2876         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2877
2878         if (phy->type == B43_PHYTYPE_B) {
2879                 value16 = b43_read16(dev, 0x005E);
2880                 value16 |= 0x0004;
2881                 b43_write16(dev, 0x005E, value16);
2882         }
2883         b43_write32(dev, 0x0100, 0x01000000);
2884         if (dev->dev->id.revision < 5)
2885                 b43_write32(dev, 0x010C, 0x01000000);
2886
2887         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2888                     & ~B43_MACCTL_INFRA);
2889         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2890                     | B43_MACCTL_INFRA);
2891
2892         /* Probe Response Timeout value */
2893         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2894         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2895
2896         /* Initially set the wireless operation mode. */
2897         b43_adjust_opmode(dev);
2898
2899         if (dev->dev->id.revision < 3) {
2900                 b43_write16(dev, 0x060E, 0x0000);
2901                 b43_write16(dev, 0x0610, 0x8000);
2902                 b43_write16(dev, 0x0604, 0x0000);
2903                 b43_write16(dev, 0x0606, 0x0200);
2904         } else {
2905                 b43_write32(dev, 0x0188, 0x80000000);
2906                 b43_write32(dev, 0x018C, 0x02000000);
2907         }
2908         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2909         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2910         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2911         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2912         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2913         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2914         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2915
2916         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2917         value32 |= 0x00100000;
2918         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2919
2920         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2921                     dev->dev->bus->chipco.fast_pwrup_delay);
2922
2923         err = 0;
2924         b43dbg(dev->wl, "Chip initialized\n");
2925 out:
2926         return err;
2927
2928 err_gpio_clean:
2929         b43_gpio_cleanup(dev);
2930         return err;
2931 }
2932
2933 static void b43_periodic_every60sec(struct b43_wldev *dev)
2934 {
2935         const struct b43_phy_operations *ops = dev->phy.ops;
2936
2937         if (ops->pwork_60sec)
2938                 ops->pwork_60sec(dev);
2939
2940         /* Force check the TX power emission now. */
2941         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2942 }
2943
2944 static void b43_periodic_every30sec(struct b43_wldev *dev)
2945 {
2946         /* Update device statistics. */
2947         b43_calculate_link_quality(dev);
2948 }
2949
2950 static void b43_periodic_every15sec(struct b43_wldev *dev)
2951 {
2952         struct b43_phy *phy = &dev->phy;
2953         u16 wdr;
2954
2955         if (dev->fw.opensource) {
2956                 /* Check if the firmware is still alive.
2957                  * It will reset the watchdog counter to 0 in its idle loop. */
2958                 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2959                 if (unlikely(wdr)) {
2960                         b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2961                         b43_controller_restart(dev, "Firmware watchdog");
2962                         return;
2963                 } else {
2964                         b43_shm_write16(dev, B43_SHM_SCRATCH,
2965                                         B43_WATCHDOG_REG, 1);
2966                 }
2967         }
2968
2969         if (phy->ops->pwork_15sec)
2970                 phy->ops->pwork_15sec(dev);
2971
2972         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2973         wmb();
2974
2975 #if B43_DEBUG
2976         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2977                 unsigned int i;
2978
2979                 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2980                        dev->irq_count / 15,
2981                        dev->tx_count / 15,
2982                        dev->rx_count / 15);
2983                 dev->irq_count = 0;
2984                 dev->tx_count = 0;
2985                 dev->rx_count = 0;
2986                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2987                         if (dev->irq_bit_count[i]) {
2988                                 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2989                                        dev->irq_bit_count[i] / 15, i, (1 << i));
2990                                 dev->irq_bit_count[i] = 0;
2991                         }
2992                 }
2993         }
2994 #endif
2995 }
2996
2997 static void do_periodic_work(struct b43_wldev *dev)
2998 {
2999         unsigned int state;
3000
3001         state = dev->periodic_state;
3002         if (state % 4 == 0)
3003                 b43_periodic_every60sec(dev);
3004         if (state % 2 == 0)
3005                 b43_periodic_every30sec(dev);
3006         b43_periodic_every15sec(dev);
3007 }
3008
3009 /* Periodic work locking policy:
3010  *      The whole periodic work handler is protected by
3011  *      wl->mutex. If another lock is needed somewhere in the
3012  *      pwork callchain, it's acquired in-place, where it's needed.
3013  */
3014 static void b43_periodic_work_handler(struct work_struct *work)
3015 {
3016         struct b43_wldev *dev = container_of(work, struct b43_wldev,
3017                                              periodic_work.work);
3018         struct b43_wl *wl = dev->wl;
3019         unsigned long delay;
3020
3021         mutex_lock(&wl->mutex);
3022
3023         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3024                 goto out;
3025         if (b43_debug(dev, B43_DBG_PWORK_STOP))
3026                 goto out_requeue;
3027
3028         do_periodic_work(dev);
3029
3030         dev->periodic_state++;
3031 out_requeue:
3032         if (b43_debug(dev, B43_DBG_PWORK_FAST))
3033                 delay = msecs_to_jiffies(50);
3034         else
3035                 delay = round_jiffies_relative(HZ * 15);
3036         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3037 out:
3038         mutex_unlock(&wl->mutex);
3039 }
3040
3041 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3042 {
3043         struct delayed_work *work = &dev->periodic_work;
3044
3045         dev->periodic_state = 0;
3046         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3047         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3048 }
3049
3050 /* Check if communication with the device works correctly. */
3051 static int b43_validate_chipaccess(struct b43_wldev *dev)
3052 {
3053         u32 v, backup0, backup4;
3054
3055         backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3056         backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3057
3058         /* Check for read/write and endianness problems. */
3059         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3060         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3061                 goto error;
3062         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3063         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3064                 goto error;
3065
3066         /* Check if unaligned 32bit SHM_SHARED access works properly.
3067          * However, don't bail out on failure, because it's noncritical. */
3068         b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3069         b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3070         b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3071         b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3072         if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3073                 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3074         b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3075         if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3076             b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3077             b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3078             b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3079                 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3080
3081         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3082         b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3083
3084         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3085                 /* The 32bit register shadows the two 16bit registers
3086                  * with update sideeffects. Validate this. */
3087                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3088                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3089                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3090                         goto error;
3091                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3092                         goto error;
3093         }
3094         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3095
3096         v = b43_read32(dev, B43_MMIO_MACCTL);
3097         v |= B43_MACCTL_GMODE;
3098         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3099                 goto error;
3100
3101         return 0;
3102 error:
3103         b43err(dev->wl, "Failed to validate the chipaccess\n");
3104         return -ENODEV;
3105 }
3106
3107 static void b43_security_init(struct b43_wldev *dev)
3108 {
3109         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3110         /* KTP is a word address, but we address SHM bytewise.
3111          * So multiply by two.
3112          */
3113         dev->ktp *= 2;
3114         /* Number of RCMTA address slots */
3115         b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3116         /* Clear the key memory. */
3117         b43_clear_keys(dev);
3118 }
3119
3120 #ifdef CONFIG_B43_HWRNG
3121 static int b43_rng_read(struct hwrng *rng, u32 *data)
3122 {
3123         struct b43_wl *wl = (struct b43_wl *)rng->priv;
3124         struct b43_wldev *dev;
3125         int count = -ENODEV;
3126
3127         mutex_lock(&wl->mutex);
3128         dev = wl->current_dev;
3129         if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3130                 *data = b43_read16(dev, B43_MMIO_RNG);
3131                 count = sizeof(u16);
3132         }
3133         mutex_unlock(&wl->mutex);
3134
3135         return count;
3136 }
3137 #endif /* CONFIG_B43_HWRNG */
3138
3139 static void b43_rng_exit(struct b43_wl *wl)
3140 {
3141 #ifdef CONFIG_B43_HWRNG
3142         if (wl->rng_initialized)
3143                 hwrng_unregister(&wl->rng);
3144 #endif /* CONFIG_B43_HWRNG */
3145 }
3146
3147 static int b43_rng_init(struct b43_wl *wl)
3148 {
3149         int err = 0;
3150
3151 #ifdef CONFIG_B43_HWRNG
3152         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3153                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3154         wl->rng.name = wl->rng_name;
3155         wl->rng.data_read = b43_rng_read;
3156         wl->rng.priv = (unsigned long)wl;
3157         wl->rng_initialized = 1;
3158         err = hwrng_register(&wl->rng);
3159         if (err) {
3160                 wl->rng_initialized = 0;
3161                 b43err(wl, "Failed to register the random "
3162                        "number generator (%d)\n", err);
3163         }
3164 #endif /* CONFIG_B43_HWRNG */
3165
3166         return err;
3167 }
3168
3169 static void b43_tx_work(struct work_struct *work)
3170 {
3171         struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3172         struct b43_wldev *dev;
3173         struct sk_buff *skb;
3174         int err = 0;
3175
3176         mutex_lock(&wl->mutex);
3177         dev = wl->current_dev;
3178         if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3179                 mutex_unlock(&wl->mutex);
3180                 return;
3181         }
3182
3183         while (skb_queue_len(&wl->tx_queue)) {
3184                 skb = skb_dequeue(&wl->tx_queue);
3185
3186                 if (b43_using_pio_transfers(dev))
3187                         err = b43_pio_tx(dev, skb);
3188                 else
3189                         err = b43_dma_tx(dev, skb);
3190                 if (unlikely(err))
3191                         dev_kfree_skb(skb); /* Drop it */
3192         }
3193
3194 #if B43_DEBUG
3195         dev->tx_count++;
3196 #endif
3197         mutex_unlock(&wl->mutex);
3198 }
3199
3200 static int b43_op_tx(struct ieee80211_hw *hw,
3201                      struct sk_buff *skb)
3202 {
3203         struct b43_wl *wl = hw_to_b43_wl(hw);
3204
3205         if (unlikely(skb->len < 2 + 2 + 6)) {
3206                 /* Too short, this can't be a valid frame. */
3207                 dev_kfree_skb_any(skb);
3208                 return NETDEV_TX_OK;
3209         }
3210         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3211
3212         skb_queue_tail(&wl->tx_queue, skb);
3213         ieee80211_queue_work(wl->hw, &wl->tx_work);
3214
3215         return NETDEV_TX_OK;
3216 }
3217
3218 static void b43_qos_params_upload(struct b43_wldev *dev,
3219                                   const struct ieee80211_tx_queue_params *p,
3220                                   u16 shm_offset)
3221 {
3222         u16 params[B43_NR_QOSPARAMS];
3223         int bslots, tmp;
3224         unsigned int i;
3225
3226         if (!dev->qos_enabled)
3227                 return;
3228
3229         bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3230
3231         memset(&params, 0, sizeof(params));
3232
3233         params[B43_QOSPARAM_TXOP] = p->txop * 32;
3234         params[B43_QOSPARAM_CWMIN] = p->cw_min;
3235         params[B43_QOSPARAM_CWMAX] = p->cw_max;
3236         params[B43_QOSPARAM_CWCUR] = p->cw_min;
3237         params[B43_QOSPARAM_AIFS] = p->aifs;
3238         params[B43_QOSPARAM_BSLOTS] = bslots;
3239         params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3240
3241         for (i = 0; i < ARRAY_SIZE(params); i++) {
3242                 if (i == B43_QOSPARAM_STATUS) {
3243                         tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3244                                              shm_offset + (i * 2));
3245                         /* Mark the parameters as updated. */
3246                         tmp |= 0x100;
3247                         b43_shm_write16(dev, B43_SHM_SHARED,
3248                                         shm_offset + (i * 2),
3249                                         tmp);
3250                 } else {
3251                         b43_shm_write16(dev, B43_SHM_SHARED,
3252                                         shm_offset + (i * 2),
3253                                         params[i]);
3254                 }
3255         }
3256 }
3257
3258 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3259 static const u16 b43_qos_shm_offsets[] = {
3260         /* [mac80211-queue-nr] = SHM_OFFSET, */
3261         [0] = B43_QOS_VOICE,
3262         [1] = B43_QOS_VIDEO,
3263         [2] = B43_QOS_BESTEFFORT,
3264         [3] = B43_QOS_BACKGROUND,
3265 };
3266
3267 /* Update all QOS parameters in hardware. */
3268 static void b43_qos_upload_all(struct b43_wldev *dev)
3269 {
3270         struct b43_wl *wl = dev->wl;
3271         struct b43_qos_params *params;
3272         unsigned int i;
3273
3274         if (!dev->qos_enabled)
3275                 return;
3276
3277         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3278                      ARRAY_SIZE(wl->qos_params));
3279
3280         b43_mac_suspend(dev);
3281         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3282                 params = &(wl->qos_params[i]);
3283                 b43_qos_params_upload(dev, &(params->p),
3284                                       b43_qos_shm_offsets[i]);
3285         }
3286         b43_mac_enable(dev);
3287 }
3288
3289 static void b43_qos_clear(struct b43_wl *wl)
3290 {
3291         struct b43_qos_params *params;
3292         unsigned int i;
3293
3294         /* Initialize QoS parameters to sane defaults. */
3295
3296         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3297                      ARRAY_SIZE(wl->qos_params));
3298
3299         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3300                 params = &(wl->qos_params[i]);
3301
3302                 switch (b43_qos_shm_offsets[i]) {
3303                 case B43_QOS_VOICE:
3304                         params->p.txop = 0;
3305                         params->p.aifs = 2;
3306                         params->p.cw_min = 0x0001;
3307                         params->p.cw_max = 0x0001;
3308                         break;
3309                 case B43_QOS_VIDEO:
3310                         params->p.txop = 0;
3311                         params->p.aifs = 2;
3312                         params->p.cw_min = 0x0001;
3313                         params->p.cw_max = 0x0001;
3314                         break;
3315                 case B43_QOS_BESTEFFORT:
3316                         params->p.txop = 0;
3317                         params->p.aifs = 3;
3318                         params->p.cw_min = 0x0001;
3319                         params->p.cw_max = 0x03FF;
3320                         break;
3321                 case B43_QOS_BACKGROUND:
3322                         params->p.txop = 0;
3323                         params->p.aifs = 7;
3324                         params->p.cw_min = 0x0001;
3325                         params->p.cw_max = 0x03FF;
3326                         break;
3327                 default:
3328                         B43_WARN_ON(1);
3329                 }
3330         }
3331 }
3332
3333 /* Initialize the core's QOS capabilities */
3334 static void b43_qos_init(struct b43_wldev *dev)
3335 {
3336         if (!dev->qos_enabled) {
3337                 /* Disable QOS support. */
3338                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3339                 b43_write16(dev, B43_MMIO_IFSCTL,
3340                             b43_read16(dev, B43_MMIO_IFSCTL)
3341                             & ~B43_MMIO_IFSCTL_USE_EDCF);
3342                 b43dbg(dev->wl, "QoS disabled\n");
3343                 return;
3344         }
3345
3346         /* Upload the current QOS parameters. */
3347         b43_qos_upload_all(dev);
3348
3349         /* Enable QOS support. */
3350         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3351         b43_write16(dev, B43_MMIO_IFSCTL,
3352                     b43_read16(dev, B43_MMIO_IFSCTL)
3353                     | B43_MMIO_IFSCTL_USE_EDCF);
3354         b43dbg(dev->wl, "QoS enabled\n");
3355 }
3356
3357 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3358                           const struct ieee80211_tx_queue_params *params)
3359 {
3360         struct b43_wl *wl = hw_to_b43_wl(hw);
3361         struct b43_wldev *dev;
3362         unsigned int queue = (unsigned int)_queue;
3363         int err = -ENODEV;
3364
3365         if (queue >= ARRAY_SIZE(wl->qos_params)) {
3366                 /* Queue not available or don't support setting
3367                  * params on this queue. Return success to not
3368                  * confuse mac80211. */
3369                 return 0;
3370         }
3371         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3372                      ARRAY_SIZE(wl->qos_params));
3373
3374         mutex_lock(&wl->mutex);
3375         dev = wl->current_dev;
3376         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3377                 goto out_unlock;
3378
3379         memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3380         b43_mac_suspend(dev);
3381         b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3382                               b43_qos_shm_offsets[queue]);
3383         b43_mac_enable(dev);
3384         err = 0;
3385
3386 out_unlock:
3387         mutex_unlock(&wl->mutex);
3388
3389         return err;
3390 }
3391
3392 static int b43_op_get_stats(struct ieee80211_hw *hw,
3393                             struct ieee80211_low_level_stats *stats)
3394 {
3395         struct b43_wl *wl = hw_to_b43_wl(hw);
3396
3397         mutex_lock(&wl->mutex);
3398         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3399         mutex_unlock(&wl->mutex);
3400
3401         return 0;
3402 }
3403
3404 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3405 {
3406         struct b43_wl *wl = hw_to_b43_wl(hw);
3407         struct b43_wldev *dev;
3408         u64 tsf;
3409
3410         mutex_lock(&wl->mutex);
3411         dev = wl->current_dev;
3412
3413         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3414                 b43_tsf_read(dev, &tsf);
3415         else
3416                 tsf = 0;
3417
3418         mutex_unlock(&wl->mutex);
3419
3420         return tsf;
3421 }
3422
3423 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3424 {
3425         struct b43_wl *wl = hw_to_b43_wl(hw);
3426         struct b43_wldev *dev;
3427
3428         mutex_lock(&wl->mutex);
3429         dev = wl->current_dev;
3430
3431         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3432                 b43_tsf_write(dev, tsf);
3433
3434         mutex_unlock(&wl->mutex);
3435 }
3436
3437 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3438 {
3439         struct ssb_device *sdev = dev->dev;
3440         u32 tmslow;
3441
3442         tmslow = ssb_read32(sdev, SSB_TMSLOW);
3443         tmslow &= ~B43_TMSLOW_GMODE;
3444         tmslow |= B43_TMSLOW_PHYRESET;
3445         tmslow |= SSB_TMSLOW_FGC;
3446         ssb_write32(sdev, SSB_TMSLOW, tmslow);
3447         msleep(1);
3448
3449         tmslow = ssb_read32(sdev, SSB_TMSLOW);
3450         tmslow &= ~SSB_TMSLOW_FGC;
3451         tmslow |= B43_TMSLOW_PHYRESET;
3452         ssb_write32(sdev, SSB_TMSLOW, tmslow);
3453         msleep(1);
3454 }
3455
3456 static const char *band_to_string(enum ieee80211_band band)
3457 {
3458         switch (band) {
3459         case IEEE80211_BAND_5GHZ:
3460                 return "5";
3461         case IEEE80211_BAND_2GHZ:
3462                 return "2.4";
3463         default:
3464                 break;
3465         }
3466         B43_WARN_ON(1);
3467         return "";
3468 }
3469
3470 /* Expects wl->mutex locked */
3471 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3472 {
3473         struct b43_wldev *up_dev = NULL;
3474         struct b43_wldev *down_dev;
3475         struct b43_wldev *d;
3476         int err;
3477         bool uninitialized_var(gmode);
3478         int prev_status;
3479
3480         /* Find a device and PHY which supports the band. */
3481         list_for_each_entry(d, &wl->devlist, list) {
3482                 switch (chan->band) {
3483                 case IEEE80211_BAND_5GHZ:
3484                         if (d->phy.supports_5ghz) {
3485                                 up_dev = d;
3486                                 gmode = 0;
3487                         }
3488                         break;
3489                 case IEEE80211_BAND_2GHZ:
3490                         if (d->phy.supports_2ghz) {
3491                                 up_dev = d;
3492                                 gmode = 1;
3493                         }
3494                         break;
3495                 default:
3496                         B43_WARN_ON(1);
3497                         return -EINVAL;
3498                 }
3499                 if (up_dev)
3500                         break;
3501         }
3502         if (!up_dev) {
3503                 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3504                        band_to_string(chan->band));
3505                 return -ENODEV;
3506         }
3507         if ((up_dev == wl->current_dev) &&
3508             (!!wl->current_dev->phy.gmode == !!gmode)) {
3509                 /* This device is already running. */
3510                 return 0;
3511         }
3512         b43dbg(wl, "Switching to %s-GHz band\n",
3513                band_to_string(chan->band));
3514         down_dev = wl->current_dev;
3515
3516         prev_status = b43_status(down_dev);
3517         /* Shutdown the currently running core. */
3518         if (prev_status >= B43_STAT_STARTED)
3519                 down_dev = b43_wireless_core_stop(down_dev);
3520         if (prev_status >= B43_STAT_INITIALIZED)
3521                 b43_wireless_core_exit(down_dev);
3522
3523         if (down_dev != up_dev) {
3524                 /* We switch to a different core, so we put PHY into
3525                  * RESET on the old core. */
3526                 b43_put_phy_into_reset(down_dev);
3527         }
3528
3529         /* Now start the new core. */
3530         up_dev->phy.gmode = gmode;
3531         if (prev_status >= B43_STAT_INITIALIZED) {
3532                 err = b43_wireless_core_init(up_dev);
3533                 if (err) {
3534                         b43err(wl, "Fatal: Could not initialize device for "
3535                                "selected %s-GHz band\n",
3536                                band_to_string(chan->band));
3537                         goto init_failure;
3538                 }
3539         }
3540         if (prev_status >= B43_STAT_STARTED) {
3541                 err = b43_wireless_core_start(up_dev);
3542                 if (err) {
3543                         b43err(wl, "Fatal: Coult not start device for "
3544                                "selected %s-GHz band\n",
3545                                band_to_string(chan->band));
3546                         b43_wireless_core_exit(up_dev);
3547                         goto init_failure;
3548                 }
3549         }
3550         B43_WARN_ON(b43_status(up_dev) != prev_status);
3551
3552         wl->current_dev = up_dev;
3553
3554         return 0;
3555 init_failure:
3556         /* Whoops, failed to init the new core. No core is operating now. */
3557         wl->current_dev = NULL;
3558         return err;
3559 }
3560
3561 /* Write the short and long frame retry limit values. */
3562 static void b43_set_retry_limits(struct b43_wldev *dev,
3563                                  unsigned int short_retry,
3564                                  unsigned int long_retry)
3565 {
3566         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3567          * the chip-internal counter. */
3568         short_retry = min(short_retry, (unsigned int)0xF);
3569         long_retry = min(long_retry, (unsigned int)0xF);
3570
3571         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3572                         short_retry);
3573         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3574                         long_retry);
3575 }
3576
3577 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3578 {
3579         struct b43_wl *wl = hw_to_b43_wl(hw);
3580         struct b43_wldev *dev;
3581         struct b43_phy *phy;
3582         struct ieee80211_conf *conf = &hw->conf;
3583         int antenna;
3584         int err = 0;
3585
3586         mutex_lock(&wl->mutex);
3587
3588         /* Switch the band (if necessary). This might change the active core. */
3589         err = b43_switch_band(wl, conf->channel);
3590         if (err)
3591                 goto out_unlock_mutex;
3592         dev = wl->current_dev;
3593         phy = &dev->phy;
3594
3595         if (conf_is_ht(conf))
3596                 phy->is_40mhz =
3597                         (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3598         else
3599                 phy->is_40mhz = false;
3600
3601         b43_mac_suspend(dev);
3602
3603         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3604                 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3605                                           conf->long_frame_max_tx_count);
3606         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3607         if (!changed)
3608                 goto out_mac_enable;
3609
3610         /* Switch to the requested channel.
3611          * The firmware takes care of races with the TX handler. */
3612         if (conf->channel->hw_value != phy->channel)
3613                 b43_switch_channel(dev, conf->channel->hw_value);
3614
3615         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3616
3617         /* Adjust the desired TX power level. */
3618         if (conf->power_level != 0) {
3619                 if (conf->power_level != phy->desired_txpower) {
3620                         phy->desired_txpower = conf->power_level;
3621                         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3622                                                    B43_TXPWR_IGNORE_TSSI);
3623                 }
3624         }
3625
3626         /* Antennas for RX and management frame TX. */
3627         antenna = B43_ANTENNA_DEFAULT;
3628         b43_mgmtframe_txantenna(dev, antenna);
3629         antenna = B43_ANTENNA_DEFAULT;
3630         if (phy->ops->set_rx_antenna)
3631                 phy->ops->set_rx_antenna(dev, antenna);
3632
3633         if (wl->radio_enabled != phy->radio_on) {
3634                 if (wl->radio_enabled) {
3635                         b43_software_rfkill(dev, false);
3636                         b43info(dev->wl, "Radio turned on by software\n");
3637                         if (!dev->radio_hw_enable) {
3638                                 b43info(dev->wl, "The hardware RF-kill button "
3639                                         "still turns the radio physically off. "
3640                                         "Press the button to turn it on.\n");
3641                         }
3642                 } else {
3643                         b43_software_rfkill(dev, true);
3644                         b43info(dev->wl, "Radio turned off by software\n");
3645                 }
3646         }
3647
3648 out_mac_enable:
3649         b43_mac_enable(dev);
3650 out_unlock_mutex:
3651         mutex_unlock(&wl->mutex);
3652
3653         return err;
3654 }
3655
3656 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3657 {
3658         struct ieee80211_supported_band *sband =
3659                 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3660         struct ieee80211_rate *rate;
3661         int i;
3662         u16 basic, direct, offset, basic_offset, rateptr;
3663
3664         for (i = 0; i < sband->n_bitrates; i++) {
3665                 rate = &sband->bitrates[i];
3666
3667                 if (b43_is_cck_rate(rate->hw_value)) {
3668                         direct = B43_SHM_SH_CCKDIRECT;
3669                         basic = B43_SHM_SH_CCKBASIC;
3670                         offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3671                         offset &= 0xF;
3672                 } else {
3673                         direct = B43_SHM_SH_OFDMDIRECT;
3674                         basic = B43_SHM_SH_OFDMBASIC;
3675                         offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3676                         offset &= 0xF;
3677                 }
3678
3679                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3680
3681                 if (b43_is_cck_rate(rate->hw_value)) {
3682                         basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3683                         basic_offset &= 0xF;
3684                 } else {
3685                         basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3686                         basic_offset &= 0xF;
3687                 }
3688
3689                 /*
3690                  * Get the pointer that we need to point to
3691                  * from the direct map
3692                  */
3693                 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3694                                          direct + 2 * basic_offset);
3695                 /* and write it to the basic map */
3696                 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3697                                 rateptr);
3698         }
3699 }
3700
3701 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3702                                     struct ieee80211_vif *vif,
3703                                     struct ieee80211_bss_conf *conf,
3704                                     u32 changed)
3705 {
3706         struct b43_wl *wl = hw_to_b43_wl(hw);
3707         struct b43_wldev *dev;
3708
3709         mutex_lock(&wl->mutex);
3710
3711         dev = wl->current_dev;
3712         if (!dev || b43_status(dev) < B43_STAT_STARTED)
3713                 goto out_unlock_mutex;
3714
3715         B43_WARN_ON(wl->vif != vif);
3716
3717         if (changed & BSS_CHANGED_BSSID) {
3718                 if (conf->bssid)
3719                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3720                 else
3721                         memset(wl->bssid, 0, ETH_ALEN);
3722         }
3723
3724         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3725                 if (changed & BSS_CHANGED_BEACON &&
3726                     (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3727                      b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3728                      b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3729                         b43_update_templates(wl);
3730
3731                 if (changed & BSS_CHANGED_BSSID)
3732                         b43_write_mac_bssid_templates(dev);
3733         }
3734
3735         b43_mac_suspend(dev);
3736
3737         /* Update templates for AP/mesh mode. */
3738         if (changed & BSS_CHANGED_BEACON_INT &&
3739             (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3740              b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3741              b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3742                 b43_set_beacon_int(dev, conf->beacon_int);
3743
3744         if (changed & BSS_CHANGED_BASIC_RATES)
3745                 b43_update_basic_rates(dev, conf->basic_rates);
3746
3747         if (changed & BSS_CHANGED_ERP_SLOT) {
3748                 if (conf->use_short_slot)
3749                         b43_short_slot_timing_enable(dev);
3750                 else
3751                         b43_short_slot_timing_disable(dev);
3752         }
3753
3754         b43_mac_enable(dev);
3755 out_unlock_mutex:
3756         mutex_unlock(&wl->mutex);
3757 }
3758
3759 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3760                           struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3761                           struct ieee80211_key_conf *key)
3762 {
3763         struct b43_wl *wl = hw_to_b43_wl(hw);
3764         struct b43_wldev *dev;
3765         u8 algorithm;
3766         u8 index;
3767         int err;
3768         static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3769
3770         if (modparam_nohwcrypt)
3771                 return -ENOSPC; /* User disabled HW-crypto */
3772
3773         mutex_lock(&wl->mutex);
3774
3775         dev = wl->current_dev;
3776         err = -ENODEV;
3777         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3778                 goto out_unlock;
3779
3780         if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3781                 /* We don't have firmware for the crypto engine.
3782                  * Must use software-crypto. */
3783                 err = -EOPNOTSUPP;
3784                 goto out_unlock;
3785         }
3786
3787         err = -EINVAL;
3788         switch (key->cipher) {
3789         case WLAN_CIPHER_SUITE_WEP40:
3790                 algorithm = B43_SEC_ALGO_WEP40;
3791                 break;
3792         case WLAN_CIPHER_SUITE_WEP104:
3793                 algorithm = B43_SEC_ALGO_WEP104;
3794                 break;
3795         case WLAN_CIPHER_SUITE_TKIP:
3796                 algorithm = B43_SEC_ALGO_TKIP;
3797                 break;
3798         case WLAN_CIPHER_SUITE_CCMP:
3799                 algorithm = B43_SEC_ALGO_AES;
3800                 break;
3801         default:
3802                 B43_WARN_ON(1);
3803                 goto out_unlock;
3804         }
3805         index = (u8) (key->keyidx);
3806         if (index > 3)
3807                 goto out_unlock;
3808
3809         switch (cmd) {
3810         case SET_KEY:
3811                 if (algorithm == B43_SEC_ALGO_TKIP &&
3812                     (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3813                     !modparam_hwtkip)) {
3814                         /* We support only pairwise key */
3815                         err = -EOPNOTSUPP;
3816                         goto out_unlock;
3817                 }
3818
3819                 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3820                         if (WARN_ON(!sta)) {
3821                                 err = -EOPNOTSUPP;
3822                                 goto out_unlock;
3823                         }
3824                         /* Pairwise key with an assigned MAC address. */
3825                         err = b43_key_write(dev, -1, algorithm,
3826                                             key->key, key->keylen,
3827                                             sta->addr, key);
3828                 } else {
3829                         /* Group key */
3830                         err = b43_key_write(dev, index, algorithm,
3831                                             key->key, key->keylen, NULL, key);
3832                 }
3833                 if (err)
3834                         goto out_unlock;
3835
3836                 if (algorithm == B43_SEC_ALGO_WEP40 ||
3837                     algorithm == B43_SEC_ALGO_WEP104) {
3838                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3839                 } else {
3840                         b43_hf_write(dev,
3841                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3842                 }
3843                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3844                 if (algorithm == B43_SEC_ALGO_TKIP)
3845                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3846                 break;
3847         case DISABLE_KEY: {
3848                 err = b43_key_clear(dev, key->hw_key_idx);
3849                 if (err)
3850                         goto out_unlock;
3851                 break;
3852         }
3853         default:
3854                 B43_WARN_ON(1);
3855         }
3856
3857 out_unlock:
3858         if (!err) {
3859                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3860                        "mac: %pM\n",
3861                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3862                        sta ? sta->addr : bcast_addr);
3863                 b43_dump_keymemory(dev);
3864         }
3865         mutex_unlock(&wl->mutex);
3866
3867         return err;
3868 }
3869
3870 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3871                                     unsigned int changed, unsigned int *fflags,
3872                                     u64 multicast)
3873 {
3874         struct b43_wl *wl = hw_to_b43_wl(hw);
3875         struct b43_wldev *dev;
3876
3877         mutex_lock(&wl->mutex);
3878         dev = wl->current_dev;
3879         if (!dev) {
3880                 *fflags = 0;
3881                 goto out_unlock;
3882         }
3883
3884         *fflags &= FIF_PROMISC_IN_BSS |
3885                   FIF_ALLMULTI |
3886                   FIF_FCSFAIL |
3887                   FIF_PLCPFAIL |
3888                   FIF_CONTROL |
3889                   FIF_OTHER_BSS |
3890                   FIF_BCN_PRBRESP_PROMISC;
3891
3892         changed &= FIF_PROMISC_IN_BSS |
3893                    FIF_ALLMULTI |
3894                    FIF_FCSFAIL |
3895                    FIF_PLCPFAIL |
3896                    FIF_CONTROL |
3897                    FIF_OTHER_BSS |
3898                    FIF_BCN_PRBRESP_PROMISC;
3899
3900         wl->filter_flags = *fflags;
3901
3902         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3903                 b43_adjust_opmode(dev);
3904
3905 out_unlock:
3906         mutex_unlock(&wl->mutex);
3907 }
3908
3909 /* Locking: wl->mutex
3910  * Returns the current dev. This might be different from the passed in dev,
3911  * because the core might be gone away while we unlocked the mutex. */
3912 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3913 {
3914         struct b43_wl *wl = dev->wl;
3915         struct b43_wldev *orig_dev;
3916         u32 mask;
3917
3918 redo:
3919         if (!dev || b43_status(dev) < B43_STAT_STARTED)
3920                 return dev;
3921
3922         /* Cancel work. Unlock to avoid deadlocks. */
3923         mutex_unlock(&wl->mutex);
3924         cancel_delayed_work_sync(&dev->periodic_work);
3925         cancel_work_sync(&wl->tx_work);
3926         mutex_lock(&wl->mutex);
3927         dev = wl->current_dev;
3928         if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3929                 /* Whoops, aliens ate up the device while we were unlocked. */
3930                 return dev;
3931         }
3932
3933         /* Disable interrupts on the device. */
3934         b43_set_status(dev, B43_STAT_INITIALIZED);
3935         if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3936                 /* wl->mutex is locked. That is enough. */
3937                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3938                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3939         } else {
3940                 spin_lock_irq(&wl->hardirq_lock);
3941                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3942                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3943                 spin_unlock_irq(&wl->hardirq_lock);
3944         }
3945         /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3946         orig_dev = dev;
3947         mutex_unlock(&wl->mutex);
3948         if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3949                 b43_sdio_free_irq(dev);
3950         } else {
3951                 synchronize_irq(dev->dev->irq);
3952                 free_irq(dev->dev->irq, dev);
3953         }
3954         mutex_lock(&wl->mutex);
3955         dev = wl->current_dev;
3956         if (!dev)
3957                 return dev;
3958         if (dev != orig_dev) {
3959                 if (b43_status(dev) >= B43_STAT_STARTED)
3960                         goto redo;
3961                 return dev;
3962         }
3963         mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3964         B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3965
3966         /* Drain the TX queue */
3967         while (skb_queue_len(&wl->tx_queue))
3968                 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3969
3970         b43_mac_suspend(dev);
3971         b43_leds_exit(dev);
3972         b43dbg(wl, "Wireless interface stopped\n");
3973
3974         return dev;
3975 }
3976
3977 /* Locking: wl->mutex */
3978 static int b43_wireless_core_start(struct b43_wldev *dev)
3979 {
3980         int err;
3981
3982         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3983
3984         drain_txstatus_queue(dev);
3985         if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3986                 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3987                 if (err) {
3988                         b43err(dev->wl, "Cannot request SDIO IRQ\n");
3989                         goto out;
3990                 }
3991         } else {
3992                 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3993                                            b43_interrupt_thread_handler,
3994                                            IRQF_SHARED, KBUILD_MODNAME, dev);
3995                 if (err) {
3996                         b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3997                         goto out;
3998                 }
3999         }
4000
4001         /* We are ready to run. */
4002         ieee80211_wake_queues(dev->wl->hw);
4003         b43_set_status(dev, B43_STAT_STARTED);
4004
4005         /* Start data flow (TX/RX). */
4006         b43_mac_enable(dev);
4007         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4008
4009         /* Start maintainance work */
4010         b43_periodic_tasks_setup(dev);
4011
4012         b43_leds_init(dev);
4013
4014         b43dbg(dev->wl, "Wireless interface started\n");
4015 out:
4016         return err;
4017 }
4018
4019 /* Get PHY and RADIO versioning numbers */
4020 static int b43_phy_versioning(struct b43_wldev *dev)
4021 {
4022         struct b43_phy *phy = &dev->phy;
4023         u32 tmp;
4024         u8 analog_type;
4025         u8 phy_type;
4026         u8 phy_rev;
4027         u16 radio_manuf;
4028         u16 radio_ver;
4029         u16 radio_rev;
4030         int unsupported = 0;
4031
4032         /* Get PHY versioning */
4033         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4034         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4035         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4036         phy_rev = (tmp & B43_PHYVER_VERSION);
4037         switch (phy_type) {
4038         case B43_PHYTYPE_A:
4039                 if (phy_rev >= 4)
4040                         unsupported = 1;
4041                 break;
4042         case B43_PHYTYPE_B:
4043                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4044                     && phy_rev != 7)
4045                         unsupported = 1;
4046                 break;
4047         case B43_PHYTYPE_G:
4048                 if (phy_rev > 9)
4049                         unsupported = 1;
4050                 break;
4051 #ifdef CONFIG_B43_PHY_N
4052         case B43_PHYTYPE_N:
4053                 if (phy_rev > 2)
4054                         unsupported = 1;
4055                 break;
4056 #endif
4057 #ifdef CONFIG_B43_PHY_LP
4058         case B43_PHYTYPE_LP:
4059                 if (phy_rev > 2)
4060                         unsupported = 1;
4061                 break;
4062 #endif
4063         default:
4064                 unsupported = 1;
4065         };
4066         if (unsupported) {
4067                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4068                        "(Analog %u, Type %u, Revision %u)\n",
4069                        analog_type, phy_type, phy_rev);
4070                 return -EOPNOTSUPP;
4071         }
4072         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4073                analog_type, phy_type, phy_rev);
4074
4075         /* Get RADIO versioning */
4076         if (dev->dev->bus->chip_id == 0x4317) {
4077                 if (dev->dev->bus->chip_rev == 0)
4078                         tmp = 0x3205017F;
4079                 else if (dev->dev->bus->chip_rev == 1)
4080                         tmp = 0x4205017F;
4081                 else
4082                         tmp = 0x5205017F;
4083         } else {
4084                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4085                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4086                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4087                 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4088         }
4089         radio_manuf = (tmp & 0x00000FFF);
4090         radio_ver = (tmp & 0x0FFFF000) >> 12;
4091         radio_rev = (tmp & 0xF0000000) >> 28;
4092         if (radio_manuf != 0x17F /* Broadcom */)
4093                 unsupported = 1;
4094         switch (phy_type) {
4095         case B43_PHYTYPE_A:
4096                 if (radio_ver != 0x2060)
4097                         unsupported = 1;
4098                 if (radio_rev != 1)
4099                         unsupported = 1;
4100                 if (radio_manuf != 0x17F)
4101                         unsupported = 1;
4102                 break;
4103         case B43_PHYTYPE_B:
4104                 if ((radio_ver & 0xFFF0) != 0x2050)
4105                         unsupported = 1;
4106                 break;
4107         case B43_PHYTYPE_G:
4108                 if (radio_ver != 0x2050)
4109                         unsupported = 1;
4110                 break;
4111         case B43_PHYTYPE_N:
4112                 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4113                         unsupported = 1;
4114                 break;
4115         case B43_PHYTYPE_LP:
4116                 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4117                         unsupported = 1;
4118                 break;
4119         default:
4120                 B43_WARN_ON(1);
4121         }
4122         if (unsupported) {
4123                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4124                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4125                        radio_manuf, radio_ver, radio_rev);
4126                 return -EOPNOTSUPP;
4127         }
4128         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4129                radio_manuf, radio_ver, radio_rev);
4130
4131         phy->radio_manuf = radio_manuf;
4132         phy->radio_ver = radio_ver;
4133         phy->radio_rev = radio_rev;
4134
4135         phy->analog = analog_type;
4136         phy->type = phy_type;
4137         phy->rev = phy_rev;
4138
4139         return 0;
4140 }
4141
4142 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4143                                       struct b43_phy *phy)
4144 {
4145         phy->hardware_power_control = !!modparam_hwpctl;
4146         phy->next_txpwr_check_time = jiffies;
4147         /* PHY TX errors counter. */
4148         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4149
4150 #if B43_DEBUG
4151         phy->phy_locked = 0;
4152         phy->radio_locked = 0;
4153 #endif
4154 }
4155
4156 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4157 {
4158         dev->dfq_valid = 0;
4159
4160         /* Assume the radio is enabled. If it's not enabled, the state will
4161          * immediately get fixed on the first periodic work run. */
4162         dev->radio_hw_enable = 1;
4163
4164         /* Stats */
4165         memset(&dev->stats, 0, sizeof(dev->stats));
4166
4167         setup_struct_phy_for_init(dev, &dev->phy);
4168
4169         /* IRQ related flags */
4170         dev->irq_reason = 0;
4171         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4172         dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4173         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4174                 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4175
4176         dev->mac_suspended = 1;
4177
4178         /* Noise calculation context */
4179         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4180 }
4181
4182 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4183 {
4184         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4185         u64 hf;
4186
4187         if (!modparam_btcoex)
4188                 return;
4189         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4190                 return;
4191         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4192                 return;
4193
4194         hf = b43_hf_read(dev);
4195         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4196                 hf |= B43_HF_BTCOEXALT;
4197         else
4198                 hf |= B43_HF_BTCOEX;
4199         b43_hf_write(dev, hf);
4200 }
4201
4202 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4203 {
4204         if (!modparam_btcoex)
4205                 return;
4206         //TODO
4207 }
4208
4209 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4210 {
4211 #ifdef CONFIG_SSB_DRIVER_PCICORE
4212         struct ssb_bus *bus = dev->dev->bus;
4213         u32 tmp;
4214
4215         if (bus->pcicore.dev &&
4216             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4217             bus->pcicore.dev->id.revision <= 5) {
4218                 /* IMCFGLO timeouts workaround. */
4219                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4220                 switch (bus->bustype) {
4221                 case SSB_BUSTYPE_PCI:
4222                 case SSB_BUSTYPE_PCMCIA:
4223                         tmp &= ~SSB_IMCFGLO_REQTO;
4224                         tmp &= ~SSB_IMCFGLO_SERTO;
4225                         tmp |= 0x32;
4226                         break;
4227                 case SSB_BUSTYPE_SSB:
4228                         tmp &= ~SSB_IMCFGLO_REQTO;
4229                         tmp &= ~SSB_IMCFGLO_SERTO;
4230                         tmp |= 0x53;
4231                         break;
4232                 default:
4233                         break;
4234                 }
4235                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4236         }
4237 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4238 }
4239
4240 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4241 {
4242         u16 pu_delay;
4243
4244         /* The time value is in microseconds. */
4245         if (dev->phy.type == B43_PHYTYPE_A)
4246                 pu_delay = 3700;
4247         else
4248                 pu_delay = 1050;
4249         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4250                 pu_delay = 500;
4251         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4252                 pu_delay = max(pu_delay, (u16)2400);
4253
4254         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4255 }
4256
4257 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4258 static void b43_set_pretbtt(struct b43_wldev *dev)
4259 {
4260         u16 pretbtt;
4261
4262         /* The time value is in microseconds. */
4263         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4264                 pretbtt = 2;
4265         } else {
4266                 if (dev->phy.type == B43_PHYTYPE_A)
4267                         pretbtt = 120;
4268                 else
4269                         pretbtt = 250;
4270         }
4271         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4272         b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4273 }
4274
4275 /* Shutdown a wireless core */
4276 /* Locking: wl->mutex */
4277 static void b43_wireless_core_exit(struct b43_wldev *dev)
4278 {
4279         u32 macctl;
4280
4281         B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4282         if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4283                 return;
4284
4285         /* Unregister HW RNG driver */
4286         b43_rng_exit(dev->wl);
4287
4288         b43_set_status(dev, B43_STAT_UNINIT);
4289
4290         /* Stop the microcode PSM. */
4291         macctl = b43_read32(dev, B43_MMIO_MACCTL);
4292         macctl &= ~B43_MACCTL_PSM_RUN;
4293         macctl |= B43_MACCTL_PSM_JMP0;
4294         b43_write32(dev, B43_MMIO_MACCTL, macctl);
4295
4296         b43_dma_free(dev);
4297         b43_pio_free(dev);
4298         b43_chip_exit(dev);
4299         dev->phy.ops->switch_analog(dev, 0);
4300         if (dev->wl->current_beacon) {
4301                 dev_kfree_skb_any(dev->wl->current_beacon);
4302                 dev->wl->current_beacon = NULL;
4303         }
4304
4305         ssb_device_disable(dev->dev, 0);
4306         ssb_bus_may_powerdown(dev->dev->bus);
4307 }
4308
4309 /* Initialize a wireless core */
4310 static int b43_wireless_core_init(struct b43_wldev *dev)
4311 {
4312         struct ssb_bus *bus = dev->dev->bus;
4313         struct ssb_sprom *sprom = &bus->sprom;
4314         struct b43_phy *phy = &dev->phy;
4315         int err;
4316         u64 hf;
4317         u32 tmp;
4318
4319         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4320
4321         err = ssb_bus_powerup(bus, 0);
4322         if (err)
4323                 goto out;
4324         if (!ssb_device_is_enabled(dev->dev)) {
4325                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4326                 b43_wireless_core_reset(dev, tmp);
4327         }
4328
4329         /* Reset all data structures. */
4330         setup_struct_wldev_for_init(dev);
4331         phy->ops->prepare_structs(dev);
4332
4333         /* Enable IRQ routing to this device. */
4334         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4335
4336         b43_imcfglo_timeouts_workaround(dev);
4337         b43_bluetooth_coext_disable(dev);
4338         if (phy->ops->prepare_hardware) {
4339                 err = phy->ops->prepare_hardware(dev);
4340                 if (err)
4341                         goto err_busdown;
4342         }
4343         err = b43_chip_init(dev);
4344         if (err)
4345                 goto err_busdown;
4346         b43_shm_write16(dev, B43_SHM_SHARED,
4347                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4348         hf = b43_hf_read(dev);
4349         if (phy->type == B43_PHYTYPE_G) {
4350                 hf |= B43_HF_SYMW;
4351                 if (phy->rev == 1)
4352                         hf |= B43_HF_GDCW;
4353                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4354                         hf |= B43_HF_OFDMPABOOST;
4355         }
4356         if (phy->radio_ver == 0x2050) {
4357                 if (phy->radio_rev == 6)
4358                         hf |= B43_HF_4318TSSI;
4359                 if (phy->radio_rev < 6)
4360                         hf |= B43_HF_VCORECALC;
4361         }
4362         if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4363                 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4364 #ifdef CONFIG_SSB_DRIVER_PCICORE
4365         if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4366             (bus->pcicore.dev->id.revision <= 10))
4367                 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4368 #endif
4369         hf &= ~B43_HF_SKCFPUP;
4370         b43_hf_write(dev, hf);
4371
4372         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4373                              B43_DEFAULT_LONG_RETRY_LIMIT);
4374         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4375         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4376
4377         /* Disable sending probe responses from firmware.
4378          * Setting the MaxTime to one usec will always trigger
4379          * a timeout, so we never send any probe resp.
4380          * A timeout of zero is infinite. */
4381         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4382
4383         b43_rate_memory_init(dev);
4384         b43_set_phytxctl_defaults(dev);
4385
4386         /* Minimum Contention Window */
4387         if (phy->type == B43_PHYTYPE_B)
4388                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4389         else
4390                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4391         /* Maximum Contention Window */
4392         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4393
4394         if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4395             (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4396             dev->use_pio) {
4397                 dev->__using_pio_transfers = 1;
4398                 err = b43_pio_init(dev);
4399         } else {
4400                 dev->__using_pio_transfers = 0;
4401                 err = b43_dma_init(dev);
4402         }
4403         if (err)
4404                 goto err_chip_exit;
4405         b43_qos_init(dev);
4406         b43_set_synth_pu_delay(dev, 1);
4407         b43_bluetooth_coext_enable(dev);
4408
4409         ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4410         b43_upload_card_macaddress(dev);
4411         b43_security_init(dev);
4412
4413         ieee80211_wake_queues(dev->wl->hw);
4414
4415         b43_set_status(dev, B43_STAT_INITIALIZED);
4416
4417         /* Register HW RNG driver */
4418         b43_rng_init(dev->wl);
4419
4420 out:
4421         return err;
4422
4423 err_chip_exit:
4424         b43_chip_exit(dev);
4425 err_busdown:
4426         ssb_bus_may_powerdown(bus);
4427         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4428         return err;
4429 }
4430
4431 static int b43_op_add_interface(struct ieee80211_hw *hw,
4432                                 struct ieee80211_vif *vif)
4433 {
4434         struct b43_wl *wl = hw_to_b43_wl(hw);
4435         struct b43_wldev *dev;
4436         int err = -EOPNOTSUPP;
4437
4438         /* TODO: allow WDS/AP devices to coexist */
4439
4440         if (vif->type != NL80211_IFTYPE_AP &&
4441             vif->type != NL80211_IFTYPE_MESH_POINT &&
4442             vif->type != NL80211_IFTYPE_STATION &&
4443             vif->type != NL80211_IFTYPE_WDS &&
4444             vif->type != NL80211_IFTYPE_ADHOC)
4445                 return -EOPNOTSUPP;
4446
4447         mutex_lock(&wl->mutex);
4448         if (wl->operating)
4449                 goto out_mutex_unlock;
4450
4451         b43dbg(wl, "Adding Interface type %d\n", vif->type);
4452
4453         dev = wl->current_dev;
4454         wl->operating = 1;
4455         wl->vif = vif;
4456         wl->if_type = vif->type;
4457         memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4458
4459         b43_adjust_opmode(dev);
4460         b43_set_pretbtt(dev);
4461         b43_set_synth_pu_delay(dev, 0);
4462         b43_upload_card_macaddress(dev);
4463
4464         err = 0;
4465  out_mutex_unlock:
4466         mutex_unlock(&wl->mutex);
4467
4468         return err;
4469 }
4470
4471 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4472                                     struct ieee80211_vif *vif)
4473 {
4474         struct b43_wl *wl = hw_to_b43_wl(hw);
4475         struct b43_wldev *dev = wl->current_dev;
4476
4477         b43dbg(wl, "Removing Interface type %d\n", vif->type);
4478
4479         mutex_lock(&wl->mutex);
4480
4481         B43_WARN_ON(!wl->operating);
4482         B43_WARN_ON(wl->vif != vif);
4483         wl->vif = NULL;
4484
4485         wl->operating = 0;
4486
4487         b43_adjust_opmode(dev);
4488         memset(wl->mac_addr, 0, ETH_ALEN);
4489         b43_upload_card_macaddress(dev);
4490
4491         mutex_unlock(&wl->mutex);
4492 }
4493
4494 static int b43_op_start(struct ieee80211_hw *hw)
4495 {
4496         struct b43_wl *wl = hw_to_b43_wl(hw);
4497         struct b43_wldev *dev = wl->current_dev;
4498         int did_init = 0;
4499         int err = 0;
4500
4501         /* Kill all old instance specific information to make sure
4502          * the card won't use it in the short timeframe between start
4503          * and mac80211 reconfiguring it. */
4504         memset(wl->bssid, 0, ETH_ALEN);
4505         memset(wl->mac_addr, 0, ETH_ALEN);
4506         wl->filter_flags = 0;
4507         wl->radiotap_enabled = 0;
4508         b43_qos_clear(wl);
4509         wl->beacon0_uploaded = 0;
4510         wl->beacon1_uploaded = 0;
4511         wl->beacon_templates_virgin = 1;
4512         wl->radio_enabled = 1;
4513
4514         mutex_lock(&wl->mutex);
4515
4516         if (b43_status(dev) < B43_STAT_INITIALIZED) {
4517                 err = b43_wireless_core_init(dev);
4518                 if (err)
4519                         goto out_mutex_unlock;
4520                 did_init = 1;
4521         }
4522
4523         if (b43_status(dev) < B43_STAT_STARTED) {
4524                 err = b43_wireless_core_start(dev);
4525                 if (err) {
4526                         if (did_init)
4527                                 b43_wireless_core_exit(dev);
4528                         goto out_mutex_unlock;
4529                 }
4530         }
4531
4532         /* XXX: only do if device doesn't support rfkill irq */
4533         wiphy_rfkill_start_polling(hw->wiphy);
4534
4535  out_mutex_unlock:
4536         mutex_unlock(&wl->mutex);
4537
4538         return err;
4539 }
4540
4541 static void b43_op_stop(struct ieee80211_hw *hw)
4542 {
4543         struct b43_wl *wl = hw_to_b43_wl(hw);
4544         struct b43_wldev *dev = wl->current_dev;
4545
4546         cancel_work_sync(&(wl->beacon_update_trigger));
4547
4548         mutex_lock(&wl->mutex);
4549         if (b43_status(dev) >= B43_STAT_STARTED) {
4550                 dev = b43_wireless_core_stop(dev);
4551                 if (!dev)
4552                         goto out_unlock;
4553         }
4554         b43_wireless_core_exit(dev);
4555         wl->radio_enabled = 0;
4556
4557 out_unlock:
4558         mutex_unlock(&wl->mutex);
4559
4560         cancel_work_sync(&(wl->txpower_adjust_work));
4561 }
4562
4563 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4564                                  struct ieee80211_sta *sta, bool set)
4565 {
4566         struct b43_wl *wl = hw_to_b43_wl(hw);
4567
4568         /* FIXME: add locking */
4569         b43_update_templates(wl);
4570
4571         return 0;
4572 }
4573
4574 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4575                               struct ieee80211_vif *vif,
4576                               enum sta_notify_cmd notify_cmd,
4577                               struct ieee80211_sta *sta)
4578 {
4579         struct b43_wl *wl = hw_to_b43_wl(hw);
4580
4581         B43_WARN_ON(!vif || wl->vif != vif);
4582 }
4583
4584 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4585 {
4586         struct b43_wl *wl = hw_to_b43_wl(hw);
4587         struct b43_wldev *dev;
4588
4589         mutex_lock(&wl->mutex);
4590         dev = wl->current_dev;
4591         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4592                 /* Disable CFP update during scan on other channels. */
4593                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4594         }
4595         mutex_unlock(&wl->mutex);
4596 }
4597
4598 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4599 {
4600         struct b43_wl *wl = hw_to_b43_wl(hw);
4601         struct b43_wldev *dev;
4602
4603         mutex_lock(&wl->mutex);
4604         dev = wl->current_dev;
4605         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4606                 /* Re-enable CFP update. */
4607                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4608         }
4609         mutex_unlock(&wl->mutex);
4610 }
4611
4612 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4613                              struct survey_info *survey)
4614 {
4615         struct b43_wl *wl = hw_to_b43_wl(hw);
4616         struct b43_wldev *dev = wl->current_dev;
4617         struct ieee80211_conf *conf = &hw->conf;
4618
4619         if (idx != 0)
4620                 return -ENOENT;
4621
4622         survey->channel = conf->channel;
4623         survey->filled = SURVEY_INFO_NOISE_DBM;
4624         survey->noise = dev->stats.link_noise;
4625
4626         return 0;
4627 }
4628
4629 static const struct ieee80211_ops b43_hw_ops = {
4630         .tx                     = b43_op_tx,
4631         .conf_tx                = b43_op_conf_tx,
4632         .add_interface          = b43_op_add_interface,
4633         .remove_interface       = b43_op_remove_interface,
4634         .config                 = b43_op_config,
4635         .bss_info_changed       = b43_op_bss_info_changed,
4636         .configure_filter       = b43_op_configure_filter,
4637         .set_key                = b43_op_set_key,
4638         .update_tkip_key        = b43_op_update_tkip_key,
4639         .get_stats              = b43_op_get_stats,
4640         .get_tsf                = b43_op_get_tsf,
4641         .set_tsf                = b43_op_set_tsf,
4642         .start                  = b43_op_start,
4643         .stop                   = b43_op_stop,
4644         .set_tim                = b43_op_beacon_set_tim,
4645         .sta_notify             = b43_op_sta_notify,
4646         .sw_scan_start          = b43_op_sw_scan_start_notifier,
4647         .sw_scan_complete       = b43_op_sw_scan_complete_notifier,
4648         .get_survey             = b43_op_get_survey,
4649         .rfkill_poll            = b43_rfkill_poll,
4650 };
4651
4652 /* Hard-reset the chip. Do not call this directly.
4653  * Use b43_controller_restart()
4654  */
4655 static void b43_chip_reset(struct work_struct *work)
4656 {
4657         struct b43_wldev *dev =
4658             container_of(work, struct b43_wldev, restart_work);
4659         struct b43_wl *wl = dev->wl;
4660         int err = 0;
4661         int prev_status;
4662
4663         mutex_lock(&wl->mutex);
4664
4665         prev_status = b43_status(dev);
4666         /* Bring the device down... */
4667         if (prev_status >= B43_STAT_STARTED) {
4668                 dev = b43_wireless_core_stop(dev);
4669                 if (!dev) {
4670                         err = -ENODEV;
4671                         goto out;
4672                 }
4673         }
4674         if (prev_status >= B43_STAT_INITIALIZED)
4675                 b43_wireless_core_exit(dev);
4676
4677         /* ...and up again. */
4678         if (prev_status >= B43_STAT_INITIALIZED) {
4679                 err = b43_wireless_core_init(dev);
4680                 if (err)
4681                         goto out;
4682         }
4683         if (prev_status >= B43_STAT_STARTED) {
4684                 err = b43_wireless_core_start(dev);
4685                 if (err) {
4686                         b43_wireless_core_exit(dev);
4687                         goto out;
4688                 }
4689         }
4690 out:
4691         if (err)
4692                 wl->current_dev = NULL; /* Failed to init the dev. */
4693         mutex_unlock(&wl->mutex);
4694         if (err)
4695                 b43err(wl, "Controller restart FAILED\n");
4696         else
4697                 b43info(wl, "Controller restarted\n");
4698 }
4699
4700 static int b43_setup_bands(struct b43_wldev *dev,
4701                            bool have_2ghz_phy, bool have_5ghz_phy)
4702 {
4703         struct ieee80211_hw *hw = dev->wl->hw;
4704
4705         if (have_2ghz_phy)
4706                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4707         if (dev->phy.type == B43_PHYTYPE_N) {
4708                 if (have_5ghz_phy)
4709                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4710         } else {
4711                 if (have_5ghz_phy)
4712                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4713         }
4714
4715         dev->phy.supports_2ghz = have_2ghz_phy;
4716         dev->phy.supports_5ghz = have_5ghz_phy;
4717
4718         return 0;
4719 }
4720
4721 static void b43_wireless_core_detach(struct b43_wldev *dev)
4722 {
4723         /* We release firmware that late to not be required to re-request
4724          * is all the time when we reinit the core. */
4725         b43_release_firmware(dev);
4726         b43_phy_free(dev);
4727 }
4728
4729 static int b43_wireless_core_attach(struct b43_wldev *dev)
4730 {
4731         struct b43_wl *wl = dev->wl;
4732         struct ssb_bus *bus = dev->dev->bus;
4733         struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
4734         int err;
4735         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4736         u32 tmp;
4737
4738         /* Do NOT do any device initialization here.
4739          * Do it in wireless_core_init() instead.
4740          * This function is for gathering basic information about the HW, only.
4741          * Also some structs may be set up here. But most likely you want to have
4742          * that in core_init(), too.
4743          */
4744
4745         err = ssb_bus_powerup(bus, 0);
4746         if (err) {
4747                 b43err(wl, "Bus powerup failed\n");
4748                 goto out;
4749         }
4750         /* Get the PHY type. */
4751         if (dev->dev->id.revision >= 5) {
4752                 u32 tmshigh;
4753
4754                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4755                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4756                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4757         } else
4758                 B43_WARN_ON(1);
4759
4760         dev->phy.gmode = have_2ghz_phy;
4761         dev->phy.radio_on = 1;
4762         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4763         b43_wireless_core_reset(dev, tmp);
4764
4765         err = b43_phy_versioning(dev);
4766         if (err)
4767                 goto err_powerdown;
4768         /* Check if this device supports multiband. */
4769         if (!pdev ||
4770             (pdev->device != 0x4312 &&
4771              pdev->device != 0x4319 && pdev->device != 0x4324)) {
4772                 /* No multiband support. */
4773                 have_2ghz_phy = 0;
4774                 have_5ghz_phy = 0;
4775                 switch (dev->phy.type) {
4776                 case B43_PHYTYPE_A:
4777                         have_5ghz_phy = 1;
4778                         break;
4779                 case B43_PHYTYPE_LP: //FIXME not always!
4780 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4781                         have_5ghz_phy = 1;
4782 #endif
4783                 case B43_PHYTYPE_G:
4784                 case B43_PHYTYPE_N:
4785                         have_2ghz_phy = 1;
4786                         break;
4787                 default:
4788                         B43_WARN_ON(1);
4789                 }
4790         }
4791         if (dev->phy.type == B43_PHYTYPE_A) {
4792                 /* FIXME */
4793                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4794                 err = -EOPNOTSUPP;
4795                 goto err_powerdown;
4796         }
4797         if (1 /* disable A-PHY */) {
4798                 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4799                 if (dev->phy.type != B43_PHYTYPE_N &&
4800                     dev->phy.type != B43_PHYTYPE_LP) {
4801                         have_2ghz_phy = 1;
4802                         have_5ghz_phy = 0;
4803                 }
4804         }
4805
4806         err = b43_phy_allocate(dev);
4807         if (err)
4808                 goto err_powerdown;
4809
4810         dev->phy.gmode = have_2ghz_phy;
4811         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4812         b43_wireless_core_reset(dev, tmp);
4813
4814         err = b43_validate_chipaccess(dev);
4815         if (err)
4816                 goto err_phy_free;
4817         err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4818         if (err)
4819                 goto err_phy_free;
4820
4821         /* Now set some default "current_dev" */
4822         if (!wl->current_dev)
4823                 wl->current_dev = dev;
4824         INIT_WORK(&dev->restart_work, b43_chip_reset);
4825
4826         dev->phy.ops->switch_analog(dev, 0);
4827         ssb_device_disable(dev->dev, 0);
4828         ssb_bus_may_powerdown(bus);
4829
4830 out:
4831         return err;
4832
4833 err_phy_free:
4834         b43_phy_free(dev);
4835 err_powerdown:
4836         ssb_bus_may_powerdown(bus);
4837         return err;
4838 }
4839
4840 static void b43_one_core_detach(struct ssb_device *dev)
4841 {
4842         struct b43_wldev *wldev;
4843         struct b43_wl *wl;
4844
4845         /* Do not cancel ieee80211-workqueue based work here.
4846          * See comment in b43_remove(). */
4847
4848         wldev = ssb_get_drvdata(dev);
4849         wl = wldev->wl;
4850         b43_debugfs_remove_device(wldev);
4851         b43_wireless_core_detach(wldev);
4852         list_del(&wldev->list);
4853         wl->nr_devs--;
4854         ssb_set_drvdata(dev, NULL);
4855         kfree(wldev);
4856 }
4857
4858 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4859 {
4860         struct b43_wldev *wldev;
4861         struct pci_dev *pdev;
4862         int err = -ENOMEM;
4863
4864         if (!list_empty(&wl->devlist)) {
4865                 /* We are not the first core on this chip. */
4866                 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
4867                 /* Only special chips support more than one wireless
4868                  * core, although some of the other chips have more than
4869                  * one wireless core as well. Check for this and
4870                  * bail out early.
4871                  */
4872                 if (!pdev ||
4873                     ((pdev->device != 0x4321) &&
4874                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4875                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4876                         return -ENODEV;
4877                 }
4878         }
4879
4880         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4881         if (!wldev)
4882                 goto out;
4883
4884         wldev->use_pio = b43_modparam_pio;
4885         wldev->dev = dev;
4886         wldev->wl = wl;
4887         b43_set_status(wldev, B43_STAT_UNINIT);
4888         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4889         INIT_LIST_HEAD(&wldev->list);
4890
4891         err = b43_wireless_core_attach(wldev);
4892         if (err)
4893                 goto err_kfree_wldev;
4894
4895         list_add(&wldev->list, &wl->devlist);
4896         wl->nr_devs++;
4897         ssb_set_drvdata(dev, wldev);
4898         b43_debugfs_add_device(wldev);
4899
4900       out:
4901         return err;
4902
4903       err_kfree_wldev:
4904         kfree(wldev);
4905         return err;
4906 }
4907
4908 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice)         ( \
4909         (pdev->vendor == PCI_VENDOR_ID_##_vendor) &&                    \
4910         (pdev->device == _device) &&                                    \
4911         (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) &&       \
4912         (pdev->subsystem_device == _subdevice)                          )
4913
4914 static void b43_sprom_fixup(struct ssb_bus *bus)
4915 {
4916         struct pci_dev *pdev;
4917
4918         /* boardflags workarounds */
4919         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4920             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4921                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4922         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4923             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4924                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4925         if (bus->bustype == SSB_BUSTYPE_PCI) {
4926                 pdev = bus->host_pci;
4927                 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4928                     IS_PDEV(pdev, BROADCOM, 0x4320,    DELL, 0x0003) ||
4929                     IS_PDEV(pdev, BROADCOM, 0x4320,      HP, 0x12f8) ||
4930                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4931                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4932                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4933                     IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4934                         bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4935         }
4936 }
4937
4938 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4939 {
4940         struct ieee80211_hw *hw = wl->hw;
4941
4942         ssb_set_devtypedata(dev, NULL);
4943         ieee80211_free_hw(hw);
4944 }
4945
4946 static int b43_wireless_init(struct ssb_device *dev)
4947 {
4948         struct ssb_sprom *sprom = &dev->bus->sprom;
4949         struct ieee80211_hw *hw;
4950         struct b43_wl *wl;
4951         int err = -ENOMEM;
4952
4953         b43_sprom_fixup(dev->bus);
4954
4955         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4956         if (!hw) {
4957                 b43err(NULL, "Could not allocate ieee80211 device\n");
4958                 goto out;
4959         }
4960         wl = hw_to_b43_wl(hw);
4961
4962         /* fill hw info */
4963         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4964                     IEEE80211_HW_SIGNAL_DBM;
4965
4966         hw->wiphy->interface_modes =
4967                 BIT(NL80211_IFTYPE_AP) |
4968                 BIT(NL80211_IFTYPE_MESH_POINT) |
4969                 BIT(NL80211_IFTYPE_STATION) |
4970                 BIT(NL80211_IFTYPE_WDS) |
4971                 BIT(NL80211_IFTYPE_ADHOC);
4972
4973         hw->queues = modparam_qos ? 4 : 1;
4974         wl->mac80211_initially_registered_queues = hw->queues;
4975         hw->max_rates = 2;
4976         SET_IEEE80211_DEV(hw, dev->dev);
4977         if (is_valid_ether_addr(sprom->et1mac))
4978                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4979         else
4980                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4981
4982         /* Initialize struct b43_wl */
4983         wl->hw = hw;
4984         mutex_init(&wl->mutex);
4985         spin_lock_init(&wl->hardirq_lock);
4986         INIT_LIST_HEAD(&wl->devlist);
4987         INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4988         INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4989         INIT_WORK(&wl->tx_work, b43_tx_work);
4990         skb_queue_head_init(&wl->tx_queue);
4991
4992         ssb_set_devtypedata(dev, wl);
4993         b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4994                 dev->bus->chip_id, dev->id.revision);
4995         err = 0;
4996 out:
4997         return err;
4998 }
4999
5000 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
5001 {
5002         struct b43_wl *wl;
5003         int err;
5004         int first = 0;
5005
5006         wl = ssb_get_devtypedata(dev);
5007         if (!wl) {
5008                 /* Probing the first core. Must setup common struct b43_wl */
5009                 first = 1;
5010                 err = b43_wireless_init(dev);
5011                 if (err)
5012                         goto out;
5013                 wl = ssb_get_devtypedata(dev);
5014                 B43_WARN_ON(!wl);
5015         }
5016         err = b43_one_core_attach(dev, wl);
5017         if (err)
5018                 goto err_wireless_exit;
5019
5020         if (first) {
5021                 err = ieee80211_register_hw(wl->hw);
5022                 if (err)
5023                         goto err_one_core_detach;
5024                 b43_leds_register(wl->current_dev);
5025         }
5026
5027       out:
5028         return err;
5029
5030       err_one_core_detach:
5031         b43_one_core_detach(dev);
5032       err_wireless_exit:
5033         if (first)
5034                 b43_wireless_exit(dev, wl);
5035         return err;
5036 }
5037
5038 static void b43_remove(struct ssb_device *dev)
5039 {
5040         struct b43_wl *wl = ssb_get_devtypedata(dev);
5041         struct b43_wldev *wldev = ssb_get_drvdata(dev);
5042
5043         /* We must cancel any work here before unregistering from ieee80211,
5044          * as the ieee80211 unreg will destroy the workqueue. */
5045         cancel_work_sync(&wldev->restart_work);
5046
5047         B43_WARN_ON(!wl);
5048         if (wl->current_dev == wldev) {
5049                 /* Restore the queues count before unregistering, because firmware detect
5050                  * might have modified it. Restoring is important, so the networking
5051                  * stack can properly free resources. */
5052                 wl->hw->queues = wl->mac80211_initially_registered_queues;
5053                 b43_leds_stop(wldev);
5054                 ieee80211_unregister_hw(wl->hw);
5055         }
5056
5057         b43_one_core_detach(dev);
5058
5059         if (list_empty(&wl->devlist)) {
5060                 b43_leds_unregister(wl);
5061                 /* Last core on the chip unregistered.
5062                  * We can destroy common struct b43_wl.
5063                  */
5064                 b43_wireless_exit(dev, wl);
5065         }
5066 }
5067
5068 /* Perform a hardware reset. This can be called from any context. */
5069 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5070 {
5071         /* Must avoid requeueing, if we are in shutdown. */
5072         if (b43_status(dev) < B43_STAT_INITIALIZED)
5073                 return;
5074         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5075         ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5076 }
5077
5078 static struct ssb_driver b43_ssb_driver = {
5079         .name           = KBUILD_MODNAME,
5080         .id_table       = b43_ssb_tbl,
5081         .probe          = b43_probe,
5082         .remove         = b43_remove,
5083 };
5084
5085 static void b43_print_driverinfo(void)
5086 {
5087         const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5088                    *feat_leds = "", *feat_sdio = "";
5089
5090 #ifdef CONFIG_B43_PCI_AUTOSELECT
5091         feat_pci = "P";
5092 #endif
5093 #ifdef CONFIG_B43_PCMCIA
5094         feat_pcmcia = "M";
5095 #endif
5096 #ifdef CONFIG_B43_PHY_N
5097         feat_nphy = "N";
5098 #endif
5099 #ifdef CONFIG_B43_LEDS
5100         feat_leds = "L";
5101 #endif
5102 #ifdef CONFIG_B43_SDIO
5103         feat_sdio = "S";
5104 #endif
5105         printk(KERN_INFO "Broadcom 43xx driver loaded "
5106                "[ Features: %s%s%s%s%s, Firmware-ID: "
5107                B43_SUPPORTED_FIRMWARE_ID " ]\n",
5108                feat_pci, feat_pcmcia, feat_nphy,
5109                feat_leds, feat_sdio);
5110 }
5111
5112 static int __init b43_init(void)
5113 {
5114         int err;
5115
5116         b43_debugfs_init();
5117         err = b43_pcmcia_init();
5118         if (err)
5119                 goto err_dfs_exit;
5120         err = b43_sdio_init();
5121         if (err)
5122                 goto err_pcmcia_exit;
5123         err = ssb_driver_register(&b43_ssb_driver);
5124         if (err)
5125                 goto err_sdio_exit;
5126         b43_print_driverinfo();
5127
5128         return err;
5129
5130 err_sdio_exit:
5131         b43_sdio_exit();
5132 err_pcmcia_exit:
5133         b43_pcmcia_exit();
5134 err_dfs_exit:
5135         b43_debugfs_exit();
5136         return err;
5137 }
5138
5139 static void __exit b43_exit(void)
5140 {
5141         ssb_driver_unregister(&b43_ssb_driver);
5142         b43_sdio_exit();
5143         b43_pcmcia_exit();
5144         b43_debugfs_exit();
5145 }
5146
5147 module_init(b43_init)
5148 module_exit(b43_exit)