3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 #ifdef CONFIG_B43_BCMA_EXTRA
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
129 #ifdef CONFIG_B43_SSB
130 static const struct ssb_device_id b43_ssb_tbl[] = {
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
146 /* Channel and ratetables are shared for all devices.
147 * They can't be const, because ieee80211 puts some precalculated
148 * data in there. This data is the same for all devices, so we don't
149 * get concurrency issues */
150 #define RATETAB_ENT(_rateid, _flags) \
152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
153 .hw_value = (_rateid), \
158 * NOTE: When changing this, sync with xmit.c's
159 * b43_plcp_get_bitrate_idx_* functions!
161 static struct ieee80211_rate __b43_ratetable[] = {
162 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
176 #define b43_a_ratetable (__b43_ratetable + 4)
177 #define b43_a_ratetable_size 8
178 #define b43_b_ratetable (__b43_ratetable + 0)
179 #define b43_b_ratetable_size 4
180 #define b43_g_ratetable (__b43_ratetable + 0)
181 #define b43_g_ratetable_size 12
183 #define CHAN4G(_channel, _freq, _flags) { \
184 .band = IEEE80211_BAND_2GHZ, \
185 .center_freq = (_freq), \
186 .hw_value = (_channel), \
188 .max_antenna_gain = 0, \
191 static struct ieee80211_channel b43_2ghz_chantable[] = {
209 #define CHAN5G(_channel, _flags) { \
210 .band = IEEE80211_BAND_5GHZ, \
211 .center_freq = 5000 + (5 * (_channel)), \
212 .hw_value = (_channel), \
214 .max_antenna_gain = 0, \
217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218 CHAN5G(32, 0), CHAN5G(34, 0),
219 CHAN5G(36, 0), CHAN5G(38, 0),
220 CHAN5G(40, 0), CHAN5G(42, 0),
221 CHAN5G(44, 0), CHAN5G(46, 0),
222 CHAN5G(48, 0), CHAN5G(50, 0),
223 CHAN5G(52, 0), CHAN5G(54, 0),
224 CHAN5G(56, 0), CHAN5G(58, 0),
225 CHAN5G(60, 0), CHAN5G(62, 0),
226 CHAN5G(64, 0), CHAN5G(66, 0),
227 CHAN5G(68, 0), CHAN5G(70, 0),
228 CHAN5G(72, 0), CHAN5G(74, 0),
229 CHAN5G(76, 0), CHAN5G(78, 0),
230 CHAN5G(80, 0), CHAN5G(82, 0),
231 CHAN5G(84, 0), CHAN5G(86, 0),
232 CHAN5G(88, 0), CHAN5G(90, 0),
233 CHAN5G(92, 0), CHAN5G(94, 0),
234 CHAN5G(96, 0), CHAN5G(98, 0),
235 CHAN5G(100, 0), CHAN5G(102, 0),
236 CHAN5G(104, 0), CHAN5G(106, 0),
237 CHAN5G(108, 0), CHAN5G(110, 0),
238 CHAN5G(112, 0), CHAN5G(114, 0),
239 CHAN5G(116, 0), CHAN5G(118, 0),
240 CHAN5G(120, 0), CHAN5G(122, 0),
241 CHAN5G(124, 0), CHAN5G(126, 0),
242 CHAN5G(128, 0), CHAN5G(130, 0),
243 CHAN5G(132, 0), CHAN5G(134, 0),
244 CHAN5G(136, 0), CHAN5G(138, 0),
245 CHAN5G(140, 0), CHAN5G(142, 0),
246 CHAN5G(144, 0), CHAN5G(145, 0),
247 CHAN5G(146, 0), CHAN5G(147, 0),
248 CHAN5G(148, 0), CHAN5G(149, 0),
249 CHAN5G(150, 0), CHAN5G(151, 0),
250 CHAN5G(152, 0), CHAN5G(153, 0),
251 CHAN5G(154, 0), CHAN5G(155, 0),
252 CHAN5G(156, 0), CHAN5G(157, 0),
253 CHAN5G(158, 0), CHAN5G(159, 0),
254 CHAN5G(160, 0), CHAN5G(161, 0),
255 CHAN5G(162, 0), CHAN5G(163, 0),
256 CHAN5G(164, 0), CHAN5G(165, 0),
257 CHAN5G(166, 0), CHAN5G(168, 0),
258 CHAN5G(170, 0), CHAN5G(172, 0),
259 CHAN5G(174, 0), CHAN5G(176, 0),
260 CHAN5G(178, 0), CHAN5G(180, 0),
261 CHAN5G(182, 0), CHAN5G(184, 0),
262 CHAN5G(186, 0), CHAN5G(188, 0),
263 CHAN5G(190, 0), CHAN5G(192, 0),
264 CHAN5G(194, 0), CHAN5G(196, 0),
265 CHAN5G(198, 0), CHAN5G(200, 0),
266 CHAN5G(202, 0), CHAN5G(204, 0),
267 CHAN5G(206, 0), CHAN5G(208, 0),
268 CHAN5G(210, 0), CHAN5G(212, 0),
269 CHAN5G(214, 0), CHAN5G(216, 0),
270 CHAN5G(218, 0), CHAN5G(220, 0),
271 CHAN5G(222, 0), CHAN5G(224, 0),
272 CHAN5G(226, 0), CHAN5G(228, 0),
275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276 CHAN5G(34, 0), CHAN5G(36, 0),
277 CHAN5G(38, 0), CHAN5G(40, 0),
278 CHAN5G(42, 0), CHAN5G(44, 0),
279 CHAN5G(46, 0), CHAN5G(48, 0),
280 CHAN5G(52, 0), CHAN5G(56, 0),
281 CHAN5G(60, 0), CHAN5G(64, 0),
282 CHAN5G(100, 0), CHAN5G(104, 0),
283 CHAN5G(108, 0), CHAN5G(112, 0),
284 CHAN5G(116, 0), CHAN5G(120, 0),
285 CHAN5G(124, 0), CHAN5G(128, 0),
286 CHAN5G(132, 0), CHAN5G(136, 0),
287 CHAN5G(140, 0), CHAN5G(149, 0),
288 CHAN5G(153, 0), CHAN5G(157, 0),
289 CHAN5G(161, 0), CHAN5G(165, 0),
290 CHAN5G(184, 0), CHAN5G(188, 0),
291 CHAN5G(192, 0), CHAN5G(196, 0),
292 CHAN5G(200, 0), CHAN5G(204, 0),
293 CHAN5G(208, 0), CHAN5G(212, 0),
298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299 .band = IEEE80211_BAND_5GHZ,
300 .channels = b43_5ghz_nphy_chantable,
301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302 .bitrates = b43_a_ratetable,
303 .n_bitrates = b43_a_ratetable_size,
306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307 .band = IEEE80211_BAND_5GHZ,
308 .channels = b43_5ghz_aphy_chantable,
309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310 .bitrates = b43_a_ratetable,
311 .n_bitrates = b43_a_ratetable_size,
314 static struct ieee80211_supported_band b43_band_2GHz = {
315 .band = IEEE80211_BAND_2GHZ,
316 .channels = b43_2ghz_chantable,
317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
318 .bitrates = b43_g_ratetable,
319 .n_bitrates = b43_g_ratetable_size,
322 static void b43_wireless_core_exit(struct b43_wldev *dev);
323 static int b43_wireless_core_init(struct b43_wldev *dev);
324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
325 static int b43_wireless_core_start(struct b43_wldev *dev);
326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327 struct ieee80211_vif *vif,
328 struct ieee80211_bss_conf *conf,
331 static int b43_ratelimit(struct b43_wl *wl)
333 if (!wl || !wl->current_dev)
335 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
337 /* We are up and running.
338 * Ratelimit the messages to avoid DoS over the net. */
339 return net_ratelimit();
342 void b43info(struct b43_wl *wl, const char *fmt, ...)
344 struct va_format vaf;
347 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
349 if (!b43_ratelimit(wl))
357 printk(KERN_INFO "b43-%s: %pV",
358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
363 void b43err(struct b43_wl *wl, const char *fmt, ...)
365 struct va_format vaf;
368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
370 if (!b43_ratelimit(wl))
378 printk(KERN_ERR "b43-%s ERROR: %pV",
379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
386 struct va_format vaf;
389 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
391 if (!b43_ratelimit(wl))
399 printk(KERN_WARNING "b43-%s warning: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
407 struct va_format vaf;
410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
418 printk(KERN_DEBUG "b43-%s debug: %pV",
419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
428 B43_WARN_ON(offset % 4 != 0);
430 macctl = b43_read32(dev, B43_MMIO_MACCTL);
431 if (macctl & B43_MACCTL_BE)
434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
436 b43_write32(dev, B43_MMIO_RAM_DATA, val);
439 static inline void b43_shm_control_word(struct b43_wldev *dev,
440 u16 routing, u16 offset)
444 /* "offset" is the WORD offset. */
448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
455 if (routing == B43_SHM_SHARED) {
456 B43_WARN_ON(offset & 0x0001);
457 if (offset & 0x0003) {
458 /* Unaligned access */
459 b43_shm_control_word(dev, routing, offset >> 2);
460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
468 b43_shm_control_word(dev, routing, offset);
469 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
489 b43_shm_control_word(dev, routing, offset);
490 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
497 if (routing == B43_SHM_SHARED) {
498 B43_WARN_ON(offset & 0x0001);
499 if (offset & 0x0003) {
500 /* Unaligned access */
501 b43_shm_control_word(dev, routing, offset >> 2);
502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 b43_write16(dev, B43_MMIO_SHM_DATA,
506 (value >> 16) & 0xFFFF);
511 b43_shm_control_word(dev, routing, offset);
512 b43_write32(dev, B43_MMIO_SHM_DATA, value);
515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
517 if (routing == B43_SHM_SHARED) {
518 B43_WARN_ON(offset & 0x0001);
519 if (offset & 0x0003) {
520 /* Unaligned access */
521 b43_shm_control_word(dev, routing, offset >> 2);
522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
527 b43_shm_control_word(dev, routing, offset);
528 b43_write16(dev, B43_MMIO_SHM_DATA, value);
532 u64 b43_hf_read(struct b43_wldev *dev)
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
545 /* Write HostFlags */
546 void b43_hf_write(struct b43_wldev *dev, u64 value)
550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
561 B43_WARN_ON(!dev->fw.opensource);
562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
569 B43_WARN_ON(dev->dev->core_rev < 3);
571 /* The hardware guarantees us an atomic read, if we
572 * read the low register first. */
573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
581 static void b43_time_lock(struct b43_wldev *dev)
583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
591 /* Commit the write */
592 b43_read32(dev, B43_MMIO_MACCTL);
595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
599 B43_WARN_ON(dev->dev->core_rev < 3);
603 /* The hardware guarantees us an atomic write, if we
604 * write the low register first. */
605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
614 b43_tsf_write_locked(dev, tsf);
615 b43_time_unlock(dev);
619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
621 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
645 u8 mac_bssid[ETH_ALEN * 2];
649 bssid = dev->wl->bssid;
650 mac = dev->wl->mac_addr;
652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
654 memcpy(mac_bssid, mac, ETH_ALEN);
655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
657 /* Write our MAC address and BSSID to template ram */
658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659 tmp = (u32) (mac_bssid[i + 0]);
660 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663 b43_ram_write(dev, 0x20 + i, tmp);
667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
669 b43_write_mac_bssid_templates(dev);
670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
675 /* slot_time is in usec. */
676 /* This test used to exit for all but a G PHY. */
677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680 /* Shared memory location 0x0010 is the slot time and should be
681 * set to slot_time; however, this register is initially 0 and changing
682 * the value adversely affects the transmit rate for BCM4311
683 * devices. Until this behavior is unterstood, delete this step
685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
691 b43_set_slot_time(dev, 9);
694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
696 b43_set_slot_time(dev, 20);
699 /* DummyTransmission function, as documented on
700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
717 buffer[0] = 0x000201CC;
720 buffer[0] = 0x000B846E;
723 for (i = 0; i < 5; i++)
724 b43_ram_write(dev, i * 4, buffer[i]);
726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
728 if (dev->dev->core_rev < 11)
729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
733 value = (ofdm ? 0x41 : 0x40);
734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736 phy->type == B43_PHYTYPE_LCN)
737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
747 if (!pa_on && phy->type == B43_PHYTYPE_N)
748 ; /*b43_nphy_pa_override(dev, false) */
752 case B43_PHYTYPE_LCN:
753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
761 b43_read16(dev, B43_MMIO_TXE0_AUX);
763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764 b43_radio_write16(dev, 0x0051, 0x0017);
765 for (i = 0x00; i < max_loop; i++) {
766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
771 for (i = 0x00; i < 0x0A; i++) {
772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
777 for (i = 0x00; i < 0x19; i++) {
778 value = b43_read16(dev, B43_MMIO_IFSSTAT);
779 if (!(value & 0x0100))
783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784 b43_radio_write16(dev, 0x0051, 0x0037);
787 static void key_write(struct b43_wldev *dev,
788 u8 index, u8 algorithm, const u8 *key)
795 /* Key index/algo block */
796 kidx = b43_kidx_to_fw(dev, index);
797 value = ((kidx << 4) | algorithm);
798 b43_shm_write16(dev, B43_SHM_SHARED,
799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
801 /* Write the key to the Key Table Pointer offset */
802 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
805 value |= (u16) (key[i + 1]) << 8;
806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
812 u32 addrtmp[2] = { 0, 0, };
813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
815 if (b43_new_kidx_api(dev))
816 pairwise_keys_start = B43_NR_GROUP_KEYS;
818 B43_WARN_ON(index < pairwise_keys_start);
819 /* We have four default TX keys and possibly four default RX keys.
820 * Physical mac 0 is mapped to physical key 4 or 8, depending
821 * on the firmware version.
822 * So we must adjust the index here.
824 index -= pairwise_keys_start;
825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
828 addrtmp[0] = addr[0];
829 addrtmp[0] |= ((u32) (addr[1]) << 8);
830 addrtmp[0] |= ((u32) (addr[2]) << 16);
831 addrtmp[0] |= ((u32) (addr[3]) << 24);
832 addrtmp[1] = addr[4];
833 addrtmp[1] |= ((u32) (addr[5]) << 8);
836 /* Receive match transmitter address (RCMTA) mechanism */
837 b43_shm_write32(dev, B43_SHM_RCMTA,
838 (index * 2) + 0, addrtmp[0]);
839 b43_shm_write16(dev, B43_SHM_RCMTA,
840 (index * 2) + 1, addrtmp[1]);
843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
844 * When a packet is received, the iv32 is checked.
845 * - if it doesn't the packet is returned without modification (and software
846 * decryption can be done). That's what happen when iv16 wrap.
847 * - if it does, the rc4 key is computed, and decryption is tried.
848 * Either it will success and B43_RX_MAC_DEC is returned,
849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850 * and the packet is not usable (it got modified by the ucode).
851 * So in order to never have B43_RX_MAC_DECERR, we should provide
852 * a iv32 and phase1key that match. Because we drop packets in case of
853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854 * packets will be lost without higher layer knowing (ie no resync possible
857 * NOTE : this should support 50 key like RCMTA because
858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
867 if (!modparam_hwtkip)
870 if (b43_new_kidx_api(dev))
871 pairwise_keys_start = B43_NR_GROUP_KEYS;
873 B43_WARN_ON(index < pairwise_keys_start);
874 /* We have four default TX keys and possibly four default RX keys.
875 * Physical mac 0 is mapped to physical key 4 or 8, depending
876 * on the firmware version.
877 * So we must adjust the index here.
879 index -= pairwise_keys_start;
880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
882 if (b43_debug(dev, B43_DBG_KEYS)) {
883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
886 /* Write the key to the RX tkip shared mem */
887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888 for (i = 0; i < 10; i += 2) {
889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890 phase1key ? phase1key[i / 2] : 0);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
897 struct ieee80211_vif *vif,
898 struct ieee80211_key_conf *keyconf,
899 struct ieee80211_sta *sta,
900 u32 iv32, u16 *phase1key)
902 struct b43_wl *wl = hw_to_b43_wl(hw);
903 struct b43_wldev *dev;
904 int index = keyconf->hw_key_idx;
906 if (B43_WARN_ON(!modparam_hwtkip))
909 /* This is only called from the RX path through mac80211, where
910 * our mutex is already locked. */
911 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
912 dev = wl->current_dev;
913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
917 rx_tkip_phase1_write(dev, index, iv32, phase1key);
918 /* only pairwise TKIP keys are supported right now */
921 keymac_write(dev, index, sta->addr);
924 static void do_key_write(struct b43_wldev *dev,
925 u8 index, u8 algorithm,
926 const u8 *key, size_t key_len, const u8 *mac_addr)
928 u8 buf[B43_SEC_KEYSIZE] = { 0, };
929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
931 if (b43_new_kidx_api(dev))
932 pairwise_keys_start = B43_NR_GROUP_KEYS;
934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, NULL); /* First zero out mac. */
939 if (algorithm == B43_SEC_ALGO_TKIP) {
941 * We should provide an initial iv32, phase1key pair.
942 * We could start with iv32=0 and compute the corresponding
943 * phase1key, but this means calling ieee80211_get_tkip_key
944 * with a fake skb (or export other tkip function).
945 * Because we are lazy we hope iv32 won't start with
946 * 0xffffffff and let's b43_op_update_tkip_key provide a
949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950 } else if (index >= pairwise_keys_start) /* clear it */
951 rx_tkip_phase1_write(dev, index, 0, NULL);
953 memcpy(buf, key, key_len);
954 key_write(dev, index, algorithm, buf);
955 if (index >= pairwise_keys_start)
956 keymac_write(dev, index, mac_addr);
958 dev->key[index].algorithm = algorithm;
961 static int b43_key_write(struct b43_wldev *dev,
962 int index, u8 algorithm,
963 const u8 *key, size_t key_len,
965 struct ieee80211_key_conf *keyconf)
968 int pairwise_keys_start;
970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971 * - Temporal Encryption Key (128 bits)
972 * - Temporal Authenticator Tx MIC Key (64 bits)
973 * - Temporal Authenticator Rx MIC Key (64 bits)
975 * Hardware only store TEK
977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
979 if (key_len > B43_SEC_KEYSIZE)
981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
982 /* Check that we don't already have this key. */
983 B43_WARN_ON(dev->key[i].keyconf == keyconf);
986 /* Pairwise key. Get an empty slot for the key. */
987 if (b43_new_kidx_api(dev))
988 pairwise_keys_start = B43_NR_GROUP_KEYS;
990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991 for (i = pairwise_keys_start;
992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
995 if (!dev->key[i].keyconf) {
1002 b43warn(dev->wl, "Out of hardware key memory\n");
1006 B43_WARN_ON(index > 3);
1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010 /* Default RX key */
1011 B43_WARN_ON(mac_addr);
1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1014 keyconf->hw_key_idx = index;
1015 dev->key[index].keyconf = keyconf;
1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1024 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1030 dev->key[index].keyconf = NULL;
1035 static void b43_clear_keys(struct b43_wldev *dev)
1039 if (b43_new_kidx_api(dev))
1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043 for (i = 0; i < count; i++)
1044 b43_key_clear(dev, i);
1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1049 unsigned int i, index, count, offset, pairwise_keys_start;
1055 struct b43_key *key;
1057 if (!b43_debug(dev, B43_DBG_KEYS))
1060 hf = b43_hf_read(dev);
1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1062 !!(hf & B43_HF_USEDEFKEYS));
1063 if (b43_new_kidx_api(dev)) {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1070 for (index = 0; index < count; index++) {
1071 key = &(dev->key[index]);
1072 printk(KERN_DEBUG "Key slot %02u: %s",
1073 index, (key->keyconf == NULL) ? " " : "*");
1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1080 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082 printk(" Algo: %04X/%02X", algo, key->algorithm);
1084 if (index >= pairwise_keys_start) {
1085 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088 for (i = 0; i < 14; i += 2) {
1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094 ((index - pairwise_keys_start) * 2) + 0);
1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096 ((index - pairwise_keys_start) * 2) + 1);
1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099 printk(" MAC: %pM", mac);
1101 printk(" DEFAULT KEY");
1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115 (ps_flags & B43_PS_DISABLED));
1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1118 if (ps_flags & B43_PS_ENABLED) {
1120 } else if (ps_flags & B43_PS_DISABLED) {
1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124 // and thus is not an AP and we are associated, set bit 25
1126 if (ps_flags & B43_PS_AWAKE) {
1128 } else if (ps_flags & B43_PS_ASLEEP) {
1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133 // successful, set bit26
1136 /* FIXME: For now we force awake-on and hwps-off */
1140 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1142 macctl |= B43_MACCTL_HWPS;
1144 macctl &= ~B43_MACCTL_HWPS;
1146 macctl |= B43_MACCTL_AWAKE;
1148 macctl &= ~B43_MACCTL_AWAKE;
1149 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1151 b43_read32(dev, B43_MMIO_MACCTL);
1152 if (awake && dev->dev->core_rev >= 5) {
1153 /* Wait for the microcode to wake up. */
1154 for (i = 0; i < 100; i++) {
1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156 B43_SHM_SH_UCODESTAT);
1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1164 #ifdef CONFIG_B43_BCMA
1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1169 /* Put PHY into reset */
1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171 flags |= B43_BCMA_IOCTL_PHY_RESET;
1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1176 /* Take PHY out of reset */
1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179 flags |= BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1183 /* Do not force clock anymore */
1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185 flags &= ~BCMA_IOCTL_FGC;
1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194 b43_bcma_phy_reset(dev);
1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1199 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1201 struct ssb_device *sdev = dev->dev->sdev;
1206 flags |= B43_TMSLOW_GMODE;
1207 flags |= B43_TMSLOW_PHYCLKEN;
1208 flags |= B43_TMSLOW_PHYRESET;
1209 if (dev->phy.type == B43_PHYTYPE_N)
1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211 b43_device_enable(dev, flags);
1212 msleep(2); /* Wait for the PLL to turn on. */
1214 /* Now take the PHY out of Reset again */
1215 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1216 tmslow |= SSB_TMSLOW_FGC;
1217 tmslow &= ~B43_TMSLOW_PHYRESET;
1218 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1221 tmslow &= ~SSB_TMSLOW_FGC;
1222 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1227 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1231 switch (dev->dev->bus_type) {
1232 #ifdef CONFIG_B43_BCMA
1234 b43_bcma_wireless_core_reset(dev, gmode);
1237 #ifdef CONFIG_B43_SSB
1239 b43_ssb_wireless_core_reset(dev, gmode);
1244 /* Turn Analog ON, but only if we already know the PHY-type.
1245 * This protects against very early setup where we don't know the
1246 * PHY-type, yet. wireless_core_reset will be called once again later,
1247 * when we know the PHY-type. */
1249 dev->phy.ops->switch_analog(dev, 1);
1251 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252 macctl &= ~B43_MACCTL_GMODE;
1254 macctl |= B43_MACCTL_GMODE;
1255 macctl |= B43_MACCTL_IHR_ENABLED;
1256 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1259 static void handle_irq_transmit_status(struct b43_wldev *dev)
1263 struct b43_txstatus stat;
1266 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267 if (!(v0 & 0x00000001))
1269 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1271 stat.cookie = (v0 >> 16);
1272 stat.seq = (v1 & 0x0000FFFF);
1273 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274 tmp = (v0 & 0x0000FFFF);
1275 stat.frame_count = ((tmp & 0xF000) >> 12);
1276 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278 stat.pm_indicated = !!(tmp & 0x0080);
1279 stat.intermediate = !!(tmp & 0x0040);
1280 stat.for_ampdu = !!(tmp & 0x0020);
1281 stat.acked = !!(tmp & 0x0002);
1283 b43_handle_txstatus(dev, &stat);
1287 static void drain_txstatus_queue(struct b43_wldev *dev)
1291 if (dev->dev->core_rev < 5)
1293 /* Read all entries from the microcode TXstatus FIFO
1294 * and throw them away.
1297 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298 if (!(dummy & 0x00000001))
1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1304 static u32 b43_jssi_read(struct b43_wldev *dev)
1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1315 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1321 static void b43_generate_noise_sample(struct b43_wldev *dev)
1323 b43_jssi_write(dev, 0x7F7F7F7F);
1324 b43_write32(dev, B43_MMIO_MACCMD,
1325 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1328 static void b43_calculate_link_quality(struct b43_wldev *dev)
1330 /* Top half of Link Quality calculation. */
1332 if (dev->phy.type != B43_PHYTYPE_G)
1334 if (dev->noisecalc.calculation_running)
1336 dev->noisecalc.calculation_running = true;
1337 dev->noisecalc.nr_samples = 0;
1339 b43_generate_noise_sample(dev);
1342 static void handle_irq_noise(struct b43_wldev *dev)
1344 struct b43_phy_g *phy = dev->phy.g;
1350 /* Bottom half of Link Quality calculation. */
1352 if (dev->phy.type != B43_PHYTYPE_G)
1355 /* Possible race condition: It might be possible that the user
1356 * changed to a different channel in the meantime since we
1357 * started the calculation. We ignore that fact, since it's
1358 * not really that much of a problem. The background noise is
1359 * an estimation only anyway. Slightly wrong results will get damped
1360 * by the averaging of the 8 sample rounds. Additionally the
1361 * value is shortlived. So it will be replaced by the next noise
1362 * calculation round soon. */
1364 B43_WARN_ON(!dev->noisecalc.calculation_running);
1365 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1366 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367 noise[2] == 0x7F || noise[3] == 0x7F)
1370 /* Get the noise samples. */
1371 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372 i = dev->noisecalc.nr_samples;
1373 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381 dev->noisecalc.nr_samples++;
1382 if (dev->noisecalc.nr_samples == 8) {
1383 /* Calculate the Link Quality by the noise samples. */
1385 for (i = 0; i < 8; i++) {
1386 for (j = 0; j < 4; j++)
1387 average += dev->noisecalc.samples[i][j];
1393 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394 tmp = (tmp / 128) & 0x1F;
1404 dev->stats.link_noise = average;
1405 dev->noisecalc.calculation_running = false;
1409 b43_generate_noise_sample(dev);
1412 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1414 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1417 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418 b43_power_saving_ctl_bits(dev, 0);
1420 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1421 dev->dfq_valid = true;
1424 static void handle_irq_atim_end(struct b43_wldev *dev)
1426 if (dev->dfq_valid) {
1427 b43_write32(dev, B43_MMIO_MACCMD,
1428 b43_read32(dev, B43_MMIO_MACCMD)
1429 | B43_MACCMD_DFQ_VALID);
1430 dev->dfq_valid = false;
1434 static void handle_irq_pmq(struct b43_wldev *dev)
1441 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442 if (!(tmp & 0x00000008))
1445 /* 16bit write is odd, but correct. */
1446 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1449 static void b43_write_template_common(struct b43_wldev *dev,
1450 const u8 *data, u16 size,
1452 u16 shm_size_offset, u8 rate)
1455 struct b43_plcp_hdr4 plcp;
1458 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460 ram_offset += sizeof(u32);
1461 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462 * So leave the first two bytes of the next write blank.
1464 tmp = (u32) (data[0]) << 16;
1465 tmp |= (u32) (data[1]) << 24;
1466 b43_ram_write(dev, ram_offset, tmp);
1467 ram_offset += sizeof(u32);
1468 for (i = 2; i < size; i += sizeof(u32)) {
1469 tmp = (u32) (data[i + 0]);
1471 tmp |= (u32) (data[i + 1]) << 8;
1473 tmp |= (u32) (data[i + 2]) << 16;
1475 tmp |= (u32) (data[i + 3]) << 24;
1476 b43_ram_write(dev, ram_offset + i - 2, tmp);
1478 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479 size + sizeof(struct b43_plcp_hdr6));
1482 /* Check if the use of the antenna that ieee80211 told us to
1483 * use is possible. This will fall back to DEFAULT.
1484 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1485 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1490 if (antenna_nr == 0) {
1491 /* Zero means "use default antenna". That's always OK. */
1495 /* Get the mask of available antennas. */
1497 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1499 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1501 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502 /* This antenna is not available. Fall back to default. */
1509 /* Convert a b43 antenna number value to the PHY TX control value. */
1510 static u16 b43_antenna_to_phyctl(int antenna)
1514 return B43_TXH_PHY_ANT0;
1516 return B43_TXH_PHY_ANT1;
1518 return B43_TXH_PHY_ANT2;
1520 return B43_TXH_PHY_ANT3;
1521 case B43_ANTENNA_AUTO0:
1522 case B43_ANTENNA_AUTO1:
1523 return B43_TXH_PHY_ANT01AUTO;
1529 static void b43_write_beacon_template(struct b43_wldev *dev,
1531 u16 shm_size_offset)
1533 unsigned int i, len, variable_len;
1534 const struct ieee80211_mgmt *bcn;
1536 bool tim_found = false;
1540 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1542 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543 len = min((size_t) dev->wl->current_beacon->len,
1544 0x200 - sizeof(struct b43_plcp_hdr6));
1545 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1547 b43_write_template_common(dev, (const u8 *)bcn,
1548 len, ram_offset, shm_size_offset, rate);
1550 /* Write the PHY TX control parameters. */
1551 antenna = B43_ANTENNA_DEFAULT;
1552 antenna = b43_antenna_to_phyctl(antenna);
1553 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554 /* We can't send beacons with short preamble. Would get PHY errors. */
1555 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556 ctl &= ~B43_TXH_PHY_ANT;
1557 ctl &= ~B43_TXH_PHY_ENC;
1559 if (b43_is_cck_rate(rate))
1560 ctl |= B43_TXH_PHY_ENC_CCK;
1562 ctl |= B43_TXH_PHY_ENC_OFDM;
1563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1565 /* Find the position of the TIM and the DTIM_period value
1566 * and write them to SHM. */
1567 ie = bcn->u.beacon.variable;
1568 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569 for (i = 0; i < variable_len - 2; ) {
1570 uint8_t ie_id, ie_len;
1577 /* This is the TIM Information Element */
1579 /* Check whether the ie_len is in the beacon data range. */
1580 if (variable_len < ie_len + 2 + i)
1582 /* A valid TIM is at least 4 bytes long. */
1587 tim_position = sizeof(struct b43_plcp_hdr6);
1588 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1591 dtim_period = ie[i + 3];
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_TIMBPOS, tim_position);
1595 b43_shm_write16(dev, B43_SHM_SHARED,
1596 B43_SHM_SH_DTIMPER, dtim_period);
1603 * If ucode wants to modify TIM do it behind the beacon, this
1604 * will happen, for example, when doing mesh networking.
1606 b43_shm_write16(dev, B43_SHM_SHARED,
1608 len + sizeof(struct b43_plcp_hdr6));
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_DTIMPER, 0);
1612 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1615 static void b43_upload_beacon0(struct b43_wldev *dev)
1617 struct b43_wl *wl = dev->wl;
1619 if (wl->beacon0_uploaded)
1621 b43_write_beacon_template(dev, 0x68, 0x18);
1622 wl->beacon0_uploaded = true;
1625 static void b43_upload_beacon1(struct b43_wldev *dev)
1627 struct b43_wl *wl = dev->wl;
1629 if (wl->beacon1_uploaded)
1631 b43_write_beacon_template(dev, 0x468, 0x1A);
1632 wl->beacon1_uploaded = true;
1635 static void handle_irq_beacon(struct b43_wldev *dev)
1637 struct b43_wl *wl = dev->wl;
1638 u32 cmd, beacon0_valid, beacon1_valid;
1640 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1641 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1645 /* This is the bottom half of the asynchronous beacon update. */
1647 /* Ignore interrupt in the future. */
1648 dev->irq_mask &= ~B43_IRQ_BEACON;
1650 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1654 /* Schedule interrupt manually, if busy. */
1655 if (beacon0_valid && beacon1_valid) {
1656 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1657 dev->irq_mask |= B43_IRQ_BEACON;
1661 if (unlikely(wl->beacon_templates_virgin)) {
1662 /* We never uploaded a beacon before.
1663 * Upload both templates now, but only mark one valid. */
1664 wl->beacon_templates_virgin = false;
1665 b43_upload_beacon0(dev);
1666 b43_upload_beacon1(dev);
1667 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668 cmd |= B43_MACCMD_BEACON0_VALID;
1669 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1671 if (!beacon0_valid) {
1672 b43_upload_beacon0(dev);
1673 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674 cmd |= B43_MACCMD_BEACON0_VALID;
1675 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676 } else if (!beacon1_valid) {
1677 b43_upload_beacon1(dev);
1678 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679 cmd |= B43_MACCMD_BEACON1_VALID;
1680 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1685 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1687 u32 old_irq_mask = dev->irq_mask;
1689 /* update beacon right away or defer to irq */
1690 handle_irq_beacon(dev);
1691 if (old_irq_mask != dev->irq_mask) {
1692 /* The handler updated the IRQ mask. */
1693 B43_WARN_ON(!dev->irq_mask);
1694 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1697 /* Device interrupts are currently disabled. That means
1698 * we just ran the hardirq handler and scheduled the
1699 * IRQ thread. The thread will write the IRQ mask when
1700 * it finished, so there's nothing to do here. Writing
1701 * the mask _here_ would incorrectly re-enable IRQs. */
1706 static void b43_beacon_update_trigger_work(struct work_struct *work)
1708 struct b43_wl *wl = container_of(work, struct b43_wl,
1709 beacon_update_trigger);
1710 struct b43_wldev *dev;
1712 mutex_lock(&wl->mutex);
1713 dev = wl->current_dev;
1714 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1715 if (b43_bus_host_is_sdio(dev->dev)) {
1716 /* wl->mutex is enough. */
1717 b43_do_beacon_update_trigger_work(dev);
1720 spin_lock_irq(&wl->hardirq_lock);
1721 b43_do_beacon_update_trigger_work(dev);
1723 spin_unlock_irq(&wl->hardirq_lock);
1726 mutex_unlock(&wl->mutex);
1729 /* Asynchronously update the packet templates in template RAM.
1730 * Locking: Requires wl->mutex to be locked. */
1731 static void b43_update_templates(struct b43_wl *wl)
1733 struct sk_buff *beacon;
1735 /* This is the top half of the ansynchronous beacon update.
1736 * The bottom half is the beacon IRQ.
1737 * Beacon update must be asynchronous to avoid sending an
1738 * invalid beacon. This can happen for example, if the firmware
1739 * transmits a beacon while we are updating it. */
1741 /* We could modify the existing beacon and set the aid bit in
1742 * the TIM field, but that would probably require resizing and
1743 * moving of data within the beacon template.
1744 * Simply request a new beacon and let mac80211 do the hard work. */
1745 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746 if (unlikely(!beacon))
1749 if (wl->current_beacon)
1750 dev_kfree_skb_any(wl->current_beacon);
1751 wl->current_beacon = beacon;
1752 wl->beacon0_uploaded = false;
1753 wl->beacon1_uploaded = false;
1754 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1757 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1760 if (dev->dev->core_rev >= 3) {
1761 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1764 b43_write16(dev, 0x606, (beacon_int >> 6));
1765 b43_write16(dev, 0x610, beacon_int);
1767 b43_time_unlock(dev);
1768 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1771 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1775 /* Read the register that contains the reason code for the panic. */
1776 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1781 b43dbg(dev->wl, "The panic reason is unknown.\n");
1783 case B43_FWPANIC_DIE:
1784 /* Do not restart the controller or firmware.
1785 * The device is nonfunctional from now on.
1786 * Restarting would result in this panic to trigger again,
1787 * so we avoid that recursion. */
1789 case B43_FWPANIC_RESTART:
1790 b43_controller_restart(dev, "Microcode panic");
1795 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1797 unsigned int i, cnt;
1798 u16 reason, marker_id, marker_line;
1801 /* The proprietary firmware doesn't have this IRQ. */
1802 if (!dev->fw.opensource)
1805 /* Read the register that contains the reason code for this IRQ. */
1806 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1809 case B43_DEBUGIRQ_PANIC:
1810 b43_handle_firmware_panic(dev);
1812 case B43_DEBUGIRQ_DUMP_SHM:
1814 break; /* Only with driver debugging enabled. */
1815 buf = kmalloc(4096, GFP_ATOMIC);
1817 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1820 for (i = 0; i < 4096; i += 2) {
1821 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822 buf[i / 2] = cpu_to_le16(tmp);
1824 b43info(dev->wl, "Shared memory dump:\n");
1825 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826 16, 2, buf, 4096, 1);
1829 case B43_DEBUGIRQ_DUMP_REGS:
1831 break; /* Only with driver debugging enabled. */
1832 b43info(dev->wl, "Microcode register dump:\n");
1833 for (i = 0, cnt = 0; i < 64; i++) {
1834 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1837 printk("r%02u: 0x%04X ", i, tmp);
1846 case B43_DEBUGIRQ_MARKER:
1848 break; /* Only with driver debugging enabled. */
1849 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1851 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852 B43_MARKER_LINE_REG);
1853 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854 "at line number %u\n",
1855 marker_id, marker_line);
1858 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1862 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863 b43_shm_write16(dev, B43_SHM_SCRATCH,
1864 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1867 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1870 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871 u32 merged_dma_reason = 0;
1874 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1877 reason = dev->irq_reason;
1878 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879 dma_reason[i] = dev->dma_reason[i];
1880 merged_dma_reason |= dma_reason[i];
1883 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884 b43err(dev->wl, "MAC transmission error\n");
1886 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1887 b43err(dev->wl, "PHY transmission error\n");
1889 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890 atomic_set(&dev->phy.txerr_cnt,
1891 B43_PHY_TX_BADNESS_LIMIT);
1892 b43err(dev->wl, "Too many PHY TX errors, "
1893 "restarting the controller\n");
1894 b43_controller_restart(dev, "PHY TX errors");
1898 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1899 B43_DMAIRQ_NONFATALMASK))) {
1900 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1901 b43err(dev->wl, "Fatal DMA error: "
1902 "0x%08X, 0x%08X, 0x%08X, "
1903 "0x%08X, 0x%08X, 0x%08X\n",
1904 dma_reason[0], dma_reason[1],
1905 dma_reason[2], dma_reason[3],
1906 dma_reason[4], dma_reason[5]);
1907 b43err(dev->wl, "This device does not support DMA "
1908 "on your system. It will now be switched to PIO.\n");
1909 /* Fall back to PIO transfers if we get fatal DMA errors! */
1910 dev->use_pio = true;
1911 b43_controller_restart(dev, "DMA error");
1914 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1915 b43err(dev->wl, "DMA error: "
1916 "0x%08X, 0x%08X, 0x%08X, "
1917 "0x%08X, 0x%08X, 0x%08X\n",
1918 dma_reason[0], dma_reason[1],
1919 dma_reason[2], dma_reason[3],
1920 dma_reason[4], dma_reason[5]);
1924 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1925 handle_irq_ucode_debug(dev);
1926 if (reason & B43_IRQ_TBTT_INDI)
1927 handle_irq_tbtt_indication(dev);
1928 if (reason & B43_IRQ_ATIM_END)
1929 handle_irq_atim_end(dev);
1930 if (reason & B43_IRQ_BEACON)
1931 handle_irq_beacon(dev);
1932 if (reason & B43_IRQ_PMQ)
1933 handle_irq_pmq(dev);
1934 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1936 if (reason & B43_IRQ_NOISESAMPLE_OK)
1937 handle_irq_noise(dev);
1939 /* Check the DMA reason registers for received data. */
1940 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941 if (b43_using_pio_transfers(dev))
1942 b43_pio_rx(dev->pio.rx_queue);
1944 b43_dma_rx(dev->dma.rx_ring);
1946 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1948 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1949 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1952 if (reason & B43_IRQ_TX_OK)
1953 handle_irq_transmit_status(dev);
1955 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1956 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1959 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1961 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962 if (reason & (1 << i))
1963 dev->irq_bit_count[i]++;
1969 /* Interrupt thread handler. Handles device interrupts in thread context. */
1970 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1972 struct b43_wldev *dev = dev_id;
1974 mutex_lock(&dev->wl->mutex);
1975 b43_do_interrupt_thread(dev);
1977 mutex_unlock(&dev->wl->mutex);
1982 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1986 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987 * On SDIO, this runs under wl->mutex. */
1989 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990 if (reason == 0xffffffff) /* shared IRQ */
1992 reason &= dev->irq_mask;
1996 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1998 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2000 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2002 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2004 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2007 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2011 /* ACK the interrupt. */
2012 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2019 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2022 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2023 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2024 /* Save the reason bitmasks for the IRQ thread handler. */
2025 dev->irq_reason = reason;
2027 return IRQ_WAKE_THREAD;
2030 /* Interrupt handler top-half. This runs with interrupts disabled. */
2031 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2033 struct b43_wldev *dev = dev_id;
2036 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2039 spin_lock(&dev->wl->hardirq_lock);
2040 ret = b43_do_interrupt(dev);
2042 spin_unlock(&dev->wl->hardirq_lock);
2047 /* SDIO interrupt handler. This runs in process context. */
2048 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2050 struct b43_wl *wl = dev->wl;
2053 mutex_lock(&wl->mutex);
2055 ret = b43_do_interrupt(dev);
2056 if (ret == IRQ_WAKE_THREAD)
2057 b43_do_interrupt_thread(dev);
2059 mutex_unlock(&wl->mutex);
2062 void b43_do_release_fw(struct b43_firmware_file *fw)
2064 release_firmware(fw->data);
2066 fw->filename = NULL;
2069 static void b43_release_firmware(struct b43_wldev *dev)
2071 b43_do_release_fw(&dev->fw.ucode);
2072 b43_do_release_fw(&dev->fw.pcm);
2073 b43_do_release_fw(&dev->fw.initvals);
2074 b43_do_release_fw(&dev->fw.initvals_band);
2077 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2081 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2082 "and download the correct firmware for this driver version. " \
2083 "Please carefully read all instructions on this website.\n";
2091 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2093 struct b43_firmware_file *fw)
2095 const struct firmware *blob;
2096 struct b43_fw_header *hdr;
2101 /* Don't fetch anything. Free possibly cached firmware. */
2102 /* FIXME: We should probably keep it anyway, to save some headache
2103 * on suspend/resume with multiband devices. */
2104 b43_do_release_fw(fw);
2108 if ((fw->type == ctx->req_type) &&
2109 (strcmp(fw->filename, name) == 0))
2110 return 0; /* Already have this fw. */
2111 /* Free the cached firmware first. */
2112 /* FIXME: We should probably do this later after we successfully
2113 * got the new fw. This could reduce headache with multiband devices.
2114 * We could also redesign this to cache the firmware for all possible
2115 * bands all the time. */
2116 b43_do_release_fw(fw);
2119 switch (ctx->req_type) {
2120 case B43_FWTYPE_PROPRIETARY:
2121 snprintf(ctx->fwname, sizeof(ctx->fwname),
2123 modparam_fwpostfix, name);
2125 case B43_FWTYPE_OPENSOURCE:
2126 snprintf(ctx->fwname, sizeof(ctx->fwname),
2128 modparam_fwpostfix, name);
2134 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2135 if (err == -ENOENT) {
2136 snprintf(ctx->errors[ctx->req_type],
2137 sizeof(ctx->errors[ctx->req_type]),
2138 "Firmware file \"%s\" not found\n", ctx->fwname);
2141 snprintf(ctx->errors[ctx->req_type],
2142 sizeof(ctx->errors[ctx->req_type]),
2143 "Firmware file \"%s\" request failed (err=%d)\n",
2147 if (blob->size < sizeof(struct b43_fw_header))
2149 hdr = (struct b43_fw_header *)(blob->data);
2150 switch (hdr->type) {
2151 case B43_FW_TYPE_UCODE:
2152 case B43_FW_TYPE_PCM:
2153 size = be32_to_cpu(hdr->size);
2154 if (size != blob->size - sizeof(struct b43_fw_header))
2157 case B43_FW_TYPE_IV:
2166 fw->filename = name;
2167 fw->type = ctx->req_type;
2172 snprintf(ctx->errors[ctx->req_type],
2173 sizeof(ctx->errors[ctx->req_type]),
2174 "Firmware file \"%s\" format error.\n", ctx->fwname);
2175 release_firmware(blob);
2180 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2182 struct b43_wldev *dev = ctx->dev;
2183 struct b43_firmware *fw = &ctx->dev->fw;
2184 const u8 rev = ctx->dev->dev->core_rev;
2185 const char *filename;
2189 /* Files for HT and LCN were found by trying one by one */
2192 if ((rev >= 5) && (rev <= 10)) {
2193 filename = "ucode5";
2194 } else if ((rev >= 11) && (rev <= 12)) {
2195 filename = "ucode11";
2196 } else if (rev == 13) {
2197 filename = "ucode13";
2198 } else if (rev == 14) {
2199 filename = "ucode14";
2200 } else if (rev == 15) {
2201 filename = "ucode15";
2203 switch (dev->phy.type) {
2206 filename = "ucode16_mimo";
2210 case B43_PHYTYPE_HT:
2212 filename = "ucode29_mimo";
2216 case B43_PHYTYPE_LCN:
2218 filename = "ucode24_mimo";
2226 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2231 if ((rev >= 5) && (rev <= 10))
2237 fw->pcm_request_failed = false;
2238 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2239 if (err == -ENOENT) {
2240 /* We did not find a PCM file? Not fatal, but
2241 * core rev <= 10 must do without hwcrypto then. */
2242 fw->pcm_request_failed = true;
2247 switch (dev->phy.type) {
2249 if ((rev >= 5) && (rev <= 10)) {
2250 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2251 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2252 filename = "a0g1initvals5";
2254 filename = "a0g0initvals5";
2256 goto err_no_initvals;
2259 if ((rev >= 5) && (rev <= 10))
2260 filename = "b0g0initvals5";
2262 filename = "b0g0initvals13";
2264 goto err_no_initvals;
2268 filename = "n0initvals16";
2269 else if ((rev >= 11) && (rev <= 12))
2270 filename = "n0initvals11";
2272 goto err_no_initvals;
2274 case B43_PHYTYPE_LP:
2276 filename = "lp0initvals13";
2278 filename = "lp0initvals14";
2280 filename = "lp0initvals15";
2282 goto err_no_initvals;
2284 case B43_PHYTYPE_HT:
2286 filename = "ht0initvals29";
2288 goto err_no_initvals;
2290 case B43_PHYTYPE_LCN:
2292 filename = "lcn0initvals24";
2294 goto err_no_initvals;
2297 goto err_no_initvals;
2299 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2303 /* Get bandswitch initvals */
2304 switch (dev->phy.type) {
2306 if ((rev >= 5) && (rev <= 10)) {
2307 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2308 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2309 filename = "a0g1bsinitvals5";
2311 filename = "a0g0bsinitvals5";
2312 } else if (rev >= 11)
2315 goto err_no_initvals;
2318 if ((rev >= 5) && (rev <= 10))
2319 filename = "b0g0bsinitvals5";
2323 goto err_no_initvals;
2327 filename = "n0bsinitvals16";
2328 else if ((rev >= 11) && (rev <= 12))
2329 filename = "n0bsinitvals11";
2331 goto err_no_initvals;
2333 case B43_PHYTYPE_LP:
2335 filename = "lp0bsinitvals13";
2337 filename = "lp0bsinitvals14";
2339 filename = "lp0bsinitvals15";
2341 goto err_no_initvals;
2343 case B43_PHYTYPE_HT:
2345 filename = "ht0bsinitvals29";
2347 goto err_no_initvals;
2349 case B43_PHYTYPE_LCN:
2351 filename = "lcn0bsinitvals24";
2353 goto err_no_initvals;
2356 goto err_no_initvals;
2358 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2362 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2367 err = ctx->fatal_failure = -EOPNOTSUPP;
2368 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2369 "is required for your device (wl-core rev %u)\n", rev);
2373 err = ctx->fatal_failure = -EOPNOTSUPP;
2374 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2375 "is required for your device (wl-core rev %u)\n", rev);
2379 err = ctx->fatal_failure = -EOPNOTSUPP;
2380 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2381 "is required for your device (wl-core rev %u)\n", rev);
2385 /* We failed to load this firmware image. The error message
2386 * already is in ctx->errors. Return and let our caller decide
2391 b43_release_firmware(dev);
2395 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2396 static void b43_one_core_detach(struct b43_bus_dev *dev);
2398 static void b43_request_firmware(struct work_struct *work)
2400 struct b43_wl *wl = container_of(work,
2401 struct b43_wl, firmware_load);
2402 struct b43_wldev *dev = wl->current_dev;
2403 struct b43_request_fw_context *ctx;
2408 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2413 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2414 err = b43_try_request_fw(ctx);
2416 goto start_ieee80211; /* Successfully loaded it. */
2417 /* Was fw version known? */
2418 if (ctx->fatal_failure)
2421 /* proprietary fw not found, try open source */
2422 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2423 err = b43_try_request_fw(ctx);
2425 goto start_ieee80211; /* Successfully loaded it. */
2426 if(ctx->fatal_failure)
2429 /* Could not find a usable firmware. Print the errors. */
2430 for (i = 0; i < B43_NR_FWTYPES; i++) {
2431 errmsg = ctx->errors[i];
2433 b43err(dev->wl, errmsg);
2435 b43_print_fw_helptext(dev->wl, 1);
2439 wl->hw->queues = B43_QOS_QUEUE_NUM;
2440 if (!modparam_qos || dev->fw.opensource)
2443 err = ieee80211_register_hw(wl->hw);
2445 goto err_one_core_detach;
2446 wl->hw_registred = true;
2447 b43_leds_register(wl->current_dev);
2450 err_one_core_detach:
2451 b43_one_core_detach(dev->dev);
2457 static int b43_upload_microcode(struct b43_wldev *dev)
2459 struct wiphy *wiphy = dev->wl->hw->wiphy;
2460 const size_t hdr_len = sizeof(struct b43_fw_header);
2462 unsigned int i, len;
2463 u16 fwrev, fwpatch, fwdate, fwtime;
2467 /* Jump the microcode PSM to offset 0 */
2468 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2469 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2470 macctl |= B43_MACCTL_PSM_JMP0;
2471 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2472 /* Zero out all microcode PSM registers and shared memory. */
2473 for (i = 0; i < 64; i++)
2474 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2475 for (i = 0; i < 4096; i += 2)
2476 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2478 /* Upload Microcode. */
2479 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2480 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2481 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2482 for (i = 0; i < len; i++) {
2483 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2487 if (dev->fw.pcm.data) {
2488 /* Upload PCM data. */
2489 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2490 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2491 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2492 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2493 /* No need for autoinc bit in SHM_HW */
2494 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2495 for (i = 0; i < len; i++) {
2496 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2501 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2503 /* Start the microcode PSM */
2504 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2505 B43_MACCTL_PSM_RUN);
2507 /* Wait for the microcode to load and respond */
2510 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2511 if (tmp == B43_IRQ_MAC_SUSPENDED)
2515 b43err(dev->wl, "Microcode not responding\n");
2516 b43_print_fw_helptext(dev->wl, 1);
2522 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2524 /* Get and check the revisions. */
2525 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2526 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2527 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2528 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2530 if (fwrev <= 0x128) {
2531 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2532 "binary drivers older than version 4.x is unsupported. "
2533 "You must upgrade your firmware files.\n");
2534 b43_print_fw_helptext(dev->wl, 1);
2538 dev->fw.rev = fwrev;
2539 dev->fw.patch = fwpatch;
2540 if (dev->fw.rev >= 598)
2541 dev->fw.hdr_format = B43_FW_HDR_598;
2542 else if (dev->fw.rev >= 410)
2543 dev->fw.hdr_format = B43_FW_HDR_410;
2545 dev->fw.hdr_format = B43_FW_HDR_351;
2546 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2548 dev->qos_enabled = dev->wl->hw->queues > 1;
2549 /* Default to firmware/hardware crypto acceleration. */
2550 dev->hwcrypto_enabled = true;
2552 if (dev->fw.opensource) {
2555 /* Patchlevel info is encoded in the "time" field. */
2556 dev->fw.patch = fwtime;
2557 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2558 dev->fw.rev, dev->fw.patch);
2560 fwcapa = b43_fwcapa_read(dev);
2561 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2562 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2563 /* Disable hardware crypto and fall back to software crypto. */
2564 dev->hwcrypto_enabled = false;
2566 /* adding QoS support should use an offline discovery mechanism */
2567 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2569 b43info(dev->wl, "Loading firmware version %u.%u "
2570 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2572 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2573 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2574 if (dev->fw.pcm_request_failed) {
2575 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2576 "Hardware accelerated cryptography is disabled.\n");
2577 b43_print_fw_helptext(dev->wl, 0);
2581 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2582 dev->fw.rev, dev->fw.patch);
2583 wiphy->hw_version = dev->dev->core_id;
2585 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2586 /* We're over the deadline, but we keep support for old fw
2587 * until it turns out to be in major conflict with something new. */
2588 b43warn(dev->wl, "You are using an old firmware image. "
2589 "Support for old firmware will be removed soon "
2590 "(official deadline was July 2008).\n");
2591 b43_print_fw_helptext(dev->wl, 0);
2597 /* Stop the microcode PSM. */
2598 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2599 B43_MACCTL_PSM_JMP0);
2604 static int b43_write_initvals(struct b43_wldev *dev,
2605 const struct b43_iv *ivals,
2609 const struct b43_iv *iv;
2614 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2616 for (i = 0; i < count; i++) {
2617 if (array_size < sizeof(iv->offset_size))
2619 array_size -= sizeof(iv->offset_size);
2620 offset = be16_to_cpu(iv->offset_size);
2621 bit32 = !!(offset & B43_IV_32BIT);
2622 offset &= B43_IV_OFFSET_MASK;
2623 if (offset >= 0x1000)
2628 if (array_size < sizeof(iv->data.d32))
2630 array_size -= sizeof(iv->data.d32);
2632 value = get_unaligned_be32(&iv->data.d32);
2633 b43_write32(dev, offset, value);
2635 iv = (const struct b43_iv *)((const uint8_t *)iv +
2641 if (array_size < sizeof(iv->data.d16))
2643 array_size -= sizeof(iv->data.d16);
2645 value = be16_to_cpu(iv->data.d16);
2646 b43_write16(dev, offset, value);
2648 iv = (const struct b43_iv *)((const uint8_t *)iv +
2659 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2660 b43_print_fw_helptext(dev->wl, 1);
2665 static int b43_upload_initvals(struct b43_wldev *dev)
2667 const size_t hdr_len = sizeof(struct b43_fw_header);
2668 const struct b43_fw_header *hdr;
2669 struct b43_firmware *fw = &dev->fw;
2670 const struct b43_iv *ivals;
2674 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2675 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2676 count = be32_to_cpu(hdr->size);
2677 err = b43_write_initvals(dev, ivals, count,
2678 fw->initvals.data->size - hdr_len);
2681 if (fw->initvals_band.data) {
2682 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2683 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2684 count = be32_to_cpu(hdr->size);
2685 err = b43_write_initvals(dev, ivals, count,
2686 fw->initvals_band.data->size - hdr_len);
2695 /* Initialize the GPIOs
2696 * http://bcm-specs.sipsolutions.net/GPIO
2698 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2700 struct ssb_bus *bus = dev->dev->sdev->bus;
2702 #ifdef CONFIG_SSB_DRIVER_PCICORE
2703 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2705 return bus->chipco.dev;
2709 static int b43_gpio_init(struct b43_wldev *dev)
2711 struct ssb_device *gpiodev;
2714 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2715 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2719 if (dev->dev->chip_id == 0x4301) {
2723 if (dev->dev->chip_id == 0x5354)
2725 if (0 /* FIXME: conditional unknown */ ) {
2726 b43_write16(dev, B43_MMIO_GPIO_MASK,
2727 b43_read16(dev, B43_MMIO_GPIO_MASK)
2732 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2733 b43_write16(dev, B43_MMIO_GPIO_MASK,
2734 b43_read16(dev, B43_MMIO_GPIO_MASK)
2739 if (dev->dev->core_rev >= 2)
2740 mask |= 0x0010; /* FIXME: This is redundant. */
2742 switch (dev->dev->bus_type) {
2743 #ifdef CONFIG_B43_BCMA
2745 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2746 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2747 BCMA_CC_GPIOCTL) & mask) | set);
2750 #ifdef CONFIG_B43_SSB
2752 gpiodev = b43_ssb_gpio_dev(dev);
2754 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2755 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2764 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2765 static void b43_gpio_cleanup(struct b43_wldev *dev)
2767 struct ssb_device *gpiodev;
2769 switch (dev->dev->bus_type) {
2770 #ifdef CONFIG_B43_BCMA
2772 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2776 #ifdef CONFIG_B43_SSB
2778 gpiodev = b43_ssb_gpio_dev(dev);
2780 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2786 /* http://bcm-specs.sipsolutions.net/EnableMac */
2787 void b43_mac_enable(struct b43_wldev *dev)
2789 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2792 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2793 B43_SHM_SH_UCODESTAT);
2794 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2795 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2796 b43err(dev->wl, "b43_mac_enable(): The firmware "
2797 "should be suspended, but current state is %u\n",
2802 dev->mac_suspended--;
2803 B43_WARN_ON(dev->mac_suspended < 0);
2804 if (dev->mac_suspended == 0) {
2805 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2806 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2807 B43_IRQ_MAC_SUSPENDED);
2809 b43_read32(dev, B43_MMIO_MACCTL);
2810 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2811 b43_power_saving_ctl_bits(dev, 0);
2815 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2816 void b43_mac_suspend(struct b43_wldev *dev)
2822 B43_WARN_ON(dev->mac_suspended < 0);
2824 if (dev->mac_suspended == 0) {
2825 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2826 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2827 /* force pci to flush the write */
2828 b43_read32(dev, B43_MMIO_MACCTL);
2829 for (i = 35; i; i--) {
2830 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2831 if (tmp & B43_IRQ_MAC_SUSPENDED)
2835 /* Hm, it seems this will take some time. Use msleep(). */
2836 for (i = 40; i; i--) {
2837 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2838 if (tmp & B43_IRQ_MAC_SUSPENDED)
2842 b43err(dev->wl, "MAC suspend failed\n");
2845 dev->mac_suspended++;
2848 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2849 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2853 switch (dev->dev->bus_type) {
2854 #ifdef CONFIG_B43_BCMA
2856 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2858 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2860 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2861 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2864 #ifdef CONFIG_B43_SSB
2866 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2868 tmp |= B43_TMSLOW_MACPHYCLKEN;
2870 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2871 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2877 static void b43_adjust_opmode(struct b43_wldev *dev)
2879 struct b43_wl *wl = dev->wl;
2883 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2884 /* Reset status to STA infrastructure mode. */
2885 ctl &= ~B43_MACCTL_AP;
2886 ctl &= ~B43_MACCTL_KEEP_CTL;
2887 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2888 ctl &= ~B43_MACCTL_KEEP_BAD;
2889 ctl &= ~B43_MACCTL_PROMISC;
2890 ctl &= ~B43_MACCTL_BEACPROMISC;
2891 ctl |= B43_MACCTL_INFRA;
2893 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2894 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2895 ctl |= B43_MACCTL_AP;
2896 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2897 ctl &= ~B43_MACCTL_INFRA;
2899 if (wl->filter_flags & FIF_CONTROL)
2900 ctl |= B43_MACCTL_KEEP_CTL;
2901 if (wl->filter_flags & FIF_FCSFAIL)
2902 ctl |= B43_MACCTL_KEEP_BAD;
2903 if (wl->filter_flags & FIF_PLCPFAIL)
2904 ctl |= B43_MACCTL_KEEP_BADPLCP;
2905 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2906 ctl |= B43_MACCTL_PROMISC;
2907 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2908 ctl |= B43_MACCTL_BEACPROMISC;
2910 /* Workaround: On old hardware the HW-MAC-address-filter
2911 * doesn't work properly, so always run promisc in filter
2912 * it in software. */
2913 if (dev->dev->core_rev <= 4)
2914 ctl |= B43_MACCTL_PROMISC;
2916 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2919 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2920 if (dev->dev->chip_id == 0x4306 &&
2921 dev->dev->chip_rev == 3)
2926 b43_write16(dev, 0x612, cfp_pretbtt);
2928 /* FIXME: We don't currently implement the PMQ mechanism,
2929 * so always disable it. If we want to implement PMQ,
2930 * we need to enable it here (clear DISCPMQ) in AP mode.
2932 if (0 /* ctl & B43_MACCTL_AP */)
2933 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2935 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2938 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2944 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2947 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2949 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2950 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2953 static void b43_rate_memory_init(struct b43_wldev *dev)
2955 switch (dev->phy.type) {
2959 case B43_PHYTYPE_LP:
2960 case B43_PHYTYPE_HT:
2961 case B43_PHYTYPE_LCN:
2962 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2963 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2967 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2968 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2969 if (dev->phy.type == B43_PHYTYPE_A)
2973 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2974 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2975 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2976 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2983 /* Set the default values for the PHY TX Control Words. */
2984 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2988 ctl |= B43_TXH_PHY_ENC_CCK;
2989 ctl |= B43_TXH_PHY_ANT01AUTO;
2990 ctl |= B43_TXH_PHY_TXPWR;
2992 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2993 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2994 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2997 /* Set the TX-Antenna for management frames sent by firmware. */
2998 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3003 ant = b43_antenna_to_phyctl(antenna);
3006 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3007 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3008 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3009 /* For Probe Resposes */
3010 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3011 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3012 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3015 /* This is the opposite of b43_chip_init() */
3016 static void b43_chip_exit(struct b43_wldev *dev)
3019 b43_gpio_cleanup(dev);
3020 /* firmware is released later */
3023 /* Initialize the chip
3024 * http://bcm-specs.sipsolutions.net/ChipInit
3026 static int b43_chip_init(struct b43_wldev *dev)
3028 struct b43_phy *phy = &dev->phy;
3033 /* Initialize the MAC control */
3034 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3036 macctl |= B43_MACCTL_GMODE;
3037 macctl |= B43_MACCTL_INFRA;
3038 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3040 err = b43_upload_microcode(dev);
3042 goto out; /* firmware is released later */
3044 err = b43_gpio_init(dev);
3046 goto out; /* firmware is released later */
3048 err = b43_upload_initvals(dev);
3050 goto err_gpio_clean;
3052 /* Turn the Analog on and initialize the PHY. */
3053 phy->ops->switch_analog(dev, 1);
3054 err = b43_phy_init(dev);
3056 goto err_gpio_clean;
3058 /* Disable Interference Mitigation. */
3059 if (phy->ops->interf_mitigation)
3060 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3062 /* Select the antennae */
3063 if (phy->ops->set_rx_antenna)
3064 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3065 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3067 if (phy->type == B43_PHYTYPE_B) {
3068 value16 = b43_read16(dev, 0x005E);
3070 b43_write16(dev, 0x005E, value16);
3072 b43_write32(dev, 0x0100, 0x01000000);
3073 if (dev->dev->core_rev < 5)
3074 b43_write32(dev, 0x010C, 0x01000000);
3076 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3077 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3079 /* Probe Response Timeout value */
3080 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3081 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3083 /* Initially set the wireless operation mode. */
3084 b43_adjust_opmode(dev);
3086 if (dev->dev->core_rev < 3) {
3087 b43_write16(dev, 0x060E, 0x0000);
3088 b43_write16(dev, 0x0610, 0x8000);
3089 b43_write16(dev, 0x0604, 0x0000);
3090 b43_write16(dev, 0x0606, 0x0200);
3092 b43_write32(dev, 0x0188, 0x80000000);
3093 b43_write32(dev, 0x018C, 0x02000000);
3095 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3096 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3097 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3098 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3099 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3100 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3103 b43_mac_phy_clock_set(dev, true);
3105 switch (dev->dev->bus_type) {
3106 #ifdef CONFIG_B43_BCMA
3108 /* FIXME: 0xE74 is quite common, but should be read from CC */
3109 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3112 #ifdef CONFIG_B43_SSB
3114 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3115 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3121 b43dbg(dev->wl, "Chip initialized\n");
3126 b43_gpio_cleanup(dev);
3130 static void b43_periodic_every60sec(struct b43_wldev *dev)
3132 const struct b43_phy_operations *ops = dev->phy.ops;
3134 if (ops->pwork_60sec)
3135 ops->pwork_60sec(dev);
3137 /* Force check the TX power emission now. */
3138 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3141 static void b43_periodic_every30sec(struct b43_wldev *dev)
3143 /* Update device statistics. */
3144 b43_calculate_link_quality(dev);
3147 static void b43_periodic_every15sec(struct b43_wldev *dev)
3149 struct b43_phy *phy = &dev->phy;
3152 if (dev->fw.opensource) {
3153 /* Check if the firmware is still alive.
3154 * It will reset the watchdog counter to 0 in its idle loop. */
3155 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3156 if (unlikely(wdr)) {
3157 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3158 b43_controller_restart(dev, "Firmware watchdog");
3161 b43_shm_write16(dev, B43_SHM_SCRATCH,
3162 B43_WATCHDOG_REG, 1);
3166 if (phy->ops->pwork_15sec)
3167 phy->ops->pwork_15sec(dev);
3169 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3173 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3176 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3177 dev->irq_count / 15,
3179 dev->rx_count / 15);
3183 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3184 if (dev->irq_bit_count[i]) {
3185 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3186 dev->irq_bit_count[i] / 15, i, (1 << i));
3187 dev->irq_bit_count[i] = 0;
3194 static void do_periodic_work(struct b43_wldev *dev)
3198 state = dev->periodic_state;
3200 b43_periodic_every60sec(dev);
3202 b43_periodic_every30sec(dev);
3203 b43_periodic_every15sec(dev);
3206 /* Periodic work locking policy:
3207 * The whole periodic work handler is protected by
3208 * wl->mutex. If another lock is needed somewhere in the
3209 * pwork callchain, it's acquired in-place, where it's needed.
3211 static void b43_periodic_work_handler(struct work_struct *work)
3213 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3214 periodic_work.work);
3215 struct b43_wl *wl = dev->wl;
3216 unsigned long delay;
3218 mutex_lock(&wl->mutex);
3220 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3222 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3225 do_periodic_work(dev);
3227 dev->periodic_state++;
3229 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3230 delay = msecs_to_jiffies(50);
3232 delay = round_jiffies_relative(HZ * 15);
3233 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3235 mutex_unlock(&wl->mutex);
3238 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3240 struct delayed_work *work = &dev->periodic_work;
3242 dev->periodic_state = 0;
3243 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3244 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3247 /* Check if communication with the device works correctly. */
3248 static int b43_validate_chipaccess(struct b43_wldev *dev)
3250 u32 v, backup0, backup4;
3252 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3253 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3255 /* Check for read/write and endianness problems. */
3256 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3257 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3259 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3260 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3263 /* Check if unaligned 32bit SHM_SHARED access works properly.
3264 * However, don't bail out on failure, because it's noncritical. */
3265 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3266 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3267 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3268 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3269 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3270 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3271 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3272 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3273 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3274 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3275 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3276 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3278 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3279 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3281 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3282 /* The 32bit register shadows the two 16bit registers
3283 * with update sideeffects. Validate this. */
3284 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3285 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3286 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3288 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3291 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3293 v = b43_read32(dev, B43_MMIO_MACCTL);
3294 v |= B43_MACCTL_GMODE;
3295 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3300 b43err(dev->wl, "Failed to validate the chipaccess\n");
3304 static void b43_security_init(struct b43_wldev *dev)
3306 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3307 /* KTP is a word address, but we address SHM bytewise.
3308 * So multiply by two.
3311 /* Number of RCMTA address slots */
3312 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3313 /* Clear the key memory. */
3314 b43_clear_keys(dev);
3317 #ifdef CONFIG_B43_HWRNG
3318 static int b43_rng_read(struct hwrng *rng, u32 *data)
3320 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3321 struct b43_wldev *dev;
3322 int count = -ENODEV;
3324 mutex_lock(&wl->mutex);
3325 dev = wl->current_dev;
3326 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3327 *data = b43_read16(dev, B43_MMIO_RNG);
3328 count = sizeof(u16);
3330 mutex_unlock(&wl->mutex);
3334 #endif /* CONFIG_B43_HWRNG */
3336 static void b43_rng_exit(struct b43_wl *wl)
3338 #ifdef CONFIG_B43_HWRNG
3339 if (wl->rng_initialized)
3340 hwrng_unregister(&wl->rng);
3341 #endif /* CONFIG_B43_HWRNG */
3344 static int b43_rng_init(struct b43_wl *wl)
3348 #ifdef CONFIG_B43_HWRNG
3349 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3350 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3351 wl->rng.name = wl->rng_name;
3352 wl->rng.data_read = b43_rng_read;
3353 wl->rng.priv = (unsigned long)wl;
3354 wl->rng_initialized = true;
3355 err = hwrng_register(&wl->rng);
3357 wl->rng_initialized = false;
3358 b43err(wl, "Failed to register the random "
3359 "number generator (%d)\n", err);
3361 #endif /* CONFIG_B43_HWRNG */
3366 static void b43_tx_work(struct work_struct *work)
3368 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3369 struct b43_wldev *dev;
3370 struct sk_buff *skb;
3374 mutex_lock(&wl->mutex);
3375 dev = wl->current_dev;
3376 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3377 mutex_unlock(&wl->mutex);
3381 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3382 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3383 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3384 if (b43_using_pio_transfers(dev))
3385 err = b43_pio_tx(dev, skb);
3387 err = b43_dma_tx(dev, skb);
3388 if (err == -ENOSPC) {
3389 wl->tx_queue_stopped[queue_num] = 1;
3390 ieee80211_stop_queue(wl->hw, queue_num);
3391 skb_queue_head(&wl->tx_queue[queue_num], skb);
3395 dev_kfree_skb(skb); /* Drop it */
3400 wl->tx_queue_stopped[queue_num] = 0;
3406 mutex_unlock(&wl->mutex);
3409 static void b43_op_tx(struct ieee80211_hw *hw,
3410 struct ieee80211_tx_control *control,
3411 struct sk_buff *skb)
3413 struct b43_wl *wl = hw_to_b43_wl(hw);
3415 if (unlikely(skb->len < 2 + 2 + 6)) {
3416 /* Too short, this can't be a valid frame. */
3417 dev_kfree_skb_any(skb);
3420 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3422 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3423 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3424 ieee80211_queue_work(wl->hw, &wl->tx_work);
3426 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3430 static void b43_qos_params_upload(struct b43_wldev *dev,
3431 const struct ieee80211_tx_queue_params *p,
3434 u16 params[B43_NR_QOSPARAMS];
3438 if (!dev->qos_enabled)
3441 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3443 memset(¶ms, 0, sizeof(params));
3445 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3446 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3447 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3448 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3449 params[B43_QOSPARAM_AIFS] = p->aifs;
3450 params[B43_QOSPARAM_BSLOTS] = bslots;
3451 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3453 for (i = 0; i < ARRAY_SIZE(params); i++) {
3454 if (i == B43_QOSPARAM_STATUS) {
3455 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3456 shm_offset + (i * 2));
3457 /* Mark the parameters as updated. */
3459 b43_shm_write16(dev, B43_SHM_SHARED,
3460 shm_offset + (i * 2),
3463 b43_shm_write16(dev, B43_SHM_SHARED,
3464 shm_offset + (i * 2),
3470 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3471 static const u16 b43_qos_shm_offsets[] = {
3472 /* [mac80211-queue-nr] = SHM_OFFSET, */
3473 [0] = B43_QOS_VOICE,
3474 [1] = B43_QOS_VIDEO,
3475 [2] = B43_QOS_BESTEFFORT,
3476 [3] = B43_QOS_BACKGROUND,
3479 /* Update all QOS parameters in hardware. */
3480 static void b43_qos_upload_all(struct b43_wldev *dev)
3482 struct b43_wl *wl = dev->wl;
3483 struct b43_qos_params *params;
3486 if (!dev->qos_enabled)
3489 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3490 ARRAY_SIZE(wl->qos_params));
3492 b43_mac_suspend(dev);
3493 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3494 params = &(wl->qos_params[i]);
3495 b43_qos_params_upload(dev, &(params->p),
3496 b43_qos_shm_offsets[i]);
3498 b43_mac_enable(dev);
3501 static void b43_qos_clear(struct b43_wl *wl)
3503 struct b43_qos_params *params;
3506 /* Initialize QoS parameters to sane defaults. */
3508 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3509 ARRAY_SIZE(wl->qos_params));
3511 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3512 params = &(wl->qos_params[i]);
3514 switch (b43_qos_shm_offsets[i]) {
3518 params->p.cw_min = 0x0001;
3519 params->p.cw_max = 0x0001;
3524 params->p.cw_min = 0x0001;
3525 params->p.cw_max = 0x0001;
3527 case B43_QOS_BESTEFFORT:
3530 params->p.cw_min = 0x0001;
3531 params->p.cw_max = 0x03FF;
3533 case B43_QOS_BACKGROUND:
3536 params->p.cw_min = 0x0001;
3537 params->p.cw_max = 0x03FF;
3545 /* Initialize the core's QOS capabilities */
3546 static void b43_qos_init(struct b43_wldev *dev)
3548 if (!dev->qos_enabled) {
3549 /* Disable QOS support. */
3550 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3551 b43_write16(dev, B43_MMIO_IFSCTL,
3552 b43_read16(dev, B43_MMIO_IFSCTL)
3553 & ~B43_MMIO_IFSCTL_USE_EDCF);
3554 b43dbg(dev->wl, "QoS disabled\n");
3558 /* Upload the current QOS parameters. */
3559 b43_qos_upload_all(dev);
3561 /* Enable QOS support. */
3562 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3563 b43_write16(dev, B43_MMIO_IFSCTL,
3564 b43_read16(dev, B43_MMIO_IFSCTL)
3565 | B43_MMIO_IFSCTL_USE_EDCF);
3566 b43dbg(dev->wl, "QoS enabled\n");
3569 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3570 struct ieee80211_vif *vif, u16 _queue,
3571 const struct ieee80211_tx_queue_params *params)
3573 struct b43_wl *wl = hw_to_b43_wl(hw);
3574 struct b43_wldev *dev;
3575 unsigned int queue = (unsigned int)_queue;
3578 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3579 /* Queue not available or don't support setting
3580 * params on this queue. Return success to not
3581 * confuse mac80211. */
3584 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3585 ARRAY_SIZE(wl->qos_params));
3587 mutex_lock(&wl->mutex);
3588 dev = wl->current_dev;
3589 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3592 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3593 b43_mac_suspend(dev);
3594 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3595 b43_qos_shm_offsets[queue]);
3596 b43_mac_enable(dev);
3600 mutex_unlock(&wl->mutex);
3605 static int b43_op_get_stats(struct ieee80211_hw *hw,
3606 struct ieee80211_low_level_stats *stats)
3608 struct b43_wl *wl = hw_to_b43_wl(hw);
3610 mutex_lock(&wl->mutex);
3611 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3612 mutex_unlock(&wl->mutex);
3617 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3619 struct b43_wl *wl = hw_to_b43_wl(hw);
3620 struct b43_wldev *dev;
3623 mutex_lock(&wl->mutex);
3624 dev = wl->current_dev;
3626 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3627 b43_tsf_read(dev, &tsf);
3631 mutex_unlock(&wl->mutex);
3636 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3637 struct ieee80211_vif *vif, u64 tsf)
3639 struct b43_wl *wl = hw_to_b43_wl(hw);
3640 struct b43_wldev *dev;
3642 mutex_lock(&wl->mutex);
3643 dev = wl->current_dev;
3645 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3646 b43_tsf_write(dev, tsf);
3648 mutex_unlock(&wl->mutex);
3651 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3655 switch (dev->dev->bus_type) {
3656 #ifdef CONFIG_B43_BCMA
3659 "Putting PHY into reset not supported on BCMA\n");
3662 #ifdef CONFIG_B43_SSB
3664 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3665 tmp &= ~B43_TMSLOW_GMODE;
3666 tmp |= B43_TMSLOW_PHYRESET;
3667 tmp |= SSB_TMSLOW_FGC;
3668 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3671 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3672 tmp &= ~SSB_TMSLOW_FGC;
3673 tmp |= B43_TMSLOW_PHYRESET;
3674 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3682 static const char *band_to_string(enum ieee80211_band band)
3685 case IEEE80211_BAND_5GHZ:
3687 case IEEE80211_BAND_2GHZ:
3696 /* Expects wl->mutex locked */
3697 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3699 struct b43_wldev *up_dev = NULL;
3700 struct b43_wldev *down_dev;
3701 struct b43_wldev *d;
3703 bool uninitialized_var(gmode);
3706 /* Find a device and PHY which supports the band. */
3707 list_for_each_entry(d, &wl->devlist, list) {
3708 switch (chan->band) {
3709 case IEEE80211_BAND_5GHZ:
3710 if (d->phy.supports_5ghz) {
3715 case IEEE80211_BAND_2GHZ:
3716 if (d->phy.supports_2ghz) {
3729 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3730 band_to_string(chan->band));
3733 if ((up_dev == wl->current_dev) &&
3734 (!!wl->current_dev->phy.gmode == !!gmode)) {
3735 /* This device is already running. */
3738 b43dbg(wl, "Switching to %s-GHz band\n",
3739 band_to_string(chan->band));
3740 down_dev = wl->current_dev;
3742 prev_status = b43_status(down_dev);
3743 /* Shutdown the currently running core. */
3744 if (prev_status >= B43_STAT_STARTED)
3745 down_dev = b43_wireless_core_stop(down_dev);
3746 if (prev_status >= B43_STAT_INITIALIZED)
3747 b43_wireless_core_exit(down_dev);
3749 if (down_dev != up_dev) {
3750 /* We switch to a different core, so we put PHY into
3751 * RESET on the old core. */
3752 b43_put_phy_into_reset(down_dev);
3755 /* Now start the new core. */
3756 up_dev->phy.gmode = gmode;
3757 if (prev_status >= B43_STAT_INITIALIZED) {
3758 err = b43_wireless_core_init(up_dev);
3760 b43err(wl, "Fatal: Could not initialize device for "
3761 "selected %s-GHz band\n",
3762 band_to_string(chan->band));
3766 if (prev_status >= B43_STAT_STARTED) {
3767 err = b43_wireless_core_start(up_dev);
3769 b43err(wl, "Fatal: Could not start device for "
3770 "selected %s-GHz band\n",
3771 band_to_string(chan->band));
3772 b43_wireless_core_exit(up_dev);
3776 B43_WARN_ON(b43_status(up_dev) != prev_status);
3778 wl->current_dev = up_dev;
3782 /* Whoops, failed to init the new core. No core is operating now. */
3783 wl->current_dev = NULL;
3787 /* Write the short and long frame retry limit values. */
3788 static void b43_set_retry_limits(struct b43_wldev *dev,
3789 unsigned int short_retry,
3790 unsigned int long_retry)
3792 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3793 * the chip-internal counter. */
3794 short_retry = min(short_retry, (unsigned int)0xF);
3795 long_retry = min(long_retry, (unsigned int)0xF);
3797 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3799 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3803 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3805 struct b43_wl *wl = hw_to_b43_wl(hw);
3806 struct b43_wldev *dev;
3807 struct b43_phy *phy;
3808 struct ieee80211_conf *conf = &hw->conf;
3811 bool reload_bss = false;
3813 mutex_lock(&wl->mutex);
3815 dev = wl->current_dev;
3817 /* Switch the band (if necessary). This might change the active core. */
3818 err = b43_switch_band(wl, conf->channel);
3820 goto out_unlock_mutex;
3822 /* Need to reload all settings if the core changed */
3823 if (dev != wl->current_dev) {
3824 dev = wl->current_dev;
3831 if (conf_is_ht(conf))
3833 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3835 phy->is_40mhz = false;
3837 b43_mac_suspend(dev);
3839 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3840 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3841 conf->long_frame_max_tx_count);
3842 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3844 goto out_mac_enable;
3846 /* Switch to the requested channel.
3847 * The firmware takes care of races with the TX handler. */
3848 if (conf->channel->hw_value != phy->channel)
3849 b43_switch_channel(dev, conf->channel->hw_value);
3851 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3853 /* Adjust the desired TX power level. */
3854 if (conf->power_level != 0) {
3855 if (conf->power_level != phy->desired_txpower) {
3856 phy->desired_txpower = conf->power_level;
3857 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3858 B43_TXPWR_IGNORE_TSSI);
3862 /* Antennas for RX and management frame TX. */
3863 antenna = B43_ANTENNA_DEFAULT;
3864 b43_mgmtframe_txantenna(dev, antenna);
3865 antenna = B43_ANTENNA_DEFAULT;
3866 if (phy->ops->set_rx_antenna)
3867 phy->ops->set_rx_antenna(dev, antenna);
3869 if (wl->radio_enabled != phy->radio_on) {
3870 if (wl->radio_enabled) {
3871 b43_software_rfkill(dev, false);
3872 b43info(dev->wl, "Radio turned on by software\n");
3873 if (!dev->radio_hw_enable) {
3874 b43info(dev->wl, "The hardware RF-kill button "
3875 "still turns the radio physically off. "
3876 "Press the button to turn it on.\n");
3879 b43_software_rfkill(dev, true);
3880 b43info(dev->wl, "Radio turned off by software\n");
3885 b43_mac_enable(dev);
3887 mutex_unlock(&wl->mutex);
3889 if (wl->vif && reload_bss)
3890 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3895 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3897 struct ieee80211_supported_band *sband =
3898 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3899 struct ieee80211_rate *rate;
3901 u16 basic, direct, offset, basic_offset, rateptr;
3903 for (i = 0; i < sband->n_bitrates; i++) {
3904 rate = &sband->bitrates[i];
3906 if (b43_is_cck_rate(rate->hw_value)) {
3907 direct = B43_SHM_SH_CCKDIRECT;
3908 basic = B43_SHM_SH_CCKBASIC;
3909 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3912 direct = B43_SHM_SH_OFDMDIRECT;
3913 basic = B43_SHM_SH_OFDMBASIC;
3914 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3918 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3920 if (b43_is_cck_rate(rate->hw_value)) {
3921 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3922 basic_offset &= 0xF;
3924 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3925 basic_offset &= 0xF;
3929 * Get the pointer that we need to point to
3930 * from the direct map
3932 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3933 direct + 2 * basic_offset);
3934 /* and write it to the basic map */
3935 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3940 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3941 struct ieee80211_vif *vif,
3942 struct ieee80211_bss_conf *conf,
3945 struct b43_wl *wl = hw_to_b43_wl(hw);
3946 struct b43_wldev *dev;
3948 mutex_lock(&wl->mutex);
3950 dev = wl->current_dev;
3951 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3952 goto out_unlock_mutex;
3954 B43_WARN_ON(wl->vif != vif);
3956 if (changed & BSS_CHANGED_BSSID) {
3958 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3960 memset(wl->bssid, 0, ETH_ALEN);
3963 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3964 if (changed & BSS_CHANGED_BEACON &&
3965 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3966 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3967 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3968 b43_update_templates(wl);
3970 if (changed & BSS_CHANGED_BSSID)
3971 b43_write_mac_bssid_templates(dev);
3974 b43_mac_suspend(dev);
3976 /* Update templates for AP/mesh mode. */
3977 if (changed & BSS_CHANGED_BEACON_INT &&
3978 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3979 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3980 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3982 b43_set_beacon_int(dev, conf->beacon_int);
3984 if (changed & BSS_CHANGED_BASIC_RATES)
3985 b43_update_basic_rates(dev, conf->basic_rates);
3987 if (changed & BSS_CHANGED_ERP_SLOT) {
3988 if (conf->use_short_slot)
3989 b43_short_slot_timing_enable(dev);
3991 b43_short_slot_timing_disable(dev);
3994 b43_mac_enable(dev);
3996 mutex_unlock(&wl->mutex);
3999 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4000 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4001 struct ieee80211_key_conf *key)
4003 struct b43_wl *wl = hw_to_b43_wl(hw);
4004 struct b43_wldev *dev;
4008 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4010 if (modparam_nohwcrypt)
4011 return -ENOSPC; /* User disabled HW-crypto */
4013 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4014 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4015 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4016 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4017 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4019 * For now, disable hw crypto for the RSN IBSS group keys. This
4020 * could be optimized in the future, but until that gets
4021 * implemented, use of software crypto for group addressed
4022 * frames is a acceptable to allow RSN IBSS to be used.
4027 mutex_lock(&wl->mutex);
4029 dev = wl->current_dev;
4031 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4034 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4035 /* We don't have firmware for the crypto engine.
4036 * Must use software-crypto. */
4042 switch (key->cipher) {
4043 case WLAN_CIPHER_SUITE_WEP40:
4044 algorithm = B43_SEC_ALGO_WEP40;
4046 case WLAN_CIPHER_SUITE_WEP104:
4047 algorithm = B43_SEC_ALGO_WEP104;
4049 case WLAN_CIPHER_SUITE_TKIP:
4050 algorithm = B43_SEC_ALGO_TKIP;
4052 case WLAN_CIPHER_SUITE_CCMP:
4053 algorithm = B43_SEC_ALGO_AES;
4059 index = (u8) (key->keyidx);
4065 if (algorithm == B43_SEC_ALGO_TKIP &&
4066 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4067 !modparam_hwtkip)) {
4068 /* We support only pairwise key */
4073 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4074 if (WARN_ON(!sta)) {
4078 /* Pairwise key with an assigned MAC address. */
4079 err = b43_key_write(dev, -1, algorithm,
4080 key->key, key->keylen,
4084 err = b43_key_write(dev, index, algorithm,
4085 key->key, key->keylen, NULL, key);
4090 if (algorithm == B43_SEC_ALGO_WEP40 ||
4091 algorithm == B43_SEC_ALGO_WEP104) {
4092 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4095 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4097 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4098 if (algorithm == B43_SEC_ALGO_TKIP)
4099 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4102 err = b43_key_clear(dev, key->hw_key_idx);
4113 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4115 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4116 sta ? sta->addr : bcast_addr);
4117 b43_dump_keymemory(dev);
4119 mutex_unlock(&wl->mutex);
4124 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4125 unsigned int changed, unsigned int *fflags,
4128 struct b43_wl *wl = hw_to_b43_wl(hw);
4129 struct b43_wldev *dev;
4131 mutex_lock(&wl->mutex);
4132 dev = wl->current_dev;
4138 *fflags &= FIF_PROMISC_IN_BSS |
4144 FIF_BCN_PRBRESP_PROMISC;
4146 changed &= FIF_PROMISC_IN_BSS |
4152 FIF_BCN_PRBRESP_PROMISC;
4154 wl->filter_flags = *fflags;
4156 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4157 b43_adjust_opmode(dev);
4160 mutex_unlock(&wl->mutex);
4163 /* Locking: wl->mutex
4164 * Returns the current dev. This might be different from the passed in dev,
4165 * because the core might be gone away while we unlocked the mutex. */
4166 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4169 struct b43_wldev *orig_dev;
4177 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4180 /* Cancel work. Unlock to avoid deadlocks. */
4181 mutex_unlock(&wl->mutex);
4182 cancel_delayed_work_sync(&dev->periodic_work);
4183 cancel_work_sync(&wl->tx_work);
4184 cancel_work_sync(&wl->firmware_load);
4185 mutex_lock(&wl->mutex);
4186 dev = wl->current_dev;
4187 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4188 /* Whoops, aliens ate up the device while we were unlocked. */
4192 /* Disable interrupts on the device. */
4193 b43_set_status(dev, B43_STAT_INITIALIZED);
4194 if (b43_bus_host_is_sdio(dev->dev)) {
4195 /* wl->mutex is locked. That is enough. */
4196 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4197 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4199 spin_lock_irq(&wl->hardirq_lock);
4200 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4201 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4202 spin_unlock_irq(&wl->hardirq_lock);
4204 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4206 mutex_unlock(&wl->mutex);
4207 if (b43_bus_host_is_sdio(dev->dev)) {
4208 b43_sdio_free_irq(dev);
4210 synchronize_irq(dev->dev->irq);
4211 free_irq(dev->dev->irq, dev);
4213 mutex_lock(&wl->mutex);
4214 dev = wl->current_dev;
4217 if (dev != orig_dev) {
4218 if (b43_status(dev) >= B43_STAT_STARTED)
4222 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4223 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4225 /* Drain all TX queues. */
4226 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4227 while (skb_queue_len(&wl->tx_queue[queue_num]))
4228 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
4231 b43_mac_suspend(dev);
4233 b43dbg(wl, "Wireless interface stopped\n");
4238 /* Locking: wl->mutex */
4239 static int b43_wireless_core_start(struct b43_wldev *dev)
4243 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4245 drain_txstatus_queue(dev);
4246 if (b43_bus_host_is_sdio(dev->dev)) {
4247 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4249 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4253 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4254 b43_interrupt_thread_handler,
4255 IRQF_SHARED, KBUILD_MODNAME, dev);
4257 b43err(dev->wl, "Cannot request IRQ-%d\n",
4263 /* We are ready to run. */
4264 ieee80211_wake_queues(dev->wl->hw);
4265 b43_set_status(dev, B43_STAT_STARTED);
4267 /* Start data flow (TX/RX). */
4268 b43_mac_enable(dev);
4269 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4271 /* Start maintenance work */
4272 b43_periodic_tasks_setup(dev);
4276 b43dbg(dev->wl, "Wireless interface started\n");
4281 /* Get PHY and RADIO versioning numbers */
4282 static int b43_phy_versioning(struct b43_wldev *dev)
4284 struct b43_phy *phy = &dev->phy;
4292 int unsupported = 0;
4294 /* Get PHY versioning */
4295 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4296 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4297 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4298 phy_rev = (tmp & B43_PHYVER_VERSION);
4305 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4313 #ifdef CONFIG_B43_PHY_N
4319 #ifdef CONFIG_B43_PHY_LP
4320 case B43_PHYTYPE_LP:
4325 #ifdef CONFIG_B43_PHY_HT
4326 case B43_PHYTYPE_HT:
4331 #ifdef CONFIG_B43_PHY_LCN
4332 case B43_PHYTYPE_LCN:
4341 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4342 "(Analog %u, Type %u, Revision %u)\n",
4343 analog_type, phy_type, phy_rev);
4346 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4347 analog_type, phy_type, phy_rev);
4349 /* Get RADIO versioning */
4350 if (dev->dev->core_rev >= 24) {
4353 for (tmp = 0; tmp < 3; tmp++) {
4354 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4355 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4358 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4359 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4361 radio_manuf = 0x17F;
4362 radio_ver = (radio24[2] << 8) | radio24[1];
4363 radio_rev = (radio24[0] & 0xF);
4365 if (dev->dev->chip_id == 0x4317) {
4366 if (dev->dev->chip_rev == 0)
4368 else if (dev->dev->chip_rev == 1)
4373 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4375 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4376 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4378 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4381 radio_manuf = (tmp & 0x00000FFF);
4382 radio_ver = (tmp & 0x0FFFF000) >> 12;
4383 radio_rev = (tmp & 0xF0000000) >> 28;
4386 if (radio_manuf != 0x17F /* Broadcom */)
4390 if (radio_ver != 0x2060)
4394 if (radio_manuf != 0x17F)
4398 if ((radio_ver & 0xFFF0) != 0x2050)
4402 if (radio_ver != 0x2050)
4406 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4409 case B43_PHYTYPE_LP:
4410 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4413 case B43_PHYTYPE_HT:
4414 if (radio_ver != 0x2059)
4417 case B43_PHYTYPE_LCN:
4418 if (radio_ver != 0x2064)
4425 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4426 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4427 radio_manuf, radio_ver, radio_rev);
4430 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4431 radio_manuf, radio_ver, radio_rev);
4433 phy->radio_manuf = radio_manuf;
4434 phy->radio_ver = radio_ver;
4435 phy->radio_rev = radio_rev;
4437 phy->analog = analog_type;
4438 phy->type = phy_type;
4444 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4445 struct b43_phy *phy)
4447 phy->hardware_power_control = !!modparam_hwpctl;
4448 phy->next_txpwr_check_time = jiffies;
4449 /* PHY TX errors counter. */
4450 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4453 phy->phy_locked = false;
4454 phy->radio_locked = false;
4458 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4460 dev->dfq_valid = false;
4462 /* Assume the radio is enabled. If it's not enabled, the state will
4463 * immediately get fixed on the first periodic work run. */
4464 dev->radio_hw_enable = true;
4467 memset(&dev->stats, 0, sizeof(dev->stats));
4469 setup_struct_phy_for_init(dev, &dev->phy);
4471 /* IRQ related flags */
4472 dev->irq_reason = 0;
4473 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4474 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4475 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4476 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4478 dev->mac_suspended = 1;
4480 /* Noise calculation context */
4481 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4484 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4486 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4489 if (!modparam_btcoex)
4491 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4493 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4496 hf = b43_hf_read(dev);
4497 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4498 hf |= B43_HF_BTCOEXALT;
4500 hf |= B43_HF_BTCOEX;
4501 b43_hf_write(dev, hf);
4504 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4506 if (!modparam_btcoex)
4511 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4513 struct ssb_bus *bus;
4516 if (dev->dev->bus_type != B43_BUS_SSB)
4519 bus = dev->dev->sdev->bus;
4521 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4522 (bus->chip_id == 0x4312)) {
4523 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4524 tmp &= ~SSB_IMCFGLO_REQTO;
4525 tmp &= ~SSB_IMCFGLO_SERTO;
4527 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4528 ssb_commit_settings(bus);
4532 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4536 /* The time value is in microseconds. */
4537 if (dev->phy.type == B43_PHYTYPE_A)
4541 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4543 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4544 pu_delay = max(pu_delay, (u16)2400);
4546 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4549 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4550 static void b43_set_pretbtt(struct b43_wldev *dev)
4554 /* The time value is in microseconds. */
4555 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4558 if (dev->phy.type == B43_PHYTYPE_A)
4563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4564 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4567 /* Shutdown a wireless core */
4568 /* Locking: wl->mutex */
4569 static void b43_wireless_core_exit(struct b43_wldev *dev)
4571 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4572 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4575 /* Unregister HW RNG driver */
4576 b43_rng_exit(dev->wl);
4578 b43_set_status(dev, B43_STAT_UNINIT);
4580 /* Stop the microcode PSM. */
4581 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4582 B43_MACCTL_PSM_JMP0);
4587 dev->phy.ops->switch_analog(dev, 0);
4588 if (dev->wl->current_beacon) {
4589 dev_kfree_skb_any(dev->wl->current_beacon);
4590 dev->wl->current_beacon = NULL;
4593 b43_device_disable(dev, 0);
4594 b43_bus_may_powerdown(dev);
4597 /* Initialize a wireless core */
4598 static int b43_wireless_core_init(struct b43_wldev *dev)
4600 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4601 struct b43_phy *phy = &dev->phy;
4605 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4607 err = b43_bus_powerup(dev, 0);
4610 if (!b43_device_is_enabled(dev))
4611 b43_wireless_core_reset(dev, phy->gmode);
4613 /* Reset all data structures. */
4614 setup_struct_wldev_for_init(dev);
4615 phy->ops->prepare_structs(dev);
4617 /* Enable IRQ routing to this device. */
4618 switch (dev->dev->bus_type) {
4619 #ifdef CONFIG_B43_BCMA
4621 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4622 dev->dev->bdev, true);
4625 #ifdef CONFIG_B43_SSB
4627 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4633 b43_imcfglo_timeouts_workaround(dev);
4634 b43_bluetooth_coext_disable(dev);
4635 if (phy->ops->prepare_hardware) {
4636 err = phy->ops->prepare_hardware(dev);
4640 err = b43_chip_init(dev);
4643 b43_shm_write16(dev, B43_SHM_SHARED,
4644 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4645 hf = b43_hf_read(dev);
4646 if (phy->type == B43_PHYTYPE_G) {
4650 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4651 hf |= B43_HF_OFDMPABOOST;
4653 if (phy->radio_ver == 0x2050) {
4654 if (phy->radio_rev == 6)
4655 hf |= B43_HF_4318TSSI;
4656 if (phy->radio_rev < 6)
4657 hf |= B43_HF_VCORECALC;
4659 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4660 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4661 #ifdef CONFIG_SSB_DRIVER_PCICORE
4662 if (dev->dev->bus_type == B43_BUS_SSB &&
4663 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4664 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4665 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4667 hf &= ~B43_HF_SKCFPUP;
4668 b43_hf_write(dev, hf);
4670 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4671 B43_DEFAULT_LONG_RETRY_LIMIT);
4672 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4673 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4675 /* Disable sending probe responses from firmware.
4676 * Setting the MaxTime to one usec will always trigger
4677 * a timeout, so we never send any probe resp.
4678 * A timeout of zero is infinite. */
4679 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4681 b43_rate_memory_init(dev);
4682 b43_set_phytxctl_defaults(dev);
4684 /* Minimum Contention Window */
4685 if (phy->type == B43_PHYTYPE_B)
4686 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4688 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4689 /* Maximum Contention Window */
4690 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4692 if (b43_bus_host_is_pcmcia(dev->dev) ||
4693 b43_bus_host_is_sdio(dev->dev)) {
4694 dev->__using_pio_transfers = true;
4695 err = b43_pio_init(dev);
4696 } else if (dev->use_pio) {
4697 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4698 "This should not be needed and will result in lower "
4700 dev->__using_pio_transfers = true;
4701 err = b43_pio_init(dev);
4703 dev->__using_pio_transfers = false;
4704 err = b43_dma_init(dev);
4709 b43_set_synth_pu_delay(dev, 1);
4710 b43_bluetooth_coext_enable(dev);
4712 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4713 b43_upload_card_macaddress(dev);
4714 b43_security_init(dev);
4716 ieee80211_wake_queues(dev->wl->hw);
4718 b43_set_status(dev, B43_STAT_INITIALIZED);
4720 /* Register HW RNG driver */
4721 b43_rng_init(dev->wl);
4729 b43_bus_may_powerdown(dev);
4730 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4734 static int b43_op_add_interface(struct ieee80211_hw *hw,
4735 struct ieee80211_vif *vif)
4737 struct b43_wl *wl = hw_to_b43_wl(hw);
4738 struct b43_wldev *dev;
4739 int err = -EOPNOTSUPP;
4741 /* TODO: allow WDS/AP devices to coexist */
4743 if (vif->type != NL80211_IFTYPE_AP &&
4744 vif->type != NL80211_IFTYPE_MESH_POINT &&
4745 vif->type != NL80211_IFTYPE_STATION &&
4746 vif->type != NL80211_IFTYPE_WDS &&
4747 vif->type != NL80211_IFTYPE_ADHOC)
4750 mutex_lock(&wl->mutex);
4752 goto out_mutex_unlock;
4754 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4756 dev = wl->current_dev;
4757 wl->operating = true;
4759 wl->if_type = vif->type;
4760 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4762 b43_adjust_opmode(dev);
4763 b43_set_pretbtt(dev);
4764 b43_set_synth_pu_delay(dev, 0);
4765 b43_upload_card_macaddress(dev);
4769 mutex_unlock(&wl->mutex);
4772 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4777 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4778 struct ieee80211_vif *vif)
4780 struct b43_wl *wl = hw_to_b43_wl(hw);
4781 struct b43_wldev *dev = wl->current_dev;
4783 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4785 mutex_lock(&wl->mutex);
4787 B43_WARN_ON(!wl->operating);
4788 B43_WARN_ON(wl->vif != vif);
4791 wl->operating = false;
4793 b43_adjust_opmode(dev);
4794 memset(wl->mac_addr, 0, ETH_ALEN);
4795 b43_upload_card_macaddress(dev);
4797 mutex_unlock(&wl->mutex);
4800 static int b43_op_start(struct ieee80211_hw *hw)
4802 struct b43_wl *wl = hw_to_b43_wl(hw);
4803 struct b43_wldev *dev = wl->current_dev;
4807 /* Kill all old instance specific information to make sure
4808 * the card won't use it in the short timeframe between start
4809 * and mac80211 reconfiguring it. */
4810 memset(wl->bssid, 0, ETH_ALEN);
4811 memset(wl->mac_addr, 0, ETH_ALEN);
4812 wl->filter_flags = 0;
4813 wl->radiotap_enabled = false;
4815 wl->beacon0_uploaded = false;
4816 wl->beacon1_uploaded = false;
4817 wl->beacon_templates_virgin = true;
4818 wl->radio_enabled = true;
4820 mutex_lock(&wl->mutex);
4822 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4823 err = b43_wireless_core_init(dev);
4825 goto out_mutex_unlock;
4829 if (b43_status(dev) < B43_STAT_STARTED) {
4830 err = b43_wireless_core_start(dev);
4833 b43_wireless_core_exit(dev);
4834 goto out_mutex_unlock;
4838 /* XXX: only do if device doesn't support rfkill irq */
4839 wiphy_rfkill_start_polling(hw->wiphy);
4842 mutex_unlock(&wl->mutex);
4845 * Configuration may have been overwritten during initialization.
4846 * Reload the configuration, but only if initialization was
4847 * successful. Reloading the configuration after a failed init
4848 * may hang the system.
4851 b43_op_config(hw, ~0);
4856 static void b43_op_stop(struct ieee80211_hw *hw)
4858 struct b43_wl *wl = hw_to_b43_wl(hw);
4859 struct b43_wldev *dev = wl->current_dev;
4861 cancel_work_sync(&(wl->beacon_update_trigger));
4866 mutex_lock(&wl->mutex);
4867 if (b43_status(dev) >= B43_STAT_STARTED) {
4868 dev = b43_wireless_core_stop(dev);
4872 b43_wireless_core_exit(dev);
4873 wl->radio_enabled = false;
4876 mutex_unlock(&wl->mutex);
4878 cancel_work_sync(&(wl->txpower_adjust_work));
4881 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4882 struct ieee80211_sta *sta, bool set)
4884 struct b43_wl *wl = hw_to_b43_wl(hw);
4886 /* FIXME: add locking */
4887 b43_update_templates(wl);
4892 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4893 struct ieee80211_vif *vif,
4894 enum sta_notify_cmd notify_cmd,
4895 struct ieee80211_sta *sta)
4897 struct b43_wl *wl = hw_to_b43_wl(hw);
4899 B43_WARN_ON(!vif || wl->vif != vif);
4902 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4904 struct b43_wl *wl = hw_to_b43_wl(hw);
4905 struct b43_wldev *dev;
4907 mutex_lock(&wl->mutex);
4908 dev = wl->current_dev;
4909 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4910 /* Disable CFP update during scan on other channels. */
4911 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4913 mutex_unlock(&wl->mutex);
4916 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4918 struct b43_wl *wl = hw_to_b43_wl(hw);
4919 struct b43_wldev *dev;
4921 mutex_lock(&wl->mutex);
4922 dev = wl->current_dev;
4923 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4924 /* Re-enable CFP update. */
4925 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4927 mutex_unlock(&wl->mutex);
4930 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4931 struct survey_info *survey)
4933 struct b43_wl *wl = hw_to_b43_wl(hw);
4934 struct b43_wldev *dev = wl->current_dev;
4935 struct ieee80211_conf *conf = &hw->conf;
4940 survey->channel = conf->channel;
4941 survey->filled = SURVEY_INFO_NOISE_DBM;
4942 survey->noise = dev->stats.link_noise;
4947 static const struct ieee80211_ops b43_hw_ops = {
4949 .conf_tx = b43_op_conf_tx,
4950 .add_interface = b43_op_add_interface,
4951 .remove_interface = b43_op_remove_interface,
4952 .config = b43_op_config,
4953 .bss_info_changed = b43_op_bss_info_changed,
4954 .configure_filter = b43_op_configure_filter,
4955 .set_key = b43_op_set_key,
4956 .update_tkip_key = b43_op_update_tkip_key,
4957 .get_stats = b43_op_get_stats,
4958 .get_tsf = b43_op_get_tsf,
4959 .set_tsf = b43_op_set_tsf,
4960 .start = b43_op_start,
4961 .stop = b43_op_stop,
4962 .set_tim = b43_op_beacon_set_tim,
4963 .sta_notify = b43_op_sta_notify,
4964 .sw_scan_start = b43_op_sw_scan_start_notifier,
4965 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4966 .get_survey = b43_op_get_survey,
4967 .rfkill_poll = b43_rfkill_poll,
4970 /* Hard-reset the chip. Do not call this directly.
4971 * Use b43_controller_restart()
4973 static void b43_chip_reset(struct work_struct *work)
4975 struct b43_wldev *dev =
4976 container_of(work, struct b43_wldev, restart_work);
4977 struct b43_wl *wl = dev->wl;
4981 mutex_lock(&wl->mutex);
4983 prev_status = b43_status(dev);
4984 /* Bring the device down... */
4985 if (prev_status >= B43_STAT_STARTED) {
4986 dev = b43_wireless_core_stop(dev);
4992 if (prev_status >= B43_STAT_INITIALIZED)
4993 b43_wireless_core_exit(dev);
4995 /* ...and up again. */
4996 if (prev_status >= B43_STAT_INITIALIZED) {
4997 err = b43_wireless_core_init(dev);
5001 if (prev_status >= B43_STAT_STARTED) {
5002 err = b43_wireless_core_start(dev);
5004 b43_wireless_core_exit(dev);
5010 wl->current_dev = NULL; /* Failed to init the dev. */
5011 mutex_unlock(&wl->mutex);
5014 b43err(wl, "Controller restart FAILED\n");
5018 /* reload configuration */
5019 b43_op_config(wl->hw, ~0);
5021 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5023 b43info(wl, "Controller restarted\n");
5026 static int b43_setup_bands(struct b43_wldev *dev,
5027 bool have_2ghz_phy, bool have_5ghz_phy)
5029 struct ieee80211_hw *hw = dev->wl->hw;
5032 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5033 if (dev->phy.type == B43_PHYTYPE_N) {
5035 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5038 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5041 dev->phy.supports_2ghz = have_2ghz_phy;
5042 dev->phy.supports_5ghz = have_5ghz_phy;
5047 static void b43_wireless_core_detach(struct b43_wldev *dev)
5049 /* We release firmware that late to not be required to re-request
5050 * is all the time when we reinit the core. */
5051 b43_release_firmware(dev);
5055 static int b43_wireless_core_attach(struct b43_wldev *dev)
5057 struct b43_wl *wl = dev->wl;
5058 struct pci_dev *pdev = NULL;
5061 bool have_2ghz_phy = false, have_5ghz_phy = false;
5063 /* Do NOT do any device initialization here.
5064 * Do it in wireless_core_init() instead.
5065 * This function is for gathering basic information about the HW, only.
5066 * Also some structs may be set up here. But most likely you want to have
5067 * that in core_init(), too.
5070 #ifdef CONFIG_B43_SSB
5071 if (dev->dev->bus_type == B43_BUS_SSB &&
5072 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5073 pdev = dev->dev->sdev->bus->host_pci;
5076 err = b43_bus_powerup(dev, 0);
5078 b43err(wl, "Bus powerup failed\n");
5082 /* Get the PHY type. */
5083 switch (dev->dev->bus_type) {
5084 #ifdef CONFIG_B43_BCMA
5086 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5087 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5088 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5091 #ifdef CONFIG_B43_SSB
5093 if (dev->dev->core_rev >= 5) {
5094 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5095 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5096 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5103 dev->phy.gmode = have_2ghz_phy;
5104 dev->phy.radio_on = true;
5105 b43_wireless_core_reset(dev, dev->phy.gmode);
5107 err = b43_phy_versioning(dev);
5110 /* Check if this device supports multiband. */
5112 (pdev->device != 0x4312 &&
5113 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5114 /* No multiband support. */
5115 have_2ghz_phy = false;
5116 have_5ghz_phy = false;
5117 switch (dev->phy.type) {
5119 have_5ghz_phy = true;
5121 case B43_PHYTYPE_LP: //FIXME not always!
5122 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5127 case B43_PHYTYPE_HT:
5128 case B43_PHYTYPE_LCN:
5129 have_2ghz_phy = true;
5135 if (dev->phy.type == B43_PHYTYPE_A) {
5137 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5141 if (1 /* disable A-PHY */) {
5142 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5143 if (dev->phy.type != B43_PHYTYPE_N &&
5144 dev->phy.type != B43_PHYTYPE_LP) {
5145 have_2ghz_phy = true;
5146 have_5ghz_phy = false;
5150 err = b43_phy_allocate(dev);
5154 dev->phy.gmode = have_2ghz_phy;
5155 b43_wireless_core_reset(dev, dev->phy.gmode);
5157 err = b43_validate_chipaccess(dev);
5160 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5164 /* Now set some default "current_dev" */
5165 if (!wl->current_dev)
5166 wl->current_dev = dev;
5167 INIT_WORK(&dev->restart_work, b43_chip_reset);
5169 dev->phy.ops->switch_analog(dev, 0);
5170 b43_device_disable(dev, 0);
5171 b43_bus_may_powerdown(dev);
5179 b43_bus_may_powerdown(dev);
5183 static void b43_one_core_detach(struct b43_bus_dev *dev)
5185 struct b43_wldev *wldev;
5188 /* Do not cancel ieee80211-workqueue based work here.
5189 * See comment in b43_remove(). */
5191 wldev = b43_bus_get_wldev(dev);
5193 b43_debugfs_remove_device(wldev);
5194 b43_wireless_core_detach(wldev);
5195 list_del(&wldev->list);
5197 b43_bus_set_wldev(dev, NULL);
5201 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5203 struct b43_wldev *wldev;
5206 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5210 wldev->use_pio = b43_modparam_pio;
5213 b43_set_status(wldev, B43_STAT_UNINIT);
5214 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5215 INIT_LIST_HEAD(&wldev->list);
5217 err = b43_wireless_core_attach(wldev);
5219 goto err_kfree_wldev;
5221 list_add(&wldev->list, &wl->devlist);
5223 b43_bus_set_wldev(dev, wldev);
5224 b43_debugfs_add_device(wldev);
5234 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5235 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5236 (pdev->device == _device) && \
5237 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5238 (pdev->subsystem_device == _subdevice) )
5240 static void b43_sprom_fixup(struct ssb_bus *bus)
5242 struct pci_dev *pdev;
5244 /* boardflags workarounds */
5245 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5246 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5247 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5248 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5249 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5250 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5251 if (bus->bustype == SSB_BUSTYPE_PCI) {
5252 pdev = bus->host_pci;
5253 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5254 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5255 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5256 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5257 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5258 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5259 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5260 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5264 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5266 struct ieee80211_hw *hw = wl->hw;
5268 ssb_set_devtypedata(dev->sdev, NULL);
5269 ieee80211_free_hw(hw);
5272 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5274 struct ssb_sprom *sprom = dev->bus_sprom;
5275 struct ieee80211_hw *hw;
5280 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5282 b43err(NULL, "Could not allocate ieee80211 device\n");
5283 return ERR_PTR(-ENOMEM);
5285 wl = hw_to_b43_wl(hw);
5288 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5289 IEEE80211_HW_SIGNAL_DBM;
5291 hw->wiphy->interface_modes =
5292 BIT(NL80211_IFTYPE_AP) |
5293 BIT(NL80211_IFTYPE_MESH_POINT) |
5294 BIT(NL80211_IFTYPE_STATION) |
5295 BIT(NL80211_IFTYPE_WDS) |
5296 BIT(NL80211_IFTYPE_ADHOC);
5298 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5300 wl->hw_registred = false;
5302 SET_IEEE80211_DEV(hw, dev->dev);
5303 if (is_valid_ether_addr(sprom->et1mac))
5304 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5306 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5308 /* Initialize struct b43_wl */
5310 mutex_init(&wl->mutex);
5311 spin_lock_init(&wl->hardirq_lock);
5312 INIT_LIST_HEAD(&wl->devlist);
5313 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5314 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5315 INIT_WORK(&wl->tx_work, b43_tx_work);
5317 /* Initialize queues and flags. */
5318 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5319 skb_queue_head_init(&wl->tx_queue[queue_num]);
5320 wl->tx_queue_stopped[queue_num] = 0;
5323 snprintf(chip_name, ARRAY_SIZE(chip_name),
5324 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5325 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5330 #ifdef CONFIG_B43_BCMA
5331 static int b43_bcma_probe(struct bcma_device *core)
5333 struct b43_bus_dev *dev;
5337 dev = b43_bus_dev_bcma_init(core);
5341 wl = b43_wireless_init(dev);
5347 err = b43_one_core_attach(dev, wl);
5349 goto bcma_err_wireless_exit;
5351 /* setup and start work to load firmware */
5352 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5353 schedule_work(&wl->firmware_load);
5358 bcma_err_wireless_exit:
5359 ieee80211_free_hw(wl->hw);
5363 static void b43_bcma_remove(struct bcma_device *core)
5365 struct b43_wldev *wldev = bcma_get_drvdata(core);
5366 struct b43_wl *wl = wldev->wl;
5368 /* We must cancel any work here before unregistering from ieee80211,
5369 * as the ieee80211 unreg will destroy the workqueue. */
5370 cancel_work_sync(&wldev->restart_work);
5373 if (wl->current_dev == wldev && wl->hw_registred) {
5374 b43_leds_stop(wldev);
5375 ieee80211_unregister_hw(wl->hw);
5378 b43_one_core_detach(wldev->dev);
5380 b43_leds_unregister(wl);
5382 ieee80211_free_hw(wl->hw);
5385 static struct bcma_driver b43_bcma_driver = {
5386 .name = KBUILD_MODNAME,
5387 .id_table = b43_bcma_tbl,
5388 .probe = b43_bcma_probe,
5389 .remove = b43_bcma_remove,
5393 #ifdef CONFIG_B43_SSB
5395 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5397 struct b43_bus_dev *dev;
5402 dev = b43_bus_dev_ssb_init(sdev);
5406 wl = ssb_get_devtypedata(sdev);
5408 /* Probing the first core. Must setup common struct b43_wl */
5410 b43_sprom_fixup(sdev->bus);
5411 wl = b43_wireless_init(dev);
5416 ssb_set_devtypedata(sdev, wl);
5417 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5419 err = b43_one_core_attach(dev, wl);
5421 goto err_wireless_exit;
5423 /* setup and start work to load firmware */
5424 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5425 schedule_work(&wl->firmware_load);
5432 b43_wireless_exit(dev, wl);
5436 static void b43_ssb_remove(struct ssb_device *sdev)
5438 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5439 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5440 struct b43_bus_dev *dev = wldev->dev;
5442 /* We must cancel any work here before unregistering from ieee80211,
5443 * as the ieee80211 unreg will destroy the workqueue. */
5444 cancel_work_sync(&wldev->restart_work);
5447 if (wl->current_dev == wldev && wl->hw_registred) {
5448 b43_leds_stop(wldev);
5449 ieee80211_unregister_hw(wl->hw);
5452 b43_one_core_detach(dev);
5454 if (list_empty(&wl->devlist)) {
5455 b43_leds_unregister(wl);
5456 /* Last core on the chip unregistered.
5457 * We can destroy common struct b43_wl.
5459 b43_wireless_exit(dev, wl);
5463 static struct ssb_driver b43_ssb_driver = {
5464 .name = KBUILD_MODNAME,
5465 .id_table = b43_ssb_tbl,
5466 .probe = b43_ssb_probe,
5467 .remove = b43_ssb_remove,
5469 #endif /* CONFIG_B43_SSB */
5471 /* Perform a hardware reset. This can be called from any context. */
5472 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5474 /* Must avoid requeueing, if we are in shutdown. */
5475 if (b43_status(dev) < B43_STAT_INITIALIZED)
5477 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5478 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5481 static void b43_print_driverinfo(void)
5483 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5484 *feat_leds = "", *feat_sdio = "";
5486 #ifdef CONFIG_B43_PCI_AUTOSELECT
5489 #ifdef CONFIG_B43_PCMCIA
5492 #ifdef CONFIG_B43_PHY_N
5495 #ifdef CONFIG_B43_LEDS
5498 #ifdef CONFIG_B43_SDIO
5501 printk(KERN_INFO "Broadcom 43xx driver loaded "
5502 "[ Features: %s%s%s%s%s ]\n",
5503 feat_pci, feat_pcmcia, feat_nphy,
5504 feat_leds, feat_sdio);
5507 static int __init b43_init(void)
5512 err = b43_pcmcia_init();
5515 err = b43_sdio_init();
5517 goto err_pcmcia_exit;
5518 #ifdef CONFIG_B43_BCMA
5519 err = bcma_driver_register(&b43_bcma_driver);
5523 #ifdef CONFIG_B43_SSB
5524 err = ssb_driver_register(&b43_ssb_driver);
5526 goto err_bcma_driver_exit;
5528 b43_print_driverinfo();
5532 #ifdef CONFIG_B43_SSB
5533 err_bcma_driver_exit:
5535 #ifdef CONFIG_B43_BCMA
5536 bcma_driver_unregister(&b43_bcma_driver);
5547 static void __exit b43_exit(void)
5549 #ifdef CONFIG_B43_SSB
5550 ssb_driver_unregister(&b43_ssb_driver);
5552 #ifdef CONFIG_B43_BCMA
5553 bcma_driver_unregister(&b43_bcma_driver);
5560 module_init(b43_init)
5561 module_exit(b43_exit)