3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117 module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118 MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
120 #ifdef CONFIG_B43_BCMA
121 static const struct bcma_device_id b43_bcma_tbl[] = {
122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
128 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
131 #ifdef CONFIG_B43_SSB
132 static const struct ssb_device_id b43_ssb_tbl[] = {
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
145 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
148 /* Channel and ratetables are shared for all devices.
149 * They can't be const, because ieee80211 puts some precalculated
150 * data in there. This data is the same for all devices, so we don't
151 * get concurrency issues */
152 #define RATETAB_ENT(_rateid, _flags) \
154 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
155 .hw_value = (_rateid), \
160 * NOTE: When changing this, sync with xmit.c's
161 * b43_plcp_get_bitrate_idx_* functions!
163 static struct ieee80211_rate __b43_ratetable[] = {
164 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
165 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
167 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
168 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
178 #define b43_a_ratetable (__b43_ratetable + 4)
179 #define b43_a_ratetable_size 8
180 #define b43_b_ratetable (__b43_ratetable + 0)
181 #define b43_b_ratetable_size 4
182 #define b43_g_ratetable (__b43_ratetable + 0)
183 #define b43_g_ratetable_size 12
185 #define CHAN4G(_channel, _freq, _flags) { \
186 .band = IEEE80211_BAND_2GHZ, \
187 .center_freq = (_freq), \
188 .hw_value = (_channel), \
190 .max_antenna_gain = 0, \
193 static struct ieee80211_channel b43_2ghz_chantable[] = {
211 #define CHAN5G(_channel, _flags) { \
212 .band = IEEE80211_BAND_5GHZ, \
213 .center_freq = 5000 + (5 * (_channel)), \
214 .hw_value = (_channel), \
216 .max_antenna_gain = 0, \
219 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
220 CHAN5G(32, 0), CHAN5G(34, 0),
221 CHAN5G(36, 0), CHAN5G(38, 0),
222 CHAN5G(40, 0), CHAN5G(42, 0),
223 CHAN5G(44, 0), CHAN5G(46, 0),
224 CHAN5G(48, 0), CHAN5G(50, 0),
225 CHAN5G(52, 0), CHAN5G(54, 0),
226 CHAN5G(56, 0), CHAN5G(58, 0),
227 CHAN5G(60, 0), CHAN5G(62, 0),
228 CHAN5G(64, 0), CHAN5G(66, 0),
229 CHAN5G(68, 0), CHAN5G(70, 0),
230 CHAN5G(72, 0), CHAN5G(74, 0),
231 CHAN5G(76, 0), CHAN5G(78, 0),
232 CHAN5G(80, 0), CHAN5G(82, 0),
233 CHAN5G(84, 0), CHAN5G(86, 0),
234 CHAN5G(88, 0), CHAN5G(90, 0),
235 CHAN5G(92, 0), CHAN5G(94, 0),
236 CHAN5G(96, 0), CHAN5G(98, 0),
237 CHAN5G(100, 0), CHAN5G(102, 0),
238 CHAN5G(104, 0), CHAN5G(106, 0),
239 CHAN5G(108, 0), CHAN5G(110, 0),
240 CHAN5G(112, 0), CHAN5G(114, 0),
241 CHAN5G(116, 0), CHAN5G(118, 0),
242 CHAN5G(120, 0), CHAN5G(122, 0),
243 CHAN5G(124, 0), CHAN5G(126, 0),
244 CHAN5G(128, 0), CHAN5G(130, 0),
245 CHAN5G(132, 0), CHAN5G(134, 0),
246 CHAN5G(136, 0), CHAN5G(138, 0),
247 CHAN5G(140, 0), CHAN5G(142, 0),
248 CHAN5G(144, 0), CHAN5G(145, 0),
249 CHAN5G(146, 0), CHAN5G(147, 0),
250 CHAN5G(148, 0), CHAN5G(149, 0),
251 CHAN5G(150, 0), CHAN5G(151, 0),
252 CHAN5G(152, 0), CHAN5G(153, 0),
253 CHAN5G(154, 0), CHAN5G(155, 0),
254 CHAN5G(156, 0), CHAN5G(157, 0),
255 CHAN5G(158, 0), CHAN5G(159, 0),
256 CHAN5G(160, 0), CHAN5G(161, 0),
257 CHAN5G(162, 0), CHAN5G(163, 0),
258 CHAN5G(164, 0), CHAN5G(165, 0),
259 CHAN5G(166, 0), CHAN5G(168, 0),
260 CHAN5G(170, 0), CHAN5G(172, 0),
261 CHAN5G(174, 0), CHAN5G(176, 0),
262 CHAN5G(178, 0), CHAN5G(180, 0),
263 CHAN5G(182, 0), CHAN5G(184, 0),
264 CHAN5G(186, 0), CHAN5G(188, 0),
265 CHAN5G(190, 0), CHAN5G(192, 0),
266 CHAN5G(194, 0), CHAN5G(196, 0),
267 CHAN5G(198, 0), CHAN5G(200, 0),
268 CHAN5G(202, 0), CHAN5G(204, 0),
269 CHAN5G(206, 0), CHAN5G(208, 0),
270 CHAN5G(210, 0), CHAN5G(212, 0),
271 CHAN5G(214, 0), CHAN5G(216, 0),
272 CHAN5G(218, 0), CHAN5G(220, 0),
273 CHAN5G(222, 0), CHAN5G(224, 0),
274 CHAN5G(226, 0), CHAN5G(228, 0),
277 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
278 CHAN5G(34, 0), CHAN5G(36, 0),
279 CHAN5G(38, 0), CHAN5G(40, 0),
280 CHAN5G(42, 0), CHAN5G(44, 0),
281 CHAN5G(46, 0), CHAN5G(48, 0),
282 CHAN5G(52, 0), CHAN5G(56, 0),
283 CHAN5G(60, 0), CHAN5G(64, 0),
284 CHAN5G(100, 0), CHAN5G(104, 0),
285 CHAN5G(108, 0), CHAN5G(112, 0),
286 CHAN5G(116, 0), CHAN5G(120, 0),
287 CHAN5G(124, 0), CHAN5G(128, 0),
288 CHAN5G(132, 0), CHAN5G(136, 0),
289 CHAN5G(140, 0), CHAN5G(149, 0),
290 CHAN5G(153, 0), CHAN5G(157, 0),
291 CHAN5G(161, 0), CHAN5G(165, 0),
292 CHAN5G(184, 0), CHAN5G(188, 0),
293 CHAN5G(192, 0), CHAN5G(196, 0),
294 CHAN5G(200, 0), CHAN5G(204, 0),
295 CHAN5G(208, 0), CHAN5G(212, 0),
300 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
301 .band = IEEE80211_BAND_5GHZ,
302 .channels = b43_5ghz_nphy_chantable,
303 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
304 .bitrates = b43_a_ratetable,
305 .n_bitrates = b43_a_ratetable_size,
308 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
309 .band = IEEE80211_BAND_5GHZ,
310 .channels = b43_5ghz_aphy_chantable,
311 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
312 .bitrates = b43_a_ratetable,
313 .n_bitrates = b43_a_ratetable_size,
316 static struct ieee80211_supported_band b43_band_2GHz = {
317 .band = IEEE80211_BAND_2GHZ,
318 .channels = b43_2ghz_chantable,
319 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
320 .bitrates = b43_g_ratetable,
321 .n_bitrates = b43_g_ratetable_size,
324 static void b43_wireless_core_exit(struct b43_wldev *dev);
325 static int b43_wireless_core_init(struct b43_wldev *dev);
326 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
327 static int b43_wireless_core_start(struct b43_wldev *dev);
328 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
329 struct ieee80211_vif *vif,
330 struct ieee80211_bss_conf *conf,
333 static int b43_ratelimit(struct b43_wl *wl)
335 if (!wl || !wl->current_dev)
337 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
339 /* We are up and running.
340 * Ratelimit the messages to avoid DoS over the net. */
341 return net_ratelimit();
344 void b43info(struct b43_wl *wl, const char *fmt, ...)
346 struct va_format vaf;
349 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
351 if (!b43_ratelimit(wl))
359 printk(KERN_INFO "b43-%s: %pV",
360 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
365 void b43err(struct b43_wl *wl, const char *fmt, ...)
367 struct va_format vaf;
370 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
372 if (!b43_ratelimit(wl))
380 printk(KERN_ERR "b43-%s ERROR: %pV",
381 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
386 void b43warn(struct b43_wl *wl, const char *fmt, ...)
388 struct va_format vaf;
391 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
393 if (!b43_ratelimit(wl))
401 printk(KERN_WARNING "b43-%s warning: %pV",
402 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
407 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
409 struct va_format vaf;
412 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
420 printk(KERN_DEBUG "b43-%s debug: %pV",
421 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
426 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
430 B43_WARN_ON(offset % 4 != 0);
432 macctl = b43_read32(dev, B43_MMIO_MACCTL);
433 if (macctl & B43_MACCTL_BE)
436 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
438 b43_write32(dev, B43_MMIO_RAM_DATA, val);
441 static inline void b43_shm_control_word(struct b43_wldev *dev,
442 u16 routing, u16 offset)
446 /* "offset" is the WORD offset. */
450 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
453 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
457 if (routing == B43_SHM_SHARED) {
458 B43_WARN_ON(offset & 0x0001);
459 if (offset & 0x0003) {
460 /* Unaligned access */
461 b43_shm_control_word(dev, routing, offset >> 2);
462 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
463 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
464 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
470 b43_shm_control_word(dev, routing, offset);
471 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
476 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
480 if (routing == B43_SHM_SHARED) {
481 B43_WARN_ON(offset & 0x0001);
482 if (offset & 0x0003) {
483 /* Unaligned access */
484 b43_shm_control_word(dev, routing, offset >> 2);
485 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
491 b43_shm_control_word(dev, routing, offset);
492 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
497 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
499 if (routing == B43_SHM_SHARED) {
500 B43_WARN_ON(offset & 0x0001);
501 if (offset & 0x0003) {
502 /* Unaligned access */
503 b43_shm_control_word(dev, routing, offset >> 2);
504 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
506 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
507 b43_write16(dev, B43_MMIO_SHM_DATA,
508 (value >> 16) & 0xFFFF);
513 b43_shm_control_word(dev, routing, offset);
514 b43_write32(dev, B43_MMIO_SHM_DATA, value);
517 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
519 if (routing == B43_SHM_SHARED) {
520 B43_WARN_ON(offset & 0x0001);
521 if (offset & 0x0003) {
522 /* Unaligned access */
523 b43_shm_control_word(dev, routing, offset >> 2);
524 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
529 b43_shm_control_word(dev, routing, offset);
530 b43_write16(dev, B43_MMIO_SHM_DATA, value);
534 u64 b43_hf_read(struct b43_wldev *dev)
538 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
542 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
547 /* Write HostFlags */
548 void b43_hf_write(struct b43_wldev *dev, u64 value)
552 lo = (value & 0x00000000FFFFULL);
553 mi = (value & 0x0000FFFF0000ULL) >> 16;
554 hi = (value & 0xFFFF00000000ULL) >> 32;
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
556 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
557 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
560 /* Read the firmware capabilities bitmask (Opensource firmware only) */
561 static u16 b43_fwcapa_read(struct b43_wldev *dev)
563 B43_WARN_ON(!dev->fw.opensource);
564 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
567 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
571 B43_WARN_ON(dev->dev->core_rev < 3);
573 /* The hardware guarantees us an atomic read, if we
574 * read the low register first. */
575 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
576 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
583 static void b43_time_lock(struct b43_wldev *dev)
585 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
590 static void b43_time_unlock(struct b43_wldev *dev)
592 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
593 /* Commit the write */
594 b43_read32(dev, B43_MMIO_MACCTL);
597 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601 B43_WARN_ON(dev->dev->core_rev < 3);
605 /* The hardware guarantees us an atomic write, if we
606 * write the low register first. */
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
613 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
616 b43_tsf_write_locked(dev, tsf);
617 b43_time_unlock(dev);
621 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
623 static const u8 zero_addr[ETH_ALEN] = { 0 };
630 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
634 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
637 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
640 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
643 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
647 u8 mac_bssid[ETH_ALEN * 2];
651 bssid = dev->wl->bssid;
652 mac = dev->wl->mac_addr;
654 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
656 memcpy(mac_bssid, mac, ETH_ALEN);
657 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
659 /* Write our MAC address and BSSID to template ram */
660 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
661 tmp = (u32) (mac_bssid[i + 0]);
662 tmp |= (u32) (mac_bssid[i + 1]) << 8;
663 tmp |= (u32) (mac_bssid[i + 2]) << 16;
664 tmp |= (u32) (mac_bssid[i + 3]) << 24;
665 b43_ram_write(dev, 0x20 + i, tmp);
669 static void b43_upload_card_macaddress(struct b43_wldev *dev)
671 b43_write_mac_bssid_templates(dev);
672 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
675 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
677 /* slot_time is in usec. */
678 /* This test used to exit for all but a G PHY. */
679 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
681 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
682 /* Shared memory location 0x0010 is the slot time and should be
683 * set to slot_time; however, this register is initially 0 and changing
684 * the value adversely affects the transmit rate for BCM4311
685 * devices. Until this behavior is unterstood, delete this step
687 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
691 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
693 b43_set_slot_time(dev, 9);
696 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
698 b43_set_slot_time(dev, 20);
701 /* DummyTransmission function, as documented on
702 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
704 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
706 struct b43_phy *phy = &dev->phy;
707 unsigned int i, max_loop;
719 buffer[0] = 0x000201CC;
722 buffer[0] = 0x000B846E;
725 for (i = 0; i < 5; i++)
726 b43_ram_write(dev, i * 4, buffer[i]);
728 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
730 if (dev->dev->core_rev < 11)
731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
733 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
735 value = (ofdm ? 0x41 : 0x40);
736 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
737 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
738 phy->type == B43_PHYTYPE_LCN)
739 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
741 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
742 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
744 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
745 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
746 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
747 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
749 if (!pa_on && phy->type == B43_PHYTYPE_N)
750 ; /*b43_nphy_pa_override(dev, false) */
754 case B43_PHYTYPE_LCN:
755 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
758 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
761 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
763 b43_read16(dev, B43_MMIO_TXE0_AUX);
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0017);
767 for (i = 0x00; i < max_loop; i++) {
768 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
773 for (i = 0x00; i < 0x0A; i++) {
774 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
779 for (i = 0x00; i < 0x19; i++) {
780 value = b43_read16(dev, B43_MMIO_IFSSTAT);
781 if (!(value & 0x0100))
785 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
786 b43_radio_write16(dev, 0x0051, 0x0037);
789 static void key_write(struct b43_wldev *dev,
790 u8 index, u8 algorithm, const u8 *key)
797 /* Key index/algo block */
798 kidx = b43_kidx_to_fw(dev, index);
799 value = ((kidx << 4) | algorithm);
800 b43_shm_write16(dev, B43_SHM_SHARED,
801 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
803 /* Write the key to the Key Table Pointer offset */
804 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
805 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
807 value |= (u16) (key[i + 1]) << 8;
808 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
812 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
814 u32 addrtmp[2] = { 0, 0, };
815 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
817 if (b43_new_kidx_api(dev))
818 pairwise_keys_start = B43_NR_GROUP_KEYS;
820 B43_WARN_ON(index < pairwise_keys_start);
821 /* We have four default TX keys and possibly four default RX keys.
822 * Physical mac 0 is mapped to physical key 4 or 8, depending
823 * on the firmware version.
824 * So we must adjust the index here.
826 index -= pairwise_keys_start;
827 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
830 addrtmp[0] = addr[0];
831 addrtmp[0] |= ((u32) (addr[1]) << 8);
832 addrtmp[0] |= ((u32) (addr[2]) << 16);
833 addrtmp[0] |= ((u32) (addr[3]) << 24);
834 addrtmp[1] = addr[4];
835 addrtmp[1] |= ((u32) (addr[5]) << 8);
838 /* Receive match transmitter address (RCMTA) mechanism */
839 b43_shm_write32(dev, B43_SHM_RCMTA,
840 (index * 2) + 0, addrtmp[0]);
841 b43_shm_write16(dev, B43_SHM_RCMTA,
842 (index * 2) + 1, addrtmp[1]);
845 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
846 * When a packet is received, the iv32 is checked.
847 * - if it doesn't the packet is returned without modification (and software
848 * decryption can be done). That's what happen when iv16 wrap.
849 * - if it does, the rc4 key is computed, and decryption is tried.
850 * Either it will success and B43_RX_MAC_DEC is returned,
851 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
852 * and the packet is not usable (it got modified by the ucode).
853 * So in order to never have B43_RX_MAC_DECERR, we should provide
854 * a iv32 and phase1key that match. Because we drop packets in case of
855 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
856 * packets will be lost without higher layer knowing (ie no resync possible
859 * NOTE : this should support 50 key like RCMTA because
860 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
862 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
867 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
869 if (!modparam_hwtkip)
872 if (b43_new_kidx_api(dev))
873 pairwise_keys_start = B43_NR_GROUP_KEYS;
875 B43_WARN_ON(index < pairwise_keys_start);
876 /* We have four default TX keys and possibly four default RX keys.
877 * Physical mac 0 is mapped to physical key 4 or 8, depending
878 * on the firmware version.
879 * So we must adjust the index here.
881 index -= pairwise_keys_start;
882 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
884 if (b43_debug(dev, B43_DBG_KEYS)) {
885 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
888 /* Write the key to the RX tkip shared mem */
889 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
890 for (i = 0; i < 10; i += 2) {
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
892 phase1key ? phase1key[i / 2] : 0);
894 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
895 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
898 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
899 struct ieee80211_vif *vif,
900 struct ieee80211_key_conf *keyconf,
901 struct ieee80211_sta *sta,
902 u32 iv32, u16 *phase1key)
904 struct b43_wl *wl = hw_to_b43_wl(hw);
905 struct b43_wldev *dev;
906 int index = keyconf->hw_key_idx;
908 if (B43_WARN_ON(!modparam_hwtkip))
911 /* This is only called from the RX path through mac80211, where
912 * our mutex is already locked. */
913 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
914 dev = wl->current_dev;
915 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
917 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
919 rx_tkip_phase1_write(dev, index, iv32, phase1key);
920 /* only pairwise TKIP keys are supported right now */
923 keymac_write(dev, index, sta->addr);
926 static void do_key_write(struct b43_wldev *dev,
927 u8 index, u8 algorithm,
928 const u8 *key, size_t key_len, const u8 *mac_addr)
930 u8 buf[B43_SEC_KEYSIZE] = { 0, };
931 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
933 if (b43_new_kidx_api(dev))
934 pairwise_keys_start = B43_NR_GROUP_KEYS;
936 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
937 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
939 if (index >= pairwise_keys_start)
940 keymac_write(dev, index, NULL); /* First zero out mac. */
941 if (algorithm == B43_SEC_ALGO_TKIP) {
943 * We should provide an initial iv32, phase1key pair.
944 * We could start with iv32=0 and compute the corresponding
945 * phase1key, but this means calling ieee80211_get_tkip_key
946 * with a fake skb (or export other tkip function).
947 * Because we are lazy we hope iv32 won't start with
948 * 0xffffffff and let's b43_op_update_tkip_key provide a
951 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
952 } else if (index >= pairwise_keys_start) /* clear it */
953 rx_tkip_phase1_write(dev, index, 0, NULL);
955 memcpy(buf, key, key_len);
956 key_write(dev, index, algorithm, buf);
957 if (index >= pairwise_keys_start)
958 keymac_write(dev, index, mac_addr);
960 dev->key[index].algorithm = algorithm;
963 static int b43_key_write(struct b43_wldev *dev,
964 int index, u8 algorithm,
965 const u8 *key, size_t key_len,
967 struct ieee80211_key_conf *keyconf)
970 int pairwise_keys_start;
972 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
973 * - Temporal Encryption Key (128 bits)
974 * - Temporal Authenticator Tx MIC Key (64 bits)
975 * - Temporal Authenticator Rx MIC Key (64 bits)
977 * Hardware only store TEK
979 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
981 if (key_len > B43_SEC_KEYSIZE)
983 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
984 /* Check that we don't already have this key. */
985 B43_WARN_ON(dev->key[i].keyconf == keyconf);
988 /* Pairwise key. Get an empty slot for the key. */
989 if (b43_new_kidx_api(dev))
990 pairwise_keys_start = B43_NR_GROUP_KEYS;
992 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
993 for (i = pairwise_keys_start;
994 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
996 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
997 if (!dev->key[i].keyconf) {
1004 b43warn(dev->wl, "Out of hardware key memory\n");
1008 B43_WARN_ON(index > 3);
1010 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1011 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1012 /* Default RX key */
1013 B43_WARN_ON(mac_addr);
1014 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1016 keyconf->hw_key_idx = index;
1017 dev->key[index].keyconf = keyconf;
1022 static int b43_key_clear(struct b43_wldev *dev, int index)
1024 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1026 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1027 NULL, B43_SEC_KEYSIZE, NULL);
1028 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1029 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1030 NULL, B43_SEC_KEYSIZE, NULL);
1032 dev->key[index].keyconf = NULL;
1037 static void b43_clear_keys(struct b43_wldev *dev)
1041 if (b43_new_kidx_api(dev))
1042 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1044 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1045 for (i = 0; i < count; i++)
1046 b43_key_clear(dev, i);
1049 static void b43_dump_keymemory(struct b43_wldev *dev)
1051 unsigned int i, index, count, offset, pairwise_keys_start;
1057 struct b43_key *key;
1059 if (!b43_debug(dev, B43_DBG_KEYS))
1062 hf = b43_hf_read(dev);
1063 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1064 !!(hf & B43_HF_USEDEFKEYS));
1065 if (b43_new_kidx_api(dev)) {
1066 pairwise_keys_start = B43_NR_GROUP_KEYS;
1067 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1069 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1070 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1072 for (index = 0; index < count; index++) {
1073 key = &(dev->key[index]);
1074 printk(KERN_DEBUG "Key slot %02u: %s",
1075 index, (key->keyconf == NULL) ? " " : "*");
1076 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1077 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1078 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1079 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1082 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1083 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1084 printk(" Algo: %04X/%02X", algo, key->algorithm);
1086 if (index >= pairwise_keys_start) {
1087 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1089 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1090 for (i = 0; i < 14; i += 2) {
1091 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1092 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1095 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1096 ((index - pairwise_keys_start) * 2) + 0);
1097 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1098 ((index - pairwise_keys_start) * 2) + 1);
1099 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1100 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1101 printk(" MAC: %pM", mac);
1103 printk(" DEFAULT KEY");
1108 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1116 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1117 (ps_flags & B43_PS_DISABLED));
1118 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1120 if (ps_flags & B43_PS_ENABLED) {
1122 } else if (ps_flags & B43_PS_DISABLED) {
1125 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1126 // and thus is not an AP and we are associated, set bit 25
1128 if (ps_flags & B43_PS_AWAKE) {
1130 } else if (ps_flags & B43_PS_ASLEEP) {
1133 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1134 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1135 // successful, set bit26
1138 /* FIXME: For now we force awake-on and hwps-off */
1142 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1144 macctl |= B43_MACCTL_HWPS;
1146 macctl &= ~B43_MACCTL_HWPS;
1148 macctl |= B43_MACCTL_AWAKE;
1150 macctl &= ~B43_MACCTL_AWAKE;
1151 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1153 b43_read32(dev, B43_MMIO_MACCTL);
1154 if (awake && dev->dev->core_rev >= 5) {
1155 /* Wait for the microcode to wake up. */
1156 for (i = 0; i < 100; i++) {
1157 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1158 B43_SHM_SH_UCODESTAT);
1159 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1166 #ifdef CONFIG_B43_BCMA
1167 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1171 /* Put PHY into reset */
1172 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1173 flags |= B43_BCMA_IOCTL_PHY_RESET;
1174 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1175 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1178 b43_phy_take_out_of_reset(dev);
1181 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1183 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1184 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1185 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1186 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1189 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1191 flags |= B43_BCMA_IOCTL_GMODE;
1192 b43_device_enable(dev, flags);
1194 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1195 b43_bcma_phy_reset(dev);
1196 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1200 #ifdef CONFIG_B43_SSB
1201 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1206 flags |= B43_TMSLOW_GMODE;
1207 flags |= B43_TMSLOW_PHYCLKEN;
1208 flags |= B43_TMSLOW_PHYRESET;
1209 if (dev->phy.type == B43_PHYTYPE_N)
1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211 b43_device_enable(dev, flags);
1212 msleep(2); /* Wait for the PLL to turn on. */
1214 b43_phy_take_out_of_reset(dev);
1218 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1222 switch (dev->dev->bus_type) {
1223 #ifdef CONFIG_B43_BCMA
1225 b43_bcma_wireless_core_reset(dev, gmode);
1228 #ifdef CONFIG_B43_SSB
1230 b43_ssb_wireless_core_reset(dev, gmode);
1235 /* Turn Analog ON, but only if we already know the PHY-type.
1236 * This protects against very early setup where we don't know the
1237 * PHY-type, yet. wireless_core_reset will be called once again later,
1238 * when we know the PHY-type. */
1240 dev->phy.ops->switch_analog(dev, 1);
1242 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1243 macctl &= ~B43_MACCTL_GMODE;
1245 macctl |= B43_MACCTL_GMODE;
1246 macctl |= B43_MACCTL_IHR_ENABLED;
1247 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1250 static void handle_irq_transmit_status(struct b43_wldev *dev)
1254 struct b43_txstatus stat;
1257 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1258 if (!(v0 & 0x00000001))
1260 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1262 stat.cookie = (v0 >> 16);
1263 stat.seq = (v1 & 0x0000FFFF);
1264 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1265 tmp = (v0 & 0x0000FFFF);
1266 stat.frame_count = ((tmp & 0xF000) >> 12);
1267 stat.rts_count = ((tmp & 0x0F00) >> 8);
1268 stat.supp_reason = ((tmp & 0x001C) >> 2);
1269 stat.pm_indicated = !!(tmp & 0x0080);
1270 stat.intermediate = !!(tmp & 0x0040);
1271 stat.for_ampdu = !!(tmp & 0x0020);
1272 stat.acked = !!(tmp & 0x0002);
1274 b43_handle_txstatus(dev, &stat);
1278 static void drain_txstatus_queue(struct b43_wldev *dev)
1282 if (dev->dev->core_rev < 5)
1284 /* Read all entries from the microcode TXstatus FIFO
1285 * and throw them away.
1288 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1289 if (!(dummy & 0x00000001))
1291 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1295 static u32 b43_jssi_read(struct b43_wldev *dev)
1299 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1301 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1306 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1308 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1309 (jssi & 0x0000FFFF));
1310 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1311 (jssi & 0xFFFF0000) >> 16);
1314 static void b43_generate_noise_sample(struct b43_wldev *dev)
1316 b43_jssi_write(dev, 0x7F7F7F7F);
1317 b43_write32(dev, B43_MMIO_MACCMD,
1318 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1321 static void b43_calculate_link_quality(struct b43_wldev *dev)
1323 /* Top half of Link Quality calculation. */
1325 if (dev->phy.type != B43_PHYTYPE_G)
1327 if (dev->noisecalc.calculation_running)
1329 dev->noisecalc.calculation_running = true;
1330 dev->noisecalc.nr_samples = 0;
1332 b43_generate_noise_sample(dev);
1335 static void handle_irq_noise(struct b43_wldev *dev)
1337 struct b43_phy_g *phy = dev->phy.g;
1343 /* Bottom half of Link Quality calculation. */
1345 if (dev->phy.type != B43_PHYTYPE_G)
1348 /* Possible race condition: It might be possible that the user
1349 * changed to a different channel in the meantime since we
1350 * started the calculation. We ignore that fact, since it's
1351 * not really that much of a problem. The background noise is
1352 * an estimation only anyway. Slightly wrong results will get damped
1353 * by the averaging of the 8 sample rounds. Additionally the
1354 * value is shortlived. So it will be replaced by the next noise
1355 * calculation round soon. */
1357 B43_WARN_ON(!dev->noisecalc.calculation_running);
1358 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1359 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1360 noise[2] == 0x7F || noise[3] == 0x7F)
1363 /* Get the noise samples. */
1364 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1365 i = dev->noisecalc.nr_samples;
1366 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1367 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1368 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1369 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1370 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1371 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1372 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1373 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1374 dev->noisecalc.nr_samples++;
1375 if (dev->noisecalc.nr_samples == 8) {
1376 /* Calculate the Link Quality by the noise samples. */
1378 for (i = 0; i < 8; i++) {
1379 for (j = 0; j < 4; j++)
1380 average += dev->noisecalc.samples[i][j];
1386 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1387 tmp = (tmp / 128) & 0x1F;
1397 dev->stats.link_noise = average;
1398 dev->noisecalc.calculation_running = false;
1402 b43_generate_noise_sample(dev);
1405 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1407 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1410 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1411 b43_power_saving_ctl_bits(dev, 0);
1413 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1414 dev->dfq_valid = true;
1417 static void handle_irq_atim_end(struct b43_wldev *dev)
1419 if (dev->dfq_valid) {
1420 b43_write32(dev, B43_MMIO_MACCMD,
1421 b43_read32(dev, B43_MMIO_MACCMD)
1422 | B43_MACCMD_DFQ_VALID);
1423 dev->dfq_valid = false;
1427 static void handle_irq_pmq(struct b43_wldev *dev)
1434 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1435 if (!(tmp & 0x00000008))
1438 /* 16bit write is odd, but correct. */
1439 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1442 static void b43_write_template_common(struct b43_wldev *dev,
1443 const u8 *data, u16 size,
1445 u16 shm_size_offset, u8 rate)
1448 struct b43_plcp_hdr4 plcp;
1451 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1452 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1453 ram_offset += sizeof(u32);
1454 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1455 * So leave the first two bytes of the next write blank.
1457 tmp = (u32) (data[0]) << 16;
1458 tmp |= (u32) (data[1]) << 24;
1459 b43_ram_write(dev, ram_offset, tmp);
1460 ram_offset += sizeof(u32);
1461 for (i = 2; i < size; i += sizeof(u32)) {
1462 tmp = (u32) (data[i + 0]);
1464 tmp |= (u32) (data[i + 1]) << 8;
1466 tmp |= (u32) (data[i + 2]) << 16;
1468 tmp |= (u32) (data[i + 3]) << 24;
1469 b43_ram_write(dev, ram_offset + i - 2, tmp);
1471 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1472 size + sizeof(struct b43_plcp_hdr6));
1475 /* Check if the use of the antenna that ieee80211 told us to
1476 * use is possible. This will fall back to DEFAULT.
1477 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1478 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1483 if (antenna_nr == 0) {
1484 /* Zero means "use default antenna". That's always OK. */
1488 /* Get the mask of available antennas. */
1490 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1492 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1494 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1495 /* This antenna is not available. Fall back to default. */
1502 /* Convert a b43 antenna number value to the PHY TX control value. */
1503 static u16 b43_antenna_to_phyctl(int antenna)
1507 return B43_TXH_PHY_ANT0;
1509 return B43_TXH_PHY_ANT1;
1511 return B43_TXH_PHY_ANT2;
1513 return B43_TXH_PHY_ANT3;
1514 case B43_ANTENNA_AUTO0:
1515 case B43_ANTENNA_AUTO1:
1516 return B43_TXH_PHY_ANT01AUTO;
1522 static void b43_write_beacon_template(struct b43_wldev *dev,
1524 u16 shm_size_offset)
1526 unsigned int i, len, variable_len;
1527 const struct ieee80211_mgmt *bcn;
1529 bool tim_found = false;
1533 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1535 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1536 len = min_t(size_t, dev->wl->current_beacon->len,
1537 0x200 - sizeof(struct b43_plcp_hdr6));
1538 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1540 b43_write_template_common(dev, (const u8 *)bcn,
1541 len, ram_offset, shm_size_offset, rate);
1543 /* Write the PHY TX control parameters. */
1544 antenna = B43_ANTENNA_DEFAULT;
1545 antenna = b43_antenna_to_phyctl(antenna);
1546 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1547 /* We can't send beacons with short preamble. Would get PHY errors. */
1548 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1549 ctl &= ~B43_TXH_PHY_ANT;
1550 ctl &= ~B43_TXH_PHY_ENC;
1552 if (b43_is_cck_rate(rate))
1553 ctl |= B43_TXH_PHY_ENC_CCK;
1555 ctl |= B43_TXH_PHY_ENC_OFDM;
1556 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1558 /* Find the position of the TIM and the DTIM_period value
1559 * and write them to SHM. */
1560 ie = bcn->u.beacon.variable;
1561 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1562 for (i = 0; i < variable_len - 2; ) {
1563 uint8_t ie_id, ie_len;
1570 /* This is the TIM Information Element */
1572 /* Check whether the ie_len is in the beacon data range. */
1573 if (variable_len < ie_len + 2 + i)
1575 /* A valid TIM is at least 4 bytes long. */
1580 tim_position = sizeof(struct b43_plcp_hdr6);
1581 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1584 dtim_period = ie[i + 3];
1586 b43_shm_write16(dev, B43_SHM_SHARED,
1587 B43_SHM_SH_TIMBPOS, tim_position);
1588 b43_shm_write16(dev, B43_SHM_SHARED,
1589 B43_SHM_SH_DTIMPER, dtim_period);
1596 * If ucode wants to modify TIM do it behind the beacon, this
1597 * will happen, for example, when doing mesh networking.
1599 b43_shm_write16(dev, B43_SHM_SHARED,
1601 len + sizeof(struct b43_plcp_hdr6));
1602 b43_shm_write16(dev, B43_SHM_SHARED,
1603 B43_SHM_SH_DTIMPER, 0);
1605 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1608 static void b43_upload_beacon0(struct b43_wldev *dev)
1610 struct b43_wl *wl = dev->wl;
1612 if (wl->beacon0_uploaded)
1614 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1615 wl->beacon0_uploaded = true;
1618 static void b43_upload_beacon1(struct b43_wldev *dev)
1620 struct b43_wl *wl = dev->wl;
1622 if (wl->beacon1_uploaded)
1624 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1625 wl->beacon1_uploaded = true;
1628 static void handle_irq_beacon(struct b43_wldev *dev)
1630 struct b43_wl *wl = dev->wl;
1631 u32 cmd, beacon0_valid, beacon1_valid;
1633 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1634 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1635 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1638 /* This is the bottom half of the asynchronous beacon update. */
1640 /* Ignore interrupt in the future. */
1641 dev->irq_mask &= ~B43_IRQ_BEACON;
1643 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1644 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1645 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1647 /* Schedule interrupt manually, if busy. */
1648 if (beacon0_valid && beacon1_valid) {
1649 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1650 dev->irq_mask |= B43_IRQ_BEACON;
1654 if (unlikely(wl->beacon_templates_virgin)) {
1655 /* We never uploaded a beacon before.
1656 * Upload both templates now, but only mark one valid. */
1657 wl->beacon_templates_virgin = false;
1658 b43_upload_beacon0(dev);
1659 b43_upload_beacon1(dev);
1660 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1661 cmd |= B43_MACCMD_BEACON0_VALID;
1662 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1664 if (!beacon0_valid) {
1665 b43_upload_beacon0(dev);
1666 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1667 cmd |= B43_MACCMD_BEACON0_VALID;
1668 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1669 } else if (!beacon1_valid) {
1670 b43_upload_beacon1(dev);
1671 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1672 cmd |= B43_MACCMD_BEACON1_VALID;
1673 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1678 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1680 u32 old_irq_mask = dev->irq_mask;
1682 /* update beacon right away or defer to irq */
1683 handle_irq_beacon(dev);
1684 if (old_irq_mask != dev->irq_mask) {
1685 /* The handler updated the IRQ mask. */
1686 B43_WARN_ON(!dev->irq_mask);
1687 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1688 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1690 /* Device interrupts are currently disabled. That means
1691 * we just ran the hardirq handler and scheduled the
1692 * IRQ thread. The thread will write the IRQ mask when
1693 * it finished, so there's nothing to do here. Writing
1694 * the mask _here_ would incorrectly re-enable IRQs. */
1699 static void b43_beacon_update_trigger_work(struct work_struct *work)
1701 struct b43_wl *wl = container_of(work, struct b43_wl,
1702 beacon_update_trigger);
1703 struct b43_wldev *dev;
1705 mutex_lock(&wl->mutex);
1706 dev = wl->current_dev;
1707 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1708 if (b43_bus_host_is_sdio(dev->dev)) {
1709 /* wl->mutex is enough. */
1710 b43_do_beacon_update_trigger_work(dev);
1713 spin_lock_irq(&wl->hardirq_lock);
1714 b43_do_beacon_update_trigger_work(dev);
1716 spin_unlock_irq(&wl->hardirq_lock);
1719 mutex_unlock(&wl->mutex);
1722 /* Asynchronously update the packet templates in template RAM.
1723 * Locking: Requires wl->mutex to be locked. */
1724 static void b43_update_templates(struct b43_wl *wl)
1726 struct sk_buff *beacon;
1728 /* This is the top half of the ansynchronous beacon update.
1729 * The bottom half is the beacon IRQ.
1730 * Beacon update must be asynchronous to avoid sending an
1731 * invalid beacon. This can happen for example, if the firmware
1732 * transmits a beacon while we are updating it. */
1734 /* We could modify the existing beacon and set the aid bit in
1735 * the TIM field, but that would probably require resizing and
1736 * moving of data within the beacon template.
1737 * Simply request a new beacon and let mac80211 do the hard work. */
1738 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1739 if (unlikely(!beacon))
1742 if (wl->current_beacon)
1743 dev_kfree_skb_any(wl->current_beacon);
1744 wl->current_beacon = beacon;
1745 wl->beacon0_uploaded = false;
1746 wl->beacon1_uploaded = false;
1747 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1750 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1753 if (dev->dev->core_rev >= 3) {
1754 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1755 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1757 b43_write16(dev, 0x606, (beacon_int >> 6));
1758 b43_write16(dev, 0x610, beacon_int);
1760 b43_time_unlock(dev);
1761 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1764 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1768 /* Read the register that contains the reason code for the panic. */
1769 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1770 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1774 b43dbg(dev->wl, "The panic reason is unknown.\n");
1776 case B43_FWPANIC_DIE:
1777 /* Do not restart the controller or firmware.
1778 * The device is nonfunctional from now on.
1779 * Restarting would result in this panic to trigger again,
1780 * so we avoid that recursion. */
1782 case B43_FWPANIC_RESTART:
1783 b43_controller_restart(dev, "Microcode panic");
1788 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1790 unsigned int i, cnt;
1791 u16 reason, marker_id, marker_line;
1794 /* The proprietary firmware doesn't have this IRQ. */
1795 if (!dev->fw.opensource)
1798 /* Read the register that contains the reason code for this IRQ. */
1799 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1802 case B43_DEBUGIRQ_PANIC:
1803 b43_handle_firmware_panic(dev);
1805 case B43_DEBUGIRQ_DUMP_SHM:
1807 break; /* Only with driver debugging enabled. */
1808 buf = kmalloc(4096, GFP_ATOMIC);
1810 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1813 for (i = 0; i < 4096; i += 2) {
1814 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1815 buf[i / 2] = cpu_to_le16(tmp);
1817 b43info(dev->wl, "Shared memory dump:\n");
1818 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1819 16, 2, buf, 4096, 1);
1822 case B43_DEBUGIRQ_DUMP_REGS:
1824 break; /* Only with driver debugging enabled. */
1825 b43info(dev->wl, "Microcode register dump:\n");
1826 for (i = 0, cnt = 0; i < 64; i++) {
1827 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1830 printk("r%02u: 0x%04X ", i, tmp);
1839 case B43_DEBUGIRQ_MARKER:
1841 break; /* Only with driver debugging enabled. */
1842 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1844 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1845 B43_MARKER_LINE_REG);
1846 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1847 "at line number %u\n",
1848 marker_id, marker_line);
1851 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1855 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1856 b43_shm_write16(dev, B43_SHM_SCRATCH,
1857 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1860 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1863 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1864 u32 merged_dma_reason = 0;
1867 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1870 reason = dev->irq_reason;
1871 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1872 dma_reason[i] = dev->dma_reason[i];
1873 merged_dma_reason |= dma_reason[i];
1876 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1877 b43err(dev->wl, "MAC transmission error\n");
1879 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1880 b43err(dev->wl, "PHY transmission error\n");
1882 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1883 atomic_set(&dev->phy.txerr_cnt,
1884 B43_PHY_TX_BADNESS_LIMIT);
1885 b43err(dev->wl, "Too many PHY TX errors, "
1886 "restarting the controller\n");
1887 b43_controller_restart(dev, "PHY TX errors");
1891 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1893 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1894 dma_reason[0], dma_reason[1],
1895 dma_reason[2], dma_reason[3],
1896 dma_reason[4], dma_reason[5]);
1897 b43err(dev->wl, "This device does not support DMA "
1898 "on your system. It will now be switched to PIO.\n");
1899 /* Fall back to PIO transfers if we get fatal DMA errors! */
1900 dev->use_pio = true;
1901 b43_controller_restart(dev, "DMA error");
1905 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1906 handle_irq_ucode_debug(dev);
1907 if (reason & B43_IRQ_TBTT_INDI)
1908 handle_irq_tbtt_indication(dev);
1909 if (reason & B43_IRQ_ATIM_END)
1910 handle_irq_atim_end(dev);
1911 if (reason & B43_IRQ_BEACON)
1912 handle_irq_beacon(dev);
1913 if (reason & B43_IRQ_PMQ)
1914 handle_irq_pmq(dev);
1915 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1917 if (reason & B43_IRQ_NOISESAMPLE_OK)
1918 handle_irq_noise(dev);
1920 /* Check the DMA reason registers for received data. */
1921 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1923 b43warn(dev->wl, "RX descriptor underrun\n");
1924 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1926 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1927 if (b43_using_pio_transfers(dev))
1928 b43_pio_rx(dev->pio.rx_queue);
1930 b43_dma_rx(dev->dma.rx_ring);
1932 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1933 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1934 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1935 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1936 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1938 if (reason & B43_IRQ_TX_OK)
1939 handle_irq_transmit_status(dev);
1941 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1942 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1945 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1947 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1948 if (reason & (1 << i))
1949 dev->irq_bit_count[i]++;
1955 /* Interrupt thread handler. Handles device interrupts in thread context. */
1956 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1958 struct b43_wldev *dev = dev_id;
1960 mutex_lock(&dev->wl->mutex);
1961 b43_do_interrupt_thread(dev);
1963 mutex_unlock(&dev->wl->mutex);
1968 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1972 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1973 * On SDIO, this runs under wl->mutex. */
1975 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1976 if (reason == 0xffffffff) /* shared IRQ */
1978 reason &= dev->irq_mask;
1982 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1984 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1986 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1988 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1990 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1993 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1997 /* ACK the interrupt. */
1998 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1999 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2000 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2001 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2002 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2003 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2005 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2008 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2009 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2010 /* Save the reason bitmasks for the IRQ thread handler. */
2011 dev->irq_reason = reason;
2013 return IRQ_WAKE_THREAD;
2016 /* Interrupt handler top-half. This runs with interrupts disabled. */
2017 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2019 struct b43_wldev *dev = dev_id;
2022 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2025 spin_lock(&dev->wl->hardirq_lock);
2026 ret = b43_do_interrupt(dev);
2028 spin_unlock(&dev->wl->hardirq_lock);
2033 /* SDIO interrupt handler. This runs in process context. */
2034 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2036 struct b43_wl *wl = dev->wl;
2039 mutex_lock(&wl->mutex);
2041 ret = b43_do_interrupt(dev);
2042 if (ret == IRQ_WAKE_THREAD)
2043 b43_do_interrupt_thread(dev);
2045 mutex_unlock(&wl->mutex);
2048 void b43_do_release_fw(struct b43_firmware_file *fw)
2050 release_firmware(fw->data);
2052 fw->filename = NULL;
2055 static void b43_release_firmware(struct b43_wldev *dev)
2057 complete(&dev->fw_load_complete);
2058 b43_do_release_fw(&dev->fw.ucode);
2059 b43_do_release_fw(&dev->fw.pcm);
2060 b43_do_release_fw(&dev->fw.initvals);
2061 b43_do_release_fw(&dev->fw.initvals_band);
2064 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2068 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2069 "and download the correct firmware for this driver version. " \
2070 "Please carefully read all instructions on this website.\n";
2078 static void b43_fw_cb(const struct firmware *firmware, void *context)
2080 struct b43_request_fw_context *ctx = context;
2082 ctx->blob = firmware;
2083 complete(&ctx->dev->fw_load_complete);
2086 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2088 struct b43_firmware_file *fw, bool async)
2090 struct b43_fw_header *hdr;
2095 /* Don't fetch anything. Free possibly cached firmware. */
2096 /* FIXME: We should probably keep it anyway, to save some headache
2097 * on suspend/resume with multiband devices. */
2098 b43_do_release_fw(fw);
2102 if ((fw->type == ctx->req_type) &&
2103 (strcmp(fw->filename, name) == 0))
2104 return 0; /* Already have this fw. */
2105 /* Free the cached firmware first. */
2106 /* FIXME: We should probably do this later after we successfully
2107 * got the new fw. This could reduce headache with multiband devices.
2108 * We could also redesign this to cache the firmware for all possible
2109 * bands all the time. */
2110 b43_do_release_fw(fw);
2113 switch (ctx->req_type) {
2114 case B43_FWTYPE_PROPRIETARY:
2115 snprintf(ctx->fwname, sizeof(ctx->fwname),
2117 modparam_fwpostfix, name);
2119 case B43_FWTYPE_OPENSOURCE:
2120 snprintf(ctx->fwname, sizeof(ctx->fwname),
2122 modparam_fwpostfix, name);
2129 /* do this part asynchronously */
2130 init_completion(&ctx->dev->fw_load_complete);
2131 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2132 ctx->dev->dev->dev, GFP_KERNEL,
2135 pr_err("Unable to load firmware\n");
2138 wait_for_completion(&ctx->dev->fw_load_complete);
2141 /* On some ARM systems, the async request will fail, but the next sync
2142 * request works. For this reason, we fall through here
2145 err = request_firmware(&ctx->blob, ctx->fwname,
2146 ctx->dev->dev->dev);
2147 if (err == -ENOENT) {
2148 snprintf(ctx->errors[ctx->req_type],
2149 sizeof(ctx->errors[ctx->req_type]),
2150 "Firmware file \"%s\" not found\n",
2154 snprintf(ctx->errors[ctx->req_type],
2155 sizeof(ctx->errors[ctx->req_type]),
2156 "Firmware file \"%s\" request failed (err=%d)\n",
2161 if (ctx->blob->size < sizeof(struct b43_fw_header))
2163 hdr = (struct b43_fw_header *)(ctx->blob->data);
2164 switch (hdr->type) {
2165 case B43_FW_TYPE_UCODE:
2166 case B43_FW_TYPE_PCM:
2167 size = be32_to_cpu(hdr->size);
2168 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2171 case B43_FW_TYPE_IV:
2179 fw->data = ctx->blob;
2180 fw->filename = name;
2181 fw->type = ctx->req_type;
2186 snprintf(ctx->errors[ctx->req_type],
2187 sizeof(ctx->errors[ctx->req_type]),
2188 "Firmware file \"%s\" format error.\n", ctx->fwname);
2189 release_firmware(ctx->blob);
2194 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2196 struct b43_wldev *dev = ctx->dev;
2197 struct b43_firmware *fw = &ctx->dev->fw;
2198 const u8 rev = ctx->dev->dev->core_rev;
2199 const char *filename;
2203 /* Files for HT and LCN were found by trying one by one */
2206 if ((rev >= 5) && (rev <= 10)) {
2207 filename = "ucode5";
2208 } else if ((rev >= 11) && (rev <= 12)) {
2209 filename = "ucode11";
2210 } else if (rev == 13) {
2211 filename = "ucode13";
2212 } else if (rev == 14) {
2213 filename = "ucode14";
2214 } else if (rev == 15) {
2215 filename = "ucode15";
2217 switch (dev->phy.type) {
2220 filename = "ucode16_mimo";
2224 case B43_PHYTYPE_HT:
2226 filename = "ucode29_mimo";
2230 case B43_PHYTYPE_LCN:
2232 filename = "ucode24_mimo";
2240 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2245 if ((rev >= 5) && (rev <= 10))
2251 fw->pcm_request_failed = false;
2252 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2253 if (err == -ENOENT) {
2254 /* We did not find a PCM file? Not fatal, but
2255 * core rev <= 10 must do without hwcrypto then. */
2256 fw->pcm_request_failed = true;
2261 switch (dev->phy.type) {
2263 if ((rev >= 5) && (rev <= 10)) {
2264 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2265 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2266 filename = "a0g1initvals5";
2268 filename = "a0g0initvals5";
2270 goto err_no_initvals;
2273 if ((rev >= 5) && (rev <= 10))
2274 filename = "b0g0initvals5";
2276 filename = "b0g0initvals13";
2278 goto err_no_initvals;
2282 filename = "n0initvals16";
2283 else if ((rev >= 11) && (rev <= 12))
2284 filename = "n0initvals11";
2286 goto err_no_initvals;
2288 case B43_PHYTYPE_LP:
2290 filename = "lp0initvals13";
2292 filename = "lp0initvals14";
2294 filename = "lp0initvals15";
2296 goto err_no_initvals;
2298 case B43_PHYTYPE_HT:
2300 filename = "ht0initvals29";
2302 goto err_no_initvals;
2304 case B43_PHYTYPE_LCN:
2306 filename = "lcn0initvals24";
2308 goto err_no_initvals;
2311 goto err_no_initvals;
2313 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2317 /* Get bandswitch initvals */
2318 switch (dev->phy.type) {
2320 if ((rev >= 5) && (rev <= 10)) {
2321 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2322 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2323 filename = "a0g1bsinitvals5";
2325 filename = "a0g0bsinitvals5";
2326 } else if (rev >= 11)
2329 goto err_no_initvals;
2332 if ((rev >= 5) && (rev <= 10))
2333 filename = "b0g0bsinitvals5";
2337 goto err_no_initvals;
2341 filename = "n0bsinitvals16";
2342 else if ((rev >= 11) && (rev <= 12))
2343 filename = "n0bsinitvals11";
2345 goto err_no_initvals;
2347 case B43_PHYTYPE_LP:
2349 filename = "lp0bsinitvals13";
2351 filename = "lp0bsinitvals14";
2353 filename = "lp0bsinitvals15";
2355 goto err_no_initvals;
2357 case B43_PHYTYPE_HT:
2359 filename = "ht0bsinitvals29";
2361 goto err_no_initvals;
2363 case B43_PHYTYPE_LCN:
2365 filename = "lcn0bsinitvals24";
2367 goto err_no_initvals;
2370 goto err_no_initvals;
2372 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2376 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2381 err = ctx->fatal_failure = -EOPNOTSUPP;
2382 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2383 "is required for your device (wl-core rev %u)\n", rev);
2387 err = ctx->fatal_failure = -EOPNOTSUPP;
2388 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2389 "is required for your device (wl-core rev %u)\n", rev);
2393 err = ctx->fatal_failure = -EOPNOTSUPP;
2394 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2395 "is required for your device (wl-core rev %u)\n", rev);
2399 /* We failed to load this firmware image. The error message
2400 * already is in ctx->errors. Return and let our caller decide
2405 b43_release_firmware(dev);
2409 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2410 static void b43_one_core_detach(struct b43_bus_dev *dev);
2411 static int b43_rng_init(struct b43_wl *wl);
2413 static void b43_request_firmware(struct work_struct *work)
2415 struct b43_wl *wl = container_of(work,
2416 struct b43_wl, firmware_load);
2417 struct b43_wldev *dev = wl->current_dev;
2418 struct b43_request_fw_context *ctx;
2423 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2428 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2429 err = b43_try_request_fw(ctx);
2431 goto start_ieee80211; /* Successfully loaded it. */
2432 /* Was fw version known? */
2433 if (ctx->fatal_failure)
2436 /* proprietary fw not found, try open source */
2437 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2438 err = b43_try_request_fw(ctx);
2440 goto start_ieee80211; /* Successfully loaded it. */
2441 if(ctx->fatal_failure)
2444 /* Could not find a usable firmware. Print the errors. */
2445 for (i = 0; i < B43_NR_FWTYPES; i++) {
2446 errmsg = ctx->errors[i];
2448 b43err(dev->wl, "%s", errmsg);
2450 b43_print_fw_helptext(dev->wl, 1);
2454 wl->hw->queues = B43_QOS_QUEUE_NUM;
2455 if (!modparam_qos || dev->fw.opensource)
2458 err = ieee80211_register_hw(wl->hw);
2460 goto err_one_core_detach;
2461 wl->hw_registred = true;
2462 b43_leds_register(wl->current_dev);
2464 /* Register HW RNG driver */
2469 err_one_core_detach:
2470 b43_one_core_detach(dev->dev);
2476 static int b43_upload_microcode(struct b43_wldev *dev)
2478 struct wiphy *wiphy = dev->wl->hw->wiphy;
2479 const size_t hdr_len = sizeof(struct b43_fw_header);
2481 unsigned int i, len;
2482 u16 fwrev, fwpatch, fwdate, fwtime;
2486 /* Jump the microcode PSM to offset 0 */
2487 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2488 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2489 macctl |= B43_MACCTL_PSM_JMP0;
2490 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2491 /* Zero out all microcode PSM registers and shared memory. */
2492 for (i = 0; i < 64; i++)
2493 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2494 for (i = 0; i < 4096; i += 2)
2495 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2497 /* Upload Microcode. */
2498 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2499 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2500 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2501 for (i = 0; i < len; i++) {
2502 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2506 if (dev->fw.pcm.data) {
2507 /* Upload PCM data. */
2508 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2509 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2510 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2511 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2512 /* No need for autoinc bit in SHM_HW */
2513 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2514 for (i = 0; i < len; i++) {
2515 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2520 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2522 /* Start the microcode PSM */
2523 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2524 B43_MACCTL_PSM_RUN);
2526 /* Wait for the microcode to load and respond */
2529 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2530 if (tmp == B43_IRQ_MAC_SUSPENDED)
2534 b43err(dev->wl, "Microcode not responding\n");
2535 b43_print_fw_helptext(dev->wl, 1);
2541 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2543 /* Get and check the revisions. */
2544 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2545 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2546 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2547 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2549 if (fwrev <= 0x128) {
2550 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2551 "binary drivers older than version 4.x is unsupported. "
2552 "You must upgrade your firmware files.\n");
2553 b43_print_fw_helptext(dev->wl, 1);
2557 dev->fw.rev = fwrev;
2558 dev->fw.patch = fwpatch;
2559 if (dev->fw.rev >= 598)
2560 dev->fw.hdr_format = B43_FW_HDR_598;
2561 else if (dev->fw.rev >= 410)
2562 dev->fw.hdr_format = B43_FW_HDR_410;
2564 dev->fw.hdr_format = B43_FW_HDR_351;
2565 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2567 dev->qos_enabled = dev->wl->hw->queues > 1;
2568 /* Default to firmware/hardware crypto acceleration. */
2569 dev->hwcrypto_enabled = true;
2571 if (dev->fw.opensource) {
2574 /* Patchlevel info is encoded in the "time" field. */
2575 dev->fw.patch = fwtime;
2576 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2577 dev->fw.rev, dev->fw.patch);
2579 fwcapa = b43_fwcapa_read(dev);
2580 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2581 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2582 /* Disable hardware crypto and fall back to software crypto. */
2583 dev->hwcrypto_enabled = false;
2585 /* adding QoS support should use an offline discovery mechanism */
2586 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2588 b43info(dev->wl, "Loading firmware version %u.%u "
2589 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2591 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2592 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2593 if (dev->fw.pcm_request_failed) {
2594 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2595 "Hardware accelerated cryptography is disabled.\n");
2596 b43_print_fw_helptext(dev->wl, 0);
2600 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2601 dev->fw.rev, dev->fw.patch);
2602 wiphy->hw_version = dev->dev->core_id;
2604 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2605 /* We're over the deadline, but we keep support for old fw
2606 * until it turns out to be in major conflict with something new. */
2607 b43warn(dev->wl, "You are using an old firmware image. "
2608 "Support for old firmware will be removed soon "
2609 "(official deadline was July 2008).\n");
2610 b43_print_fw_helptext(dev->wl, 0);
2616 /* Stop the microcode PSM. */
2617 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2618 B43_MACCTL_PSM_JMP0);
2623 static int b43_write_initvals(struct b43_wldev *dev,
2624 const struct b43_iv *ivals,
2628 const struct b43_iv *iv;
2633 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2635 for (i = 0; i < count; i++) {
2636 if (array_size < sizeof(iv->offset_size))
2638 array_size -= sizeof(iv->offset_size);
2639 offset = be16_to_cpu(iv->offset_size);
2640 bit32 = !!(offset & B43_IV_32BIT);
2641 offset &= B43_IV_OFFSET_MASK;
2642 if (offset >= 0x1000)
2647 if (array_size < sizeof(iv->data.d32))
2649 array_size -= sizeof(iv->data.d32);
2651 value = get_unaligned_be32(&iv->data.d32);
2652 b43_write32(dev, offset, value);
2654 iv = (const struct b43_iv *)((const uint8_t *)iv +
2660 if (array_size < sizeof(iv->data.d16))
2662 array_size -= sizeof(iv->data.d16);
2664 value = be16_to_cpu(iv->data.d16);
2665 b43_write16(dev, offset, value);
2667 iv = (const struct b43_iv *)((const uint8_t *)iv +
2678 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2679 b43_print_fw_helptext(dev->wl, 1);
2684 static int b43_upload_initvals(struct b43_wldev *dev)
2686 const size_t hdr_len = sizeof(struct b43_fw_header);
2687 const struct b43_fw_header *hdr;
2688 struct b43_firmware *fw = &dev->fw;
2689 const struct b43_iv *ivals;
2692 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2693 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2694 count = be32_to_cpu(hdr->size);
2695 return b43_write_initvals(dev, ivals, count,
2696 fw->initvals.data->size - hdr_len);
2699 static int b43_upload_initvals_band(struct b43_wldev *dev)
2701 const size_t hdr_len = sizeof(struct b43_fw_header);
2702 const struct b43_fw_header *hdr;
2703 struct b43_firmware *fw = &dev->fw;
2704 const struct b43_iv *ivals;
2707 if (!fw->initvals_band.data)
2710 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2711 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2712 count = be32_to_cpu(hdr->size);
2713 return b43_write_initvals(dev, ivals, count,
2714 fw->initvals_band.data->size - hdr_len);
2717 /* Initialize the GPIOs
2718 * http://bcm-specs.sipsolutions.net/GPIO
2721 #ifdef CONFIG_B43_SSB
2722 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2724 struct ssb_bus *bus = dev->dev->sdev->bus;
2726 #ifdef CONFIG_SSB_DRIVER_PCICORE
2727 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2729 return bus->chipco.dev;
2734 static int b43_gpio_init(struct b43_wldev *dev)
2736 #ifdef CONFIG_B43_SSB
2737 struct ssb_device *gpiodev;
2741 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2742 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2746 if (dev->dev->chip_id == 0x4301) {
2749 } else if (dev->dev->chip_id == 0x5354) {
2750 /* Don't allow overtaking buttons GPIOs */
2751 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2754 if (0 /* FIXME: conditional unknown */ ) {
2755 b43_write16(dev, B43_MMIO_GPIO_MASK,
2756 b43_read16(dev, B43_MMIO_GPIO_MASK)
2758 /* BT Coexistance Input */
2761 /* BT Coexistance Out */
2765 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2766 /* PA is controlled by gpio 9, let ucode handle it */
2767 b43_write16(dev, B43_MMIO_GPIO_MASK,
2768 b43_read16(dev, B43_MMIO_GPIO_MASK)
2774 switch (dev->dev->bus_type) {
2775 #ifdef CONFIG_B43_BCMA
2777 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2780 #ifdef CONFIG_B43_SSB
2782 gpiodev = b43_ssb_gpio_dev(dev);
2784 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2785 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2794 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2795 static void b43_gpio_cleanup(struct b43_wldev *dev)
2797 #ifdef CONFIG_B43_SSB
2798 struct ssb_device *gpiodev;
2801 switch (dev->dev->bus_type) {
2802 #ifdef CONFIG_B43_BCMA
2804 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2807 #ifdef CONFIG_B43_SSB
2809 gpiodev = b43_ssb_gpio_dev(dev);
2811 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2817 /* http://bcm-specs.sipsolutions.net/EnableMac */
2818 void b43_mac_enable(struct b43_wldev *dev)
2820 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2823 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2824 B43_SHM_SH_UCODESTAT);
2825 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2826 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2827 b43err(dev->wl, "b43_mac_enable(): The firmware "
2828 "should be suspended, but current state is %u\n",
2833 dev->mac_suspended--;
2834 B43_WARN_ON(dev->mac_suspended < 0);
2835 if (dev->mac_suspended == 0) {
2836 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2837 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2838 B43_IRQ_MAC_SUSPENDED);
2840 b43_read32(dev, B43_MMIO_MACCTL);
2841 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2842 b43_power_saving_ctl_bits(dev, 0);
2846 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2847 void b43_mac_suspend(struct b43_wldev *dev)
2853 B43_WARN_ON(dev->mac_suspended < 0);
2855 if (dev->mac_suspended == 0) {
2856 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2857 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2858 /* force pci to flush the write */
2859 b43_read32(dev, B43_MMIO_MACCTL);
2860 for (i = 35; i; i--) {
2861 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2862 if (tmp & B43_IRQ_MAC_SUSPENDED)
2866 /* Hm, it seems this will take some time. Use msleep(). */
2867 for (i = 40; i; i--) {
2868 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2869 if (tmp & B43_IRQ_MAC_SUSPENDED)
2873 b43err(dev->wl, "MAC suspend failed\n");
2876 dev->mac_suspended++;
2879 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2880 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2884 switch (dev->dev->bus_type) {
2885 #ifdef CONFIG_B43_BCMA
2887 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2889 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2891 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2892 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2895 #ifdef CONFIG_B43_SSB
2897 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2899 tmp |= B43_TMSLOW_MACPHYCLKEN;
2901 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2902 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2908 static void b43_adjust_opmode(struct b43_wldev *dev)
2910 struct b43_wl *wl = dev->wl;
2914 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2915 /* Reset status to STA infrastructure mode. */
2916 ctl &= ~B43_MACCTL_AP;
2917 ctl &= ~B43_MACCTL_KEEP_CTL;
2918 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2919 ctl &= ~B43_MACCTL_KEEP_BAD;
2920 ctl &= ~B43_MACCTL_PROMISC;
2921 ctl &= ~B43_MACCTL_BEACPROMISC;
2922 ctl |= B43_MACCTL_INFRA;
2924 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2925 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2926 ctl |= B43_MACCTL_AP;
2927 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2928 ctl &= ~B43_MACCTL_INFRA;
2930 if (wl->filter_flags & FIF_CONTROL)
2931 ctl |= B43_MACCTL_KEEP_CTL;
2932 if (wl->filter_flags & FIF_FCSFAIL)
2933 ctl |= B43_MACCTL_KEEP_BAD;
2934 if (wl->filter_flags & FIF_PLCPFAIL)
2935 ctl |= B43_MACCTL_KEEP_BADPLCP;
2936 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2937 ctl |= B43_MACCTL_PROMISC;
2938 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2939 ctl |= B43_MACCTL_BEACPROMISC;
2941 /* Workaround: On old hardware the HW-MAC-address-filter
2942 * doesn't work properly, so always run promisc in filter
2943 * it in software. */
2944 if (dev->dev->core_rev <= 4)
2945 ctl |= B43_MACCTL_PROMISC;
2947 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2950 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2951 if (dev->dev->chip_id == 0x4306 &&
2952 dev->dev->chip_rev == 3)
2957 b43_write16(dev, 0x612, cfp_pretbtt);
2959 /* FIXME: We don't currently implement the PMQ mechanism,
2960 * so always disable it. If we want to implement PMQ,
2961 * we need to enable it here (clear DISCPMQ) in AP mode.
2963 if (0 /* ctl & B43_MACCTL_AP */)
2964 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2966 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2969 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2975 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2978 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2980 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2981 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2984 static void b43_rate_memory_init(struct b43_wldev *dev)
2986 switch (dev->phy.type) {
2990 case B43_PHYTYPE_LP:
2991 case B43_PHYTYPE_HT:
2992 case B43_PHYTYPE_LCN:
2993 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2994 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2995 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2996 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2997 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2998 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2999 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3000 if (dev->phy.type == B43_PHYTYPE_A)
3004 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3005 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3006 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3007 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3014 /* Set the default values for the PHY TX Control Words. */
3015 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3019 ctl |= B43_TXH_PHY_ENC_CCK;
3020 ctl |= B43_TXH_PHY_ANT01AUTO;
3021 ctl |= B43_TXH_PHY_TXPWR;
3023 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3024 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3025 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3028 /* Set the TX-Antenna for management frames sent by firmware. */
3029 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3034 ant = b43_antenna_to_phyctl(antenna);
3037 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3038 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3039 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3040 /* For Probe Resposes */
3041 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3042 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3043 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3046 /* This is the opposite of b43_chip_init() */
3047 static void b43_chip_exit(struct b43_wldev *dev)
3050 b43_gpio_cleanup(dev);
3051 /* firmware is released later */
3054 /* Initialize the chip
3055 * http://bcm-specs.sipsolutions.net/ChipInit
3057 static int b43_chip_init(struct b43_wldev *dev)
3059 struct b43_phy *phy = &dev->phy;
3064 /* Initialize the MAC control */
3065 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3067 macctl |= B43_MACCTL_GMODE;
3068 macctl |= B43_MACCTL_INFRA;
3069 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3071 err = b43_upload_microcode(dev);
3073 goto out; /* firmware is released later */
3075 err = b43_gpio_init(dev);
3077 goto out; /* firmware is released later */
3079 err = b43_upload_initvals(dev);
3081 goto err_gpio_clean;
3083 err = b43_upload_initvals_band(dev);
3085 goto err_gpio_clean;
3087 /* Turn the Analog on and initialize the PHY. */
3088 phy->ops->switch_analog(dev, 1);
3089 err = b43_phy_init(dev);
3091 goto err_gpio_clean;
3093 /* Disable Interference Mitigation. */
3094 if (phy->ops->interf_mitigation)
3095 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3097 /* Select the antennae */
3098 if (phy->ops->set_rx_antenna)
3099 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3100 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3102 if (phy->type == B43_PHYTYPE_B) {
3103 value16 = b43_read16(dev, 0x005E);
3105 b43_write16(dev, 0x005E, value16);
3107 b43_write32(dev, 0x0100, 0x01000000);
3108 if (dev->dev->core_rev < 5)
3109 b43_write32(dev, 0x010C, 0x01000000);
3111 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3112 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3114 /* Probe Response Timeout value */
3115 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3116 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3118 /* Initially set the wireless operation mode. */
3119 b43_adjust_opmode(dev);
3121 if (dev->dev->core_rev < 3) {
3122 b43_write16(dev, 0x060E, 0x0000);
3123 b43_write16(dev, 0x0610, 0x8000);
3124 b43_write16(dev, 0x0604, 0x0000);
3125 b43_write16(dev, 0x0606, 0x0200);
3127 b43_write32(dev, 0x0188, 0x80000000);
3128 b43_write32(dev, 0x018C, 0x02000000);
3130 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3131 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3132 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3133 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3134 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3135 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3136 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3138 b43_mac_phy_clock_set(dev, true);
3140 switch (dev->dev->bus_type) {
3141 #ifdef CONFIG_B43_BCMA
3143 /* FIXME: 0xE74 is quite common, but should be read from CC */
3144 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3147 #ifdef CONFIG_B43_SSB
3149 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3150 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3156 b43dbg(dev->wl, "Chip initialized\n");
3161 b43_gpio_cleanup(dev);
3165 static void b43_periodic_every60sec(struct b43_wldev *dev)
3167 const struct b43_phy_operations *ops = dev->phy.ops;
3169 if (ops->pwork_60sec)
3170 ops->pwork_60sec(dev);
3172 /* Force check the TX power emission now. */
3173 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3176 static void b43_periodic_every30sec(struct b43_wldev *dev)
3178 /* Update device statistics. */
3179 b43_calculate_link_quality(dev);
3182 static void b43_periodic_every15sec(struct b43_wldev *dev)
3184 struct b43_phy *phy = &dev->phy;
3187 if (dev->fw.opensource) {
3188 /* Check if the firmware is still alive.
3189 * It will reset the watchdog counter to 0 in its idle loop. */
3190 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3191 if (unlikely(wdr)) {
3192 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3193 b43_controller_restart(dev, "Firmware watchdog");
3196 b43_shm_write16(dev, B43_SHM_SCRATCH,
3197 B43_WATCHDOG_REG, 1);
3201 if (phy->ops->pwork_15sec)
3202 phy->ops->pwork_15sec(dev);
3204 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3208 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3211 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3212 dev->irq_count / 15,
3214 dev->rx_count / 15);
3218 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3219 if (dev->irq_bit_count[i]) {
3220 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3221 dev->irq_bit_count[i] / 15, i, (1 << i));
3222 dev->irq_bit_count[i] = 0;
3229 static void do_periodic_work(struct b43_wldev *dev)
3233 state = dev->periodic_state;
3235 b43_periodic_every60sec(dev);
3237 b43_periodic_every30sec(dev);
3238 b43_periodic_every15sec(dev);
3241 /* Periodic work locking policy:
3242 * The whole periodic work handler is protected by
3243 * wl->mutex. If another lock is needed somewhere in the
3244 * pwork callchain, it's acquired in-place, where it's needed.
3246 static void b43_periodic_work_handler(struct work_struct *work)
3248 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3249 periodic_work.work);
3250 struct b43_wl *wl = dev->wl;
3251 unsigned long delay;
3253 mutex_lock(&wl->mutex);
3255 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3257 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3260 do_periodic_work(dev);
3262 dev->periodic_state++;
3264 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3265 delay = msecs_to_jiffies(50);
3267 delay = round_jiffies_relative(HZ * 15);
3268 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3270 mutex_unlock(&wl->mutex);
3273 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3275 struct delayed_work *work = &dev->periodic_work;
3277 dev->periodic_state = 0;
3278 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3279 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3282 /* Check if communication with the device works correctly. */
3283 static int b43_validate_chipaccess(struct b43_wldev *dev)
3285 u32 v, backup0, backup4;
3287 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3288 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3290 /* Check for read/write and endianness problems. */
3291 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3292 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3294 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3295 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3298 /* Check if unaligned 32bit SHM_SHARED access works properly.
3299 * However, don't bail out on failure, because it's noncritical. */
3300 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3301 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3302 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3303 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3304 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3305 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3306 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3307 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3308 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3309 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3310 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3311 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3313 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3314 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3316 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3317 /* The 32bit register shadows the two 16bit registers
3318 * with update sideeffects. Validate this. */
3319 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3320 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3321 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3323 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3326 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3328 v = b43_read32(dev, B43_MMIO_MACCTL);
3329 v |= B43_MACCTL_GMODE;
3330 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3335 b43err(dev->wl, "Failed to validate the chipaccess\n");
3339 static void b43_security_init(struct b43_wldev *dev)
3341 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3342 /* KTP is a word address, but we address SHM bytewise.
3343 * So multiply by two.
3346 /* Number of RCMTA address slots */
3347 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3348 /* Clear the key memory. */
3349 b43_clear_keys(dev);
3352 #ifdef CONFIG_B43_HWRNG
3353 static int b43_rng_read(struct hwrng *rng, u32 *data)
3355 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3356 struct b43_wldev *dev;
3357 int count = -ENODEV;
3359 mutex_lock(&wl->mutex);
3360 dev = wl->current_dev;
3361 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3362 *data = b43_read16(dev, B43_MMIO_RNG);
3363 count = sizeof(u16);
3365 mutex_unlock(&wl->mutex);
3369 #endif /* CONFIG_B43_HWRNG */
3371 static void b43_rng_exit(struct b43_wl *wl)
3373 #ifdef CONFIG_B43_HWRNG
3374 if (wl->rng_initialized)
3375 hwrng_unregister(&wl->rng);
3376 #endif /* CONFIG_B43_HWRNG */
3379 static int b43_rng_init(struct b43_wl *wl)
3383 #ifdef CONFIG_B43_HWRNG
3384 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3385 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3386 wl->rng.name = wl->rng_name;
3387 wl->rng.data_read = b43_rng_read;
3388 wl->rng.priv = (unsigned long)wl;
3389 wl->rng_initialized = true;
3390 err = hwrng_register(&wl->rng);
3392 wl->rng_initialized = false;
3393 b43err(wl, "Failed to register the random "
3394 "number generator (%d)\n", err);
3396 #endif /* CONFIG_B43_HWRNG */
3401 static void b43_tx_work(struct work_struct *work)
3403 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3404 struct b43_wldev *dev;
3405 struct sk_buff *skb;
3409 mutex_lock(&wl->mutex);
3410 dev = wl->current_dev;
3411 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3412 mutex_unlock(&wl->mutex);
3416 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3417 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3418 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3419 if (b43_using_pio_transfers(dev))
3420 err = b43_pio_tx(dev, skb);
3422 err = b43_dma_tx(dev, skb);
3423 if (err == -ENOSPC) {
3424 wl->tx_queue_stopped[queue_num] = 1;
3425 ieee80211_stop_queue(wl->hw, queue_num);
3426 skb_queue_head(&wl->tx_queue[queue_num], skb);
3430 ieee80211_free_txskb(wl->hw, skb);
3435 wl->tx_queue_stopped[queue_num] = 0;
3441 mutex_unlock(&wl->mutex);
3444 static void b43_op_tx(struct ieee80211_hw *hw,
3445 struct ieee80211_tx_control *control,
3446 struct sk_buff *skb)
3448 struct b43_wl *wl = hw_to_b43_wl(hw);
3450 if (unlikely(skb->len < 2 + 2 + 6)) {
3451 /* Too short, this can't be a valid frame. */
3452 ieee80211_free_txskb(hw, skb);
3455 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3457 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3458 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3459 ieee80211_queue_work(wl->hw, &wl->tx_work);
3461 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3465 static void b43_qos_params_upload(struct b43_wldev *dev,
3466 const struct ieee80211_tx_queue_params *p,
3469 u16 params[B43_NR_QOSPARAMS];
3473 if (!dev->qos_enabled)
3476 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3478 memset(¶ms, 0, sizeof(params));
3480 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3481 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3482 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3483 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3484 params[B43_QOSPARAM_AIFS] = p->aifs;
3485 params[B43_QOSPARAM_BSLOTS] = bslots;
3486 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3488 for (i = 0; i < ARRAY_SIZE(params); i++) {
3489 if (i == B43_QOSPARAM_STATUS) {
3490 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3491 shm_offset + (i * 2));
3492 /* Mark the parameters as updated. */
3494 b43_shm_write16(dev, B43_SHM_SHARED,
3495 shm_offset + (i * 2),
3498 b43_shm_write16(dev, B43_SHM_SHARED,
3499 shm_offset + (i * 2),
3505 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3506 static const u16 b43_qos_shm_offsets[] = {
3507 /* [mac80211-queue-nr] = SHM_OFFSET, */
3508 [0] = B43_QOS_VOICE,
3509 [1] = B43_QOS_VIDEO,
3510 [2] = B43_QOS_BESTEFFORT,
3511 [3] = B43_QOS_BACKGROUND,
3514 /* Update all QOS parameters in hardware. */
3515 static void b43_qos_upload_all(struct b43_wldev *dev)
3517 struct b43_wl *wl = dev->wl;
3518 struct b43_qos_params *params;
3521 if (!dev->qos_enabled)
3524 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3525 ARRAY_SIZE(wl->qos_params));
3527 b43_mac_suspend(dev);
3528 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3529 params = &(wl->qos_params[i]);
3530 b43_qos_params_upload(dev, &(params->p),
3531 b43_qos_shm_offsets[i]);
3533 b43_mac_enable(dev);
3536 static void b43_qos_clear(struct b43_wl *wl)
3538 struct b43_qos_params *params;
3541 /* Initialize QoS parameters to sane defaults. */
3543 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3544 ARRAY_SIZE(wl->qos_params));
3546 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3547 params = &(wl->qos_params[i]);
3549 switch (b43_qos_shm_offsets[i]) {
3553 params->p.cw_min = 0x0001;
3554 params->p.cw_max = 0x0001;
3559 params->p.cw_min = 0x0001;
3560 params->p.cw_max = 0x0001;
3562 case B43_QOS_BESTEFFORT:
3565 params->p.cw_min = 0x0001;
3566 params->p.cw_max = 0x03FF;
3568 case B43_QOS_BACKGROUND:
3571 params->p.cw_min = 0x0001;
3572 params->p.cw_max = 0x03FF;
3580 /* Initialize the core's QOS capabilities */
3581 static void b43_qos_init(struct b43_wldev *dev)
3583 if (!dev->qos_enabled) {
3584 /* Disable QOS support. */
3585 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3586 b43_write16(dev, B43_MMIO_IFSCTL,
3587 b43_read16(dev, B43_MMIO_IFSCTL)
3588 & ~B43_MMIO_IFSCTL_USE_EDCF);
3589 b43dbg(dev->wl, "QoS disabled\n");
3593 /* Upload the current QOS parameters. */
3594 b43_qos_upload_all(dev);
3596 /* Enable QOS support. */
3597 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3598 b43_write16(dev, B43_MMIO_IFSCTL,
3599 b43_read16(dev, B43_MMIO_IFSCTL)
3600 | B43_MMIO_IFSCTL_USE_EDCF);
3601 b43dbg(dev->wl, "QoS enabled\n");
3604 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3605 struct ieee80211_vif *vif, u16 _queue,
3606 const struct ieee80211_tx_queue_params *params)
3608 struct b43_wl *wl = hw_to_b43_wl(hw);
3609 struct b43_wldev *dev;
3610 unsigned int queue = (unsigned int)_queue;
3613 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3614 /* Queue not available or don't support setting
3615 * params on this queue. Return success to not
3616 * confuse mac80211. */
3619 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3620 ARRAY_SIZE(wl->qos_params));
3622 mutex_lock(&wl->mutex);
3623 dev = wl->current_dev;
3624 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3627 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3628 b43_mac_suspend(dev);
3629 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3630 b43_qos_shm_offsets[queue]);
3631 b43_mac_enable(dev);
3635 mutex_unlock(&wl->mutex);
3640 static int b43_op_get_stats(struct ieee80211_hw *hw,
3641 struct ieee80211_low_level_stats *stats)
3643 struct b43_wl *wl = hw_to_b43_wl(hw);
3645 mutex_lock(&wl->mutex);
3646 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3647 mutex_unlock(&wl->mutex);
3652 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3654 struct b43_wl *wl = hw_to_b43_wl(hw);
3655 struct b43_wldev *dev;
3658 mutex_lock(&wl->mutex);
3659 dev = wl->current_dev;
3661 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3662 b43_tsf_read(dev, &tsf);
3666 mutex_unlock(&wl->mutex);
3671 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3672 struct ieee80211_vif *vif, u64 tsf)
3674 struct b43_wl *wl = hw_to_b43_wl(hw);
3675 struct b43_wldev *dev;
3677 mutex_lock(&wl->mutex);
3678 dev = wl->current_dev;
3680 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3681 b43_tsf_write(dev, tsf);
3683 mutex_unlock(&wl->mutex);
3686 static const char *band_to_string(enum ieee80211_band band)
3689 case IEEE80211_BAND_5GHZ:
3691 case IEEE80211_BAND_2GHZ:
3700 /* Expects wl->mutex locked */
3701 static int b43_switch_band(struct b43_wldev *dev,
3702 struct ieee80211_channel *chan)
3704 struct b43_phy *phy = &dev->phy;
3708 switch (chan->band) {
3709 case IEEE80211_BAND_5GHZ:
3712 case IEEE80211_BAND_2GHZ:
3720 if (!((gmode && phy->supports_2ghz) ||
3721 (!gmode && phy->supports_5ghz))) {
3722 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3723 band_to_string(chan->band));
3727 if (!!phy->gmode == !!gmode) {
3728 /* This device is already running. */
3732 b43dbg(dev->wl, "Switching to %s GHz band\n",
3733 band_to_string(chan->band));
3735 b43_software_rfkill(dev, true);
3738 b43_phy_put_into_reset(dev);
3739 switch (dev->dev->bus_type) {
3740 #ifdef CONFIG_B43_BCMA
3742 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3744 tmp |= B43_BCMA_IOCTL_GMODE;
3746 tmp &= ~B43_BCMA_IOCTL_GMODE;
3747 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3750 #ifdef CONFIG_B43_SSB
3752 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3754 tmp |= B43_TMSLOW_GMODE;
3756 tmp &= ~B43_TMSLOW_GMODE;
3757 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3761 b43_phy_take_out_of_reset(dev);
3763 b43_upload_initvals_band(dev);
3770 /* Write the short and long frame retry limit values. */
3771 static void b43_set_retry_limits(struct b43_wldev *dev,
3772 unsigned int short_retry,
3773 unsigned int long_retry)
3775 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3776 * the chip-internal counter. */
3777 short_retry = min(short_retry, (unsigned int)0xF);
3778 long_retry = min(long_retry, (unsigned int)0xF);
3780 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3782 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3786 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3788 struct b43_wl *wl = hw_to_b43_wl(hw);
3789 struct b43_wldev *dev;
3790 struct b43_phy *phy;
3791 struct ieee80211_conf *conf = &hw->conf;
3794 bool reload_bss = false;
3796 mutex_lock(&wl->mutex);
3798 dev = wl->current_dev;
3800 b43_mac_suspend(dev);
3802 /* Switch the band (if necessary). This might change the active core. */
3803 err = b43_switch_band(dev, conf->chandef.chan);
3805 goto out_unlock_mutex;
3807 /* Need to reload all settings if the core changed */
3808 if (dev != wl->current_dev) {
3809 dev = wl->current_dev;
3816 if (conf_is_ht(conf))
3818 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3820 phy->is_40mhz = false;
3822 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3823 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3824 conf->long_frame_max_tx_count);
3825 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3827 goto out_mac_enable;
3829 /* Switch to the requested channel.
3830 * The firmware takes care of races with the TX handler. */
3831 if (conf->chandef.chan->hw_value != phy->channel)
3832 b43_switch_channel(dev, conf->chandef.chan->hw_value);
3834 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3836 /* Adjust the desired TX power level. */
3837 if (conf->power_level != 0) {
3838 if (conf->power_level != phy->desired_txpower) {
3839 phy->desired_txpower = conf->power_level;
3840 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3841 B43_TXPWR_IGNORE_TSSI);
3845 /* Antennas for RX and management frame TX. */
3846 antenna = B43_ANTENNA_DEFAULT;
3847 b43_mgmtframe_txantenna(dev, antenna);
3848 antenna = B43_ANTENNA_DEFAULT;
3849 if (phy->ops->set_rx_antenna)
3850 phy->ops->set_rx_antenna(dev, antenna);
3852 if (wl->radio_enabled != phy->radio_on) {
3853 if (wl->radio_enabled) {
3854 b43_software_rfkill(dev, false);
3855 b43info(dev->wl, "Radio turned on by software\n");
3856 if (!dev->radio_hw_enable) {
3857 b43info(dev->wl, "The hardware RF-kill button "
3858 "still turns the radio physically off. "
3859 "Press the button to turn it on.\n");
3862 b43_software_rfkill(dev, true);
3863 b43info(dev->wl, "Radio turned off by software\n");
3868 b43_mac_enable(dev);
3870 mutex_unlock(&wl->mutex);
3872 if (wl->vif && reload_bss)
3873 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3878 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3880 struct ieee80211_supported_band *sband =
3881 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3882 struct ieee80211_rate *rate;
3884 u16 basic, direct, offset, basic_offset, rateptr;
3886 for (i = 0; i < sband->n_bitrates; i++) {
3887 rate = &sband->bitrates[i];
3889 if (b43_is_cck_rate(rate->hw_value)) {
3890 direct = B43_SHM_SH_CCKDIRECT;
3891 basic = B43_SHM_SH_CCKBASIC;
3892 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3895 direct = B43_SHM_SH_OFDMDIRECT;
3896 basic = B43_SHM_SH_OFDMBASIC;
3897 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3901 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3903 if (b43_is_cck_rate(rate->hw_value)) {
3904 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3905 basic_offset &= 0xF;
3907 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3908 basic_offset &= 0xF;
3912 * Get the pointer that we need to point to
3913 * from the direct map
3915 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3916 direct + 2 * basic_offset);
3917 /* and write it to the basic map */
3918 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3923 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3924 struct ieee80211_vif *vif,
3925 struct ieee80211_bss_conf *conf,
3928 struct b43_wl *wl = hw_to_b43_wl(hw);
3929 struct b43_wldev *dev;
3931 mutex_lock(&wl->mutex);
3933 dev = wl->current_dev;
3934 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3935 goto out_unlock_mutex;
3937 B43_WARN_ON(wl->vif != vif);
3939 if (changed & BSS_CHANGED_BSSID) {
3941 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3943 memset(wl->bssid, 0, ETH_ALEN);
3946 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3947 if (changed & BSS_CHANGED_BEACON &&
3948 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3949 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3950 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3951 b43_update_templates(wl);
3953 if (changed & BSS_CHANGED_BSSID)
3954 b43_write_mac_bssid_templates(dev);
3957 b43_mac_suspend(dev);
3959 /* Update templates for AP/mesh mode. */
3960 if (changed & BSS_CHANGED_BEACON_INT &&
3961 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3962 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3963 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3965 b43_set_beacon_int(dev, conf->beacon_int);
3967 if (changed & BSS_CHANGED_BASIC_RATES)
3968 b43_update_basic_rates(dev, conf->basic_rates);
3970 if (changed & BSS_CHANGED_ERP_SLOT) {
3971 if (conf->use_short_slot)
3972 b43_short_slot_timing_enable(dev);
3974 b43_short_slot_timing_disable(dev);
3977 b43_mac_enable(dev);
3979 mutex_unlock(&wl->mutex);
3982 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3983 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3984 struct ieee80211_key_conf *key)
3986 struct b43_wl *wl = hw_to_b43_wl(hw);
3987 struct b43_wldev *dev;
3991 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3993 if (modparam_nohwcrypt)
3994 return -ENOSPC; /* User disabled HW-crypto */
3996 if ((vif->type == NL80211_IFTYPE_ADHOC ||
3997 vif->type == NL80211_IFTYPE_MESH_POINT) &&
3998 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
3999 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4000 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4002 * For now, disable hw crypto for the RSN IBSS group keys. This
4003 * could be optimized in the future, but until that gets
4004 * implemented, use of software crypto for group addressed
4005 * frames is a acceptable to allow RSN IBSS to be used.
4010 mutex_lock(&wl->mutex);
4012 dev = wl->current_dev;
4014 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4017 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4018 /* We don't have firmware for the crypto engine.
4019 * Must use software-crypto. */
4025 switch (key->cipher) {
4026 case WLAN_CIPHER_SUITE_WEP40:
4027 algorithm = B43_SEC_ALGO_WEP40;
4029 case WLAN_CIPHER_SUITE_WEP104:
4030 algorithm = B43_SEC_ALGO_WEP104;
4032 case WLAN_CIPHER_SUITE_TKIP:
4033 algorithm = B43_SEC_ALGO_TKIP;
4035 case WLAN_CIPHER_SUITE_CCMP:
4036 algorithm = B43_SEC_ALGO_AES;
4042 index = (u8) (key->keyidx);
4048 if (algorithm == B43_SEC_ALGO_TKIP &&
4049 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4050 !modparam_hwtkip)) {
4051 /* We support only pairwise key */
4056 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4057 if (WARN_ON(!sta)) {
4061 /* Pairwise key with an assigned MAC address. */
4062 err = b43_key_write(dev, -1, algorithm,
4063 key->key, key->keylen,
4067 err = b43_key_write(dev, index, algorithm,
4068 key->key, key->keylen, NULL, key);
4073 if (algorithm == B43_SEC_ALGO_WEP40 ||
4074 algorithm == B43_SEC_ALGO_WEP104) {
4075 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4078 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4080 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4081 if (algorithm == B43_SEC_ALGO_TKIP)
4082 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4085 err = b43_key_clear(dev, key->hw_key_idx);
4096 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4098 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4099 sta ? sta->addr : bcast_addr);
4100 b43_dump_keymemory(dev);
4102 mutex_unlock(&wl->mutex);
4107 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4108 unsigned int changed, unsigned int *fflags,
4111 struct b43_wl *wl = hw_to_b43_wl(hw);
4112 struct b43_wldev *dev;
4114 mutex_lock(&wl->mutex);
4115 dev = wl->current_dev;
4121 *fflags &= FIF_PROMISC_IN_BSS |
4127 FIF_BCN_PRBRESP_PROMISC;
4129 changed &= FIF_PROMISC_IN_BSS |
4135 FIF_BCN_PRBRESP_PROMISC;
4137 wl->filter_flags = *fflags;
4139 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4140 b43_adjust_opmode(dev);
4143 mutex_unlock(&wl->mutex);
4146 /* Locking: wl->mutex
4147 * Returns the current dev. This might be different from the passed in dev,
4148 * because the core might be gone away while we unlocked the mutex. */
4149 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4152 struct b43_wldev *orig_dev;
4160 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4163 /* Cancel work. Unlock to avoid deadlocks. */
4164 mutex_unlock(&wl->mutex);
4165 cancel_delayed_work_sync(&dev->periodic_work);
4166 cancel_work_sync(&wl->tx_work);
4167 mutex_lock(&wl->mutex);
4168 dev = wl->current_dev;
4169 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4170 /* Whoops, aliens ate up the device while we were unlocked. */
4174 /* Disable interrupts on the device. */
4175 b43_set_status(dev, B43_STAT_INITIALIZED);
4176 if (b43_bus_host_is_sdio(dev->dev)) {
4177 /* wl->mutex is locked. That is enough. */
4178 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4179 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4181 spin_lock_irq(&wl->hardirq_lock);
4182 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4183 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4184 spin_unlock_irq(&wl->hardirq_lock);
4186 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4188 mutex_unlock(&wl->mutex);
4189 if (b43_bus_host_is_sdio(dev->dev)) {
4190 b43_sdio_free_irq(dev);
4192 synchronize_irq(dev->dev->irq);
4193 free_irq(dev->dev->irq, dev);
4195 mutex_lock(&wl->mutex);
4196 dev = wl->current_dev;
4199 if (dev != orig_dev) {
4200 if (b43_status(dev) >= B43_STAT_STARTED)
4204 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4205 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4207 /* Drain all TX queues. */
4208 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4209 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4210 struct sk_buff *skb;
4212 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4213 ieee80211_free_txskb(wl->hw, skb);
4217 b43_mac_suspend(dev);
4219 b43dbg(wl, "Wireless interface stopped\n");
4224 /* Locking: wl->mutex */
4225 static int b43_wireless_core_start(struct b43_wldev *dev)
4229 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4231 drain_txstatus_queue(dev);
4232 if (b43_bus_host_is_sdio(dev->dev)) {
4233 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4235 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4239 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4240 b43_interrupt_thread_handler,
4241 IRQF_SHARED, KBUILD_MODNAME, dev);
4243 b43err(dev->wl, "Cannot request IRQ-%d\n",
4249 /* We are ready to run. */
4250 ieee80211_wake_queues(dev->wl->hw);
4251 b43_set_status(dev, B43_STAT_STARTED);
4253 /* Start data flow (TX/RX). */
4254 b43_mac_enable(dev);
4255 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4257 /* Start maintenance work */
4258 b43_periodic_tasks_setup(dev);
4262 b43dbg(dev->wl, "Wireless interface started\n");
4267 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4278 case B43_PHYTYPE_LP:
4280 case B43_PHYTYPE_SSLPN:
4282 case B43_PHYTYPE_HT:
4284 case B43_PHYTYPE_LCN:
4286 case B43_PHYTYPE_LCNXN:
4288 case B43_PHYTYPE_LCN40:
4290 case B43_PHYTYPE_AC:
4296 /* Get PHY and RADIO versioning numbers */
4297 static int b43_phy_versioning(struct b43_wldev *dev)
4299 struct b43_phy *phy = &dev->phy;
4307 int unsupported = 0;
4309 /* Get PHY versioning */
4310 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4311 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4312 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4313 phy_rev = (tmp & B43_PHYVER_VERSION);
4320 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4328 #ifdef CONFIG_B43_PHY_N
4334 #ifdef CONFIG_B43_PHY_LP
4335 case B43_PHYTYPE_LP:
4340 #ifdef CONFIG_B43_PHY_HT
4341 case B43_PHYTYPE_HT:
4346 #ifdef CONFIG_B43_PHY_LCN
4347 case B43_PHYTYPE_LCN:
4356 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4357 analog_type, phy_type, b43_phy_name(dev, phy_type),
4361 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4362 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4364 /* Get RADIO versioning */
4365 if (dev->dev->core_rev >= 24) {
4368 for (tmp = 0; tmp < 3; tmp++) {
4369 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4370 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4373 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4374 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4376 radio_manuf = 0x17F;
4377 radio_ver = (radio24[2] << 8) | radio24[1];
4378 radio_rev = (radio24[0] & 0xF);
4380 if (dev->dev->chip_id == 0x4317) {
4381 if (dev->dev->chip_rev == 0)
4383 else if (dev->dev->chip_rev == 1)
4388 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4390 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4391 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4393 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4396 radio_manuf = (tmp & 0x00000FFF);
4397 radio_ver = (tmp & 0x0FFFF000) >> 12;
4398 radio_rev = (tmp & 0xF0000000) >> 28;
4401 if (radio_manuf != 0x17F /* Broadcom */)
4405 if (radio_ver != 0x2060)
4409 if (radio_manuf != 0x17F)
4413 if ((radio_ver & 0xFFF0) != 0x2050)
4417 if (radio_ver != 0x2050)
4421 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4424 case B43_PHYTYPE_LP:
4425 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4428 case B43_PHYTYPE_HT:
4429 if (radio_ver != 0x2059)
4432 case B43_PHYTYPE_LCN:
4433 if (radio_ver != 0x2064)
4440 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4441 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4442 radio_manuf, radio_ver, radio_rev);
4445 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4446 radio_manuf, radio_ver, radio_rev);
4448 phy->radio_manuf = radio_manuf;
4449 phy->radio_ver = radio_ver;
4450 phy->radio_rev = radio_rev;
4452 phy->analog = analog_type;
4453 phy->type = phy_type;
4459 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4460 struct b43_phy *phy)
4462 phy->hardware_power_control = !!modparam_hwpctl;
4463 phy->next_txpwr_check_time = jiffies;
4464 /* PHY TX errors counter. */
4465 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4468 phy->phy_locked = false;
4469 phy->radio_locked = false;
4473 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4475 dev->dfq_valid = false;
4477 /* Assume the radio is enabled. If it's not enabled, the state will
4478 * immediately get fixed on the first periodic work run. */
4479 dev->radio_hw_enable = true;
4482 memset(&dev->stats, 0, sizeof(dev->stats));
4484 setup_struct_phy_for_init(dev, &dev->phy);
4486 /* IRQ related flags */
4487 dev->irq_reason = 0;
4488 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4489 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4490 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4491 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4493 dev->mac_suspended = 1;
4495 /* Noise calculation context */
4496 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4499 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4501 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4504 if (!modparam_btcoex)
4506 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4508 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4511 hf = b43_hf_read(dev);
4512 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4513 hf |= B43_HF_BTCOEXALT;
4515 hf |= B43_HF_BTCOEX;
4516 b43_hf_write(dev, hf);
4519 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4521 if (!modparam_btcoex)
4526 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4528 struct ssb_bus *bus;
4531 #ifdef CONFIG_B43_SSB
4532 if (dev->dev->bus_type != B43_BUS_SSB)
4538 bus = dev->dev->sdev->bus;
4540 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4541 (bus->chip_id == 0x4312)) {
4542 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4543 tmp &= ~SSB_IMCFGLO_REQTO;
4544 tmp &= ~SSB_IMCFGLO_SERTO;
4546 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4547 ssb_commit_settings(bus);
4551 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4555 /* The time value is in microseconds. */
4556 if (dev->phy.type == B43_PHYTYPE_A)
4560 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4562 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4563 pu_delay = max(pu_delay, (u16)2400);
4565 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4568 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4569 static void b43_set_pretbtt(struct b43_wldev *dev)
4573 /* The time value is in microseconds. */
4574 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4577 if (dev->phy.type == B43_PHYTYPE_A)
4582 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4583 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4586 /* Shutdown a wireless core */
4587 /* Locking: wl->mutex */
4588 static void b43_wireless_core_exit(struct b43_wldev *dev)
4590 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4591 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4594 b43_set_status(dev, B43_STAT_UNINIT);
4596 /* Stop the microcode PSM. */
4597 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4598 B43_MACCTL_PSM_JMP0);
4600 switch (dev->dev->bus_type) {
4601 #ifdef CONFIG_B43_BCMA
4603 bcma_core_pci_down(dev->dev->bdev->bus);
4606 #ifdef CONFIG_B43_SSB
4616 dev->phy.ops->switch_analog(dev, 0);
4617 if (dev->wl->current_beacon) {
4618 dev_kfree_skb_any(dev->wl->current_beacon);
4619 dev->wl->current_beacon = NULL;
4622 b43_device_disable(dev, 0);
4623 b43_bus_may_powerdown(dev);
4626 /* Initialize a wireless core */
4627 static int b43_wireless_core_init(struct b43_wldev *dev)
4629 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4630 struct b43_phy *phy = &dev->phy;
4634 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4636 err = b43_bus_powerup(dev, 0);
4639 if (!b43_device_is_enabled(dev))
4640 b43_wireless_core_reset(dev, phy->gmode);
4642 /* Reset all data structures. */
4643 setup_struct_wldev_for_init(dev);
4644 phy->ops->prepare_structs(dev);
4646 /* Enable IRQ routing to this device. */
4647 switch (dev->dev->bus_type) {
4648 #ifdef CONFIG_B43_BCMA
4650 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4651 dev->dev->bdev, true);
4652 bcma_core_pci_up(dev->dev->bdev->bus);
4655 #ifdef CONFIG_B43_SSB
4657 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4663 b43_imcfglo_timeouts_workaround(dev);
4664 b43_bluetooth_coext_disable(dev);
4665 if (phy->ops->prepare_hardware) {
4666 err = phy->ops->prepare_hardware(dev);
4670 err = b43_chip_init(dev);
4673 b43_shm_write16(dev, B43_SHM_SHARED,
4674 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4675 hf = b43_hf_read(dev);
4676 if (phy->type == B43_PHYTYPE_G) {
4680 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4681 hf |= B43_HF_OFDMPABOOST;
4683 if (phy->radio_ver == 0x2050) {
4684 if (phy->radio_rev == 6)
4685 hf |= B43_HF_4318TSSI;
4686 if (phy->radio_rev < 6)
4687 hf |= B43_HF_VCORECALC;
4689 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4690 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4691 #if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4692 if (dev->dev->bus_type == B43_BUS_SSB &&
4693 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4694 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4695 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4697 hf &= ~B43_HF_SKCFPUP;
4698 b43_hf_write(dev, hf);
4700 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4701 B43_DEFAULT_LONG_RETRY_LIMIT);
4702 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4703 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4705 /* Disable sending probe responses from firmware.
4706 * Setting the MaxTime to one usec will always trigger
4707 * a timeout, so we never send any probe resp.
4708 * A timeout of zero is infinite. */
4709 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4711 b43_rate_memory_init(dev);
4712 b43_set_phytxctl_defaults(dev);
4714 /* Minimum Contention Window */
4715 if (phy->type == B43_PHYTYPE_B)
4716 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4718 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4719 /* Maximum Contention Window */
4720 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4722 if (b43_bus_host_is_pcmcia(dev->dev) ||
4723 b43_bus_host_is_sdio(dev->dev)) {
4724 dev->__using_pio_transfers = true;
4725 err = b43_pio_init(dev);
4726 } else if (dev->use_pio) {
4727 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4728 "This should not be needed and will result in lower "
4730 dev->__using_pio_transfers = true;
4731 err = b43_pio_init(dev);
4733 dev->__using_pio_transfers = false;
4734 err = b43_dma_init(dev);
4739 b43_set_synth_pu_delay(dev, 1);
4740 b43_bluetooth_coext_enable(dev);
4742 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4743 b43_upload_card_macaddress(dev);
4744 b43_security_init(dev);
4746 ieee80211_wake_queues(dev->wl->hw);
4748 b43_set_status(dev, B43_STAT_INITIALIZED);
4756 b43_bus_may_powerdown(dev);
4757 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4761 static int b43_op_add_interface(struct ieee80211_hw *hw,
4762 struct ieee80211_vif *vif)
4764 struct b43_wl *wl = hw_to_b43_wl(hw);
4765 struct b43_wldev *dev;
4766 int err = -EOPNOTSUPP;
4768 /* TODO: allow WDS/AP devices to coexist */
4770 if (vif->type != NL80211_IFTYPE_AP &&
4771 vif->type != NL80211_IFTYPE_MESH_POINT &&
4772 vif->type != NL80211_IFTYPE_STATION &&
4773 vif->type != NL80211_IFTYPE_WDS &&
4774 vif->type != NL80211_IFTYPE_ADHOC)
4777 mutex_lock(&wl->mutex);
4779 goto out_mutex_unlock;
4781 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4783 dev = wl->current_dev;
4784 wl->operating = true;
4786 wl->if_type = vif->type;
4787 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4789 b43_adjust_opmode(dev);
4790 b43_set_pretbtt(dev);
4791 b43_set_synth_pu_delay(dev, 0);
4792 b43_upload_card_macaddress(dev);
4796 mutex_unlock(&wl->mutex);
4799 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4804 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4805 struct ieee80211_vif *vif)
4807 struct b43_wl *wl = hw_to_b43_wl(hw);
4808 struct b43_wldev *dev = wl->current_dev;
4810 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4812 mutex_lock(&wl->mutex);
4814 B43_WARN_ON(!wl->operating);
4815 B43_WARN_ON(wl->vif != vif);
4818 wl->operating = false;
4820 b43_adjust_opmode(dev);
4821 memset(wl->mac_addr, 0, ETH_ALEN);
4822 b43_upload_card_macaddress(dev);
4824 mutex_unlock(&wl->mutex);
4827 static int b43_op_start(struct ieee80211_hw *hw)
4829 struct b43_wl *wl = hw_to_b43_wl(hw);
4830 struct b43_wldev *dev = wl->current_dev;
4834 /* Kill all old instance specific information to make sure
4835 * the card won't use it in the short timeframe between start
4836 * and mac80211 reconfiguring it. */
4837 memset(wl->bssid, 0, ETH_ALEN);
4838 memset(wl->mac_addr, 0, ETH_ALEN);
4839 wl->filter_flags = 0;
4840 wl->radiotap_enabled = false;
4842 wl->beacon0_uploaded = false;
4843 wl->beacon1_uploaded = false;
4844 wl->beacon_templates_virgin = true;
4845 wl->radio_enabled = true;
4847 mutex_lock(&wl->mutex);
4849 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4850 err = b43_wireless_core_init(dev);
4852 goto out_mutex_unlock;
4856 if (b43_status(dev) < B43_STAT_STARTED) {
4857 err = b43_wireless_core_start(dev);
4860 b43_wireless_core_exit(dev);
4861 goto out_mutex_unlock;
4865 /* XXX: only do if device doesn't support rfkill irq */
4866 wiphy_rfkill_start_polling(hw->wiphy);
4869 mutex_unlock(&wl->mutex);
4872 * Configuration may have been overwritten during initialization.
4873 * Reload the configuration, but only if initialization was
4874 * successful. Reloading the configuration after a failed init
4875 * may hang the system.
4878 b43_op_config(hw, ~0);
4883 static void b43_op_stop(struct ieee80211_hw *hw)
4885 struct b43_wl *wl = hw_to_b43_wl(hw);
4886 struct b43_wldev *dev = wl->current_dev;
4888 cancel_work_sync(&(wl->beacon_update_trigger));
4893 mutex_lock(&wl->mutex);
4894 if (b43_status(dev) >= B43_STAT_STARTED) {
4895 dev = b43_wireless_core_stop(dev);
4899 b43_wireless_core_exit(dev);
4900 wl->radio_enabled = false;
4903 mutex_unlock(&wl->mutex);
4905 cancel_work_sync(&(wl->txpower_adjust_work));
4908 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4909 struct ieee80211_sta *sta, bool set)
4911 struct b43_wl *wl = hw_to_b43_wl(hw);
4913 /* FIXME: add locking */
4914 b43_update_templates(wl);
4919 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4920 struct ieee80211_vif *vif,
4921 enum sta_notify_cmd notify_cmd,
4922 struct ieee80211_sta *sta)
4924 struct b43_wl *wl = hw_to_b43_wl(hw);
4926 B43_WARN_ON(!vif || wl->vif != vif);
4929 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4931 struct b43_wl *wl = hw_to_b43_wl(hw);
4932 struct b43_wldev *dev;
4934 mutex_lock(&wl->mutex);
4935 dev = wl->current_dev;
4936 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4937 /* Disable CFP update during scan on other channels. */
4938 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4940 mutex_unlock(&wl->mutex);
4943 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4945 struct b43_wl *wl = hw_to_b43_wl(hw);
4946 struct b43_wldev *dev;
4948 mutex_lock(&wl->mutex);
4949 dev = wl->current_dev;
4950 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4951 /* Re-enable CFP update. */
4952 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4954 mutex_unlock(&wl->mutex);
4957 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4958 struct survey_info *survey)
4960 struct b43_wl *wl = hw_to_b43_wl(hw);
4961 struct b43_wldev *dev = wl->current_dev;
4962 struct ieee80211_conf *conf = &hw->conf;
4967 survey->channel = conf->chandef.chan;
4968 survey->filled = SURVEY_INFO_NOISE_DBM;
4969 survey->noise = dev->stats.link_noise;
4974 static const struct ieee80211_ops b43_hw_ops = {
4976 .conf_tx = b43_op_conf_tx,
4977 .add_interface = b43_op_add_interface,
4978 .remove_interface = b43_op_remove_interface,
4979 .config = b43_op_config,
4980 .bss_info_changed = b43_op_bss_info_changed,
4981 .configure_filter = b43_op_configure_filter,
4982 .set_key = b43_op_set_key,
4983 .update_tkip_key = b43_op_update_tkip_key,
4984 .get_stats = b43_op_get_stats,
4985 .get_tsf = b43_op_get_tsf,
4986 .set_tsf = b43_op_set_tsf,
4987 .start = b43_op_start,
4988 .stop = b43_op_stop,
4989 .set_tim = b43_op_beacon_set_tim,
4990 .sta_notify = b43_op_sta_notify,
4991 .sw_scan_start = b43_op_sw_scan_start_notifier,
4992 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4993 .get_survey = b43_op_get_survey,
4994 .rfkill_poll = b43_rfkill_poll,
4997 /* Hard-reset the chip. Do not call this directly.
4998 * Use b43_controller_restart()
5000 static void b43_chip_reset(struct work_struct *work)
5002 struct b43_wldev *dev =
5003 container_of(work, struct b43_wldev, restart_work);
5004 struct b43_wl *wl = dev->wl;
5008 mutex_lock(&wl->mutex);
5010 prev_status = b43_status(dev);
5011 /* Bring the device down... */
5012 if (prev_status >= B43_STAT_STARTED) {
5013 dev = b43_wireless_core_stop(dev);
5019 if (prev_status >= B43_STAT_INITIALIZED)
5020 b43_wireless_core_exit(dev);
5022 /* ...and up again. */
5023 if (prev_status >= B43_STAT_INITIALIZED) {
5024 err = b43_wireless_core_init(dev);
5028 if (prev_status >= B43_STAT_STARTED) {
5029 err = b43_wireless_core_start(dev);
5031 b43_wireless_core_exit(dev);
5037 wl->current_dev = NULL; /* Failed to init the dev. */
5038 mutex_unlock(&wl->mutex);
5041 b43err(wl, "Controller restart FAILED\n");
5045 /* reload configuration */
5046 b43_op_config(wl->hw, ~0);
5048 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5050 b43info(wl, "Controller restarted\n");
5053 static int b43_setup_bands(struct b43_wldev *dev,
5054 bool have_2ghz_phy, bool have_5ghz_phy)
5056 struct ieee80211_hw *hw = dev->wl->hw;
5059 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5060 if (dev->phy.type == B43_PHYTYPE_N) {
5062 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5065 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5068 dev->phy.supports_2ghz = have_2ghz_phy;
5069 dev->phy.supports_5ghz = have_5ghz_phy;
5074 static void b43_wireless_core_detach(struct b43_wldev *dev)
5076 /* We release firmware that late to not be required to re-request
5077 * is all the time when we reinit the core. */
5078 b43_release_firmware(dev);
5082 static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5083 bool *have_5ghz_phy)
5087 #ifdef CONFIG_B43_BCMA
5088 if (dev->dev->bus_type == B43_BUS_BCMA &&
5089 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5090 dev_id = dev->dev->bdev->bus->host_pci->device;
5092 #ifdef CONFIG_B43_SSB
5093 if (dev->dev->bus_type == B43_BUS_SSB &&
5094 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5095 dev_id = dev->dev->sdev->bus->host_pci->device;
5097 /* Override with SPROM value if available */
5098 if (dev->dev->bus_sprom->dev_id)
5099 dev_id = dev->dev->bus_sprom->dev_id;
5101 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5103 case 0x4324: /* BCM4306 */
5104 case 0x4312: /* BCM4311 */
5105 case 0x4319: /* BCM4318 */
5106 case 0x4328: /* BCM4321 */
5107 case 0x432b: /* BCM4322 */
5108 case 0x4350: /* BCM43222 */
5109 case 0x4353: /* BCM43224 */
5110 case 0x0576: /* BCM43224 */
5111 case 0x435f: /* BCM6362 */
5112 case 0x4331: /* BCM4331 */
5113 case 0x4359: /* BCM43228 */
5114 case 0x43a0: /* BCM4360 */
5115 case 0x43b1: /* BCM4352 */
5116 /* Dual band devices */
5117 *have_2ghz_phy = true;
5118 *have_5ghz_phy = true;
5120 case 0x4321: /* BCM4306 */
5121 case 0x4313: /* BCM4311 */
5122 case 0x431a: /* BCM4318 */
5123 case 0x432a: /* BCM4321 */
5124 case 0x432d: /* BCM4322 */
5125 case 0x4352: /* BCM43222 */
5126 case 0x4333: /* BCM4331 */
5127 case 0x43a2: /* BCM4360 */
5128 case 0x43b3: /* BCM4352 */
5129 /* 5 GHz only devices */
5130 *have_2ghz_phy = false;
5131 *have_5ghz_phy = true;
5135 /* As a fallback, try to guess using PHY type */
5136 switch (dev->phy.type) {
5138 *have_2ghz_phy = false;
5139 *have_5ghz_phy = true;
5143 case B43_PHYTYPE_LP:
5144 case B43_PHYTYPE_HT:
5145 case B43_PHYTYPE_LCN:
5146 *have_2ghz_phy = true;
5147 *have_5ghz_phy = false;
5154 static int b43_wireless_core_attach(struct b43_wldev *dev)
5156 struct b43_wl *wl = dev->wl;
5159 bool have_2ghz_phy = false, have_5ghz_phy = false;
5161 /* Do NOT do any device initialization here.
5162 * Do it in wireless_core_init() instead.
5163 * This function is for gathering basic information about the HW, only.
5164 * Also some structs may be set up here. But most likely you want to have
5165 * that in core_init(), too.
5168 err = b43_bus_powerup(dev, 0);
5170 b43err(wl, "Bus powerup failed\n");
5174 /* Try to guess supported bands for the first init needs */
5175 switch (dev->dev->bus_type) {
5176 #ifdef CONFIG_B43_BCMA
5178 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5179 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5180 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5183 #ifdef CONFIG_B43_SSB
5185 if (dev->dev->core_rev >= 5) {
5186 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5187 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5188 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5195 dev->phy.gmode = have_2ghz_phy;
5196 b43_wireless_core_reset(dev, dev->phy.gmode);
5198 /* Get the PHY type. */
5199 err = b43_phy_versioning(dev);
5203 /* Get real info about supported bands */
5204 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5206 /* We don't support 5 GHz on some PHYs yet */
5207 switch (dev->phy.type) {
5210 case B43_PHYTYPE_LP:
5211 case B43_PHYTYPE_HT:
5212 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5213 have_5ghz_phy = false;
5216 if (!have_2ghz_phy && !have_5ghz_phy) {
5217 b43err(wl, "b43 can't support any band on this device\n");
5222 err = b43_phy_allocate(dev);
5226 dev->phy.gmode = have_2ghz_phy;
5227 b43_wireless_core_reset(dev, dev->phy.gmode);
5229 err = b43_validate_chipaccess(dev);
5232 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5236 /* Now set some default "current_dev" */
5237 if (!wl->current_dev)
5238 wl->current_dev = dev;
5239 INIT_WORK(&dev->restart_work, b43_chip_reset);
5241 dev->phy.ops->switch_analog(dev, 0);
5242 b43_device_disable(dev, 0);
5243 b43_bus_may_powerdown(dev);
5251 b43_bus_may_powerdown(dev);
5255 static void b43_one_core_detach(struct b43_bus_dev *dev)
5257 struct b43_wldev *wldev;
5260 /* Do not cancel ieee80211-workqueue based work here.
5261 * See comment in b43_remove(). */
5263 wldev = b43_bus_get_wldev(dev);
5265 b43_debugfs_remove_device(wldev);
5266 b43_wireless_core_detach(wldev);
5267 list_del(&wldev->list);
5268 b43_bus_set_wldev(dev, NULL);
5272 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5274 struct b43_wldev *wldev;
5277 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5281 wldev->use_pio = b43_modparam_pio;
5284 b43_set_status(wldev, B43_STAT_UNINIT);
5285 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5286 INIT_LIST_HEAD(&wldev->list);
5288 err = b43_wireless_core_attach(wldev);
5290 goto err_kfree_wldev;
5292 b43_bus_set_wldev(dev, wldev);
5293 b43_debugfs_add_device(wldev);
5303 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5304 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5305 (pdev->device == _device) && \
5306 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5307 (pdev->subsystem_device == _subdevice) )
5309 #ifdef CONFIG_B43_SSB
5310 static void b43_sprom_fixup(struct ssb_bus *bus)
5312 struct pci_dev *pdev;
5314 /* boardflags workarounds */
5315 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5316 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5317 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5318 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5319 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5320 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5321 if (bus->bustype == SSB_BUSTYPE_PCI) {
5322 pdev = bus->host_pci;
5323 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5324 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5325 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5326 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5327 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5328 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5329 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5330 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5334 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5336 struct ieee80211_hw *hw = wl->hw;
5338 ssb_set_devtypedata(dev->sdev, NULL);
5339 ieee80211_free_hw(hw);
5343 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5345 struct ssb_sprom *sprom = dev->bus_sprom;
5346 struct ieee80211_hw *hw;
5351 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5353 b43err(NULL, "Could not allocate ieee80211 device\n");
5354 return ERR_PTR(-ENOMEM);
5356 wl = hw_to_b43_wl(hw);
5359 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5360 IEEE80211_HW_SIGNAL_DBM;
5362 hw->wiphy->interface_modes =
5363 BIT(NL80211_IFTYPE_AP) |
5364 BIT(NL80211_IFTYPE_MESH_POINT) |
5365 BIT(NL80211_IFTYPE_STATION) |
5366 BIT(NL80211_IFTYPE_WDS) |
5367 BIT(NL80211_IFTYPE_ADHOC);
5369 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5371 wl->hw_registred = false;
5373 SET_IEEE80211_DEV(hw, dev->dev);
5374 if (is_valid_ether_addr(sprom->et1mac))
5375 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5377 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5379 /* Initialize struct b43_wl */
5381 mutex_init(&wl->mutex);
5382 spin_lock_init(&wl->hardirq_lock);
5383 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5384 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5385 INIT_WORK(&wl->tx_work, b43_tx_work);
5387 /* Initialize queues and flags. */
5388 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5389 skb_queue_head_init(&wl->tx_queue[queue_num]);
5390 wl->tx_queue_stopped[queue_num] = 0;
5393 snprintf(chip_name, ARRAY_SIZE(chip_name),
5394 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5395 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5400 #ifdef CONFIG_B43_BCMA
5401 static int b43_bcma_probe(struct bcma_device *core)
5403 struct b43_bus_dev *dev;
5407 if (!modparam_allhwsupport &&
5408 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5409 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5413 dev = b43_bus_dev_bcma_init(core);
5417 wl = b43_wireless_init(dev);
5423 err = b43_one_core_attach(dev, wl);
5425 goto bcma_err_wireless_exit;
5427 /* setup and start work to load firmware */
5428 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5429 schedule_work(&wl->firmware_load);
5434 bcma_err_wireless_exit:
5435 ieee80211_free_hw(wl->hw);
5439 static void b43_bcma_remove(struct bcma_device *core)
5441 struct b43_wldev *wldev = bcma_get_drvdata(core);
5442 struct b43_wl *wl = wldev->wl;
5444 /* We must cancel any work here before unregistering from ieee80211,
5445 * as the ieee80211 unreg will destroy the workqueue. */
5446 cancel_work_sync(&wldev->restart_work);
5447 cancel_work_sync(&wl->firmware_load);
5450 if (!wldev->fw.ucode.data)
5451 return; /* NULL if firmware never loaded */
5452 if (wl->current_dev == wldev && wl->hw_registred) {
5453 b43_leds_stop(wldev);
5454 ieee80211_unregister_hw(wl->hw);
5457 b43_one_core_detach(wldev->dev);
5459 /* Unregister HW RNG driver */
5462 b43_leds_unregister(wl);
5464 ieee80211_free_hw(wl->hw);
5467 static struct bcma_driver b43_bcma_driver = {
5468 .name = KBUILD_MODNAME,
5469 .id_table = b43_bcma_tbl,
5470 .probe = b43_bcma_probe,
5471 .remove = b43_bcma_remove,
5475 #ifdef CONFIG_B43_SSB
5477 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5479 struct b43_bus_dev *dev;
5483 dev = b43_bus_dev_ssb_init(sdev);
5487 wl = ssb_get_devtypedata(sdev);
5489 b43err(NULL, "Dual-core devices are not supported\n");
5491 goto err_ssb_kfree_dev;
5494 b43_sprom_fixup(sdev->bus);
5496 wl = b43_wireless_init(dev);
5499 goto err_ssb_kfree_dev;
5501 ssb_set_devtypedata(sdev, wl);
5502 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5504 err = b43_one_core_attach(dev, wl);
5506 goto err_ssb_wireless_exit;
5508 /* setup and start work to load firmware */
5509 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5510 schedule_work(&wl->firmware_load);
5514 err_ssb_wireless_exit:
5515 b43_wireless_exit(dev, wl);
5521 static void b43_ssb_remove(struct ssb_device *sdev)
5523 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5524 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5525 struct b43_bus_dev *dev = wldev->dev;
5527 /* We must cancel any work here before unregistering from ieee80211,
5528 * as the ieee80211 unreg will destroy the workqueue. */
5529 cancel_work_sync(&wldev->restart_work);
5530 cancel_work_sync(&wl->firmware_load);
5533 if (!wldev->fw.ucode.data)
5534 return; /* NULL if firmware never loaded */
5535 if (wl->current_dev == wldev && wl->hw_registred) {
5536 b43_leds_stop(wldev);
5537 ieee80211_unregister_hw(wl->hw);
5540 b43_one_core_detach(dev);
5542 /* Unregister HW RNG driver */
5545 b43_leds_unregister(wl);
5546 b43_wireless_exit(dev, wl);
5549 static struct ssb_driver b43_ssb_driver = {
5550 .name = KBUILD_MODNAME,
5551 .id_table = b43_ssb_tbl,
5552 .probe = b43_ssb_probe,
5553 .remove = b43_ssb_remove,
5555 #endif /* CONFIG_B43_SSB */
5557 /* Perform a hardware reset. This can be called from any context. */
5558 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5560 /* Must avoid requeueing, if we are in shutdown. */
5561 if (b43_status(dev) < B43_STAT_INITIALIZED)
5563 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5564 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5567 static void b43_print_driverinfo(void)
5569 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5570 *feat_leds = "", *feat_sdio = "";
5572 #ifdef CONFIG_B43_PCI_AUTOSELECT
5575 #ifdef CONFIG_B43_PCMCIA
5578 #ifdef CONFIG_B43_PHY_N
5581 #ifdef CONFIG_B43_LEDS
5584 #ifdef CONFIG_B43_SDIO
5587 printk(KERN_INFO "Broadcom 43xx driver loaded "
5588 "[ Features: %s%s%s%s%s ]\n",
5589 feat_pci, feat_pcmcia, feat_nphy,
5590 feat_leds, feat_sdio);
5593 static int __init b43_init(void)
5598 err = b43_pcmcia_init();
5601 err = b43_sdio_init();
5603 goto err_pcmcia_exit;
5604 #ifdef CONFIG_B43_BCMA
5605 err = bcma_driver_register(&b43_bcma_driver);
5609 #ifdef CONFIG_B43_SSB
5610 err = ssb_driver_register(&b43_ssb_driver);
5612 goto err_bcma_driver_exit;
5614 b43_print_driverinfo();
5618 #ifdef CONFIG_B43_SSB
5619 err_bcma_driver_exit:
5621 #ifdef CONFIG_B43_BCMA
5622 bcma_driver_unregister(&b43_bcma_driver);
5633 static void __exit b43_exit(void)
5635 #ifdef CONFIG_B43_SSB
5636 ssb_driver_unregister(&b43_ssb_driver);
5638 #ifdef CONFIG_B43_BCMA
5639 bcma_driver_unregister(&b43_bcma_driver);
5646 module_init(b43_init)
5647 module_exit(b43_exit)