3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 #ifdef CONFIG_B43_BCMA_EXTRA
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
129 #ifdef CONFIG_B43_SSB
130 static const struct ssb_device_id b43_ssb_tbl[] = {
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
146 /* Channel and ratetables are shared for all devices.
147 * They can't be const, because ieee80211 puts some precalculated
148 * data in there. This data is the same for all devices, so we don't
149 * get concurrency issues */
150 #define RATETAB_ENT(_rateid, _flags) \
152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
153 .hw_value = (_rateid), \
158 * NOTE: When changing this, sync with xmit.c's
159 * b43_plcp_get_bitrate_idx_* functions!
161 static struct ieee80211_rate __b43_ratetable[] = {
162 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
176 #define b43_a_ratetable (__b43_ratetable + 4)
177 #define b43_a_ratetable_size 8
178 #define b43_b_ratetable (__b43_ratetable + 0)
179 #define b43_b_ratetable_size 4
180 #define b43_g_ratetable (__b43_ratetable + 0)
181 #define b43_g_ratetable_size 12
183 #define CHAN4G(_channel, _freq, _flags) { \
184 .band = IEEE80211_BAND_2GHZ, \
185 .center_freq = (_freq), \
186 .hw_value = (_channel), \
188 .max_antenna_gain = 0, \
191 static struct ieee80211_channel b43_2ghz_chantable[] = {
209 #define CHAN5G(_channel, _flags) { \
210 .band = IEEE80211_BAND_5GHZ, \
211 .center_freq = 5000 + (5 * (_channel)), \
212 .hw_value = (_channel), \
214 .max_antenna_gain = 0, \
217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218 CHAN5G(32, 0), CHAN5G(34, 0),
219 CHAN5G(36, 0), CHAN5G(38, 0),
220 CHAN5G(40, 0), CHAN5G(42, 0),
221 CHAN5G(44, 0), CHAN5G(46, 0),
222 CHAN5G(48, 0), CHAN5G(50, 0),
223 CHAN5G(52, 0), CHAN5G(54, 0),
224 CHAN5G(56, 0), CHAN5G(58, 0),
225 CHAN5G(60, 0), CHAN5G(62, 0),
226 CHAN5G(64, 0), CHAN5G(66, 0),
227 CHAN5G(68, 0), CHAN5G(70, 0),
228 CHAN5G(72, 0), CHAN5G(74, 0),
229 CHAN5G(76, 0), CHAN5G(78, 0),
230 CHAN5G(80, 0), CHAN5G(82, 0),
231 CHAN5G(84, 0), CHAN5G(86, 0),
232 CHAN5G(88, 0), CHAN5G(90, 0),
233 CHAN5G(92, 0), CHAN5G(94, 0),
234 CHAN5G(96, 0), CHAN5G(98, 0),
235 CHAN5G(100, 0), CHAN5G(102, 0),
236 CHAN5G(104, 0), CHAN5G(106, 0),
237 CHAN5G(108, 0), CHAN5G(110, 0),
238 CHAN5G(112, 0), CHAN5G(114, 0),
239 CHAN5G(116, 0), CHAN5G(118, 0),
240 CHAN5G(120, 0), CHAN5G(122, 0),
241 CHAN5G(124, 0), CHAN5G(126, 0),
242 CHAN5G(128, 0), CHAN5G(130, 0),
243 CHAN5G(132, 0), CHAN5G(134, 0),
244 CHAN5G(136, 0), CHAN5G(138, 0),
245 CHAN5G(140, 0), CHAN5G(142, 0),
246 CHAN5G(144, 0), CHAN5G(145, 0),
247 CHAN5G(146, 0), CHAN5G(147, 0),
248 CHAN5G(148, 0), CHAN5G(149, 0),
249 CHAN5G(150, 0), CHAN5G(151, 0),
250 CHAN5G(152, 0), CHAN5G(153, 0),
251 CHAN5G(154, 0), CHAN5G(155, 0),
252 CHAN5G(156, 0), CHAN5G(157, 0),
253 CHAN5G(158, 0), CHAN5G(159, 0),
254 CHAN5G(160, 0), CHAN5G(161, 0),
255 CHAN5G(162, 0), CHAN5G(163, 0),
256 CHAN5G(164, 0), CHAN5G(165, 0),
257 CHAN5G(166, 0), CHAN5G(168, 0),
258 CHAN5G(170, 0), CHAN5G(172, 0),
259 CHAN5G(174, 0), CHAN5G(176, 0),
260 CHAN5G(178, 0), CHAN5G(180, 0),
261 CHAN5G(182, 0), CHAN5G(184, 0),
262 CHAN5G(186, 0), CHAN5G(188, 0),
263 CHAN5G(190, 0), CHAN5G(192, 0),
264 CHAN5G(194, 0), CHAN5G(196, 0),
265 CHAN5G(198, 0), CHAN5G(200, 0),
266 CHAN5G(202, 0), CHAN5G(204, 0),
267 CHAN5G(206, 0), CHAN5G(208, 0),
268 CHAN5G(210, 0), CHAN5G(212, 0),
269 CHAN5G(214, 0), CHAN5G(216, 0),
270 CHAN5G(218, 0), CHAN5G(220, 0),
271 CHAN5G(222, 0), CHAN5G(224, 0),
272 CHAN5G(226, 0), CHAN5G(228, 0),
275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276 CHAN5G(34, 0), CHAN5G(36, 0),
277 CHAN5G(38, 0), CHAN5G(40, 0),
278 CHAN5G(42, 0), CHAN5G(44, 0),
279 CHAN5G(46, 0), CHAN5G(48, 0),
280 CHAN5G(52, 0), CHAN5G(56, 0),
281 CHAN5G(60, 0), CHAN5G(64, 0),
282 CHAN5G(100, 0), CHAN5G(104, 0),
283 CHAN5G(108, 0), CHAN5G(112, 0),
284 CHAN5G(116, 0), CHAN5G(120, 0),
285 CHAN5G(124, 0), CHAN5G(128, 0),
286 CHAN5G(132, 0), CHAN5G(136, 0),
287 CHAN5G(140, 0), CHAN5G(149, 0),
288 CHAN5G(153, 0), CHAN5G(157, 0),
289 CHAN5G(161, 0), CHAN5G(165, 0),
290 CHAN5G(184, 0), CHAN5G(188, 0),
291 CHAN5G(192, 0), CHAN5G(196, 0),
292 CHAN5G(200, 0), CHAN5G(204, 0),
293 CHAN5G(208, 0), CHAN5G(212, 0),
298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299 .band = IEEE80211_BAND_5GHZ,
300 .channels = b43_5ghz_nphy_chantable,
301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302 .bitrates = b43_a_ratetable,
303 .n_bitrates = b43_a_ratetable_size,
306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307 .band = IEEE80211_BAND_5GHZ,
308 .channels = b43_5ghz_aphy_chantable,
309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310 .bitrates = b43_a_ratetable,
311 .n_bitrates = b43_a_ratetable_size,
314 static struct ieee80211_supported_band b43_band_2GHz = {
315 .band = IEEE80211_BAND_2GHZ,
316 .channels = b43_2ghz_chantable,
317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
318 .bitrates = b43_g_ratetable,
319 .n_bitrates = b43_g_ratetable_size,
322 static void b43_wireless_core_exit(struct b43_wldev *dev);
323 static int b43_wireless_core_init(struct b43_wldev *dev);
324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
325 static int b43_wireless_core_start(struct b43_wldev *dev);
326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327 struct ieee80211_vif *vif,
328 struct ieee80211_bss_conf *conf,
331 static int b43_ratelimit(struct b43_wl *wl)
333 if (!wl || !wl->current_dev)
335 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
337 /* We are up and running.
338 * Ratelimit the messages to avoid DoS over the net. */
339 return net_ratelimit();
342 void b43info(struct b43_wl *wl, const char *fmt, ...)
344 struct va_format vaf;
347 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
349 if (!b43_ratelimit(wl))
357 printk(KERN_INFO "b43-%s: %pV",
358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
363 void b43err(struct b43_wl *wl, const char *fmt, ...)
365 struct va_format vaf;
368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
370 if (!b43_ratelimit(wl))
378 printk(KERN_ERR "b43-%s ERROR: %pV",
379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
386 struct va_format vaf;
389 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
391 if (!b43_ratelimit(wl))
399 printk(KERN_WARNING "b43-%s warning: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
407 struct va_format vaf;
410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
418 printk(KERN_DEBUG "b43-%s debug: %pV",
419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
428 B43_WARN_ON(offset % 4 != 0);
430 macctl = b43_read32(dev, B43_MMIO_MACCTL);
431 if (macctl & B43_MACCTL_BE)
434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
436 b43_write32(dev, B43_MMIO_RAM_DATA, val);
439 static inline void b43_shm_control_word(struct b43_wldev *dev,
440 u16 routing, u16 offset)
444 /* "offset" is the WORD offset. */
448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
455 if (routing == B43_SHM_SHARED) {
456 B43_WARN_ON(offset & 0x0001);
457 if (offset & 0x0003) {
458 /* Unaligned access */
459 b43_shm_control_word(dev, routing, offset >> 2);
460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
468 b43_shm_control_word(dev, routing, offset);
469 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
489 b43_shm_control_word(dev, routing, offset);
490 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
497 if (routing == B43_SHM_SHARED) {
498 B43_WARN_ON(offset & 0x0001);
499 if (offset & 0x0003) {
500 /* Unaligned access */
501 b43_shm_control_word(dev, routing, offset >> 2);
502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 b43_write16(dev, B43_MMIO_SHM_DATA,
506 (value >> 16) & 0xFFFF);
511 b43_shm_control_word(dev, routing, offset);
512 b43_write32(dev, B43_MMIO_SHM_DATA, value);
515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
517 if (routing == B43_SHM_SHARED) {
518 B43_WARN_ON(offset & 0x0001);
519 if (offset & 0x0003) {
520 /* Unaligned access */
521 b43_shm_control_word(dev, routing, offset >> 2);
522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
527 b43_shm_control_word(dev, routing, offset);
528 b43_write16(dev, B43_MMIO_SHM_DATA, value);
532 u64 b43_hf_read(struct b43_wldev *dev)
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
545 /* Write HostFlags */
546 void b43_hf_write(struct b43_wldev *dev, u64 value)
550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
561 B43_WARN_ON(!dev->fw.opensource);
562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
569 B43_WARN_ON(dev->dev->core_rev < 3);
571 /* The hardware guarantees us an atomic read, if we
572 * read the low register first. */
573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
581 static void b43_time_lock(struct b43_wldev *dev)
583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
591 /* Commit the write */
592 b43_read32(dev, B43_MMIO_MACCTL);
595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
599 B43_WARN_ON(dev->dev->core_rev < 3);
603 /* The hardware guarantees us an atomic write, if we
604 * write the low register first. */
605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
614 b43_tsf_write_locked(dev, tsf);
615 b43_time_unlock(dev);
619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
621 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
645 u8 mac_bssid[ETH_ALEN * 2];
649 bssid = dev->wl->bssid;
650 mac = dev->wl->mac_addr;
652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
654 memcpy(mac_bssid, mac, ETH_ALEN);
655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
657 /* Write our MAC address and BSSID to template ram */
658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659 tmp = (u32) (mac_bssid[i + 0]);
660 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663 b43_ram_write(dev, 0x20 + i, tmp);
667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
669 b43_write_mac_bssid_templates(dev);
670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
675 /* slot_time is in usec. */
676 /* This test used to exit for all but a G PHY. */
677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680 /* Shared memory location 0x0010 is the slot time and should be
681 * set to slot_time; however, this register is initially 0 and changing
682 * the value adversely affects the transmit rate for BCM4311
683 * devices. Until this behavior is unterstood, delete this step
685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
691 b43_set_slot_time(dev, 9);
694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
696 b43_set_slot_time(dev, 20);
699 /* DummyTransmission function, as documented on
700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
717 buffer[0] = 0x000201CC;
720 buffer[0] = 0x000B846E;
723 for (i = 0; i < 5; i++)
724 b43_ram_write(dev, i * 4, buffer[i]);
726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
728 if (dev->dev->core_rev < 11)
729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
733 value = (ofdm ? 0x41 : 0x40);
734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736 phy->type == B43_PHYTYPE_LCN)
737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
747 if (!pa_on && phy->type == B43_PHYTYPE_N)
748 ; /*b43_nphy_pa_override(dev, false) */
752 case B43_PHYTYPE_LCN:
753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
761 b43_read16(dev, B43_MMIO_TXE0_AUX);
763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764 b43_radio_write16(dev, 0x0051, 0x0017);
765 for (i = 0x00; i < max_loop; i++) {
766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
771 for (i = 0x00; i < 0x0A; i++) {
772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
777 for (i = 0x00; i < 0x19; i++) {
778 value = b43_read16(dev, B43_MMIO_IFSSTAT);
779 if (!(value & 0x0100))
783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784 b43_radio_write16(dev, 0x0051, 0x0037);
787 static void key_write(struct b43_wldev *dev,
788 u8 index, u8 algorithm, const u8 *key)
795 /* Key index/algo block */
796 kidx = b43_kidx_to_fw(dev, index);
797 value = ((kidx << 4) | algorithm);
798 b43_shm_write16(dev, B43_SHM_SHARED,
799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
801 /* Write the key to the Key Table Pointer offset */
802 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
805 value |= (u16) (key[i + 1]) << 8;
806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
812 u32 addrtmp[2] = { 0, 0, };
813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
815 if (b43_new_kidx_api(dev))
816 pairwise_keys_start = B43_NR_GROUP_KEYS;
818 B43_WARN_ON(index < pairwise_keys_start);
819 /* We have four default TX keys and possibly four default RX keys.
820 * Physical mac 0 is mapped to physical key 4 or 8, depending
821 * on the firmware version.
822 * So we must adjust the index here.
824 index -= pairwise_keys_start;
825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
828 addrtmp[0] = addr[0];
829 addrtmp[0] |= ((u32) (addr[1]) << 8);
830 addrtmp[0] |= ((u32) (addr[2]) << 16);
831 addrtmp[0] |= ((u32) (addr[3]) << 24);
832 addrtmp[1] = addr[4];
833 addrtmp[1] |= ((u32) (addr[5]) << 8);
836 /* Receive match transmitter address (RCMTA) mechanism */
837 b43_shm_write32(dev, B43_SHM_RCMTA,
838 (index * 2) + 0, addrtmp[0]);
839 b43_shm_write16(dev, B43_SHM_RCMTA,
840 (index * 2) + 1, addrtmp[1]);
843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
844 * When a packet is received, the iv32 is checked.
845 * - if it doesn't the packet is returned without modification (and software
846 * decryption can be done). That's what happen when iv16 wrap.
847 * - if it does, the rc4 key is computed, and decryption is tried.
848 * Either it will success and B43_RX_MAC_DEC is returned,
849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850 * and the packet is not usable (it got modified by the ucode).
851 * So in order to never have B43_RX_MAC_DECERR, we should provide
852 * a iv32 and phase1key that match. Because we drop packets in case of
853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854 * packets will be lost without higher layer knowing (ie no resync possible
857 * NOTE : this should support 50 key like RCMTA because
858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
867 if (!modparam_hwtkip)
870 if (b43_new_kidx_api(dev))
871 pairwise_keys_start = B43_NR_GROUP_KEYS;
873 B43_WARN_ON(index < pairwise_keys_start);
874 /* We have four default TX keys and possibly four default RX keys.
875 * Physical mac 0 is mapped to physical key 4 or 8, depending
876 * on the firmware version.
877 * So we must adjust the index here.
879 index -= pairwise_keys_start;
880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
882 if (b43_debug(dev, B43_DBG_KEYS)) {
883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
886 /* Write the key to the RX tkip shared mem */
887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888 for (i = 0; i < 10; i += 2) {
889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890 phase1key ? phase1key[i / 2] : 0);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
897 struct ieee80211_vif *vif,
898 struct ieee80211_key_conf *keyconf,
899 struct ieee80211_sta *sta,
900 u32 iv32, u16 *phase1key)
902 struct b43_wl *wl = hw_to_b43_wl(hw);
903 struct b43_wldev *dev;
904 int index = keyconf->hw_key_idx;
906 if (B43_WARN_ON(!modparam_hwtkip))
909 /* This is only called from the RX path through mac80211, where
910 * our mutex is already locked. */
911 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
912 dev = wl->current_dev;
913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
917 rx_tkip_phase1_write(dev, index, iv32, phase1key);
918 /* only pairwise TKIP keys are supported right now */
921 keymac_write(dev, index, sta->addr);
924 static void do_key_write(struct b43_wldev *dev,
925 u8 index, u8 algorithm,
926 const u8 *key, size_t key_len, const u8 *mac_addr)
928 u8 buf[B43_SEC_KEYSIZE] = { 0, };
929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
931 if (b43_new_kidx_api(dev))
932 pairwise_keys_start = B43_NR_GROUP_KEYS;
934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, NULL); /* First zero out mac. */
939 if (algorithm == B43_SEC_ALGO_TKIP) {
941 * We should provide an initial iv32, phase1key pair.
942 * We could start with iv32=0 and compute the corresponding
943 * phase1key, but this means calling ieee80211_get_tkip_key
944 * with a fake skb (or export other tkip function).
945 * Because we are lazy we hope iv32 won't start with
946 * 0xffffffff and let's b43_op_update_tkip_key provide a
949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950 } else if (index >= pairwise_keys_start) /* clear it */
951 rx_tkip_phase1_write(dev, index, 0, NULL);
953 memcpy(buf, key, key_len);
954 key_write(dev, index, algorithm, buf);
955 if (index >= pairwise_keys_start)
956 keymac_write(dev, index, mac_addr);
958 dev->key[index].algorithm = algorithm;
961 static int b43_key_write(struct b43_wldev *dev,
962 int index, u8 algorithm,
963 const u8 *key, size_t key_len,
965 struct ieee80211_key_conf *keyconf)
968 int pairwise_keys_start;
970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971 * - Temporal Encryption Key (128 bits)
972 * - Temporal Authenticator Tx MIC Key (64 bits)
973 * - Temporal Authenticator Rx MIC Key (64 bits)
975 * Hardware only store TEK
977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
979 if (key_len > B43_SEC_KEYSIZE)
981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
982 /* Check that we don't already have this key. */
983 B43_WARN_ON(dev->key[i].keyconf == keyconf);
986 /* Pairwise key. Get an empty slot for the key. */
987 if (b43_new_kidx_api(dev))
988 pairwise_keys_start = B43_NR_GROUP_KEYS;
990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991 for (i = pairwise_keys_start;
992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
995 if (!dev->key[i].keyconf) {
1002 b43warn(dev->wl, "Out of hardware key memory\n");
1006 B43_WARN_ON(index > 3);
1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010 /* Default RX key */
1011 B43_WARN_ON(mac_addr);
1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1014 keyconf->hw_key_idx = index;
1015 dev->key[index].keyconf = keyconf;
1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1024 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1030 dev->key[index].keyconf = NULL;
1035 static void b43_clear_keys(struct b43_wldev *dev)
1039 if (b43_new_kidx_api(dev))
1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043 for (i = 0; i < count; i++)
1044 b43_key_clear(dev, i);
1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1049 unsigned int i, index, count, offset, pairwise_keys_start;
1055 struct b43_key *key;
1057 if (!b43_debug(dev, B43_DBG_KEYS))
1060 hf = b43_hf_read(dev);
1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1062 !!(hf & B43_HF_USEDEFKEYS));
1063 if (b43_new_kidx_api(dev)) {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1070 for (index = 0; index < count; index++) {
1071 key = &(dev->key[index]);
1072 printk(KERN_DEBUG "Key slot %02u: %s",
1073 index, (key->keyconf == NULL) ? " " : "*");
1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1080 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082 printk(" Algo: %04X/%02X", algo, key->algorithm);
1084 if (index >= pairwise_keys_start) {
1085 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088 for (i = 0; i < 14; i += 2) {
1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094 ((index - pairwise_keys_start) * 2) + 0);
1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096 ((index - pairwise_keys_start) * 2) + 1);
1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099 printk(" MAC: %pM", mac);
1101 printk(" DEFAULT KEY");
1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115 (ps_flags & B43_PS_DISABLED));
1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1118 if (ps_flags & B43_PS_ENABLED) {
1120 } else if (ps_flags & B43_PS_DISABLED) {
1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124 // and thus is not an AP and we are associated, set bit 25
1126 if (ps_flags & B43_PS_AWAKE) {
1128 } else if (ps_flags & B43_PS_ASLEEP) {
1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133 // successful, set bit26
1136 /* FIXME: For now we force awake-on and hwps-off */
1140 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1142 macctl |= B43_MACCTL_HWPS;
1144 macctl &= ~B43_MACCTL_HWPS;
1146 macctl |= B43_MACCTL_AWAKE;
1148 macctl &= ~B43_MACCTL_AWAKE;
1149 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1151 b43_read32(dev, B43_MMIO_MACCTL);
1152 if (awake && dev->dev->core_rev >= 5) {
1153 /* Wait for the microcode to wake up. */
1154 for (i = 0; i < 100; i++) {
1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156 B43_SHM_SH_UCODESTAT);
1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1164 #ifdef CONFIG_B43_BCMA
1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1169 /* Put PHY into reset */
1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171 flags |= B43_BCMA_IOCTL_PHY_RESET;
1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1176 /* Take PHY out of reset */
1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179 flags |= BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1183 /* Do not force clock anymore */
1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185 flags &= ~BCMA_IOCTL_FGC;
1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1192 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1193 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1194 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1195 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1197 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1198 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1199 b43_bcma_phy_reset(dev);
1200 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1204 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1206 struct ssb_device *sdev = dev->dev->sdev;
1211 flags |= B43_TMSLOW_GMODE;
1212 flags |= B43_TMSLOW_PHYCLKEN;
1213 flags |= B43_TMSLOW_PHYRESET;
1214 if (dev->phy.type == B43_PHYTYPE_N)
1215 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1216 b43_device_enable(dev, flags);
1217 msleep(2); /* Wait for the PLL to turn on. */
1219 /* Now take the PHY out of Reset again */
1220 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1221 tmslow |= SSB_TMSLOW_FGC;
1222 tmslow &= ~B43_TMSLOW_PHYRESET;
1223 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1224 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1226 tmslow &= ~SSB_TMSLOW_FGC;
1227 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1228 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1232 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1236 switch (dev->dev->bus_type) {
1237 #ifdef CONFIG_B43_BCMA
1239 b43_bcma_wireless_core_reset(dev, gmode);
1242 #ifdef CONFIG_B43_SSB
1244 b43_ssb_wireless_core_reset(dev, gmode);
1249 /* Turn Analog ON, but only if we already know the PHY-type.
1250 * This protects against very early setup where we don't know the
1251 * PHY-type, yet. wireless_core_reset will be called once again later,
1252 * when we know the PHY-type. */
1254 dev->phy.ops->switch_analog(dev, 1);
1256 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1257 macctl &= ~B43_MACCTL_GMODE;
1259 macctl |= B43_MACCTL_GMODE;
1260 macctl |= B43_MACCTL_IHR_ENABLED;
1261 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1264 static void handle_irq_transmit_status(struct b43_wldev *dev)
1268 struct b43_txstatus stat;
1271 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1272 if (!(v0 & 0x00000001))
1274 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1276 stat.cookie = (v0 >> 16);
1277 stat.seq = (v1 & 0x0000FFFF);
1278 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1279 tmp = (v0 & 0x0000FFFF);
1280 stat.frame_count = ((tmp & 0xF000) >> 12);
1281 stat.rts_count = ((tmp & 0x0F00) >> 8);
1282 stat.supp_reason = ((tmp & 0x001C) >> 2);
1283 stat.pm_indicated = !!(tmp & 0x0080);
1284 stat.intermediate = !!(tmp & 0x0040);
1285 stat.for_ampdu = !!(tmp & 0x0020);
1286 stat.acked = !!(tmp & 0x0002);
1288 b43_handle_txstatus(dev, &stat);
1292 static void drain_txstatus_queue(struct b43_wldev *dev)
1296 if (dev->dev->core_rev < 5)
1298 /* Read all entries from the microcode TXstatus FIFO
1299 * and throw them away.
1302 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1303 if (!(dummy & 0x00000001))
1305 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1309 static u32 b43_jssi_read(struct b43_wldev *dev)
1313 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1315 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1320 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1322 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1323 (jssi & 0x0000FFFF));
1324 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1325 (jssi & 0xFFFF0000) >> 16);
1328 static void b43_generate_noise_sample(struct b43_wldev *dev)
1330 b43_jssi_write(dev, 0x7F7F7F7F);
1331 b43_write32(dev, B43_MMIO_MACCMD,
1332 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1335 static void b43_calculate_link_quality(struct b43_wldev *dev)
1337 /* Top half of Link Quality calculation. */
1339 if (dev->phy.type != B43_PHYTYPE_G)
1341 if (dev->noisecalc.calculation_running)
1343 dev->noisecalc.calculation_running = true;
1344 dev->noisecalc.nr_samples = 0;
1346 b43_generate_noise_sample(dev);
1349 static void handle_irq_noise(struct b43_wldev *dev)
1351 struct b43_phy_g *phy = dev->phy.g;
1357 /* Bottom half of Link Quality calculation. */
1359 if (dev->phy.type != B43_PHYTYPE_G)
1362 /* Possible race condition: It might be possible that the user
1363 * changed to a different channel in the meantime since we
1364 * started the calculation. We ignore that fact, since it's
1365 * not really that much of a problem. The background noise is
1366 * an estimation only anyway. Slightly wrong results will get damped
1367 * by the averaging of the 8 sample rounds. Additionally the
1368 * value is shortlived. So it will be replaced by the next noise
1369 * calculation round soon. */
1371 B43_WARN_ON(!dev->noisecalc.calculation_running);
1372 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1373 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1374 noise[2] == 0x7F || noise[3] == 0x7F)
1377 /* Get the noise samples. */
1378 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1379 i = dev->noisecalc.nr_samples;
1380 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1381 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1382 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1383 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1384 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1385 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1386 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1387 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1388 dev->noisecalc.nr_samples++;
1389 if (dev->noisecalc.nr_samples == 8) {
1390 /* Calculate the Link Quality by the noise samples. */
1392 for (i = 0; i < 8; i++) {
1393 for (j = 0; j < 4; j++)
1394 average += dev->noisecalc.samples[i][j];
1400 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1401 tmp = (tmp / 128) & 0x1F;
1411 dev->stats.link_noise = average;
1412 dev->noisecalc.calculation_running = false;
1416 b43_generate_noise_sample(dev);
1419 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1421 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1424 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1425 b43_power_saving_ctl_bits(dev, 0);
1427 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1428 dev->dfq_valid = true;
1431 static void handle_irq_atim_end(struct b43_wldev *dev)
1433 if (dev->dfq_valid) {
1434 b43_write32(dev, B43_MMIO_MACCMD,
1435 b43_read32(dev, B43_MMIO_MACCMD)
1436 | B43_MACCMD_DFQ_VALID);
1437 dev->dfq_valid = false;
1441 static void handle_irq_pmq(struct b43_wldev *dev)
1448 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1449 if (!(tmp & 0x00000008))
1452 /* 16bit write is odd, but correct. */
1453 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1456 static void b43_write_template_common(struct b43_wldev *dev,
1457 const u8 *data, u16 size,
1459 u16 shm_size_offset, u8 rate)
1462 struct b43_plcp_hdr4 plcp;
1465 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1466 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1467 ram_offset += sizeof(u32);
1468 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1469 * So leave the first two bytes of the next write blank.
1471 tmp = (u32) (data[0]) << 16;
1472 tmp |= (u32) (data[1]) << 24;
1473 b43_ram_write(dev, ram_offset, tmp);
1474 ram_offset += sizeof(u32);
1475 for (i = 2; i < size; i += sizeof(u32)) {
1476 tmp = (u32) (data[i + 0]);
1478 tmp |= (u32) (data[i + 1]) << 8;
1480 tmp |= (u32) (data[i + 2]) << 16;
1482 tmp |= (u32) (data[i + 3]) << 24;
1483 b43_ram_write(dev, ram_offset + i - 2, tmp);
1485 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1486 size + sizeof(struct b43_plcp_hdr6));
1489 /* Check if the use of the antenna that ieee80211 told us to
1490 * use is possible. This will fall back to DEFAULT.
1491 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1492 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1497 if (antenna_nr == 0) {
1498 /* Zero means "use default antenna". That's always OK. */
1502 /* Get the mask of available antennas. */
1504 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1506 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1508 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1509 /* This antenna is not available. Fall back to default. */
1516 /* Convert a b43 antenna number value to the PHY TX control value. */
1517 static u16 b43_antenna_to_phyctl(int antenna)
1521 return B43_TXH_PHY_ANT0;
1523 return B43_TXH_PHY_ANT1;
1525 return B43_TXH_PHY_ANT2;
1527 return B43_TXH_PHY_ANT3;
1528 case B43_ANTENNA_AUTO0:
1529 case B43_ANTENNA_AUTO1:
1530 return B43_TXH_PHY_ANT01AUTO;
1536 static void b43_write_beacon_template(struct b43_wldev *dev,
1538 u16 shm_size_offset)
1540 unsigned int i, len, variable_len;
1541 const struct ieee80211_mgmt *bcn;
1543 bool tim_found = false;
1547 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1549 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1550 len = min((size_t) dev->wl->current_beacon->len,
1551 0x200 - sizeof(struct b43_plcp_hdr6));
1552 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1554 b43_write_template_common(dev, (const u8 *)bcn,
1555 len, ram_offset, shm_size_offset, rate);
1557 /* Write the PHY TX control parameters. */
1558 antenna = B43_ANTENNA_DEFAULT;
1559 antenna = b43_antenna_to_phyctl(antenna);
1560 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1561 /* We can't send beacons with short preamble. Would get PHY errors. */
1562 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1563 ctl &= ~B43_TXH_PHY_ANT;
1564 ctl &= ~B43_TXH_PHY_ENC;
1566 if (b43_is_cck_rate(rate))
1567 ctl |= B43_TXH_PHY_ENC_CCK;
1569 ctl |= B43_TXH_PHY_ENC_OFDM;
1570 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1572 /* Find the position of the TIM and the DTIM_period value
1573 * and write them to SHM. */
1574 ie = bcn->u.beacon.variable;
1575 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1576 for (i = 0; i < variable_len - 2; ) {
1577 uint8_t ie_id, ie_len;
1584 /* This is the TIM Information Element */
1586 /* Check whether the ie_len is in the beacon data range. */
1587 if (variable_len < ie_len + 2 + i)
1589 /* A valid TIM is at least 4 bytes long. */
1594 tim_position = sizeof(struct b43_plcp_hdr6);
1595 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1598 dtim_period = ie[i + 3];
1600 b43_shm_write16(dev, B43_SHM_SHARED,
1601 B43_SHM_SH_TIMBPOS, tim_position);
1602 b43_shm_write16(dev, B43_SHM_SHARED,
1603 B43_SHM_SH_DTIMPER, dtim_period);
1610 * If ucode wants to modify TIM do it behind the beacon, this
1611 * will happen, for example, when doing mesh networking.
1613 b43_shm_write16(dev, B43_SHM_SHARED,
1615 len + sizeof(struct b43_plcp_hdr6));
1616 b43_shm_write16(dev, B43_SHM_SHARED,
1617 B43_SHM_SH_DTIMPER, 0);
1619 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1622 static void b43_upload_beacon0(struct b43_wldev *dev)
1624 struct b43_wl *wl = dev->wl;
1626 if (wl->beacon0_uploaded)
1628 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1629 wl->beacon0_uploaded = true;
1632 static void b43_upload_beacon1(struct b43_wldev *dev)
1634 struct b43_wl *wl = dev->wl;
1636 if (wl->beacon1_uploaded)
1638 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1639 wl->beacon1_uploaded = true;
1642 static void handle_irq_beacon(struct b43_wldev *dev)
1644 struct b43_wl *wl = dev->wl;
1645 u32 cmd, beacon0_valid, beacon1_valid;
1647 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1648 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1649 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1652 /* This is the bottom half of the asynchronous beacon update. */
1654 /* Ignore interrupt in the future. */
1655 dev->irq_mask &= ~B43_IRQ_BEACON;
1657 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1658 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1659 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1661 /* Schedule interrupt manually, if busy. */
1662 if (beacon0_valid && beacon1_valid) {
1663 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1664 dev->irq_mask |= B43_IRQ_BEACON;
1668 if (unlikely(wl->beacon_templates_virgin)) {
1669 /* We never uploaded a beacon before.
1670 * Upload both templates now, but only mark one valid. */
1671 wl->beacon_templates_virgin = false;
1672 b43_upload_beacon0(dev);
1673 b43_upload_beacon1(dev);
1674 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1675 cmd |= B43_MACCMD_BEACON0_VALID;
1676 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1678 if (!beacon0_valid) {
1679 b43_upload_beacon0(dev);
1680 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1681 cmd |= B43_MACCMD_BEACON0_VALID;
1682 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1683 } else if (!beacon1_valid) {
1684 b43_upload_beacon1(dev);
1685 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1686 cmd |= B43_MACCMD_BEACON1_VALID;
1687 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1692 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1694 u32 old_irq_mask = dev->irq_mask;
1696 /* update beacon right away or defer to irq */
1697 handle_irq_beacon(dev);
1698 if (old_irq_mask != dev->irq_mask) {
1699 /* The handler updated the IRQ mask. */
1700 B43_WARN_ON(!dev->irq_mask);
1701 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1702 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1704 /* Device interrupts are currently disabled. That means
1705 * we just ran the hardirq handler and scheduled the
1706 * IRQ thread. The thread will write the IRQ mask when
1707 * it finished, so there's nothing to do here. Writing
1708 * the mask _here_ would incorrectly re-enable IRQs. */
1713 static void b43_beacon_update_trigger_work(struct work_struct *work)
1715 struct b43_wl *wl = container_of(work, struct b43_wl,
1716 beacon_update_trigger);
1717 struct b43_wldev *dev;
1719 mutex_lock(&wl->mutex);
1720 dev = wl->current_dev;
1721 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1722 if (b43_bus_host_is_sdio(dev->dev)) {
1723 /* wl->mutex is enough. */
1724 b43_do_beacon_update_trigger_work(dev);
1727 spin_lock_irq(&wl->hardirq_lock);
1728 b43_do_beacon_update_trigger_work(dev);
1730 spin_unlock_irq(&wl->hardirq_lock);
1733 mutex_unlock(&wl->mutex);
1736 /* Asynchronously update the packet templates in template RAM.
1737 * Locking: Requires wl->mutex to be locked. */
1738 static void b43_update_templates(struct b43_wl *wl)
1740 struct sk_buff *beacon;
1742 /* This is the top half of the ansynchronous beacon update.
1743 * The bottom half is the beacon IRQ.
1744 * Beacon update must be asynchronous to avoid sending an
1745 * invalid beacon. This can happen for example, if the firmware
1746 * transmits a beacon while we are updating it. */
1748 /* We could modify the existing beacon and set the aid bit in
1749 * the TIM field, but that would probably require resizing and
1750 * moving of data within the beacon template.
1751 * Simply request a new beacon and let mac80211 do the hard work. */
1752 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1753 if (unlikely(!beacon))
1756 if (wl->current_beacon)
1757 dev_kfree_skb_any(wl->current_beacon);
1758 wl->current_beacon = beacon;
1759 wl->beacon0_uploaded = false;
1760 wl->beacon1_uploaded = false;
1761 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1764 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1767 if (dev->dev->core_rev >= 3) {
1768 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1769 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1771 b43_write16(dev, 0x606, (beacon_int >> 6));
1772 b43_write16(dev, 0x610, beacon_int);
1774 b43_time_unlock(dev);
1775 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1778 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1782 /* Read the register that contains the reason code for the panic. */
1783 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1784 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1788 b43dbg(dev->wl, "The panic reason is unknown.\n");
1790 case B43_FWPANIC_DIE:
1791 /* Do not restart the controller or firmware.
1792 * The device is nonfunctional from now on.
1793 * Restarting would result in this panic to trigger again,
1794 * so we avoid that recursion. */
1796 case B43_FWPANIC_RESTART:
1797 b43_controller_restart(dev, "Microcode panic");
1802 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1804 unsigned int i, cnt;
1805 u16 reason, marker_id, marker_line;
1808 /* The proprietary firmware doesn't have this IRQ. */
1809 if (!dev->fw.opensource)
1812 /* Read the register that contains the reason code for this IRQ. */
1813 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1816 case B43_DEBUGIRQ_PANIC:
1817 b43_handle_firmware_panic(dev);
1819 case B43_DEBUGIRQ_DUMP_SHM:
1821 break; /* Only with driver debugging enabled. */
1822 buf = kmalloc(4096, GFP_ATOMIC);
1824 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1827 for (i = 0; i < 4096; i += 2) {
1828 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1829 buf[i / 2] = cpu_to_le16(tmp);
1831 b43info(dev->wl, "Shared memory dump:\n");
1832 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1833 16, 2, buf, 4096, 1);
1836 case B43_DEBUGIRQ_DUMP_REGS:
1838 break; /* Only with driver debugging enabled. */
1839 b43info(dev->wl, "Microcode register dump:\n");
1840 for (i = 0, cnt = 0; i < 64; i++) {
1841 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1844 printk("r%02u: 0x%04X ", i, tmp);
1853 case B43_DEBUGIRQ_MARKER:
1855 break; /* Only with driver debugging enabled. */
1856 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1858 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1859 B43_MARKER_LINE_REG);
1860 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1861 "at line number %u\n",
1862 marker_id, marker_line);
1865 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1869 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1870 b43_shm_write16(dev, B43_SHM_SCRATCH,
1871 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1874 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1877 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1878 u32 merged_dma_reason = 0;
1881 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1884 reason = dev->irq_reason;
1885 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1886 dma_reason[i] = dev->dma_reason[i];
1887 merged_dma_reason |= dma_reason[i];
1890 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1891 b43err(dev->wl, "MAC transmission error\n");
1893 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1894 b43err(dev->wl, "PHY transmission error\n");
1896 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1897 atomic_set(&dev->phy.txerr_cnt,
1898 B43_PHY_TX_BADNESS_LIMIT);
1899 b43err(dev->wl, "Too many PHY TX errors, "
1900 "restarting the controller\n");
1901 b43_controller_restart(dev, "PHY TX errors");
1905 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1906 B43_DMAIRQ_NONFATALMASK))) {
1907 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1908 b43err(dev->wl, "Fatal DMA error: "
1909 "0x%08X, 0x%08X, 0x%08X, "
1910 "0x%08X, 0x%08X, 0x%08X\n",
1911 dma_reason[0], dma_reason[1],
1912 dma_reason[2], dma_reason[3],
1913 dma_reason[4], dma_reason[5]);
1914 b43err(dev->wl, "This device does not support DMA "
1915 "on your system. It will now be switched to PIO.\n");
1916 /* Fall back to PIO transfers if we get fatal DMA errors! */
1917 dev->use_pio = true;
1918 b43_controller_restart(dev, "DMA error");
1921 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1922 b43err(dev->wl, "DMA error: "
1923 "0x%08X, 0x%08X, 0x%08X, "
1924 "0x%08X, 0x%08X, 0x%08X\n",
1925 dma_reason[0], dma_reason[1],
1926 dma_reason[2], dma_reason[3],
1927 dma_reason[4], dma_reason[5]);
1931 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1932 handle_irq_ucode_debug(dev);
1933 if (reason & B43_IRQ_TBTT_INDI)
1934 handle_irq_tbtt_indication(dev);
1935 if (reason & B43_IRQ_ATIM_END)
1936 handle_irq_atim_end(dev);
1937 if (reason & B43_IRQ_BEACON)
1938 handle_irq_beacon(dev);
1939 if (reason & B43_IRQ_PMQ)
1940 handle_irq_pmq(dev);
1941 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1943 if (reason & B43_IRQ_NOISESAMPLE_OK)
1944 handle_irq_noise(dev);
1946 /* Check the DMA reason registers for received data. */
1947 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1948 if (b43_using_pio_transfers(dev))
1949 b43_pio_rx(dev->pio.rx_queue);
1951 b43_dma_rx(dev->dma.rx_ring);
1953 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1954 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1955 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1956 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1957 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1959 if (reason & B43_IRQ_TX_OK)
1960 handle_irq_transmit_status(dev);
1962 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1963 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1966 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1968 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1969 if (reason & (1 << i))
1970 dev->irq_bit_count[i]++;
1976 /* Interrupt thread handler. Handles device interrupts in thread context. */
1977 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1979 struct b43_wldev *dev = dev_id;
1981 mutex_lock(&dev->wl->mutex);
1982 b43_do_interrupt_thread(dev);
1984 mutex_unlock(&dev->wl->mutex);
1989 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1993 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1994 * On SDIO, this runs under wl->mutex. */
1996 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1997 if (reason == 0xffffffff) /* shared IRQ */
1999 reason &= dev->irq_mask;
2003 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2005 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2007 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2009 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2011 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2014 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2018 /* ACK the interrupt. */
2019 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2020 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2021 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2022 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2023 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2024 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2026 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2029 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2030 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2031 /* Save the reason bitmasks for the IRQ thread handler. */
2032 dev->irq_reason = reason;
2034 return IRQ_WAKE_THREAD;
2037 /* Interrupt handler top-half. This runs with interrupts disabled. */
2038 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2040 struct b43_wldev *dev = dev_id;
2043 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2046 spin_lock(&dev->wl->hardirq_lock);
2047 ret = b43_do_interrupt(dev);
2049 spin_unlock(&dev->wl->hardirq_lock);
2054 /* SDIO interrupt handler. This runs in process context. */
2055 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2057 struct b43_wl *wl = dev->wl;
2060 mutex_lock(&wl->mutex);
2062 ret = b43_do_interrupt(dev);
2063 if (ret == IRQ_WAKE_THREAD)
2064 b43_do_interrupt_thread(dev);
2066 mutex_unlock(&wl->mutex);
2069 void b43_do_release_fw(struct b43_firmware_file *fw)
2071 release_firmware(fw->data);
2073 fw->filename = NULL;
2076 static void b43_release_firmware(struct b43_wldev *dev)
2078 b43_do_release_fw(&dev->fw.ucode);
2079 b43_do_release_fw(&dev->fw.pcm);
2080 b43_do_release_fw(&dev->fw.initvals);
2081 b43_do_release_fw(&dev->fw.initvals_band);
2084 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2088 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2089 "and download the correct firmware for this driver version. " \
2090 "Please carefully read all instructions on this website.\n";
2098 static void b43_fw_cb(const struct firmware *firmware, void *context)
2100 struct b43_request_fw_context *ctx = context;
2102 ctx->blob = firmware;
2103 complete(&ctx->fw_load_complete);
2106 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2108 struct b43_firmware_file *fw, bool async)
2110 struct b43_fw_header *hdr;
2115 /* Don't fetch anything. Free possibly cached firmware. */
2116 /* FIXME: We should probably keep it anyway, to save some headache
2117 * on suspend/resume with multiband devices. */
2118 b43_do_release_fw(fw);
2122 if ((fw->type == ctx->req_type) &&
2123 (strcmp(fw->filename, name) == 0))
2124 return 0; /* Already have this fw. */
2125 /* Free the cached firmware first. */
2126 /* FIXME: We should probably do this later after we successfully
2127 * got the new fw. This could reduce headache with multiband devices.
2128 * We could also redesign this to cache the firmware for all possible
2129 * bands all the time. */
2130 b43_do_release_fw(fw);
2133 switch (ctx->req_type) {
2134 case B43_FWTYPE_PROPRIETARY:
2135 snprintf(ctx->fwname, sizeof(ctx->fwname),
2137 modparam_fwpostfix, name);
2139 case B43_FWTYPE_OPENSOURCE:
2140 snprintf(ctx->fwname, sizeof(ctx->fwname),
2142 modparam_fwpostfix, name);
2149 /* do this part asynchronously */
2150 init_completion(&ctx->fw_load_complete);
2151 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2152 ctx->dev->dev->dev, GFP_KERNEL,
2155 pr_err("Unable to load firmware\n");
2158 /* stall here until fw ready */
2159 wait_for_completion(&ctx->fw_load_complete);
2162 /* On some ARM systems, the async request will fail, but the next sync
2163 * request works. For this reason, we dall through here
2166 err = request_firmware(&ctx->blob, ctx->fwname,
2167 ctx->dev->dev->dev);
2168 if (err == -ENOENT) {
2169 snprintf(ctx->errors[ctx->req_type],
2170 sizeof(ctx->errors[ctx->req_type]),
2171 "Firmware file \"%s\" not found\n",
2175 snprintf(ctx->errors[ctx->req_type],
2176 sizeof(ctx->errors[ctx->req_type]),
2177 "Firmware file \"%s\" request failed (err=%d)\n",
2182 if (ctx->blob->size < sizeof(struct b43_fw_header))
2184 hdr = (struct b43_fw_header *)(ctx->blob->data);
2185 switch (hdr->type) {
2186 case B43_FW_TYPE_UCODE:
2187 case B43_FW_TYPE_PCM:
2188 size = be32_to_cpu(hdr->size);
2189 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2192 case B43_FW_TYPE_IV:
2200 fw->data = ctx->blob;
2201 fw->filename = name;
2202 fw->type = ctx->req_type;
2207 snprintf(ctx->errors[ctx->req_type],
2208 sizeof(ctx->errors[ctx->req_type]),
2209 "Firmware file \"%s\" format error.\n", ctx->fwname);
2210 release_firmware(ctx->blob);
2215 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2217 struct b43_wldev *dev = ctx->dev;
2218 struct b43_firmware *fw = &ctx->dev->fw;
2219 const u8 rev = ctx->dev->dev->core_rev;
2220 const char *filename;
2224 /* Files for HT and LCN were found by trying one by one */
2227 if ((rev >= 5) && (rev <= 10)) {
2228 filename = "ucode5";
2229 } else if ((rev >= 11) && (rev <= 12)) {
2230 filename = "ucode11";
2231 } else if (rev == 13) {
2232 filename = "ucode13";
2233 } else if (rev == 14) {
2234 filename = "ucode14";
2235 } else if (rev == 15) {
2236 filename = "ucode15";
2238 switch (dev->phy.type) {
2241 filename = "ucode16_mimo";
2245 case B43_PHYTYPE_HT:
2247 filename = "ucode29_mimo";
2251 case B43_PHYTYPE_LCN:
2253 filename = "ucode24_mimo";
2261 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2266 if ((rev >= 5) && (rev <= 10))
2272 fw->pcm_request_failed = false;
2273 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2274 if (err == -ENOENT) {
2275 /* We did not find a PCM file? Not fatal, but
2276 * core rev <= 10 must do without hwcrypto then. */
2277 fw->pcm_request_failed = true;
2282 switch (dev->phy.type) {
2284 if ((rev >= 5) && (rev <= 10)) {
2285 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2286 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2287 filename = "a0g1initvals5";
2289 filename = "a0g0initvals5";
2291 goto err_no_initvals;
2294 if ((rev >= 5) && (rev <= 10))
2295 filename = "b0g0initvals5";
2297 filename = "b0g0initvals13";
2299 goto err_no_initvals;
2303 filename = "n0initvals16";
2304 else if ((rev >= 11) && (rev <= 12))
2305 filename = "n0initvals11";
2307 goto err_no_initvals;
2309 case B43_PHYTYPE_LP:
2311 filename = "lp0initvals13";
2313 filename = "lp0initvals14";
2315 filename = "lp0initvals15";
2317 goto err_no_initvals;
2319 case B43_PHYTYPE_HT:
2321 filename = "ht0initvals29";
2323 goto err_no_initvals;
2325 case B43_PHYTYPE_LCN:
2327 filename = "lcn0initvals24";
2329 goto err_no_initvals;
2332 goto err_no_initvals;
2334 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2338 /* Get bandswitch initvals */
2339 switch (dev->phy.type) {
2341 if ((rev >= 5) && (rev <= 10)) {
2342 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2343 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2344 filename = "a0g1bsinitvals5";
2346 filename = "a0g0bsinitvals5";
2347 } else if (rev >= 11)
2350 goto err_no_initvals;
2353 if ((rev >= 5) && (rev <= 10))
2354 filename = "b0g0bsinitvals5";
2358 goto err_no_initvals;
2362 filename = "n0bsinitvals16";
2363 else if ((rev >= 11) && (rev <= 12))
2364 filename = "n0bsinitvals11";
2366 goto err_no_initvals;
2368 case B43_PHYTYPE_LP:
2370 filename = "lp0bsinitvals13";
2372 filename = "lp0bsinitvals14";
2374 filename = "lp0bsinitvals15";
2376 goto err_no_initvals;
2378 case B43_PHYTYPE_HT:
2380 filename = "ht0bsinitvals29";
2382 goto err_no_initvals;
2384 case B43_PHYTYPE_LCN:
2386 filename = "lcn0bsinitvals24";
2388 goto err_no_initvals;
2391 goto err_no_initvals;
2393 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2397 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2402 err = ctx->fatal_failure = -EOPNOTSUPP;
2403 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2404 "is required for your device (wl-core rev %u)\n", rev);
2408 err = ctx->fatal_failure = -EOPNOTSUPP;
2409 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2410 "is required for your device (wl-core rev %u)\n", rev);
2414 err = ctx->fatal_failure = -EOPNOTSUPP;
2415 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2416 "is required for your device (wl-core rev %u)\n", rev);
2420 /* We failed to load this firmware image. The error message
2421 * already is in ctx->errors. Return and let our caller decide
2426 b43_release_firmware(dev);
2430 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2431 static void b43_one_core_detach(struct b43_bus_dev *dev);
2433 static void b43_request_firmware(struct work_struct *work)
2435 struct b43_wl *wl = container_of(work,
2436 struct b43_wl, firmware_load);
2437 struct b43_wldev *dev = wl->current_dev;
2438 struct b43_request_fw_context *ctx;
2443 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2448 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2449 err = b43_try_request_fw(ctx);
2451 goto start_ieee80211; /* Successfully loaded it. */
2452 /* Was fw version known? */
2453 if (ctx->fatal_failure)
2456 /* proprietary fw not found, try open source */
2457 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2458 err = b43_try_request_fw(ctx);
2460 goto start_ieee80211; /* Successfully loaded it. */
2461 if(ctx->fatal_failure)
2464 /* Could not find a usable firmware. Print the errors. */
2465 for (i = 0; i < B43_NR_FWTYPES; i++) {
2466 errmsg = ctx->errors[i];
2468 b43err(dev->wl, errmsg);
2470 b43_print_fw_helptext(dev->wl, 1);
2474 wl->hw->queues = B43_QOS_QUEUE_NUM;
2475 if (!modparam_qos || dev->fw.opensource)
2478 err = ieee80211_register_hw(wl->hw);
2480 goto err_one_core_detach;
2481 wl->hw_registred = true;
2482 b43_leds_register(wl->current_dev);
2485 err_one_core_detach:
2486 b43_one_core_detach(dev->dev);
2492 static int b43_upload_microcode(struct b43_wldev *dev)
2494 struct wiphy *wiphy = dev->wl->hw->wiphy;
2495 const size_t hdr_len = sizeof(struct b43_fw_header);
2497 unsigned int i, len;
2498 u16 fwrev, fwpatch, fwdate, fwtime;
2502 /* Jump the microcode PSM to offset 0 */
2503 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2504 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2505 macctl |= B43_MACCTL_PSM_JMP0;
2506 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2507 /* Zero out all microcode PSM registers and shared memory. */
2508 for (i = 0; i < 64; i++)
2509 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2510 for (i = 0; i < 4096; i += 2)
2511 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2513 /* Upload Microcode. */
2514 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2515 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2516 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2517 for (i = 0; i < len; i++) {
2518 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2522 if (dev->fw.pcm.data) {
2523 /* Upload PCM data. */
2524 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2525 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2526 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2527 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2528 /* No need for autoinc bit in SHM_HW */
2529 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2530 for (i = 0; i < len; i++) {
2531 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2536 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2538 /* Start the microcode PSM */
2539 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2540 B43_MACCTL_PSM_RUN);
2542 /* Wait for the microcode to load and respond */
2545 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2546 if (tmp == B43_IRQ_MAC_SUSPENDED)
2550 b43err(dev->wl, "Microcode not responding\n");
2551 b43_print_fw_helptext(dev->wl, 1);
2557 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2559 /* Get and check the revisions. */
2560 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2561 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2562 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2563 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2565 if (fwrev <= 0x128) {
2566 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2567 "binary drivers older than version 4.x is unsupported. "
2568 "You must upgrade your firmware files.\n");
2569 b43_print_fw_helptext(dev->wl, 1);
2573 dev->fw.rev = fwrev;
2574 dev->fw.patch = fwpatch;
2575 if (dev->fw.rev >= 598)
2576 dev->fw.hdr_format = B43_FW_HDR_598;
2577 else if (dev->fw.rev >= 410)
2578 dev->fw.hdr_format = B43_FW_HDR_410;
2580 dev->fw.hdr_format = B43_FW_HDR_351;
2581 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2583 dev->qos_enabled = dev->wl->hw->queues > 1;
2584 /* Default to firmware/hardware crypto acceleration. */
2585 dev->hwcrypto_enabled = true;
2587 if (dev->fw.opensource) {
2590 /* Patchlevel info is encoded in the "time" field. */
2591 dev->fw.patch = fwtime;
2592 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2593 dev->fw.rev, dev->fw.patch);
2595 fwcapa = b43_fwcapa_read(dev);
2596 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2597 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2598 /* Disable hardware crypto and fall back to software crypto. */
2599 dev->hwcrypto_enabled = false;
2601 /* adding QoS support should use an offline discovery mechanism */
2602 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2604 b43info(dev->wl, "Loading firmware version %u.%u "
2605 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2607 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2608 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2609 if (dev->fw.pcm_request_failed) {
2610 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2611 "Hardware accelerated cryptography is disabled.\n");
2612 b43_print_fw_helptext(dev->wl, 0);
2616 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2617 dev->fw.rev, dev->fw.patch);
2618 wiphy->hw_version = dev->dev->core_id;
2620 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2621 /* We're over the deadline, but we keep support for old fw
2622 * until it turns out to be in major conflict with something new. */
2623 b43warn(dev->wl, "You are using an old firmware image. "
2624 "Support for old firmware will be removed soon "
2625 "(official deadline was July 2008).\n");
2626 b43_print_fw_helptext(dev->wl, 0);
2632 /* Stop the microcode PSM. */
2633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2634 B43_MACCTL_PSM_JMP0);
2639 static int b43_write_initvals(struct b43_wldev *dev,
2640 const struct b43_iv *ivals,
2644 const struct b43_iv *iv;
2649 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2651 for (i = 0; i < count; i++) {
2652 if (array_size < sizeof(iv->offset_size))
2654 array_size -= sizeof(iv->offset_size);
2655 offset = be16_to_cpu(iv->offset_size);
2656 bit32 = !!(offset & B43_IV_32BIT);
2657 offset &= B43_IV_OFFSET_MASK;
2658 if (offset >= 0x1000)
2663 if (array_size < sizeof(iv->data.d32))
2665 array_size -= sizeof(iv->data.d32);
2667 value = get_unaligned_be32(&iv->data.d32);
2668 b43_write32(dev, offset, value);
2670 iv = (const struct b43_iv *)((const uint8_t *)iv +
2676 if (array_size < sizeof(iv->data.d16))
2678 array_size -= sizeof(iv->data.d16);
2680 value = be16_to_cpu(iv->data.d16);
2681 b43_write16(dev, offset, value);
2683 iv = (const struct b43_iv *)((const uint8_t *)iv +
2694 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2695 b43_print_fw_helptext(dev->wl, 1);
2700 static int b43_upload_initvals(struct b43_wldev *dev)
2702 const size_t hdr_len = sizeof(struct b43_fw_header);
2703 const struct b43_fw_header *hdr;
2704 struct b43_firmware *fw = &dev->fw;
2705 const struct b43_iv *ivals;
2709 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2710 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2711 count = be32_to_cpu(hdr->size);
2712 err = b43_write_initvals(dev, ivals, count,
2713 fw->initvals.data->size - hdr_len);
2716 if (fw->initvals_band.data) {
2717 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2718 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2719 count = be32_to_cpu(hdr->size);
2720 err = b43_write_initvals(dev, ivals, count,
2721 fw->initvals_band.data->size - hdr_len);
2730 /* Initialize the GPIOs
2731 * http://bcm-specs.sipsolutions.net/GPIO
2733 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2735 struct ssb_bus *bus = dev->dev->sdev->bus;
2737 #ifdef CONFIG_SSB_DRIVER_PCICORE
2738 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2740 return bus->chipco.dev;
2744 static int b43_gpio_init(struct b43_wldev *dev)
2746 struct ssb_device *gpiodev;
2749 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2750 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2754 if (dev->dev->chip_id == 0x4301) {
2757 } else if (dev->dev->chip_id == 0x5354) {
2758 /* Don't allow overtaking buttons GPIOs */
2759 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2762 if (0 /* FIXME: conditional unknown */ ) {
2763 b43_write16(dev, B43_MMIO_GPIO_MASK,
2764 b43_read16(dev, B43_MMIO_GPIO_MASK)
2766 /* BT Coexistance Input */
2769 /* BT Coexistance Out */
2773 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2774 /* PA is controlled by gpio 9, let ucode handle it */
2775 b43_write16(dev, B43_MMIO_GPIO_MASK,
2776 b43_read16(dev, B43_MMIO_GPIO_MASK)
2782 switch (dev->dev->bus_type) {
2783 #ifdef CONFIG_B43_BCMA
2785 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2788 #ifdef CONFIG_B43_SSB
2790 gpiodev = b43_ssb_gpio_dev(dev);
2792 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2793 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2802 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2803 static void b43_gpio_cleanup(struct b43_wldev *dev)
2805 struct ssb_device *gpiodev;
2807 switch (dev->dev->bus_type) {
2808 #ifdef CONFIG_B43_BCMA
2810 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2813 #ifdef CONFIG_B43_SSB
2815 gpiodev = b43_ssb_gpio_dev(dev);
2817 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2823 /* http://bcm-specs.sipsolutions.net/EnableMac */
2824 void b43_mac_enable(struct b43_wldev *dev)
2826 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2829 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2830 B43_SHM_SH_UCODESTAT);
2831 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2832 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2833 b43err(dev->wl, "b43_mac_enable(): The firmware "
2834 "should be suspended, but current state is %u\n",
2839 dev->mac_suspended--;
2840 B43_WARN_ON(dev->mac_suspended < 0);
2841 if (dev->mac_suspended == 0) {
2842 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2843 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2844 B43_IRQ_MAC_SUSPENDED);
2846 b43_read32(dev, B43_MMIO_MACCTL);
2847 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2848 b43_power_saving_ctl_bits(dev, 0);
2852 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2853 void b43_mac_suspend(struct b43_wldev *dev)
2859 B43_WARN_ON(dev->mac_suspended < 0);
2861 if (dev->mac_suspended == 0) {
2862 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2863 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2864 /* force pci to flush the write */
2865 b43_read32(dev, B43_MMIO_MACCTL);
2866 for (i = 35; i; i--) {
2867 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2868 if (tmp & B43_IRQ_MAC_SUSPENDED)
2872 /* Hm, it seems this will take some time. Use msleep(). */
2873 for (i = 40; i; i--) {
2874 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2875 if (tmp & B43_IRQ_MAC_SUSPENDED)
2879 b43err(dev->wl, "MAC suspend failed\n");
2882 dev->mac_suspended++;
2885 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2886 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2890 switch (dev->dev->bus_type) {
2891 #ifdef CONFIG_B43_BCMA
2893 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2895 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2897 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2898 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2901 #ifdef CONFIG_B43_SSB
2903 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2905 tmp |= B43_TMSLOW_MACPHYCLKEN;
2907 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2908 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2914 static void b43_adjust_opmode(struct b43_wldev *dev)
2916 struct b43_wl *wl = dev->wl;
2920 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2921 /* Reset status to STA infrastructure mode. */
2922 ctl &= ~B43_MACCTL_AP;
2923 ctl &= ~B43_MACCTL_KEEP_CTL;
2924 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2925 ctl &= ~B43_MACCTL_KEEP_BAD;
2926 ctl &= ~B43_MACCTL_PROMISC;
2927 ctl &= ~B43_MACCTL_BEACPROMISC;
2928 ctl |= B43_MACCTL_INFRA;
2930 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2931 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2932 ctl |= B43_MACCTL_AP;
2933 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2934 ctl &= ~B43_MACCTL_INFRA;
2936 if (wl->filter_flags & FIF_CONTROL)
2937 ctl |= B43_MACCTL_KEEP_CTL;
2938 if (wl->filter_flags & FIF_FCSFAIL)
2939 ctl |= B43_MACCTL_KEEP_BAD;
2940 if (wl->filter_flags & FIF_PLCPFAIL)
2941 ctl |= B43_MACCTL_KEEP_BADPLCP;
2942 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2943 ctl |= B43_MACCTL_PROMISC;
2944 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2945 ctl |= B43_MACCTL_BEACPROMISC;
2947 /* Workaround: On old hardware the HW-MAC-address-filter
2948 * doesn't work properly, so always run promisc in filter
2949 * it in software. */
2950 if (dev->dev->core_rev <= 4)
2951 ctl |= B43_MACCTL_PROMISC;
2953 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2956 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2957 if (dev->dev->chip_id == 0x4306 &&
2958 dev->dev->chip_rev == 3)
2963 b43_write16(dev, 0x612, cfp_pretbtt);
2965 /* FIXME: We don't currently implement the PMQ mechanism,
2966 * so always disable it. If we want to implement PMQ,
2967 * we need to enable it here (clear DISCPMQ) in AP mode.
2969 if (0 /* ctl & B43_MACCTL_AP */)
2970 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2972 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2975 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2981 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2984 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2986 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2987 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2990 static void b43_rate_memory_init(struct b43_wldev *dev)
2992 switch (dev->phy.type) {
2996 case B43_PHYTYPE_LP:
2997 case B43_PHYTYPE_HT:
2998 case B43_PHYTYPE_LCN:
2999 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3000 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3001 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3002 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3003 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3004 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3005 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3006 if (dev->phy.type == B43_PHYTYPE_A)
3010 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3011 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3012 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3013 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3020 /* Set the default values for the PHY TX Control Words. */
3021 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3025 ctl |= B43_TXH_PHY_ENC_CCK;
3026 ctl |= B43_TXH_PHY_ANT01AUTO;
3027 ctl |= B43_TXH_PHY_TXPWR;
3029 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3030 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3031 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3034 /* Set the TX-Antenna for management frames sent by firmware. */
3035 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3040 ant = b43_antenna_to_phyctl(antenna);
3043 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3044 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3045 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3046 /* For Probe Resposes */
3047 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3048 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3049 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3052 /* This is the opposite of b43_chip_init() */
3053 static void b43_chip_exit(struct b43_wldev *dev)
3056 b43_gpio_cleanup(dev);
3057 /* firmware is released later */
3060 /* Initialize the chip
3061 * http://bcm-specs.sipsolutions.net/ChipInit
3063 static int b43_chip_init(struct b43_wldev *dev)
3065 struct b43_phy *phy = &dev->phy;
3070 /* Initialize the MAC control */
3071 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3073 macctl |= B43_MACCTL_GMODE;
3074 macctl |= B43_MACCTL_INFRA;
3075 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3077 err = b43_upload_microcode(dev);
3079 goto out; /* firmware is released later */
3081 err = b43_gpio_init(dev);
3083 goto out; /* firmware is released later */
3085 err = b43_upload_initvals(dev);
3087 goto err_gpio_clean;
3089 /* Turn the Analog on and initialize the PHY. */
3090 phy->ops->switch_analog(dev, 1);
3091 err = b43_phy_init(dev);
3093 goto err_gpio_clean;
3095 /* Disable Interference Mitigation. */
3096 if (phy->ops->interf_mitigation)
3097 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3099 /* Select the antennae */
3100 if (phy->ops->set_rx_antenna)
3101 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3102 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3104 if (phy->type == B43_PHYTYPE_B) {
3105 value16 = b43_read16(dev, 0x005E);
3107 b43_write16(dev, 0x005E, value16);
3109 b43_write32(dev, 0x0100, 0x01000000);
3110 if (dev->dev->core_rev < 5)
3111 b43_write32(dev, 0x010C, 0x01000000);
3113 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3114 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3116 /* Probe Response Timeout value */
3117 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3118 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3120 /* Initially set the wireless operation mode. */
3121 b43_adjust_opmode(dev);
3123 if (dev->dev->core_rev < 3) {
3124 b43_write16(dev, 0x060E, 0x0000);
3125 b43_write16(dev, 0x0610, 0x8000);
3126 b43_write16(dev, 0x0604, 0x0000);
3127 b43_write16(dev, 0x0606, 0x0200);
3129 b43_write32(dev, 0x0188, 0x80000000);
3130 b43_write32(dev, 0x018C, 0x02000000);
3132 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3133 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3134 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3135 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3136 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3137 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3138 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3140 b43_mac_phy_clock_set(dev, true);
3142 switch (dev->dev->bus_type) {
3143 #ifdef CONFIG_B43_BCMA
3145 /* FIXME: 0xE74 is quite common, but should be read from CC */
3146 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3149 #ifdef CONFIG_B43_SSB
3151 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3152 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3158 b43dbg(dev->wl, "Chip initialized\n");
3163 b43_gpio_cleanup(dev);
3167 static void b43_periodic_every60sec(struct b43_wldev *dev)
3169 const struct b43_phy_operations *ops = dev->phy.ops;
3171 if (ops->pwork_60sec)
3172 ops->pwork_60sec(dev);
3174 /* Force check the TX power emission now. */
3175 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3178 static void b43_periodic_every30sec(struct b43_wldev *dev)
3180 /* Update device statistics. */
3181 b43_calculate_link_quality(dev);
3184 static void b43_periodic_every15sec(struct b43_wldev *dev)
3186 struct b43_phy *phy = &dev->phy;
3189 if (dev->fw.opensource) {
3190 /* Check if the firmware is still alive.
3191 * It will reset the watchdog counter to 0 in its idle loop. */
3192 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3193 if (unlikely(wdr)) {
3194 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3195 b43_controller_restart(dev, "Firmware watchdog");
3198 b43_shm_write16(dev, B43_SHM_SCRATCH,
3199 B43_WATCHDOG_REG, 1);
3203 if (phy->ops->pwork_15sec)
3204 phy->ops->pwork_15sec(dev);
3206 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3210 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3213 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3214 dev->irq_count / 15,
3216 dev->rx_count / 15);
3220 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3221 if (dev->irq_bit_count[i]) {
3222 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3223 dev->irq_bit_count[i] / 15, i, (1 << i));
3224 dev->irq_bit_count[i] = 0;
3231 static void do_periodic_work(struct b43_wldev *dev)
3235 state = dev->periodic_state;
3237 b43_periodic_every60sec(dev);
3239 b43_periodic_every30sec(dev);
3240 b43_periodic_every15sec(dev);
3243 /* Periodic work locking policy:
3244 * The whole periodic work handler is protected by
3245 * wl->mutex. If another lock is needed somewhere in the
3246 * pwork callchain, it's acquired in-place, where it's needed.
3248 static void b43_periodic_work_handler(struct work_struct *work)
3250 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3251 periodic_work.work);
3252 struct b43_wl *wl = dev->wl;
3253 unsigned long delay;
3255 mutex_lock(&wl->mutex);
3257 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3259 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3262 do_periodic_work(dev);
3264 dev->periodic_state++;
3266 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3267 delay = msecs_to_jiffies(50);
3269 delay = round_jiffies_relative(HZ * 15);
3270 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3272 mutex_unlock(&wl->mutex);
3275 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3277 struct delayed_work *work = &dev->periodic_work;
3279 dev->periodic_state = 0;
3280 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3281 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3284 /* Check if communication with the device works correctly. */
3285 static int b43_validate_chipaccess(struct b43_wldev *dev)
3287 u32 v, backup0, backup4;
3289 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3290 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3292 /* Check for read/write and endianness problems. */
3293 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3294 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3296 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3297 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3300 /* Check if unaligned 32bit SHM_SHARED access works properly.
3301 * However, don't bail out on failure, because it's noncritical. */
3302 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3303 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3304 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3305 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3306 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3307 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3308 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3309 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3310 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3311 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3312 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3313 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3315 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3316 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3318 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3319 /* The 32bit register shadows the two 16bit registers
3320 * with update sideeffects. Validate this. */
3321 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3322 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3323 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3325 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3328 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3330 v = b43_read32(dev, B43_MMIO_MACCTL);
3331 v |= B43_MACCTL_GMODE;
3332 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3337 b43err(dev->wl, "Failed to validate the chipaccess\n");
3341 static void b43_security_init(struct b43_wldev *dev)
3343 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3344 /* KTP is a word address, but we address SHM bytewise.
3345 * So multiply by two.
3348 /* Number of RCMTA address slots */
3349 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3350 /* Clear the key memory. */
3351 b43_clear_keys(dev);
3354 #ifdef CONFIG_B43_HWRNG
3355 static int b43_rng_read(struct hwrng *rng, u32 *data)
3357 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3358 struct b43_wldev *dev;
3359 int count = -ENODEV;
3361 mutex_lock(&wl->mutex);
3362 dev = wl->current_dev;
3363 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3364 *data = b43_read16(dev, B43_MMIO_RNG);
3365 count = sizeof(u16);
3367 mutex_unlock(&wl->mutex);
3371 #endif /* CONFIG_B43_HWRNG */
3373 static void b43_rng_exit(struct b43_wl *wl)
3375 #ifdef CONFIG_B43_HWRNG
3376 if (wl->rng_initialized)
3377 hwrng_unregister(&wl->rng);
3378 #endif /* CONFIG_B43_HWRNG */
3381 static int b43_rng_init(struct b43_wl *wl)
3385 #ifdef CONFIG_B43_HWRNG
3386 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3387 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3388 wl->rng.name = wl->rng_name;
3389 wl->rng.data_read = b43_rng_read;
3390 wl->rng.priv = (unsigned long)wl;
3391 wl->rng_initialized = true;
3392 err = hwrng_register(&wl->rng);
3394 wl->rng_initialized = false;
3395 b43err(wl, "Failed to register the random "
3396 "number generator (%d)\n", err);
3398 #endif /* CONFIG_B43_HWRNG */
3403 static void b43_tx_work(struct work_struct *work)
3405 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3406 struct b43_wldev *dev;
3407 struct sk_buff *skb;
3411 mutex_lock(&wl->mutex);
3412 dev = wl->current_dev;
3413 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3414 mutex_unlock(&wl->mutex);
3418 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3419 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3420 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3421 if (b43_using_pio_transfers(dev))
3422 err = b43_pio_tx(dev, skb);
3424 err = b43_dma_tx(dev, skb);
3425 if (err == -ENOSPC) {
3426 wl->tx_queue_stopped[queue_num] = 1;
3427 ieee80211_stop_queue(wl->hw, queue_num);
3428 skb_queue_head(&wl->tx_queue[queue_num], skb);
3432 ieee80211_free_txskb(wl->hw, skb);
3437 wl->tx_queue_stopped[queue_num] = 0;
3443 mutex_unlock(&wl->mutex);
3446 static void b43_op_tx(struct ieee80211_hw *hw,
3447 struct ieee80211_tx_control *control,
3448 struct sk_buff *skb)
3450 struct b43_wl *wl = hw_to_b43_wl(hw);
3452 if (unlikely(skb->len < 2 + 2 + 6)) {
3453 /* Too short, this can't be a valid frame. */
3454 ieee80211_free_txskb(hw, skb);
3457 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3459 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3460 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3461 ieee80211_queue_work(wl->hw, &wl->tx_work);
3463 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3467 static void b43_qos_params_upload(struct b43_wldev *dev,
3468 const struct ieee80211_tx_queue_params *p,
3471 u16 params[B43_NR_QOSPARAMS];
3475 if (!dev->qos_enabled)
3478 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3480 memset(¶ms, 0, sizeof(params));
3482 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3483 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3484 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3485 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3486 params[B43_QOSPARAM_AIFS] = p->aifs;
3487 params[B43_QOSPARAM_BSLOTS] = bslots;
3488 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3490 for (i = 0; i < ARRAY_SIZE(params); i++) {
3491 if (i == B43_QOSPARAM_STATUS) {
3492 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3493 shm_offset + (i * 2));
3494 /* Mark the parameters as updated. */
3496 b43_shm_write16(dev, B43_SHM_SHARED,
3497 shm_offset + (i * 2),
3500 b43_shm_write16(dev, B43_SHM_SHARED,
3501 shm_offset + (i * 2),
3507 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3508 static const u16 b43_qos_shm_offsets[] = {
3509 /* [mac80211-queue-nr] = SHM_OFFSET, */
3510 [0] = B43_QOS_VOICE,
3511 [1] = B43_QOS_VIDEO,
3512 [2] = B43_QOS_BESTEFFORT,
3513 [3] = B43_QOS_BACKGROUND,
3516 /* Update all QOS parameters in hardware. */
3517 static void b43_qos_upload_all(struct b43_wldev *dev)
3519 struct b43_wl *wl = dev->wl;
3520 struct b43_qos_params *params;
3523 if (!dev->qos_enabled)
3526 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3527 ARRAY_SIZE(wl->qos_params));
3529 b43_mac_suspend(dev);
3530 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3531 params = &(wl->qos_params[i]);
3532 b43_qos_params_upload(dev, &(params->p),
3533 b43_qos_shm_offsets[i]);
3535 b43_mac_enable(dev);
3538 static void b43_qos_clear(struct b43_wl *wl)
3540 struct b43_qos_params *params;
3543 /* Initialize QoS parameters to sane defaults. */
3545 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3546 ARRAY_SIZE(wl->qos_params));
3548 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3549 params = &(wl->qos_params[i]);
3551 switch (b43_qos_shm_offsets[i]) {
3555 params->p.cw_min = 0x0001;
3556 params->p.cw_max = 0x0001;
3561 params->p.cw_min = 0x0001;
3562 params->p.cw_max = 0x0001;
3564 case B43_QOS_BESTEFFORT:
3567 params->p.cw_min = 0x0001;
3568 params->p.cw_max = 0x03FF;
3570 case B43_QOS_BACKGROUND:
3573 params->p.cw_min = 0x0001;
3574 params->p.cw_max = 0x03FF;
3582 /* Initialize the core's QOS capabilities */
3583 static void b43_qos_init(struct b43_wldev *dev)
3585 if (!dev->qos_enabled) {
3586 /* Disable QOS support. */
3587 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3588 b43_write16(dev, B43_MMIO_IFSCTL,
3589 b43_read16(dev, B43_MMIO_IFSCTL)
3590 & ~B43_MMIO_IFSCTL_USE_EDCF);
3591 b43dbg(dev->wl, "QoS disabled\n");
3595 /* Upload the current QOS parameters. */
3596 b43_qos_upload_all(dev);
3598 /* Enable QOS support. */
3599 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3600 b43_write16(dev, B43_MMIO_IFSCTL,
3601 b43_read16(dev, B43_MMIO_IFSCTL)
3602 | B43_MMIO_IFSCTL_USE_EDCF);
3603 b43dbg(dev->wl, "QoS enabled\n");
3606 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3607 struct ieee80211_vif *vif, u16 _queue,
3608 const struct ieee80211_tx_queue_params *params)
3610 struct b43_wl *wl = hw_to_b43_wl(hw);
3611 struct b43_wldev *dev;
3612 unsigned int queue = (unsigned int)_queue;
3615 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3616 /* Queue not available or don't support setting
3617 * params on this queue. Return success to not
3618 * confuse mac80211. */
3621 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3622 ARRAY_SIZE(wl->qos_params));
3624 mutex_lock(&wl->mutex);
3625 dev = wl->current_dev;
3626 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3629 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3630 b43_mac_suspend(dev);
3631 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3632 b43_qos_shm_offsets[queue]);
3633 b43_mac_enable(dev);
3637 mutex_unlock(&wl->mutex);
3642 static int b43_op_get_stats(struct ieee80211_hw *hw,
3643 struct ieee80211_low_level_stats *stats)
3645 struct b43_wl *wl = hw_to_b43_wl(hw);
3647 mutex_lock(&wl->mutex);
3648 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3649 mutex_unlock(&wl->mutex);
3654 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3656 struct b43_wl *wl = hw_to_b43_wl(hw);
3657 struct b43_wldev *dev;
3660 mutex_lock(&wl->mutex);
3661 dev = wl->current_dev;
3663 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3664 b43_tsf_read(dev, &tsf);
3668 mutex_unlock(&wl->mutex);
3673 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3674 struct ieee80211_vif *vif, u64 tsf)
3676 struct b43_wl *wl = hw_to_b43_wl(hw);
3677 struct b43_wldev *dev;
3679 mutex_lock(&wl->mutex);
3680 dev = wl->current_dev;
3682 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3683 b43_tsf_write(dev, tsf);
3685 mutex_unlock(&wl->mutex);
3688 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3692 switch (dev->dev->bus_type) {
3693 #ifdef CONFIG_B43_BCMA
3696 "Putting PHY into reset not supported on BCMA\n");
3699 #ifdef CONFIG_B43_SSB
3701 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3702 tmp &= ~B43_TMSLOW_GMODE;
3703 tmp |= B43_TMSLOW_PHYRESET;
3704 tmp |= SSB_TMSLOW_FGC;
3705 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3708 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3709 tmp &= ~SSB_TMSLOW_FGC;
3710 tmp |= B43_TMSLOW_PHYRESET;
3711 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3719 static const char *band_to_string(enum ieee80211_band band)
3722 case IEEE80211_BAND_5GHZ:
3724 case IEEE80211_BAND_2GHZ:
3733 /* Expects wl->mutex locked */
3734 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3736 struct b43_wldev *up_dev = NULL;
3737 struct b43_wldev *down_dev;
3738 struct b43_wldev *d;
3740 bool uninitialized_var(gmode);
3743 /* Find a device and PHY which supports the band. */
3744 list_for_each_entry(d, &wl->devlist, list) {
3745 switch (chan->band) {
3746 case IEEE80211_BAND_5GHZ:
3747 if (d->phy.supports_5ghz) {
3752 case IEEE80211_BAND_2GHZ:
3753 if (d->phy.supports_2ghz) {
3766 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3767 band_to_string(chan->band));
3770 if ((up_dev == wl->current_dev) &&
3771 (!!wl->current_dev->phy.gmode == !!gmode)) {
3772 /* This device is already running. */
3775 b43dbg(wl, "Switching to %s-GHz band\n",
3776 band_to_string(chan->band));
3777 down_dev = wl->current_dev;
3779 prev_status = b43_status(down_dev);
3780 /* Shutdown the currently running core. */
3781 if (prev_status >= B43_STAT_STARTED)
3782 down_dev = b43_wireless_core_stop(down_dev);
3783 if (prev_status >= B43_STAT_INITIALIZED)
3784 b43_wireless_core_exit(down_dev);
3786 if (down_dev != up_dev) {
3787 /* We switch to a different core, so we put PHY into
3788 * RESET on the old core. */
3789 b43_put_phy_into_reset(down_dev);
3792 /* Now start the new core. */
3793 up_dev->phy.gmode = gmode;
3794 if (prev_status >= B43_STAT_INITIALIZED) {
3795 err = b43_wireless_core_init(up_dev);
3797 b43err(wl, "Fatal: Could not initialize device for "
3798 "selected %s-GHz band\n",
3799 band_to_string(chan->band));
3803 if (prev_status >= B43_STAT_STARTED) {
3804 err = b43_wireless_core_start(up_dev);
3806 b43err(wl, "Fatal: Could not start device for "
3807 "selected %s-GHz band\n",
3808 band_to_string(chan->band));
3809 b43_wireless_core_exit(up_dev);
3813 B43_WARN_ON(b43_status(up_dev) != prev_status);
3815 wl->current_dev = up_dev;
3819 /* Whoops, failed to init the new core. No core is operating now. */
3820 wl->current_dev = NULL;
3824 /* Write the short and long frame retry limit values. */
3825 static void b43_set_retry_limits(struct b43_wldev *dev,
3826 unsigned int short_retry,
3827 unsigned int long_retry)
3829 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3830 * the chip-internal counter. */
3831 short_retry = min(short_retry, (unsigned int)0xF);
3832 long_retry = min(long_retry, (unsigned int)0xF);
3834 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3836 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3840 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3842 struct b43_wl *wl = hw_to_b43_wl(hw);
3843 struct b43_wldev *dev;
3844 struct b43_phy *phy;
3845 struct ieee80211_conf *conf = &hw->conf;
3848 bool reload_bss = false;
3850 mutex_lock(&wl->mutex);
3852 dev = wl->current_dev;
3854 /* Switch the band (if necessary). This might change the active core. */
3855 err = b43_switch_band(wl, conf->channel);
3857 goto out_unlock_mutex;
3859 /* Need to reload all settings if the core changed */
3860 if (dev != wl->current_dev) {
3861 dev = wl->current_dev;
3868 if (conf_is_ht(conf))
3870 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3872 phy->is_40mhz = false;
3874 b43_mac_suspend(dev);
3876 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3877 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3878 conf->long_frame_max_tx_count);
3879 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3881 goto out_mac_enable;
3883 /* Switch to the requested channel.
3884 * The firmware takes care of races with the TX handler. */
3885 if (conf->channel->hw_value != phy->channel)
3886 b43_switch_channel(dev, conf->channel->hw_value);
3888 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3890 /* Adjust the desired TX power level. */
3891 if (conf->power_level != 0) {
3892 if (conf->power_level != phy->desired_txpower) {
3893 phy->desired_txpower = conf->power_level;
3894 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3895 B43_TXPWR_IGNORE_TSSI);
3899 /* Antennas for RX and management frame TX. */
3900 antenna = B43_ANTENNA_DEFAULT;
3901 b43_mgmtframe_txantenna(dev, antenna);
3902 antenna = B43_ANTENNA_DEFAULT;
3903 if (phy->ops->set_rx_antenna)
3904 phy->ops->set_rx_antenna(dev, antenna);
3906 if (wl->radio_enabled != phy->radio_on) {
3907 if (wl->radio_enabled) {
3908 b43_software_rfkill(dev, false);
3909 b43info(dev->wl, "Radio turned on by software\n");
3910 if (!dev->radio_hw_enable) {
3911 b43info(dev->wl, "The hardware RF-kill button "
3912 "still turns the radio physically off. "
3913 "Press the button to turn it on.\n");
3916 b43_software_rfkill(dev, true);
3917 b43info(dev->wl, "Radio turned off by software\n");
3922 b43_mac_enable(dev);
3924 mutex_unlock(&wl->mutex);
3926 if (wl->vif && reload_bss)
3927 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3932 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3934 struct ieee80211_supported_band *sband =
3935 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3936 struct ieee80211_rate *rate;
3938 u16 basic, direct, offset, basic_offset, rateptr;
3940 for (i = 0; i < sband->n_bitrates; i++) {
3941 rate = &sband->bitrates[i];
3943 if (b43_is_cck_rate(rate->hw_value)) {
3944 direct = B43_SHM_SH_CCKDIRECT;
3945 basic = B43_SHM_SH_CCKBASIC;
3946 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3949 direct = B43_SHM_SH_OFDMDIRECT;
3950 basic = B43_SHM_SH_OFDMBASIC;
3951 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3955 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3957 if (b43_is_cck_rate(rate->hw_value)) {
3958 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3959 basic_offset &= 0xF;
3961 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3962 basic_offset &= 0xF;
3966 * Get the pointer that we need to point to
3967 * from the direct map
3969 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3970 direct + 2 * basic_offset);
3971 /* and write it to the basic map */
3972 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3977 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3978 struct ieee80211_vif *vif,
3979 struct ieee80211_bss_conf *conf,
3982 struct b43_wl *wl = hw_to_b43_wl(hw);
3983 struct b43_wldev *dev;
3985 mutex_lock(&wl->mutex);
3987 dev = wl->current_dev;
3988 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3989 goto out_unlock_mutex;
3991 B43_WARN_ON(wl->vif != vif);
3993 if (changed & BSS_CHANGED_BSSID) {
3995 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3997 memset(wl->bssid, 0, ETH_ALEN);
4000 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4001 if (changed & BSS_CHANGED_BEACON &&
4002 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4003 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4004 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4005 b43_update_templates(wl);
4007 if (changed & BSS_CHANGED_BSSID)
4008 b43_write_mac_bssid_templates(dev);
4011 b43_mac_suspend(dev);
4013 /* Update templates for AP/mesh mode. */
4014 if (changed & BSS_CHANGED_BEACON_INT &&
4015 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4016 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4017 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4019 b43_set_beacon_int(dev, conf->beacon_int);
4021 if (changed & BSS_CHANGED_BASIC_RATES)
4022 b43_update_basic_rates(dev, conf->basic_rates);
4024 if (changed & BSS_CHANGED_ERP_SLOT) {
4025 if (conf->use_short_slot)
4026 b43_short_slot_timing_enable(dev);
4028 b43_short_slot_timing_disable(dev);
4031 b43_mac_enable(dev);
4033 mutex_unlock(&wl->mutex);
4036 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4037 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4038 struct ieee80211_key_conf *key)
4040 struct b43_wl *wl = hw_to_b43_wl(hw);
4041 struct b43_wldev *dev;
4045 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4047 if (modparam_nohwcrypt)
4048 return -ENOSPC; /* User disabled HW-crypto */
4050 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4051 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4052 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4053 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4054 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4056 * For now, disable hw crypto for the RSN IBSS group keys. This
4057 * could be optimized in the future, but until that gets
4058 * implemented, use of software crypto for group addressed
4059 * frames is a acceptable to allow RSN IBSS to be used.
4064 mutex_lock(&wl->mutex);
4066 dev = wl->current_dev;
4068 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4071 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4072 /* We don't have firmware for the crypto engine.
4073 * Must use software-crypto. */
4079 switch (key->cipher) {
4080 case WLAN_CIPHER_SUITE_WEP40:
4081 algorithm = B43_SEC_ALGO_WEP40;
4083 case WLAN_CIPHER_SUITE_WEP104:
4084 algorithm = B43_SEC_ALGO_WEP104;
4086 case WLAN_CIPHER_SUITE_TKIP:
4087 algorithm = B43_SEC_ALGO_TKIP;
4089 case WLAN_CIPHER_SUITE_CCMP:
4090 algorithm = B43_SEC_ALGO_AES;
4096 index = (u8) (key->keyidx);
4102 if (algorithm == B43_SEC_ALGO_TKIP &&
4103 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4104 !modparam_hwtkip)) {
4105 /* We support only pairwise key */
4110 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4111 if (WARN_ON(!sta)) {
4115 /* Pairwise key with an assigned MAC address. */
4116 err = b43_key_write(dev, -1, algorithm,
4117 key->key, key->keylen,
4121 err = b43_key_write(dev, index, algorithm,
4122 key->key, key->keylen, NULL, key);
4127 if (algorithm == B43_SEC_ALGO_WEP40 ||
4128 algorithm == B43_SEC_ALGO_WEP104) {
4129 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4132 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4134 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4135 if (algorithm == B43_SEC_ALGO_TKIP)
4136 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4139 err = b43_key_clear(dev, key->hw_key_idx);
4150 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4152 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4153 sta ? sta->addr : bcast_addr);
4154 b43_dump_keymemory(dev);
4156 mutex_unlock(&wl->mutex);
4161 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4162 unsigned int changed, unsigned int *fflags,
4165 struct b43_wl *wl = hw_to_b43_wl(hw);
4166 struct b43_wldev *dev;
4168 mutex_lock(&wl->mutex);
4169 dev = wl->current_dev;
4175 *fflags &= FIF_PROMISC_IN_BSS |
4181 FIF_BCN_PRBRESP_PROMISC;
4183 changed &= FIF_PROMISC_IN_BSS |
4189 FIF_BCN_PRBRESP_PROMISC;
4191 wl->filter_flags = *fflags;
4193 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4194 b43_adjust_opmode(dev);
4197 mutex_unlock(&wl->mutex);
4200 /* Locking: wl->mutex
4201 * Returns the current dev. This might be different from the passed in dev,
4202 * because the core might be gone away while we unlocked the mutex. */
4203 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4206 struct b43_wldev *orig_dev;
4214 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4217 /* Cancel work. Unlock to avoid deadlocks. */
4218 mutex_unlock(&wl->mutex);
4219 cancel_delayed_work_sync(&dev->periodic_work);
4220 cancel_work_sync(&wl->tx_work);
4221 mutex_lock(&wl->mutex);
4222 dev = wl->current_dev;
4223 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4224 /* Whoops, aliens ate up the device while we were unlocked. */
4228 /* Disable interrupts on the device. */
4229 b43_set_status(dev, B43_STAT_INITIALIZED);
4230 if (b43_bus_host_is_sdio(dev->dev)) {
4231 /* wl->mutex is locked. That is enough. */
4232 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4233 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4235 spin_lock_irq(&wl->hardirq_lock);
4236 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4237 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4238 spin_unlock_irq(&wl->hardirq_lock);
4240 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4242 mutex_unlock(&wl->mutex);
4243 if (b43_bus_host_is_sdio(dev->dev)) {
4244 b43_sdio_free_irq(dev);
4246 synchronize_irq(dev->dev->irq);
4247 free_irq(dev->dev->irq, dev);
4249 mutex_lock(&wl->mutex);
4250 dev = wl->current_dev;
4253 if (dev != orig_dev) {
4254 if (b43_status(dev) >= B43_STAT_STARTED)
4258 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4259 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4261 /* Drain all TX queues. */
4262 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4263 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4264 struct sk_buff *skb;
4266 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4267 ieee80211_free_txskb(wl->hw, skb);
4271 b43_mac_suspend(dev);
4273 b43dbg(wl, "Wireless interface stopped\n");
4278 /* Locking: wl->mutex */
4279 static int b43_wireless_core_start(struct b43_wldev *dev)
4283 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4285 drain_txstatus_queue(dev);
4286 if (b43_bus_host_is_sdio(dev->dev)) {
4287 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4289 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4293 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4294 b43_interrupt_thread_handler,
4295 IRQF_SHARED, KBUILD_MODNAME, dev);
4297 b43err(dev->wl, "Cannot request IRQ-%d\n",
4303 /* We are ready to run. */
4304 ieee80211_wake_queues(dev->wl->hw);
4305 b43_set_status(dev, B43_STAT_STARTED);
4307 /* Start data flow (TX/RX). */
4308 b43_mac_enable(dev);
4309 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4311 /* Start maintenance work */
4312 b43_periodic_tasks_setup(dev);
4316 b43dbg(dev->wl, "Wireless interface started\n");
4321 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4332 case B43_PHYTYPE_LP:
4334 case B43_PHYTYPE_SSLPN:
4336 case B43_PHYTYPE_HT:
4338 case B43_PHYTYPE_LCN:
4340 case B43_PHYTYPE_LCNXN:
4342 case B43_PHYTYPE_LCN40:
4344 case B43_PHYTYPE_AC:
4350 /* Get PHY and RADIO versioning numbers */
4351 static int b43_phy_versioning(struct b43_wldev *dev)
4353 struct b43_phy *phy = &dev->phy;
4361 int unsupported = 0;
4363 /* Get PHY versioning */
4364 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4365 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4366 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4367 phy_rev = (tmp & B43_PHYVER_VERSION);
4374 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4382 #ifdef CONFIG_B43_PHY_N
4388 #ifdef CONFIG_B43_PHY_LP
4389 case B43_PHYTYPE_LP:
4394 #ifdef CONFIG_B43_PHY_HT
4395 case B43_PHYTYPE_HT:
4400 #ifdef CONFIG_B43_PHY_LCN
4401 case B43_PHYTYPE_LCN:
4410 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4411 analog_type, phy_type, b43_phy_name(dev, phy_type),
4415 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4416 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4418 /* Get RADIO versioning */
4419 if (dev->dev->core_rev >= 24) {
4422 for (tmp = 0; tmp < 3; tmp++) {
4423 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4424 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4427 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4428 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4430 radio_manuf = 0x17F;
4431 radio_ver = (radio24[2] << 8) | radio24[1];
4432 radio_rev = (radio24[0] & 0xF);
4434 if (dev->dev->chip_id == 0x4317) {
4435 if (dev->dev->chip_rev == 0)
4437 else if (dev->dev->chip_rev == 1)
4442 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4444 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4445 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4447 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4450 radio_manuf = (tmp & 0x00000FFF);
4451 radio_ver = (tmp & 0x0FFFF000) >> 12;
4452 radio_rev = (tmp & 0xF0000000) >> 28;
4455 if (radio_manuf != 0x17F /* Broadcom */)
4459 if (radio_ver != 0x2060)
4463 if (radio_manuf != 0x17F)
4467 if ((radio_ver & 0xFFF0) != 0x2050)
4471 if (radio_ver != 0x2050)
4475 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4478 case B43_PHYTYPE_LP:
4479 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4482 case B43_PHYTYPE_HT:
4483 if (radio_ver != 0x2059)
4486 case B43_PHYTYPE_LCN:
4487 if (radio_ver != 0x2064)
4494 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4495 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4496 radio_manuf, radio_ver, radio_rev);
4499 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4500 radio_manuf, radio_ver, radio_rev);
4502 phy->radio_manuf = radio_manuf;
4503 phy->radio_ver = radio_ver;
4504 phy->radio_rev = radio_rev;
4506 phy->analog = analog_type;
4507 phy->type = phy_type;
4513 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4514 struct b43_phy *phy)
4516 phy->hardware_power_control = !!modparam_hwpctl;
4517 phy->next_txpwr_check_time = jiffies;
4518 /* PHY TX errors counter. */
4519 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4522 phy->phy_locked = false;
4523 phy->radio_locked = false;
4527 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4529 dev->dfq_valid = false;
4531 /* Assume the radio is enabled. If it's not enabled, the state will
4532 * immediately get fixed on the first periodic work run. */
4533 dev->radio_hw_enable = true;
4536 memset(&dev->stats, 0, sizeof(dev->stats));
4538 setup_struct_phy_for_init(dev, &dev->phy);
4540 /* IRQ related flags */
4541 dev->irq_reason = 0;
4542 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4543 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4544 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4545 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4547 dev->mac_suspended = 1;
4549 /* Noise calculation context */
4550 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4553 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4555 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4558 if (!modparam_btcoex)
4560 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4562 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4565 hf = b43_hf_read(dev);
4566 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4567 hf |= B43_HF_BTCOEXALT;
4569 hf |= B43_HF_BTCOEX;
4570 b43_hf_write(dev, hf);
4573 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4575 if (!modparam_btcoex)
4580 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4582 struct ssb_bus *bus;
4585 if (dev->dev->bus_type != B43_BUS_SSB)
4588 bus = dev->dev->sdev->bus;
4590 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4591 (bus->chip_id == 0x4312)) {
4592 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4593 tmp &= ~SSB_IMCFGLO_REQTO;
4594 tmp &= ~SSB_IMCFGLO_SERTO;
4596 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4597 ssb_commit_settings(bus);
4601 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4605 /* The time value is in microseconds. */
4606 if (dev->phy.type == B43_PHYTYPE_A)
4610 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4612 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4613 pu_delay = max(pu_delay, (u16)2400);
4615 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4618 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4619 static void b43_set_pretbtt(struct b43_wldev *dev)
4623 /* The time value is in microseconds. */
4624 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4627 if (dev->phy.type == B43_PHYTYPE_A)
4632 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4633 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4636 /* Shutdown a wireless core */
4637 /* Locking: wl->mutex */
4638 static void b43_wireless_core_exit(struct b43_wldev *dev)
4640 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4641 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4644 /* Unregister HW RNG driver */
4645 b43_rng_exit(dev->wl);
4647 b43_set_status(dev, B43_STAT_UNINIT);
4649 /* Stop the microcode PSM. */
4650 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4651 B43_MACCTL_PSM_JMP0);
4656 dev->phy.ops->switch_analog(dev, 0);
4657 if (dev->wl->current_beacon) {
4658 dev_kfree_skb_any(dev->wl->current_beacon);
4659 dev->wl->current_beacon = NULL;
4662 b43_device_disable(dev, 0);
4663 b43_bus_may_powerdown(dev);
4666 /* Initialize a wireless core */
4667 static int b43_wireless_core_init(struct b43_wldev *dev)
4669 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4670 struct b43_phy *phy = &dev->phy;
4674 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4676 err = b43_bus_powerup(dev, 0);
4679 if (!b43_device_is_enabled(dev))
4680 b43_wireless_core_reset(dev, phy->gmode);
4682 /* Reset all data structures. */
4683 setup_struct_wldev_for_init(dev);
4684 phy->ops->prepare_structs(dev);
4686 /* Enable IRQ routing to this device. */
4687 switch (dev->dev->bus_type) {
4688 #ifdef CONFIG_B43_BCMA
4690 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4691 dev->dev->bdev, true);
4694 #ifdef CONFIG_B43_SSB
4696 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4702 b43_imcfglo_timeouts_workaround(dev);
4703 b43_bluetooth_coext_disable(dev);
4704 if (phy->ops->prepare_hardware) {
4705 err = phy->ops->prepare_hardware(dev);
4709 err = b43_chip_init(dev);
4712 b43_shm_write16(dev, B43_SHM_SHARED,
4713 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4714 hf = b43_hf_read(dev);
4715 if (phy->type == B43_PHYTYPE_G) {
4719 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4720 hf |= B43_HF_OFDMPABOOST;
4722 if (phy->radio_ver == 0x2050) {
4723 if (phy->radio_rev == 6)
4724 hf |= B43_HF_4318TSSI;
4725 if (phy->radio_rev < 6)
4726 hf |= B43_HF_VCORECALC;
4728 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4729 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4730 #ifdef CONFIG_SSB_DRIVER_PCICORE
4731 if (dev->dev->bus_type == B43_BUS_SSB &&
4732 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4733 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4734 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4736 hf &= ~B43_HF_SKCFPUP;
4737 b43_hf_write(dev, hf);
4739 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4740 B43_DEFAULT_LONG_RETRY_LIMIT);
4741 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4742 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4744 /* Disable sending probe responses from firmware.
4745 * Setting the MaxTime to one usec will always trigger
4746 * a timeout, so we never send any probe resp.
4747 * A timeout of zero is infinite. */
4748 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4750 b43_rate_memory_init(dev);
4751 b43_set_phytxctl_defaults(dev);
4753 /* Minimum Contention Window */
4754 if (phy->type == B43_PHYTYPE_B)
4755 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4757 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4758 /* Maximum Contention Window */
4759 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4761 if (b43_bus_host_is_pcmcia(dev->dev) ||
4762 b43_bus_host_is_sdio(dev->dev)) {
4763 dev->__using_pio_transfers = true;
4764 err = b43_pio_init(dev);
4765 } else if (dev->use_pio) {
4766 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4767 "This should not be needed and will result in lower "
4769 dev->__using_pio_transfers = true;
4770 err = b43_pio_init(dev);
4772 dev->__using_pio_transfers = false;
4773 err = b43_dma_init(dev);
4778 b43_set_synth_pu_delay(dev, 1);
4779 b43_bluetooth_coext_enable(dev);
4781 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4782 b43_upload_card_macaddress(dev);
4783 b43_security_init(dev);
4785 ieee80211_wake_queues(dev->wl->hw);
4787 b43_set_status(dev, B43_STAT_INITIALIZED);
4789 /* Register HW RNG driver */
4790 b43_rng_init(dev->wl);
4798 b43_bus_may_powerdown(dev);
4799 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4803 static int b43_op_add_interface(struct ieee80211_hw *hw,
4804 struct ieee80211_vif *vif)
4806 struct b43_wl *wl = hw_to_b43_wl(hw);
4807 struct b43_wldev *dev;
4808 int err = -EOPNOTSUPP;
4810 /* TODO: allow WDS/AP devices to coexist */
4812 if (vif->type != NL80211_IFTYPE_AP &&
4813 vif->type != NL80211_IFTYPE_MESH_POINT &&
4814 vif->type != NL80211_IFTYPE_STATION &&
4815 vif->type != NL80211_IFTYPE_WDS &&
4816 vif->type != NL80211_IFTYPE_ADHOC)
4819 mutex_lock(&wl->mutex);
4821 goto out_mutex_unlock;
4823 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4825 dev = wl->current_dev;
4826 wl->operating = true;
4828 wl->if_type = vif->type;
4829 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4831 b43_adjust_opmode(dev);
4832 b43_set_pretbtt(dev);
4833 b43_set_synth_pu_delay(dev, 0);
4834 b43_upload_card_macaddress(dev);
4838 mutex_unlock(&wl->mutex);
4841 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4846 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4847 struct ieee80211_vif *vif)
4849 struct b43_wl *wl = hw_to_b43_wl(hw);
4850 struct b43_wldev *dev = wl->current_dev;
4852 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4854 mutex_lock(&wl->mutex);
4856 B43_WARN_ON(!wl->operating);
4857 B43_WARN_ON(wl->vif != vif);
4860 wl->operating = false;
4862 b43_adjust_opmode(dev);
4863 memset(wl->mac_addr, 0, ETH_ALEN);
4864 b43_upload_card_macaddress(dev);
4866 mutex_unlock(&wl->mutex);
4869 static int b43_op_start(struct ieee80211_hw *hw)
4871 struct b43_wl *wl = hw_to_b43_wl(hw);
4872 struct b43_wldev *dev = wl->current_dev;
4876 /* Kill all old instance specific information to make sure
4877 * the card won't use it in the short timeframe between start
4878 * and mac80211 reconfiguring it. */
4879 memset(wl->bssid, 0, ETH_ALEN);
4880 memset(wl->mac_addr, 0, ETH_ALEN);
4881 wl->filter_flags = 0;
4882 wl->radiotap_enabled = false;
4884 wl->beacon0_uploaded = false;
4885 wl->beacon1_uploaded = false;
4886 wl->beacon_templates_virgin = true;
4887 wl->radio_enabled = true;
4889 mutex_lock(&wl->mutex);
4891 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4892 err = b43_wireless_core_init(dev);
4894 goto out_mutex_unlock;
4898 if (b43_status(dev) < B43_STAT_STARTED) {
4899 err = b43_wireless_core_start(dev);
4902 b43_wireless_core_exit(dev);
4903 goto out_mutex_unlock;
4907 /* XXX: only do if device doesn't support rfkill irq */
4908 wiphy_rfkill_start_polling(hw->wiphy);
4911 mutex_unlock(&wl->mutex);
4914 * Configuration may have been overwritten during initialization.
4915 * Reload the configuration, but only if initialization was
4916 * successful. Reloading the configuration after a failed init
4917 * may hang the system.
4920 b43_op_config(hw, ~0);
4925 static void b43_op_stop(struct ieee80211_hw *hw)
4927 struct b43_wl *wl = hw_to_b43_wl(hw);
4928 struct b43_wldev *dev = wl->current_dev;
4930 cancel_work_sync(&(wl->beacon_update_trigger));
4935 mutex_lock(&wl->mutex);
4936 if (b43_status(dev) >= B43_STAT_STARTED) {
4937 dev = b43_wireless_core_stop(dev);
4941 b43_wireless_core_exit(dev);
4942 wl->radio_enabled = false;
4945 mutex_unlock(&wl->mutex);
4947 cancel_work_sync(&(wl->txpower_adjust_work));
4950 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4951 struct ieee80211_sta *sta, bool set)
4953 struct b43_wl *wl = hw_to_b43_wl(hw);
4955 /* FIXME: add locking */
4956 b43_update_templates(wl);
4961 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4962 struct ieee80211_vif *vif,
4963 enum sta_notify_cmd notify_cmd,
4964 struct ieee80211_sta *sta)
4966 struct b43_wl *wl = hw_to_b43_wl(hw);
4968 B43_WARN_ON(!vif || wl->vif != vif);
4971 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4973 struct b43_wl *wl = hw_to_b43_wl(hw);
4974 struct b43_wldev *dev;
4976 mutex_lock(&wl->mutex);
4977 dev = wl->current_dev;
4978 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4979 /* Disable CFP update during scan on other channels. */
4980 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4982 mutex_unlock(&wl->mutex);
4985 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4987 struct b43_wl *wl = hw_to_b43_wl(hw);
4988 struct b43_wldev *dev;
4990 mutex_lock(&wl->mutex);
4991 dev = wl->current_dev;
4992 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4993 /* Re-enable CFP update. */
4994 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4996 mutex_unlock(&wl->mutex);
4999 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5000 struct survey_info *survey)
5002 struct b43_wl *wl = hw_to_b43_wl(hw);
5003 struct b43_wldev *dev = wl->current_dev;
5004 struct ieee80211_conf *conf = &hw->conf;
5009 survey->channel = conf->channel;
5010 survey->filled = SURVEY_INFO_NOISE_DBM;
5011 survey->noise = dev->stats.link_noise;
5016 static const struct ieee80211_ops b43_hw_ops = {
5018 .conf_tx = b43_op_conf_tx,
5019 .add_interface = b43_op_add_interface,
5020 .remove_interface = b43_op_remove_interface,
5021 .config = b43_op_config,
5022 .bss_info_changed = b43_op_bss_info_changed,
5023 .configure_filter = b43_op_configure_filter,
5024 .set_key = b43_op_set_key,
5025 .update_tkip_key = b43_op_update_tkip_key,
5026 .get_stats = b43_op_get_stats,
5027 .get_tsf = b43_op_get_tsf,
5028 .set_tsf = b43_op_set_tsf,
5029 .start = b43_op_start,
5030 .stop = b43_op_stop,
5031 .set_tim = b43_op_beacon_set_tim,
5032 .sta_notify = b43_op_sta_notify,
5033 .sw_scan_start = b43_op_sw_scan_start_notifier,
5034 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
5035 .get_survey = b43_op_get_survey,
5036 .rfkill_poll = b43_rfkill_poll,
5039 /* Hard-reset the chip. Do not call this directly.
5040 * Use b43_controller_restart()
5042 static void b43_chip_reset(struct work_struct *work)
5044 struct b43_wldev *dev =
5045 container_of(work, struct b43_wldev, restart_work);
5046 struct b43_wl *wl = dev->wl;
5050 mutex_lock(&wl->mutex);
5052 prev_status = b43_status(dev);
5053 /* Bring the device down... */
5054 if (prev_status >= B43_STAT_STARTED) {
5055 dev = b43_wireless_core_stop(dev);
5061 if (prev_status >= B43_STAT_INITIALIZED)
5062 b43_wireless_core_exit(dev);
5064 /* ...and up again. */
5065 if (prev_status >= B43_STAT_INITIALIZED) {
5066 err = b43_wireless_core_init(dev);
5070 if (prev_status >= B43_STAT_STARTED) {
5071 err = b43_wireless_core_start(dev);
5073 b43_wireless_core_exit(dev);
5079 wl->current_dev = NULL; /* Failed to init the dev. */
5080 mutex_unlock(&wl->mutex);
5083 b43err(wl, "Controller restart FAILED\n");
5087 /* reload configuration */
5088 b43_op_config(wl->hw, ~0);
5090 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5092 b43info(wl, "Controller restarted\n");
5095 static int b43_setup_bands(struct b43_wldev *dev,
5096 bool have_2ghz_phy, bool have_5ghz_phy)
5098 struct ieee80211_hw *hw = dev->wl->hw;
5101 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5102 if (dev->phy.type == B43_PHYTYPE_N) {
5104 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5107 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5110 dev->phy.supports_2ghz = have_2ghz_phy;
5111 dev->phy.supports_5ghz = have_5ghz_phy;
5116 static void b43_wireless_core_detach(struct b43_wldev *dev)
5118 /* We release firmware that late to not be required to re-request
5119 * is all the time when we reinit the core. */
5120 b43_release_firmware(dev);
5124 static int b43_wireless_core_attach(struct b43_wldev *dev)
5126 struct b43_wl *wl = dev->wl;
5127 struct pci_dev *pdev = NULL;
5130 bool have_2ghz_phy = false, have_5ghz_phy = false;
5132 /* Do NOT do any device initialization here.
5133 * Do it in wireless_core_init() instead.
5134 * This function is for gathering basic information about the HW, only.
5135 * Also some structs may be set up here. But most likely you want to have
5136 * that in core_init(), too.
5139 #ifdef CONFIG_B43_SSB
5140 if (dev->dev->bus_type == B43_BUS_SSB &&
5141 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5142 pdev = dev->dev->sdev->bus->host_pci;
5145 err = b43_bus_powerup(dev, 0);
5147 b43err(wl, "Bus powerup failed\n");
5151 /* Get the PHY type. */
5152 switch (dev->dev->bus_type) {
5153 #ifdef CONFIG_B43_BCMA
5155 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5156 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5157 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5160 #ifdef CONFIG_B43_SSB
5162 if (dev->dev->core_rev >= 5) {
5163 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5164 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5165 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5172 dev->phy.gmode = have_2ghz_phy;
5173 dev->phy.radio_on = true;
5174 b43_wireless_core_reset(dev, dev->phy.gmode);
5176 err = b43_phy_versioning(dev);
5179 /* Check if this device supports multiband. */
5181 (pdev->device != 0x4312 &&
5182 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5183 /* No multiband support. */
5184 have_2ghz_phy = false;
5185 have_5ghz_phy = false;
5186 switch (dev->phy.type) {
5188 have_5ghz_phy = true;
5190 case B43_PHYTYPE_LP: //FIXME not always!
5191 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5196 case B43_PHYTYPE_HT:
5197 case B43_PHYTYPE_LCN:
5198 have_2ghz_phy = true;
5204 if (dev->phy.type == B43_PHYTYPE_A) {
5206 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5210 if (1 /* disable A-PHY */) {
5211 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5212 if (dev->phy.type != B43_PHYTYPE_N &&
5213 dev->phy.type != B43_PHYTYPE_LP) {
5214 have_2ghz_phy = true;
5215 have_5ghz_phy = false;
5219 err = b43_phy_allocate(dev);
5223 dev->phy.gmode = have_2ghz_phy;
5224 b43_wireless_core_reset(dev, dev->phy.gmode);
5226 err = b43_validate_chipaccess(dev);
5229 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5233 /* Now set some default "current_dev" */
5234 if (!wl->current_dev)
5235 wl->current_dev = dev;
5236 INIT_WORK(&dev->restart_work, b43_chip_reset);
5238 dev->phy.ops->switch_analog(dev, 0);
5239 b43_device_disable(dev, 0);
5240 b43_bus_may_powerdown(dev);
5248 b43_bus_may_powerdown(dev);
5252 static void b43_one_core_detach(struct b43_bus_dev *dev)
5254 struct b43_wldev *wldev;
5257 /* Do not cancel ieee80211-workqueue based work here.
5258 * See comment in b43_remove(). */
5260 wldev = b43_bus_get_wldev(dev);
5262 b43_debugfs_remove_device(wldev);
5263 b43_wireless_core_detach(wldev);
5264 list_del(&wldev->list);
5266 b43_bus_set_wldev(dev, NULL);
5270 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5272 struct b43_wldev *wldev;
5275 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5279 wldev->use_pio = b43_modparam_pio;
5282 b43_set_status(wldev, B43_STAT_UNINIT);
5283 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5284 INIT_LIST_HEAD(&wldev->list);
5286 err = b43_wireless_core_attach(wldev);
5288 goto err_kfree_wldev;
5290 list_add(&wldev->list, &wl->devlist);
5292 b43_bus_set_wldev(dev, wldev);
5293 b43_debugfs_add_device(wldev);
5303 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5304 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5305 (pdev->device == _device) && \
5306 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5307 (pdev->subsystem_device == _subdevice) )
5309 static void b43_sprom_fixup(struct ssb_bus *bus)
5311 struct pci_dev *pdev;
5313 /* boardflags workarounds */
5314 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5315 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5316 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5317 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5318 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5319 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5320 if (bus->bustype == SSB_BUSTYPE_PCI) {
5321 pdev = bus->host_pci;
5322 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5323 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5324 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5325 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5326 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5327 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5328 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5329 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5333 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5335 struct ieee80211_hw *hw = wl->hw;
5337 ssb_set_devtypedata(dev->sdev, NULL);
5338 ieee80211_free_hw(hw);
5341 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5343 struct ssb_sprom *sprom = dev->bus_sprom;
5344 struct ieee80211_hw *hw;
5349 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5351 b43err(NULL, "Could not allocate ieee80211 device\n");
5352 return ERR_PTR(-ENOMEM);
5354 wl = hw_to_b43_wl(hw);
5357 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5358 IEEE80211_HW_SIGNAL_DBM;
5360 hw->wiphy->interface_modes =
5361 BIT(NL80211_IFTYPE_AP) |
5362 BIT(NL80211_IFTYPE_MESH_POINT) |
5363 BIT(NL80211_IFTYPE_STATION) |
5364 BIT(NL80211_IFTYPE_WDS) |
5365 BIT(NL80211_IFTYPE_ADHOC);
5367 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5369 wl->hw_registred = false;
5371 SET_IEEE80211_DEV(hw, dev->dev);
5372 if (is_valid_ether_addr(sprom->et1mac))
5373 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5375 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5377 /* Initialize struct b43_wl */
5379 mutex_init(&wl->mutex);
5380 spin_lock_init(&wl->hardirq_lock);
5381 INIT_LIST_HEAD(&wl->devlist);
5382 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5383 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5384 INIT_WORK(&wl->tx_work, b43_tx_work);
5386 /* Initialize queues and flags. */
5387 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5388 skb_queue_head_init(&wl->tx_queue[queue_num]);
5389 wl->tx_queue_stopped[queue_num] = 0;
5392 snprintf(chip_name, ARRAY_SIZE(chip_name),
5393 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5394 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5399 #ifdef CONFIG_B43_BCMA
5400 static int b43_bcma_probe(struct bcma_device *core)
5402 struct b43_bus_dev *dev;
5406 dev = b43_bus_dev_bcma_init(core);
5410 wl = b43_wireless_init(dev);
5416 err = b43_one_core_attach(dev, wl);
5418 goto bcma_err_wireless_exit;
5420 /* setup and start work to load firmware */
5421 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5422 schedule_work(&wl->firmware_load);
5427 bcma_err_wireless_exit:
5428 ieee80211_free_hw(wl->hw);
5432 static void b43_bcma_remove(struct bcma_device *core)
5434 struct b43_wldev *wldev = bcma_get_drvdata(core);
5435 struct b43_wl *wl = wldev->wl;
5437 /* We must cancel any work here before unregistering from ieee80211,
5438 * as the ieee80211 unreg will destroy the workqueue. */
5439 cancel_work_sync(&wldev->restart_work);
5440 cancel_work_sync(&wl->firmware_load);
5443 if (!wldev->fw.ucode.data)
5444 return; /* NULL if firmware never loaded */
5445 if (wl->current_dev == wldev && wl->hw_registred) {
5446 b43_leds_stop(wldev);
5447 ieee80211_unregister_hw(wl->hw);
5450 b43_one_core_detach(wldev->dev);
5452 b43_leds_unregister(wl);
5454 ieee80211_free_hw(wl->hw);
5457 static struct bcma_driver b43_bcma_driver = {
5458 .name = KBUILD_MODNAME,
5459 .id_table = b43_bcma_tbl,
5460 .probe = b43_bcma_probe,
5461 .remove = b43_bcma_remove,
5465 #ifdef CONFIG_B43_SSB
5467 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5469 struct b43_bus_dev *dev;
5474 dev = b43_bus_dev_ssb_init(sdev);
5478 wl = ssb_get_devtypedata(sdev);
5480 /* Probing the first core. Must setup common struct b43_wl */
5482 b43_sprom_fixup(sdev->bus);
5483 wl = b43_wireless_init(dev);
5488 ssb_set_devtypedata(sdev, wl);
5489 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5491 err = b43_one_core_attach(dev, wl);
5493 goto err_wireless_exit;
5495 /* setup and start work to load firmware */
5496 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5497 schedule_work(&wl->firmware_load);
5504 b43_wireless_exit(dev, wl);
5508 static void b43_ssb_remove(struct ssb_device *sdev)
5510 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5511 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5512 struct b43_bus_dev *dev = wldev->dev;
5514 /* We must cancel any work here before unregistering from ieee80211,
5515 * as the ieee80211 unreg will destroy the workqueue. */
5516 cancel_work_sync(&wldev->restart_work);
5517 cancel_work_sync(&wl->firmware_load);
5520 if (!wldev->fw.ucode.data)
5521 return; /* NULL if firmware never loaded */
5522 if (wl->current_dev == wldev && wl->hw_registred) {
5523 b43_leds_stop(wldev);
5524 ieee80211_unregister_hw(wl->hw);
5527 b43_one_core_detach(dev);
5529 if (list_empty(&wl->devlist)) {
5530 b43_leds_unregister(wl);
5531 /* Last core on the chip unregistered.
5532 * We can destroy common struct b43_wl.
5534 b43_wireless_exit(dev, wl);
5538 static struct ssb_driver b43_ssb_driver = {
5539 .name = KBUILD_MODNAME,
5540 .id_table = b43_ssb_tbl,
5541 .probe = b43_ssb_probe,
5542 .remove = b43_ssb_remove,
5544 #endif /* CONFIG_B43_SSB */
5546 /* Perform a hardware reset. This can be called from any context. */
5547 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5549 /* Must avoid requeueing, if we are in shutdown. */
5550 if (b43_status(dev) < B43_STAT_INITIALIZED)
5552 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5553 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5556 static void b43_print_driverinfo(void)
5558 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5559 *feat_leds = "", *feat_sdio = "";
5561 #ifdef CONFIG_B43_PCI_AUTOSELECT
5564 #ifdef CONFIG_B43_PCMCIA
5567 #ifdef CONFIG_B43_PHY_N
5570 #ifdef CONFIG_B43_LEDS
5573 #ifdef CONFIG_B43_SDIO
5576 printk(KERN_INFO "Broadcom 43xx driver loaded "
5577 "[ Features: %s%s%s%s%s ]\n",
5578 feat_pci, feat_pcmcia, feat_nphy,
5579 feat_leds, feat_sdio);
5582 static int __init b43_init(void)
5587 err = b43_pcmcia_init();
5590 err = b43_sdio_init();
5592 goto err_pcmcia_exit;
5593 #ifdef CONFIG_B43_BCMA
5594 err = bcma_driver_register(&b43_bcma_driver);
5598 #ifdef CONFIG_B43_SSB
5599 err = ssb_driver_register(&b43_ssb_driver);
5601 goto err_bcma_driver_exit;
5603 b43_print_driverinfo();
5607 #ifdef CONFIG_B43_SSB
5608 err_bcma_driver_exit:
5610 #ifdef CONFIG_B43_BCMA
5611 bcma_driver_unregister(&b43_bcma_driver);
5622 static void __exit b43_exit(void)
5624 #ifdef CONFIG_B43_SSB
5625 ssb_driver_unregister(&b43_ssb_driver);
5627 #ifdef CONFIG_B43_BCMA
5628 bcma_driver_unregister(&b43_bcma_driver);
5635 module_init(b43_init)
5636 module_exit(b43_exit)