3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
286 static int b43_ratelimit(struct b43_wl *wl)
288 if (!wl || !wl->current_dev)
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
301 if (!b43_ratelimit(wl))
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
314 if (!b43_ratelimit(wl))
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
327 if (!b43_ratelimit(wl))
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
353 B43_WARN_ON(offset % 4 != 0);
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
378 struct b43_wl *wl = dev->wl;
382 spin_lock_irqsave(&wl->shm_lock, flags);
383 if (routing == B43_SHM_SHARED) {
384 B43_WARN_ON(offset & 0x0001);
385 if (offset & 0x0003) {
386 /* Unaligned access */
387 b43_shm_control_word(dev, routing, offset >> 2);
388 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
390 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
391 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
397 b43_shm_control_word(dev, routing, offset);
398 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
400 spin_unlock_irqrestore(&wl->shm_lock, flags);
405 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
407 struct b43_wl *wl = dev->wl;
411 spin_lock_irqsave(&wl->shm_lock, flags);
412 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev, routing, offset >> 2);
417 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423 b43_shm_control_word(dev, routing, offset);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
426 spin_unlock_irqrestore(&wl->shm_lock, flags);
431 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
433 struct b43_wl *wl = dev->wl;
436 spin_lock_irqsave(&wl->shm_lock, flags);
437 if (routing == B43_SHM_SHARED) {
438 B43_WARN_ON(offset & 0x0001);
439 if (offset & 0x0003) {
440 /* Unaligned access */
441 b43_shm_control_word(dev, routing, offset >> 2);
442 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
443 (value >> 16) & 0xffff);
444 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
445 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
450 b43_shm_control_word(dev, routing, offset);
451 b43_write32(dev, B43_MMIO_SHM_DATA, value);
453 spin_unlock_irqrestore(&wl->shm_lock, flags);
456 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
458 struct b43_wl *wl = dev->wl;
461 spin_lock_irqsave(&wl->shm_lock, flags);
462 if (routing == B43_SHM_SHARED) {
463 B43_WARN_ON(offset & 0x0001);
464 if (offset & 0x0003) {
465 /* Unaligned access */
466 b43_shm_control_word(dev, routing, offset >> 2);
467 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
472 b43_shm_control_word(dev, routing, offset);
473 b43_write16(dev, B43_MMIO_SHM_DATA, value);
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
479 u64 b43_hf_read(struct b43_wldev * dev)
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
492 /* Write HostFlags */
493 void b43_hf_write(struct b43_wldev *dev, u64 value)
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
505 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
507 /* We need to be careful. As we read the TSF from multiple
508 * registers, we should take care of register overflows.
509 * In theory, the whole tsf read process should be atomic.
510 * We try to be atomic here, by restaring the read process,
511 * if any of the high registers changed (overflew).
513 if (dev->dev->id.revision >= 3) {
514 u32 low, high, high2;
517 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
518 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
519 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
520 } while (unlikely(high != high2));
528 u16 test1, test2, test3;
531 v3 = b43_read16(dev, B43_MMIO_TSF_3);
532 v2 = b43_read16(dev, B43_MMIO_TSF_2);
533 v1 = b43_read16(dev, B43_MMIO_TSF_1);
534 v0 = b43_read16(dev, B43_MMIO_TSF_0);
536 test3 = b43_read16(dev, B43_MMIO_TSF_3);
537 test2 = b43_read16(dev, B43_MMIO_TSF_2);
538 test1 = b43_read16(dev, B43_MMIO_TSF_1);
539 } while (v3 != test3 || v2 != test2 || v1 != test1);
553 static void b43_time_lock(struct b43_wldev *dev)
557 macctl = b43_read32(dev, B43_MMIO_MACCTL);
558 macctl |= B43_MACCTL_TBTTHOLD;
559 b43_write32(dev, B43_MMIO_MACCTL, macctl);
560 /* Commit the write */
561 b43_read32(dev, B43_MMIO_MACCTL);
564 static void b43_time_unlock(struct b43_wldev *dev)
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl &= ~B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
575 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
577 /* Be careful with the in-progress timer.
578 * First zero out the low register, so we have a full
579 * register-overflow duration to complete the operation.
581 if (dev->dev->id.revision >= 3) {
582 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
583 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
587 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
589 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
591 u16 v0 = (tsf & 0x000000000000FFFFULL);
592 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
593 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
594 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
596 b43_write16(dev, B43_MMIO_TSF_0, 0);
598 b43_write16(dev, B43_MMIO_TSF_3, v3);
600 b43_write16(dev, B43_MMIO_TSF_2, v2);
602 b43_write16(dev, B43_MMIO_TSF_1, v1);
604 b43_write16(dev, B43_MMIO_TSF_0, v0);
608 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
611 b43_tsf_write_locked(dev, tsf);
612 b43_time_unlock(dev);
616 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
618 static const u8 zero_addr[ETH_ALEN] = { 0 };
625 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
642 u8 mac_bssid[ETH_ALEN * 2];
646 bssid = dev->wl->bssid;
647 mac = dev->wl->mac_addr;
649 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
651 memcpy(mac_bssid, mac, ETH_ALEN);
652 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
654 /* Write our MAC address and BSSID to template ram */
655 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
656 tmp = (u32) (mac_bssid[i + 0]);
657 tmp |= (u32) (mac_bssid[i + 1]) << 8;
658 tmp |= (u32) (mac_bssid[i + 2]) << 16;
659 tmp |= (u32) (mac_bssid[i + 3]) << 24;
660 b43_ram_write(dev, 0x20 + i, tmp);
664 static void b43_upload_card_macaddress(struct b43_wldev *dev)
666 b43_write_mac_bssid_templates(dev);
667 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
670 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
672 /* slot_time is in usec. */
673 if (dev->phy.type != B43_PHYTYPE_G)
675 b43_write16(dev, 0x684, 510 + slot_time);
676 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
679 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
681 b43_set_slot_time(dev, 9);
685 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
687 b43_set_slot_time(dev, 20);
691 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
692 * Returns the _previously_ enabled IRQ mask.
694 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
698 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
699 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
704 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
705 * Returns the _previously_ enabled IRQ mask.
707 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
711 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
712 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
717 /* Synchronize IRQ top- and bottom-half.
718 * IRQs must be masked before calling this.
719 * This must not be called with the irq_lock held.
721 static void b43_synchronize_irq(struct b43_wldev *dev)
723 synchronize_irq(dev->dev->irq);
724 tasklet_kill(&dev->isr_tasklet);
727 /* DummyTransmission function, as documented on
728 * http://bcm-specs.sipsolutions.net/DummyTransmission
730 void b43_dummy_transmission(struct b43_wldev *dev)
732 struct b43_wl *wl = dev->wl;
733 struct b43_phy *phy = &dev->phy;
734 unsigned int i, max_loop;
747 buffer[0] = 0x000201CC;
752 buffer[0] = 0x000B846E;
759 spin_lock_irq(&wl->irq_lock);
760 write_lock(&wl->tx_lock);
762 for (i = 0; i < 5; i++)
763 b43_ram_write(dev, i * 4, buffer[i]);
766 b43_read32(dev, B43_MMIO_MACCTL);
768 b43_write16(dev, 0x0568, 0x0000);
769 b43_write16(dev, 0x07C0, 0x0000);
770 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
771 b43_write16(dev, 0x050C, value);
772 b43_write16(dev, 0x0508, 0x0000);
773 b43_write16(dev, 0x050A, 0x0000);
774 b43_write16(dev, 0x054C, 0x0000);
775 b43_write16(dev, 0x056A, 0x0014);
776 b43_write16(dev, 0x0568, 0x0826);
777 b43_write16(dev, 0x0500, 0x0000);
778 b43_write16(dev, 0x0502, 0x0030);
780 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
781 b43_radio_write16(dev, 0x0051, 0x0017);
782 for (i = 0x00; i < max_loop; i++) {
783 value = b43_read16(dev, 0x050E);
788 for (i = 0x00; i < 0x0A; i++) {
789 value = b43_read16(dev, 0x050E);
794 for (i = 0x00; i < 0x0A; i++) {
795 value = b43_read16(dev, 0x0690);
796 if (!(value & 0x0100))
800 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
801 b43_radio_write16(dev, 0x0051, 0x0037);
803 write_unlock(&wl->tx_lock);
804 spin_unlock_irq(&wl->irq_lock);
807 static void key_write(struct b43_wldev *dev,
808 u8 index, u8 algorithm, const u8 * key)
815 /* Key index/algo block */
816 kidx = b43_kidx_to_fw(dev, index);
817 value = ((kidx << 4) | algorithm);
818 b43_shm_write16(dev, B43_SHM_SHARED,
819 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
821 /* Write the key to the Key Table Pointer offset */
822 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
823 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
825 value |= (u16) (key[i + 1]) << 8;
826 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
830 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
832 u32 addrtmp[2] = { 0, 0, };
833 u8 per_sta_keys_start = 8;
835 if (b43_new_kidx_api(dev))
836 per_sta_keys_start = 4;
838 B43_WARN_ON(index < per_sta_keys_start);
839 /* We have two default TX keys and possibly two default RX keys.
840 * Physical mac 0 is mapped to physical key 4 or 8, depending
841 * on the firmware version.
842 * So we must adjust the index here.
844 index -= per_sta_keys_start;
847 addrtmp[0] = addr[0];
848 addrtmp[0] |= ((u32) (addr[1]) << 8);
849 addrtmp[0] |= ((u32) (addr[2]) << 16);
850 addrtmp[0] |= ((u32) (addr[3]) << 24);
851 addrtmp[1] = addr[4];
852 addrtmp[1] |= ((u32) (addr[5]) << 8);
855 if (dev->dev->id.revision >= 5) {
856 /* Receive match transmitter address mechanism */
857 b43_shm_write32(dev, B43_SHM_RCMTA,
858 (index * 2) + 0, addrtmp[0]);
859 b43_shm_write16(dev, B43_SHM_RCMTA,
860 (index * 2) + 1, addrtmp[1]);
862 /* RXE (Receive Engine) and
863 * PSM (Programmable State Machine) mechanism
866 /* TODO write to RCM 16, 19, 22 and 25 */
868 b43_shm_write32(dev, B43_SHM_SHARED,
869 B43_SHM_SH_PSM + (index * 6) + 0,
871 b43_shm_write16(dev, B43_SHM_SHARED,
872 B43_SHM_SH_PSM + (index * 6) + 4,
878 static void do_key_write(struct b43_wldev *dev,
879 u8 index, u8 algorithm,
880 const u8 * key, size_t key_len, const u8 * mac_addr)
882 u8 buf[B43_SEC_KEYSIZE] = { 0, };
883 u8 per_sta_keys_start = 8;
885 if (b43_new_kidx_api(dev))
886 per_sta_keys_start = 4;
888 B43_WARN_ON(index >= dev->max_nr_keys);
889 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
891 if (index >= per_sta_keys_start)
892 keymac_write(dev, index, NULL); /* First zero out mac. */
894 memcpy(buf, key, key_len);
895 key_write(dev, index, algorithm, buf);
896 if (index >= per_sta_keys_start)
897 keymac_write(dev, index, mac_addr);
899 dev->key[index].algorithm = algorithm;
902 static int b43_key_write(struct b43_wldev *dev,
903 int index, u8 algorithm,
904 const u8 * key, size_t key_len,
906 struct ieee80211_key_conf *keyconf)
911 if (key_len > B43_SEC_KEYSIZE)
913 for (i = 0; i < dev->max_nr_keys; i++) {
914 /* Check that we don't already have this key. */
915 B43_WARN_ON(dev->key[i].keyconf == keyconf);
918 /* Either pairwise key or address is 00:00:00:00:00:00
919 * for transmit-only keys. Search the index. */
920 if (b43_new_kidx_api(dev))
924 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
925 if (!dev->key[i].keyconf) {
932 b43err(dev->wl, "Out of hardware key memory\n");
936 B43_WARN_ON(index > 3);
938 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
939 if ((index <= 3) && !b43_new_kidx_api(dev)) {
941 B43_WARN_ON(mac_addr);
942 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
944 keyconf->hw_key_idx = index;
945 dev->key[index].keyconf = keyconf;
950 static int b43_key_clear(struct b43_wldev *dev, int index)
952 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
954 do_key_write(dev, index, B43_SEC_ALGO_NONE,
955 NULL, B43_SEC_KEYSIZE, NULL);
956 if ((index <= 3) && !b43_new_kidx_api(dev)) {
957 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
958 NULL, B43_SEC_KEYSIZE, NULL);
960 dev->key[index].keyconf = NULL;
965 static void b43_clear_keys(struct b43_wldev *dev)
969 for (i = 0; i < dev->max_nr_keys; i++)
970 b43_key_clear(dev, i);
973 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
981 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
982 (ps_flags & B43_PS_DISABLED));
983 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
985 if (ps_flags & B43_PS_ENABLED) {
987 } else if (ps_flags & B43_PS_DISABLED) {
990 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
991 // and thus is not an AP and we are associated, set bit 25
993 if (ps_flags & B43_PS_AWAKE) {
995 } else if (ps_flags & B43_PS_ASLEEP) {
998 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
999 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1000 // successful, set bit26
1003 /* FIXME: For now we force awake-on and hwps-off */
1007 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1009 macctl |= B43_MACCTL_HWPS;
1011 macctl &= ~B43_MACCTL_HWPS;
1013 macctl |= B43_MACCTL_AWAKE;
1015 macctl &= ~B43_MACCTL_AWAKE;
1016 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1018 b43_read32(dev, B43_MMIO_MACCTL);
1019 if (awake && dev->dev->id.revision >= 5) {
1020 /* Wait for the microcode to wake up. */
1021 for (i = 0; i < 100; i++) {
1022 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1023 B43_SHM_SH_UCODESTAT);
1024 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1031 /* Turn the Analog ON/OFF */
1032 static void b43_switch_analog(struct b43_wldev *dev, int on)
1034 switch (dev->phy.type) {
1037 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1048 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1053 flags |= B43_TMSLOW_PHYCLKEN;
1054 flags |= B43_TMSLOW_PHYRESET;
1055 ssb_device_enable(dev->dev, flags);
1056 msleep(2); /* Wait for the PLL to turn on. */
1058 /* Now take the PHY out of Reset again */
1059 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1060 tmslow |= SSB_TMSLOW_FGC;
1061 tmslow &= ~B43_TMSLOW_PHYRESET;
1062 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1063 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1065 tmslow &= ~SSB_TMSLOW_FGC;
1066 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1067 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1070 /* Turn Analog ON */
1071 b43_switch_analog(dev, 1);
1073 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1074 macctl &= ~B43_MACCTL_GMODE;
1075 if (flags & B43_TMSLOW_GMODE)
1076 macctl |= B43_MACCTL_GMODE;
1077 macctl |= B43_MACCTL_IHR_ENABLED;
1078 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1081 static void handle_irq_transmit_status(struct b43_wldev *dev)
1085 struct b43_txstatus stat;
1088 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1089 if (!(v0 & 0x00000001))
1091 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1093 stat.cookie = (v0 >> 16);
1094 stat.seq = (v1 & 0x0000FFFF);
1095 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1096 tmp = (v0 & 0x0000FFFF);
1097 stat.frame_count = ((tmp & 0xF000) >> 12);
1098 stat.rts_count = ((tmp & 0x0F00) >> 8);
1099 stat.supp_reason = ((tmp & 0x001C) >> 2);
1100 stat.pm_indicated = !!(tmp & 0x0080);
1101 stat.intermediate = !!(tmp & 0x0040);
1102 stat.for_ampdu = !!(tmp & 0x0020);
1103 stat.acked = !!(tmp & 0x0002);
1105 b43_handle_txstatus(dev, &stat);
1109 static void drain_txstatus_queue(struct b43_wldev *dev)
1113 if (dev->dev->id.revision < 5)
1115 /* Read all entries from the microcode TXstatus FIFO
1116 * and throw them away.
1119 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1120 if (!(dummy & 0x00000001))
1122 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1126 static u32 b43_jssi_read(struct b43_wldev *dev)
1130 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1132 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1137 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1139 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1140 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1143 static void b43_generate_noise_sample(struct b43_wldev *dev)
1145 b43_jssi_write(dev, 0x7F7F7F7F);
1146 b43_write32(dev, B43_MMIO_MACCMD,
1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1148 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1151 static void b43_calculate_link_quality(struct b43_wldev *dev)
1153 /* Top half of Link Quality calculation. */
1155 if (dev->noisecalc.calculation_running)
1157 dev->noisecalc.channel_at_start = dev->phy.channel;
1158 dev->noisecalc.calculation_running = 1;
1159 dev->noisecalc.nr_samples = 0;
1161 b43_generate_noise_sample(dev);
1164 static void handle_irq_noise(struct b43_wldev *dev)
1166 struct b43_phy *phy = &dev->phy;
1172 /* Bottom half of Link Quality calculation. */
1174 B43_WARN_ON(!dev->noisecalc.calculation_running);
1175 if (dev->noisecalc.channel_at_start != phy->channel)
1176 goto drop_calculation;
1177 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1178 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1179 noise[2] == 0x7F || noise[3] == 0x7F)
1182 /* Get the noise samples. */
1183 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1184 i = dev->noisecalc.nr_samples;
1185 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1186 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1187 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1188 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1189 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1190 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1191 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1192 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1193 dev->noisecalc.nr_samples++;
1194 if (dev->noisecalc.nr_samples == 8) {
1195 /* Calculate the Link Quality by the noise samples. */
1197 for (i = 0; i < 8; i++) {
1198 for (j = 0; j < 4; j++)
1199 average += dev->noisecalc.samples[i][j];
1205 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1206 tmp = (tmp / 128) & 0x1F;
1216 dev->stats.link_noise = average;
1218 dev->noisecalc.calculation_running = 0;
1222 b43_generate_noise_sample(dev);
1225 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1227 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1230 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1231 b43_power_saving_ctl_bits(dev, 0);
1233 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1237 static void handle_irq_atim_end(struct b43_wldev *dev)
1239 if (dev->dfq_valid) {
1240 b43_write32(dev, B43_MMIO_MACCMD,
1241 b43_read32(dev, B43_MMIO_MACCMD)
1242 | B43_MACCMD_DFQ_VALID);
1247 static void handle_irq_pmq(struct b43_wldev *dev)
1254 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1255 if (!(tmp & 0x00000008))
1258 /* 16bit write is odd, but correct. */
1259 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1262 static void b43_write_template_common(struct b43_wldev *dev,
1263 const u8 * data, u16 size,
1265 u16 shm_size_offset, u8 rate)
1268 struct b43_plcp_hdr4 plcp;
1271 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1272 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1273 ram_offset += sizeof(u32);
1274 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1275 * So leave the first two bytes of the next write blank.
1277 tmp = (u32) (data[0]) << 16;
1278 tmp |= (u32) (data[1]) << 24;
1279 b43_ram_write(dev, ram_offset, tmp);
1280 ram_offset += sizeof(u32);
1281 for (i = 2; i < size; i += sizeof(u32)) {
1282 tmp = (u32) (data[i + 0]);
1284 tmp |= (u32) (data[i + 1]) << 8;
1286 tmp |= (u32) (data[i + 2]) << 16;
1288 tmp |= (u32) (data[i + 3]) << 24;
1289 b43_ram_write(dev, ram_offset + i - 2, tmp);
1291 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1292 size + sizeof(struct b43_plcp_hdr6));
1295 /* Check if the use of the antenna that ieee80211 told us to
1296 * use is possible. This will fall back to DEFAULT.
1297 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1298 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1303 if (antenna_nr == 0) {
1304 /* Zero means "use default antenna". That's always OK. */
1308 /* Get the mask of available antennas. */
1310 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1312 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1314 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1315 /* This antenna is not available. Fall back to default. */
1322 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1324 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1326 case 0: /* default/diversity */
1327 return B43_ANTENNA_DEFAULT;
1328 case 1: /* Antenna 0 */
1329 return B43_ANTENNA0;
1330 case 2: /* Antenna 1 */
1331 return B43_ANTENNA1;
1332 case 3: /* Antenna 2 */
1333 return B43_ANTENNA2;
1334 case 4: /* Antenna 3 */
1335 return B43_ANTENNA3;
1337 return B43_ANTENNA_DEFAULT;
1341 /* Convert a b43 antenna number value to the PHY TX control value. */
1342 static u16 b43_antenna_to_phyctl(int antenna)
1346 return B43_TXH_PHY_ANT0;
1348 return B43_TXH_PHY_ANT1;
1350 return B43_TXH_PHY_ANT2;
1352 return B43_TXH_PHY_ANT3;
1353 case B43_ANTENNA_AUTO:
1354 return B43_TXH_PHY_ANT01AUTO;
1360 static void b43_write_beacon_template(struct b43_wldev *dev,
1362 u16 shm_size_offset)
1364 unsigned int i, len, variable_len;
1365 const struct ieee80211_mgmt *bcn;
1372 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1373 len = min((size_t) dev->wl->current_beacon->len,
1374 0x200 - sizeof(struct b43_plcp_hdr6));
1375 rate = dev->wl->beacon_txctl.tx_rate->hw_value;
1377 b43_write_template_common(dev, (const u8 *)bcn,
1378 len, ram_offset, shm_size_offset, rate);
1380 /* Write the PHY TX control parameters. */
1381 antenna = b43_antenna_from_ieee80211(dev,
1382 dev->wl->beacon_txctl.antenna_sel_tx);
1383 antenna = b43_antenna_to_phyctl(antenna);
1384 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1385 /* We can't send beacons with short preamble. Would get PHY errors. */
1386 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1387 ctl &= ~B43_TXH_PHY_ANT;
1388 ctl &= ~B43_TXH_PHY_ENC;
1390 if (b43_is_cck_rate(rate))
1391 ctl |= B43_TXH_PHY_ENC_CCK;
1393 ctl |= B43_TXH_PHY_ENC_OFDM;
1394 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1396 /* Find the position of the TIM and the DTIM_period value
1397 * and write them to SHM. */
1398 ie = bcn->u.beacon.variable;
1399 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1400 for (i = 0; i < variable_len - 2; ) {
1401 uint8_t ie_id, ie_len;
1408 /* This is the TIM Information Element */
1410 /* Check whether the ie_len is in the beacon data range. */
1411 if (variable_len < ie_len + 2 + i)
1413 /* A valid TIM is at least 4 bytes long. */
1418 tim_position = sizeof(struct b43_plcp_hdr6);
1419 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1422 dtim_period = ie[i + 3];
1424 b43_shm_write16(dev, B43_SHM_SHARED,
1425 B43_SHM_SH_TIMBPOS, tim_position);
1426 b43_shm_write16(dev, B43_SHM_SHARED,
1427 B43_SHM_SH_DTIMPER, dtim_period);
1433 b43warn(dev->wl, "Did not find a valid TIM IE in "
1434 "the beacon template packet. AP or IBSS operation "
1435 "may be broken.\n");
1437 b43dbg(dev->wl, "Updated beacon template\n");
1440 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1441 u16 shm_offset, u16 size,
1442 struct ieee80211_rate *rate)
1444 struct b43_plcp_hdr4 plcp;
1449 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1450 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1453 /* Write PLCP in two parts and timing for packet transfer */
1454 tmp = le32_to_cpu(plcp.data);
1455 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1456 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1457 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1460 /* Instead of using custom probe response template, this function
1461 * just patches custom beacon template by:
1462 * 1) Changing packet type
1463 * 2) Patching duration field
1466 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1468 struct ieee80211_rate *rate)
1472 u16 src_size, elem_size, src_pos, dest_pos;
1474 struct ieee80211_hdr *hdr;
1477 src_size = dev->wl->current_beacon->len;
1478 src_data = (const u8 *)dev->wl->current_beacon->data;
1480 /* Get the start offset of the variable IEs in the packet. */
1481 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1482 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1484 if (B43_WARN_ON(src_size < ie_start))
1487 dest_data = kmalloc(src_size, GFP_ATOMIC);
1488 if (unlikely(!dest_data))
1491 /* Copy the static data and all Information Elements, except the TIM. */
1492 memcpy(dest_data, src_data, ie_start);
1494 dest_pos = ie_start;
1495 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1496 elem_size = src_data[src_pos + 1] + 2;
1497 if (src_data[src_pos] == 5) {
1498 /* This is the TIM. */
1501 memcpy(dest_data + dest_pos, src_data + src_pos,
1503 dest_pos += elem_size;
1505 *dest_size = dest_pos;
1506 hdr = (struct ieee80211_hdr *)dest_data;
1508 /* Set the frame control. */
1509 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1510 IEEE80211_STYPE_PROBE_RESP);
1511 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1512 dev->wl->vif, *dest_size,
1514 hdr->duration_id = dur;
1519 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1521 u16 shm_size_offset,
1522 struct ieee80211_rate *rate)
1524 const u8 *probe_resp_data;
1527 size = dev->wl->current_beacon->len;
1528 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1529 if (unlikely(!probe_resp_data))
1532 /* Looks like PLCP headers plus packet timings are stored for
1533 * all possible basic rates
1535 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1536 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1537 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1538 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1540 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1541 b43_write_template_common(dev, probe_resp_data,
1542 size, ram_offset, shm_size_offset,
1544 kfree(probe_resp_data);
1547 static void handle_irq_beacon(struct b43_wldev *dev)
1549 struct b43_wl *wl = dev->wl;
1550 u32 cmd, beacon0_valid, beacon1_valid;
1552 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1555 /* This is the bottom half of the asynchronous beacon update. */
1557 /* Ignore interrupt in the future. */
1558 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1560 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1561 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1562 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1564 /* Schedule interrupt manually, if busy. */
1565 if (beacon0_valid && beacon1_valid) {
1566 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1567 dev->irq_savedstate |= B43_IRQ_BEACON;
1571 if (!beacon0_valid) {
1572 if (!wl->beacon0_uploaded) {
1573 b43_write_beacon_template(dev, 0x68, 0x18);
1574 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1575 &__b43_ratetable[3]);
1576 wl->beacon0_uploaded = 1;
1578 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1579 cmd |= B43_MACCMD_BEACON0_VALID;
1580 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1581 } else if (!beacon1_valid) {
1582 if (!wl->beacon1_uploaded) {
1583 b43_write_beacon_template(dev, 0x468, 0x1A);
1584 wl->beacon1_uploaded = 1;
1586 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1587 cmd |= B43_MACCMD_BEACON1_VALID;
1588 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1592 static void b43_beacon_update_trigger_work(struct work_struct *work)
1594 struct b43_wl *wl = container_of(work, struct b43_wl,
1595 beacon_update_trigger);
1596 struct b43_wldev *dev;
1598 mutex_lock(&wl->mutex);
1599 dev = wl->current_dev;
1600 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1601 spin_lock_irq(&wl->irq_lock);
1602 /* update beacon right away or defer to irq */
1603 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1604 handle_irq_beacon(dev);
1605 /* The handler might have updated the IRQ mask. */
1606 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1607 dev->irq_savedstate);
1609 spin_unlock_irq(&wl->irq_lock);
1611 mutex_unlock(&wl->mutex);
1614 /* Asynchronously update the packet templates in template RAM.
1615 * Locking: Requires wl->irq_lock to be locked. */
1616 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon,
1617 const struct ieee80211_tx_control *txctl)
1619 /* This is the top half of the ansynchronous beacon update.
1620 * The bottom half is the beacon IRQ.
1621 * Beacon update must be asynchronous to avoid sending an
1622 * invalid beacon. This can happen for example, if the firmware
1623 * transmits a beacon while we are updating it. */
1625 if (wl->current_beacon)
1626 dev_kfree_skb_any(wl->current_beacon);
1627 wl->current_beacon = beacon;
1628 memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
1629 wl->beacon0_uploaded = 0;
1630 wl->beacon1_uploaded = 0;
1631 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1634 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1639 len = min((u16) ssid_len, (u16) 0x100);
1640 for (i = 0; i < len; i += sizeof(u32)) {
1641 tmp = (u32) (ssid[i + 0]);
1643 tmp |= (u32) (ssid[i + 1]) << 8;
1645 tmp |= (u32) (ssid[i + 2]) << 16;
1647 tmp |= (u32) (ssid[i + 3]) << 24;
1648 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1650 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1653 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1656 if (dev->dev->id.revision >= 3) {
1657 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1658 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1660 b43_write16(dev, 0x606, (beacon_int >> 6));
1661 b43_write16(dev, 0x610, beacon_int);
1663 b43_time_unlock(dev);
1664 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1667 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1672 /* Interrupt handler bottom-half */
1673 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1676 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1677 u32 merged_dma_reason = 0;
1679 unsigned long flags;
1681 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1683 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1685 reason = dev->irq_reason;
1686 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1687 dma_reason[i] = dev->dma_reason[i];
1688 merged_dma_reason |= dma_reason[i];
1691 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1692 b43err(dev->wl, "MAC transmission error\n");
1694 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1695 b43err(dev->wl, "PHY transmission error\n");
1697 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1698 atomic_set(&dev->phy.txerr_cnt,
1699 B43_PHY_TX_BADNESS_LIMIT);
1700 b43err(dev->wl, "Too many PHY TX errors, "
1701 "restarting the controller\n");
1702 b43_controller_restart(dev, "PHY TX errors");
1706 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1707 B43_DMAIRQ_NONFATALMASK))) {
1708 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1709 b43err(dev->wl, "Fatal DMA error: "
1710 "0x%08X, 0x%08X, 0x%08X, "
1711 "0x%08X, 0x%08X, 0x%08X\n",
1712 dma_reason[0], dma_reason[1],
1713 dma_reason[2], dma_reason[3],
1714 dma_reason[4], dma_reason[5]);
1715 b43_controller_restart(dev, "DMA error");
1717 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1720 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1721 b43err(dev->wl, "DMA error: "
1722 "0x%08X, 0x%08X, 0x%08X, "
1723 "0x%08X, 0x%08X, 0x%08X\n",
1724 dma_reason[0], dma_reason[1],
1725 dma_reason[2], dma_reason[3],
1726 dma_reason[4], dma_reason[5]);
1730 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1731 handle_irq_ucode_debug(dev);
1732 if (reason & B43_IRQ_TBTT_INDI)
1733 handle_irq_tbtt_indication(dev);
1734 if (reason & B43_IRQ_ATIM_END)
1735 handle_irq_atim_end(dev);
1736 if (reason & B43_IRQ_BEACON)
1737 handle_irq_beacon(dev);
1738 if (reason & B43_IRQ_PMQ)
1739 handle_irq_pmq(dev);
1740 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1742 if (reason & B43_IRQ_NOISESAMPLE_OK)
1743 handle_irq_noise(dev);
1745 /* Check the DMA reason registers for received data. */
1746 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1747 if (b43_using_pio_transfers(dev))
1748 b43_pio_rx(dev->pio.rx_queue);
1750 b43_dma_rx(dev->dma.rx_ring);
1752 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1753 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1754 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1755 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1756 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1758 if (reason & B43_IRQ_TX_OK)
1759 handle_irq_transmit_status(dev);
1761 b43_interrupt_enable(dev, dev->irq_savedstate);
1763 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1766 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1768 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1770 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1771 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1772 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1773 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1774 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1775 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1778 /* Interrupt handler top-half */
1779 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1781 irqreturn_t ret = IRQ_NONE;
1782 struct b43_wldev *dev = dev_id;
1788 spin_lock(&dev->wl->irq_lock);
1790 if (b43_status(dev) < B43_STAT_STARTED)
1792 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1793 if (reason == 0xffffffff) /* shared IRQ */
1796 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1800 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1802 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1804 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1806 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1808 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1810 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1813 b43_interrupt_ack(dev, reason);
1814 /* disable all IRQs. They are enabled again in the bottom half. */
1815 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1816 /* save the reason code and call our bottom half. */
1817 dev->irq_reason = reason;
1818 tasklet_schedule(&dev->isr_tasklet);
1821 spin_unlock(&dev->wl->irq_lock);
1826 static void do_release_fw(struct b43_firmware_file *fw)
1828 release_firmware(fw->data);
1830 fw->filename = NULL;
1833 static void b43_release_firmware(struct b43_wldev *dev)
1835 do_release_fw(&dev->fw.ucode);
1836 do_release_fw(&dev->fw.pcm);
1837 do_release_fw(&dev->fw.initvals);
1838 do_release_fw(&dev->fw.initvals_band);
1841 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1845 text = "You must go to "
1846 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1847 "and download the latest firmware (version 4).\n";
1854 static int do_request_fw(struct b43_wldev *dev,
1856 struct b43_firmware_file *fw)
1858 char path[sizeof(modparam_fwpostfix) + 32];
1859 const struct firmware *blob;
1860 struct b43_fw_header *hdr;
1865 /* Don't fetch anything. Free possibly cached firmware. */
1870 if (strcmp(fw->filename, name) == 0)
1871 return 0; /* Already have this fw. */
1872 /* Free the cached firmware first. */
1876 snprintf(path, ARRAY_SIZE(path),
1878 modparam_fwpostfix, name);
1879 err = request_firmware(&blob, path, dev->dev->dev);
1881 b43err(dev->wl, "Firmware file \"%s\" not found "
1882 "or load failed.\n", path);
1885 if (blob->size < sizeof(struct b43_fw_header))
1887 hdr = (struct b43_fw_header *)(blob->data);
1888 switch (hdr->type) {
1889 case B43_FW_TYPE_UCODE:
1890 case B43_FW_TYPE_PCM:
1891 size = be32_to_cpu(hdr->size);
1892 if (size != blob->size - sizeof(struct b43_fw_header))
1895 case B43_FW_TYPE_IV:
1904 fw->filename = name;
1909 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1910 release_firmware(blob);
1915 static int b43_request_firmware(struct b43_wldev *dev)
1917 struct b43_firmware *fw = &dev->fw;
1918 const u8 rev = dev->dev->id.revision;
1919 const char *filename;
1924 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1925 if ((rev >= 5) && (rev <= 10))
1926 filename = "ucode5";
1927 else if ((rev >= 11) && (rev <= 12))
1928 filename = "ucode11";
1930 filename = "ucode13";
1933 err = do_request_fw(dev, filename, &fw->ucode);
1938 if ((rev >= 5) && (rev <= 10))
1944 err = do_request_fw(dev, filename, &fw->pcm);
1949 switch (dev->phy.type) {
1951 if ((rev >= 5) && (rev <= 10)) {
1952 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1953 filename = "a0g1initvals5";
1955 filename = "a0g0initvals5";
1957 goto err_no_initvals;
1960 if ((rev >= 5) && (rev <= 10))
1961 filename = "b0g0initvals5";
1963 filename = "lp0initvals13";
1965 goto err_no_initvals;
1968 if ((rev >= 11) && (rev <= 12))
1969 filename = "n0initvals11";
1971 goto err_no_initvals;
1974 goto err_no_initvals;
1976 err = do_request_fw(dev, filename, &fw->initvals);
1980 /* Get bandswitch initvals */
1981 switch (dev->phy.type) {
1983 if ((rev >= 5) && (rev <= 10)) {
1984 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1985 filename = "a0g1bsinitvals5";
1987 filename = "a0g0bsinitvals5";
1988 } else if (rev >= 11)
1991 goto err_no_initvals;
1994 if ((rev >= 5) && (rev <= 10))
1995 filename = "b0g0bsinitvals5";
1999 goto err_no_initvals;
2002 if ((rev >= 11) && (rev <= 12))
2003 filename = "n0bsinitvals11";
2005 goto err_no_initvals;
2008 goto err_no_initvals;
2010 err = do_request_fw(dev, filename, &fw->initvals_band);
2017 b43_print_fw_helptext(dev->wl, 1);
2022 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2027 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2032 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2033 "core rev %u\n", dev->phy.type, rev);
2037 b43_release_firmware(dev);
2041 static int b43_upload_microcode(struct b43_wldev *dev)
2043 const size_t hdr_len = sizeof(struct b43_fw_header);
2045 unsigned int i, len;
2046 u16 fwrev, fwpatch, fwdate, fwtime;
2050 /* Jump the microcode PSM to offset 0 */
2051 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2052 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2053 macctl |= B43_MACCTL_PSM_JMP0;
2054 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2055 /* Zero out all microcode PSM registers and shared memory. */
2056 for (i = 0; i < 64; i++)
2057 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2058 for (i = 0; i < 4096; i += 2)
2059 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2061 /* Upload Microcode. */
2062 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2063 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2064 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2065 for (i = 0; i < len; i++) {
2066 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2070 if (dev->fw.pcm.data) {
2071 /* Upload PCM data. */
2072 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2073 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2074 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2075 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2076 /* No need for autoinc bit in SHM_HW */
2077 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2078 for (i = 0; i < len; i++) {
2079 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2084 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2086 /* Start the microcode PSM */
2087 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2088 macctl &= ~B43_MACCTL_PSM_JMP0;
2089 macctl |= B43_MACCTL_PSM_RUN;
2090 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2092 /* Wait for the microcode to load and respond */
2095 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2096 if (tmp == B43_IRQ_MAC_SUSPENDED)
2100 b43err(dev->wl, "Microcode not responding\n");
2101 b43_print_fw_helptext(dev->wl, 1);
2105 msleep_interruptible(50);
2106 if (signal_pending(current)) {
2111 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2113 /* Get and check the revisions. */
2114 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2115 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2116 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2117 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2119 if (fwrev <= 0x128) {
2120 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2121 "binary drivers older than version 4.x is unsupported. "
2122 "You must upgrade your firmware files.\n");
2123 b43_print_fw_helptext(dev->wl, 1);
2127 b43info(dev->wl, "Loading firmware version %u.%u "
2128 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2130 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2131 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2133 dev->fw.rev = fwrev;
2134 dev->fw.patch = fwpatch;
2136 if (b43_is_old_txhdr_format(dev)) {
2137 b43warn(dev->wl, "You are using an old firmware image. "
2138 "Support for old firmware will be removed in July 2008.\n");
2139 b43_print_fw_helptext(dev->wl, 0);
2145 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2146 macctl &= ~B43_MACCTL_PSM_RUN;
2147 macctl |= B43_MACCTL_PSM_JMP0;
2148 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2153 static int b43_write_initvals(struct b43_wldev *dev,
2154 const struct b43_iv *ivals,
2158 const struct b43_iv *iv;
2163 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2165 for (i = 0; i < count; i++) {
2166 if (array_size < sizeof(iv->offset_size))
2168 array_size -= sizeof(iv->offset_size);
2169 offset = be16_to_cpu(iv->offset_size);
2170 bit32 = !!(offset & B43_IV_32BIT);
2171 offset &= B43_IV_OFFSET_MASK;
2172 if (offset >= 0x1000)
2177 if (array_size < sizeof(iv->data.d32))
2179 array_size -= sizeof(iv->data.d32);
2181 value = get_unaligned_be32(&iv->data.d32);
2182 b43_write32(dev, offset, value);
2184 iv = (const struct b43_iv *)((const uint8_t *)iv +
2190 if (array_size < sizeof(iv->data.d16))
2192 array_size -= sizeof(iv->data.d16);
2194 value = be16_to_cpu(iv->data.d16);
2195 b43_write16(dev, offset, value);
2197 iv = (const struct b43_iv *)((const uint8_t *)iv +
2208 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2209 b43_print_fw_helptext(dev->wl, 1);
2214 static int b43_upload_initvals(struct b43_wldev *dev)
2216 const size_t hdr_len = sizeof(struct b43_fw_header);
2217 const struct b43_fw_header *hdr;
2218 struct b43_firmware *fw = &dev->fw;
2219 const struct b43_iv *ivals;
2223 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2224 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2225 count = be32_to_cpu(hdr->size);
2226 err = b43_write_initvals(dev, ivals, count,
2227 fw->initvals.data->size - hdr_len);
2230 if (fw->initvals_band.data) {
2231 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2232 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2233 count = be32_to_cpu(hdr->size);
2234 err = b43_write_initvals(dev, ivals, count,
2235 fw->initvals_band.data->size - hdr_len);
2244 /* Initialize the GPIOs
2245 * http://bcm-specs.sipsolutions.net/GPIO
2247 static int b43_gpio_init(struct b43_wldev *dev)
2249 struct ssb_bus *bus = dev->dev->bus;
2250 struct ssb_device *gpiodev, *pcidev = NULL;
2253 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2254 & ~B43_MACCTL_GPOUTSMSK);
2256 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2261 if (dev->dev->bus->chip_id == 0x4301) {
2265 if (0 /* FIXME: conditional unknown */ ) {
2266 b43_write16(dev, B43_MMIO_GPIO_MASK,
2267 b43_read16(dev, B43_MMIO_GPIO_MASK)
2272 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2273 b43_write16(dev, B43_MMIO_GPIO_MASK,
2274 b43_read16(dev, B43_MMIO_GPIO_MASK)
2279 if (dev->dev->id.revision >= 2)
2280 mask |= 0x0010; /* FIXME: This is redundant. */
2282 #ifdef CONFIG_SSB_DRIVER_PCICORE
2283 pcidev = bus->pcicore.dev;
2285 gpiodev = bus->chipco.dev ? : pcidev;
2288 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2289 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2295 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2296 static void b43_gpio_cleanup(struct b43_wldev *dev)
2298 struct ssb_bus *bus = dev->dev->bus;
2299 struct ssb_device *gpiodev, *pcidev = NULL;
2301 #ifdef CONFIG_SSB_DRIVER_PCICORE
2302 pcidev = bus->pcicore.dev;
2304 gpiodev = bus->chipco.dev ? : pcidev;
2307 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2310 /* http://bcm-specs.sipsolutions.net/EnableMac */
2311 void b43_mac_enable(struct b43_wldev *dev)
2313 dev->mac_suspended--;
2314 B43_WARN_ON(dev->mac_suspended < 0);
2315 if (dev->mac_suspended == 0) {
2316 b43_write32(dev, B43_MMIO_MACCTL,
2317 b43_read32(dev, B43_MMIO_MACCTL)
2318 | B43_MACCTL_ENABLED);
2319 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2320 B43_IRQ_MAC_SUSPENDED);
2322 b43_read32(dev, B43_MMIO_MACCTL);
2323 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2324 b43_power_saving_ctl_bits(dev, 0);
2328 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2329 void b43_mac_suspend(struct b43_wldev *dev)
2335 B43_WARN_ON(dev->mac_suspended < 0);
2337 if (dev->mac_suspended == 0) {
2338 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2339 b43_write32(dev, B43_MMIO_MACCTL,
2340 b43_read32(dev, B43_MMIO_MACCTL)
2341 & ~B43_MACCTL_ENABLED);
2342 /* force pci to flush the write */
2343 b43_read32(dev, B43_MMIO_MACCTL);
2344 for (i = 35; i; i--) {
2345 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2346 if (tmp & B43_IRQ_MAC_SUSPENDED)
2350 /* Hm, it seems this will take some time. Use msleep(). */
2351 for (i = 40; i; i--) {
2352 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2353 if (tmp & B43_IRQ_MAC_SUSPENDED)
2357 b43err(dev->wl, "MAC suspend failed\n");
2360 dev->mac_suspended++;
2363 static void b43_adjust_opmode(struct b43_wldev *dev)
2365 struct b43_wl *wl = dev->wl;
2369 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2370 /* Reset status to STA infrastructure mode. */
2371 ctl &= ~B43_MACCTL_AP;
2372 ctl &= ~B43_MACCTL_KEEP_CTL;
2373 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2374 ctl &= ~B43_MACCTL_KEEP_BAD;
2375 ctl &= ~B43_MACCTL_PROMISC;
2376 ctl &= ~B43_MACCTL_BEACPROMISC;
2377 ctl |= B43_MACCTL_INFRA;
2379 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2380 ctl |= B43_MACCTL_AP;
2381 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2382 ctl &= ~B43_MACCTL_INFRA;
2384 if (wl->filter_flags & FIF_CONTROL)
2385 ctl |= B43_MACCTL_KEEP_CTL;
2386 if (wl->filter_flags & FIF_FCSFAIL)
2387 ctl |= B43_MACCTL_KEEP_BAD;
2388 if (wl->filter_flags & FIF_PLCPFAIL)
2389 ctl |= B43_MACCTL_KEEP_BADPLCP;
2390 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2391 ctl |= B43_MACCTL_PROMISC;
2392 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2393 ctl |= B43_MACCTL_BEACPROMISC;
2395 /* Workaround: On old hardware the HW-MAC-address-filter
2396 * doesn't work properly, so always run promisc in filter
2397 * it in software. */
2398 if (dev->dev->id.revision <= 4)
2399 ctl |= B43_MACCTL_PROMISC;
2401 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2404 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2405 if (dev->dev->bus->chip_id == 0x4306 &&
2406 dev->dev->bus->chip_rev == 3)
2411 b43_write16(dev, 0x612, cfp_pretbtt);
2414 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2420 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2423 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2425 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2426 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2429 static void b43_rate_memory_init(struct b43_wldev *dev)
2431 switch (dev->phy.type) {
2435 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2436 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2437 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2438 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2439 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2440 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2441 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2442 if (dev->phy.type == B43_PHYTYPE_A)
2446 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2447 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2448 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2449 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2456 /* Set the default values for the PHY TX Control Words. */
2457 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2461 ctl |= B43_TXH_PHY_ENC_CCK;
2462 ctl |= B43_TXH_PHY_ANT01AUTO;
2463 ctl |= B43_TXH_PHY_TXPWR;
2465 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2466 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2467 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2470 /* Set the TX-Antenna for management frames sent by firmware. */
2471 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2476 ant = b43_antenna_to_phyctl(antenna);
2479 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2480 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2481 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2482 /* For Probe Resposes */
2483 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2484 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2485 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2488 /* This is the opposite of b43_chip_init() */
2489 static void b43_chip_exit(struct b43_wldev *dev)
2491 b43_radio_turn_off(dev, 1);
2492 b43_gpio_cleanup(dev);
2493 b43_lo_g_cleanup(dev);
2494 /* firmware is released later */
2497 /* Initialize the chip
2498 * http://bcm-specs.sipsolutions.net/ChipInit
2500 static int b43_chip_init(struct b43_wldev *dev)
2502 struct b43_phy *phy = &dev->phy;
2504 u32 value32, macctl;
2507 /* Initialize the MAC control */
2508 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2510 macctl |= B43_MACCTL_GMODE;
2511 macctl |= B43_MACCTL_INFRA;
2512 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2514 err = b43_request_firmware(dev);
2517 err = b43_upload_microcode(dev);
2519 goto out; /* firmware is released later */
2521 err = b43_gpio_init(dev);
2523 goto out; /* firmware is released later */
2525 err = b43_upload_initvals(dev);
2527 goto err_gpio_clean;
2528 b43_radio_turn_on(dev);
2530 b43_write16(dev, 0x03E6, 0x0000);
2531 err = b43_phy_init(dev);
2535 /* Select initial Interference Mitigation. */
2536 tmp = phy->interfmode;
2537 phy->interfmode = B43_INTERFMODE_NONE;
2538 b43_radio_set_interference_mitigation(dev, tmp);
2540 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2541 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2543 if (phy->type == B43_PHYTYPE_B) {
2544 value16 = b43_read16(dev, 0x005E);
2546 b43_write16(dev, 0x005E, value16);
2548 b43_write32(dev, 0x0100, 0x01000000);
2549 if (dev->dev->id.revision < 5)
2550 b43_write32(dev, 0x010C, 0x01000000);
2552 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2553 & ~B43_MACCTL_INFRA);
2554 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2555 | B43_MACCTL_INFRA);
2557 /* Probe Response Timeout value */
2558 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2559 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2561 /* Initially set the wireless operation mode. */
2562 b43_adjust_opmode(dev);
2564 if (dev->dev->id.revision < 3) {
2565 b43_write16(dev, 0x060E, 0x0000);
2566 b43_write16(dev, 0x0610, 0x8000);
2567 b43_write16(dev, 0x0604, 0x0000);
2568 b43_write16(dev, 0x0606, 0x0200);
2570 b43_write32(dev, 0x0188, 0x80000000);
2571 b43_write32(dev, 0x018C, 0x02000000);
2573 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2574 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2575 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2576 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2577 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2578 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2579 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2581 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2582 value32 |= 0x00100000;
2583 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2585 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2586 dev->dev->bus->chipco.fast_pwrup_delay);
2589 b43dbg(dev->wl, "Chip initialized\n");
2594 b43_radio_turn_off(dev, 1);
2596 b43_gpio_cleanup(dev);
2600 static void b43_periodic_every60sec(struct b43_wldev *dev)
2602 struct b43_phy *phy = &dev->phy;
2604 if (phy->type != B43_PHYTYPE_G)
2606 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2607 b43_mac_suspend(dev);
2608 b43_calc_nrssi_slope(dev);
2609 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2610 u8 old_chan = phy->channel;
2612 /* VCO Calibration */
2614 b43_radio_selectchannel(dev, 1, 0);
2616 b43_radio_selectchannel(dev, 13, 0);
2617 b43_radio_selectchannel(dev, old_chan, 0);
2619 b43_mac_enable(dev);
2623 static void b43_periodic_every30sec(struct b43_wldev *dev)
2625 /* Update device statistics. */
2626 b43_calculate_link_quality(dev);
2629 static void b43_periodic_every15sec(struct b43_wldev *dev)
2631 struct b43_phy *phy = &dev->phy;
2633 if (phy->type == B43_PHYTYPE_G) {
2634 //TODO: update_aci_moving_average
2635 if (phy->aci_enable && phy->aci_wlan_automatic) {
2636 b43_mac_suspend(dev);
2637 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2638 if (0 /*TODO: bunch of conditions */ ) {
2639 b43_radio_set_interference_mitigation
2640 (dev, B43_INTERFMODE_MANUALWLAN);
2642 } else if (1 /*TODO*/) {
2644 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2645 b43_radio_set_interference_mitigation(dev,
2646 B43_INTERFMODE_NONE);
2650 b43_mac_enable(dev);
2651 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2653 //TODO: implement rev1 workaround
2656 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2657 b43_lo_g_maintanance_work(dev);
2658 //TODO for APHY (temperature?)
2660 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2664 static void do_periodic_work(struct b43_wldev *dev)
2668 state = dev->periodic_state;
2670 b43_periodic_every60sec(dev);
2672 b43_periodic_every30sec(dev);
2673 b43_periodic_every15sec(dev);
2676 /* Periodic work locking policy:
2677 * The whole periodic work handler is protected by
2678 * wl->mutex. If another lock is needed somewhere in the
2679 * pwork callchain, it's aquired in-place, where it's needed.
2681 static void b43_periodic_work_handler(struct work_struct *work)
2683 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2684 periodic_work.work);
2685 struct b43_wl *wl = dev->wl;
2686 unsigned long delay;
2688 mutex_lock(&wl->mutex);
2690 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2692 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2695 do_periodic_work(dev);
2697 dev->periodic_state++;
2699 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2700 delay = msecs_to_jiffies(50);
2702 delay = round_jiffies_relative(HZ * 15);
2703 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2705 mutex_unlock(&wl->mutex);
2708 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2710 struct delayed_work *work = &dev->periodic_work;
2712 dev->periodic_state = 0;
2713 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2714 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2717 /* Check if communication with the device works correctly. */
2718 static int b43_validate_chipaccess(struct b43_wldev *dev)
2722 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2724 /* Check for read/write and endianness problems. */
2725 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2726 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2728 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2729 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2732 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2734 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2735 /* The 32bit register shadows the two 16bit registers
2736 * with update sideeffects. Validate this. */
2737 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2738 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2739 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2741 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2744 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2746 v = b43_read32(dev, B43_MMIO_MACCTL);
2747 v |= B43_MACCTL_GMODE;
2748 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2753 b43err(dev->wl, "Failed to validate the chipaccess\n");
2757 static void b43_security_init(struct b43_wldev *dev)
2759 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2760 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2761 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2762 /* KTP is a word address, but we address SHM bytewise.
2763 * So multiply by two.
2766 if (dev->dev->id.revision >= 5) {
2767 /* Number of RCMTA address slots */
2768 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2770 b43_clear_keys(dev);
2773 static int b43_rng_read(struct hwrng *rng, u32 * data)
2775 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2776 unsigned long flags;
2778 /* Don't take wl->mutex here, as it could deadlock with
2779 * hwrng internal locking. It's not needed to take
2780 * wl->mutex here, anyway. */
2782 spin_lock_irqsave(&wl->irq_lock, flags);
2783 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2784 spin_unlock_irqrestore(&wl->irq_lock, flags);
2786 return (sizeof(u16));
2789 static void b43_rng_exit(struct b43_wl *wl)
2791 if (wl->rng_initialized)
2792 hwrng_unregister(&wl->rng);
2795 static int b43_rng_init(struct b43_wl *wl)
2799 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2800 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2801 wl->rng.name = wl->rng_name;
2802 wl->rng.data_read = b43_rng_read;
2803 wl->rng.priv = (unsigned long)wl;
2804 wl->rng_initialized = 1;
2805 err = hwrng_register(&wl->rng);
2807 wl->rng_initialized = 0;
2808 b43err(wl, "Failed to register the random "
2809 "number generator (%d)\n", err);
2815 static int b43_op_tx(struct ieee80211_hw *hw,
2816 struct sk_buff *skb,
2817 struct ieee80211_tx_control *ctl)
2819 struct b43_wl *wl = hw_to_b43_wl(hw);
2820 struct b43_wldev *dev = wl->current_dev;
2821 unsigned long flags;
2824 if (unlikely(skb->len < 2 + 2 + 6)) {
2825 /* Too short, this can't be a valid frame. */
2826 dev_kfree_skb_any(skb);
2827 return NETDEV_TX_OK;
2829 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2831 return NETDEV_TX_BUSY;
2833 /* Transmissions on seperate queues can run concurrently. */
2834 read_lock_irqsave(&wl->tx_lock, flags);
2837 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2838 if (b43_using_pio_transfers(dev))
2839 err = b43_pio_tx(dev, skb, ctl);
2841 err = b43_dma_tx(dev, skb, ctl);
2844 read_unlock_irqrestore(&wl->tx_lock, flags);
2847 return NETDEV_TX_BUSY;
2848 return NETDEV_TX_OK;
2851 /* Locking: wl->irq_lock */
2852 static void b43_qos_params_upload(struct b43_wldev *dev,
2853 const struct ieee80211_tx_queue_params *p,
2856 u16 params[B43_NR_QOSPARAMS];
2857 int cw_min, cw_max, aifs, bslots, tmp;
2860 const u16 aCWmin = 0x0001;
2861 const u16 aCWmax = 0x03FF;
2863 /* Calculate the default values for the parameters, if needed. */
2864 switch (shm_offset) {
2866 aifs = (p->aifs == -1) ? 2 : p->aifs;
2867 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2868 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2871 aifs = (p->aifs == -1) ? 2 : p->aifs;
2872 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2873 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2875 case B43_QOS_BESTEFFORT:
2876 aifs = (p->aifs == -1) ? 3 : p->aifs;
2877 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2878 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2880 case B43_QOS_BACKGROUND:
2881 aifs = (p->aifs == -1) ? 7 : p->aifs;
2882 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2883 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2893 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2895 memset(¶ms, 0, sizeof(params));
2897 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2898 params[B43_QOSPARAM_CWMIN] = cw_min;
2899 params[B43_QOSPARAM_CWMAX] = cw_max;
2900 params[B43_QOSPARAM_CWCUR] = cw_min;
2901 params[B43_QOSPARAM_AIFS] = aifs;
2902 params[B43_QOSPARAM_BSLOTS] = bslots;
2903 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2905 for (i = 0; i < ARRAY_SIZE(params); i++) {
2906 if (i == B43_QOSPARAM_STATUS) {
2907 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2908 shm_offset + (i * 2));
2909 /* Mark the parameters as updated. */
2911 b43_shm_write16(dev, B43_SHM_SHARED,
2912 shm_offset + (i * 2),
2915 b43_shm_write16(dev, B43_SHM_SHARED,
2916 shm_offset + (i * 2),
2922 /* Update the QOS parameters in hardware. */
2923 static void b43_qos_update(struct b43_wldev *dev)
2925 struct b43_wl *wl = dev->wl;
2926 struct b43_qos_params *params;
2927 unsigned long flags;
2930 /* Mapping of mac80211 queues to b43 SHM offsets. */
2931 static const u16 qos_shm_offsets[] = {
2932 [0] = B43_QOS_VOICE,
2933 [1] = B43_QOS_VIDEO,
2934 [2] = B43_QOS_BESTEFFORT,
2935 [3] = B43_QOS_BACKGROUND,
2937 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
2939 b43_mac_suspend(dev);
2940 spin_lock_irqsave(&wl->irq_lock, flags);
2942 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2943 params = &(wl->qos_params[i]);
2944 if (params->need_hw_update) {
2945 b43_qos_params_upload(dev, &(params->p),
2946 qos_shm_offsets[i]);
2947 params->need_hw_update = 0;
2951 spin_unlock_irqrestore(&wl->irq_lock, flags);
2952 b43_mac_enable(dev);
2955 static void b43_qos_clear(struct b43_wl *wl)
2957 struct b43_qos_params *params;
2960 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2961 params = &(wl->qos_params[i]);
2963 memset(&(params->p), 0, sizeof(params->p));
2964 params->p.aifs = -1;
2965 params->need_hw_update = 1;
2969 /* Initialize the core's QOS capabilities */
2970 static void b43_qos_init(struct b43_wldev *dev)
2972 struct b43_wl *wl = dev->wl;
2975 /* Upload the current QOS parameters. */
2976 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
2977 wl->qos_params[i].need_hw_update = 1;
2978 b43_qos_update(dev);
2980 /* Enable QOS support. */
2981 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
2982 b43_write16(dev, B43_MMIO_IFSCTL,
2983 b43_read16(dev, B43_MMIO_IFSCTL)
2984 | B43_MMIO_IFSCTL_USE_EDCF);
2987 static void b43_qos_update_work(struct work_struct *work)
2989 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
2990 struct b43_wldev *dev;
2992 mutex_lock(&wl->mutex);
2993 dev = wl->current_dev;
2994 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
2995 b43_qos_update(dev);
2996 mutex_unlock(&wl->mutex);
2999 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3001 const struct ieee80211_tx_queue_params *params)
3003 struct b43_wl *wl = hw_to_b43_wl(hw);
3004 unsigned long flags;
3005 unsigned int queue = (unsigned int)_queue;
3006 struct b43_qos_params *p;
3008 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3009 /* Queue not available or don't support setting
3010 * params on this queue. Return success to not
3011 * confuse mac80211. */
3015 spin_lock_irqsave(&wl->irq_lock, flags);
3016 p = &(wl->qos_params[queue]);
3017 memcpy(&(p->p), params, sizeof(p->p));
3018 p->need_hw_update = 1;
3019 spin_unlock_irqrestore(&wl->irq_lock, flags);
3021 queue_work(hw->workqueue, &wl->qos_update_work);
3026 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3027 struct ieee80211_tx_queue_stats *stats)
3029 struct b43_wl *wl = hw_to_b43_wl(hw);
3030 struct b43_wldev *dev = wl->current_dev;
3031 unsigned long flags;
3036 spin_lock_irqsave(&wl->irq_lock, flags);
3037 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3038 if (b43_using_pio_transfers(dev))
3039 b43_pio_get_tx_stats(dev, stats);
3041 b43_dma_get_tx_stats(dev, stats);
3044 spin_unlock_irqrestore(&wl->irq_lock, flags);
3049 static int b43_op_get_stats(struct ieee80211_hw *hw,
3050 struct ieee80211_low_level_stats *stats)
3052 struct b43_wl *wl = hw_to_b43_wl(hw);
3053 unsigned long flags;
3055 spin_lock_irqsave(&wl->irq_lock, flags);
3056 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3057 spin_unlock_irqrestore(&wl->irq_lock, flags);
3062 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3064 struct ssb_device *sdev = dev->dev;
3067 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3068 tmslow &= ~B43_TMSLOW_GMODE;
3069 tmslow |= B43_TMSLOW_PHYRESET;
3070 tmslow |= SSB_TMSLOW_FGC;
3071 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3074 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3075 tmslow &= ~SSB_TMSLOW_FGC;
3076 tmslow |= B43_TMSLOW_PHYRESET;
3077 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3081 static const char * band_to_string(enum ieee80211_band band)
3084 case IEEE80211_BAND_5GHZ:
3086 case IEEE80211_BAND_2GHZ:
3095 /* Expects wl->mutex locked */
3096 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3098 struct b43_wldev *up_dev = NULL;
3099 struct b43_wldev *down_dev;
3100 struct b43_wldev *d;
3105 /* Find a device and PHY which supports the band. */
3106 list_for_each_entry(d, &wl->devlist, list) {
3107 switch (chan->band) {
3108 case IEEE80211_BAND_5GHZ:
3109 if (d->phy.supports_5ghz) {
3114 case IEEE80211_BAND_2GHZ:
3115 if (d->phy.supports_2ghz) {
3128 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3129 band_to_string(chan->band));
3132 if ((up_dev == wl->current_dev) &&
3133 (!!wl->current_dev->phy.gmode == !!gmode)) {
3134 /* This device is already running. */
3137 b43dbg(wl, "Switching to %s-GHz band\n",
3138 band_to_string(chan->band));
3139 down_dev = wl->current_dev;
3141 prev_status = b43_status(down_dev);
3142 /* Shutdown the currently running core. */
3143 if (prev_status >= B43_STAT_STARTED)
3144 b43_wireless_core_stop(down_dev);
3145 if (prev_status >= B43_STAT_INITIALIZED)
3146 b43_wireless_core_exit(down_dev);
3148 if (down_dev != up_dev) {
3149 /* We switch to a different core, so we put PHY into
3150 * RESET on the old core. */
3151 b43_put_phy_into_reset(down_dev);
3154 /* Now start the new core. */
3155 up_dev->phy.gmode = gmode;
3156 if (prev_status >= B43_STAT_INITIALIZED) {
3157 err = b43_wireless_core_init(up_dev);
3159 b43err(wl, "Fatal: Could not initialize device for "
3160 "selected %s-GHz band\n",
3161 band_to_string(chan->band));
3165 if (prev_status >= B43_STAT_STARTED) {
3166 err = b43_wireless_core_start(up_dev);
3168 b43err(wl, "Fatal: Coult not start device for "
3169 "selected %s-GHz band\n",
3170 band_to_string(chan->band));
3171 b43_wireless_core_exit(up_dev);
3175 B43_WARN_ON(b43_status(up_dev) != prev_status);
3177 wl->current_dev = up_dev;
3181 /* Whoops, failed to init the new core. No core is operating now. */
3182 wl->current_dev = NULL;
3186 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3188 struct b43_wl *wl = hw_to_b43_wl(hw);
3189 struct b43_wldev *dev;
3190 struct b43_phy *phy;
3191 unsigned long flags;
3196 mutex_lock(&wl->mutex);
3198 /* Switch the band (if necessary). This might change the active core. */
3199 err = b43_switch_band(wl, conf->channel);
3201 goto out_unlock_mutex;
3202 dev = wl->current_dev;
3205 /* Disable IRQs while reconfiguring the device.
3206 * This makes it possible to drop the spinlock throughout
3207 * the reconfiguration process. */
3208 spin_lock_irqsave(&wl->irq_lock, flags);
3209 if (b43_status(dev) < B43_STAT_STARTED) {
3210 spin_unlock_irqrestore(&wl->irq_lock, flags);
3211 goto out_unlock_mutex;
3213 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3214 spin_unlock_irqrestore(&wl->irq_lock, flags);
3215 b43_synchronize_irq(dev);
3217 /* Switch to the requested channel.
3218 * The firmware takes care of races with the TX handler. */
3219 if (conf->channel->hw_value != phy->channel)
3220 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
3222 /* Enable/Disable ShortSlot timing. */
3223 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3225 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3226 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3227 b43_short_slot_timing_enable(dev);
3229 b43_short_slot_timing_disable(dev);
3232 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3234 /* Adjust the desired TX power level. */
3235 if (conf->power_level != 0) {
3236 if (conf->power_level != phy->power_level) {
3237 phy->power_level = conf->power_level;
3238 b43_phy_xmitpower(dev);
3242 /* Antennas for RX and management frame TX. */
3243 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3244 b43_mgmtframe_txantenna(dev, antenna);
3245 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3246 b43_set_rx_antenna(dev, antenna);
3248 /* Update templates for AP mode. */
3249 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3250 b43_set_beacon_int(dev, conf->beacon_int);
3252 if (!!conf->radio_enabled != phy->radio_on) {
3253 if (conf->radio_enabled) {
3254 b43_radio_turn_on(dev);
3255 b43info(dev->wl, "Radio turned on by software\n");
3256 if (!dev->radio_hw_enable) {
3257 b43info(dev->wl, "The hardware RF-kill button "
3258 "still turns the radio physically off. "
3259 "Press the button to turn it on.\n");
3262 b43_radio_turn_off(dev, 0);
3263 b43info(dev->wl, "Radio turned off by software\n");
3267 spin_lock_irqsave(&wl->irq_lock, flags);
3268 b43_interrupt_enable(dev, savedirqs);
3270 spin_unlock_irqrestore(&wl->irq_lock, flags);
3272 mutex_unlock(&wl->mutex);
3277 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3278 const u8 *local_addr, const u8 *addr,
3279 struct ieee80211_key_conf *key)
3281 struct b43_wl *wl = hw_to_b43_wl(hw);
3282 struct b43_wldev *dev;
3283 unsigned long flags;
3287 DECLARE_MAC_BUF(mac);
3289 if (modparam_nohwcrypt)
3290 return -ENOSPC; /* User disabled HW-crypto */
3292 mutex_lock(&wl->mutex);
3293 spin_lock_irqsave(&wl->irq_lock, flags);
3295 dev = wl->current_dev;
3297 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3303 if (key->keylen == 5)
3304 algorithm = B43_SEC_ALGO_WEP40;
3306 algorithm = B43_SEC_ALGO_WEP104;
3309 algorithm = B43_SEC_ALGO_TKIP;
3312 algorithm = B43_SEC_ALGO_AES;
3318 index = (u8) (key->keyidx);
3324 if (algorithm == B43_SEC_ALGO_TKIP) {
3325 /* FIXME: No TKIP hardware encryption for now. */
3330 if (is_broadcast_ether_addr(addr)) {
3331 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3332 err = b43_key_write(dev, index, algorithm,
3333 key->key, key->keylen, NULL, key);
3336 * either pairwise key or address is 00:00:00:00:00:00
3337 * for transmit-only keys
3339 err = b43_key_write(dev, -1, algorithm,
3340 key->key, key->keylen, addr, key);
3345 if (algorithm == B43_SEC_ALGO_WEP40 ||
3346 algorithm == B43_SEC_ALGO_WEP104) {
3347 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3350 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3352 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3355 err = b43_key_clear(dev, key->hw_key_idx);
3364 spin_unlock_irqrestore(&wl->irq_lock, flags);
3365 mutex_unlock(&wl->mutex);
3367 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3369 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3370 print_mac(mac, addr));
3375 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3376 unsigned int changed, unsigned int *fflags,
3377 int mc_count, struct dev_addr_list *mc_list)
3379 struct b43_wl *wl = hw_to_b43_wl(hw);
3380 struct b43_wldev *dev = wl->current_dev;
3381 unsigned long flags;
3388 spin_lock_irqsave(&wl->irq_lock, flags);
3389 *fflags &= FIF_PROMISC_IN_BSS |
3395 FIF_BCN_PRBRESP_PROMISC;
3397 changed &= FIF_PROMISC_IN_BSS |
3403 FIF_BCN_PRBRESP_PROMISC;
3405 wl->filter_flags = *fflags;
3407 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3408 b43_adjust_opmode(dev);
3409 spin_unlock_irqrestore(&wl->irq_lock, flags);
3412 static int b43_op_config_interface(struct ieee80211_hw *hw,
3413 struct ieee80211_vif *vif,
3414 struct ieee80211_if_conf *conf)
3416 struct b43_wl *wl = hw_to_b43_wl(hw);
3417 struct b43_wldev *dev = wl->current_dev;
3418 unsigned long flags;
3422 mutex_lock(&wl->mutex);
3423 spin_lock_irqsave(&wl->irq_lock, flags);
3424 B43_WARN_ON(wl->vif != vif);
3426 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3428 memset(wl->bssid, 0, ETH_ALEN);
3429 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3430 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3431 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3432 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3434 b43_update_templates(wl, conf->beacon,
3435 conf->beacon_control);
3438 b43_write_mac_bssid_templates(dev);
3440 spin_unlock_irqrestore(&wl->irq_lock, flags);
3441 mutex_unlock(&wl->mutex);
3446 /* Locking: wl->mutex */
3447 static void b43_wireless_core_stop(struct b43_wldev *dev)
3449 struct b43_wl *wl = dev->wl;
3450 unsigned long flags;
3452 if (b43_status(dev) < B43_STAT_STARTED)
3455 /* Disable and sync interrupts. We must do this before than
3456 * setting the status to INITIALIZED, as the interrupt handler
3457 * won't care about IRQs then. */
3458 spin_lock_irqsave(&wl->irq_lock, flags);
3459 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3460 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3461 spin_unlock_irqrestore(&wl->irq_lock, flags);
3462 b43_synchronize_irq(dev);
3464 write_lock_irqsave(&wl->tx_lock, flags);
3465 b43_set_status(dev, B43_STAT_INITIALIZED);
3466 write_unlock_irqrestore(&wl->tx_lock, flags);
3469 mutex_unlock(&wl->mutex);
3470 /* Must unlock as it would otherwise deadlock. No races here.
3471 * Cancel the possibly running self-rearming periodic work. */
3472 cancel_delayed_work_sync(&dev->periodic_work);
3473 mutex_lock(&wl->mutex);
3475 b43_mac_suspend(dev);
3476 free_irq(dev->dev->irq, dev);
3477 b43dbg(wl, "Wireless interface stopped\n");
3480 /* Locking: wl->mutex */
3481 static int b43_wireless_core_start(struct b43_wldev *dev)
3485 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3487 drain_txstatus_queue(dev);
3488 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3489 IRQF_SHARED, KBUILD_MODNAME, dev);
3491 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3495 /* We are ready to run. */
3496 b43_set_status(dev, B43_STAT_STARTED);
3498 /* Start data flow (TX/RX). */
3499 b43_mac_enable(dev);
3500 b43_interrupt_enable(dev, dev->irq_savedstate);
3501 ieee80211_start_queues(dev->wl->hw);
3503 /* Start maintainance work */
3504 b43_periodic_tasks_setup(dev);
3506 b43dbg(dev->wl, "Wireless interface started\n");
3511 /* Get PHY and RADIO versioning numbers */
3512 static int b43_phy_versioning(struct b43_wldev *dev)
3514 struct b43_phy *phy = &dev->phy;
3522 int unsupported = 0;
3524 /* Get PHY versioning */
3525 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3526 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3527 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3528 phy_rev = (tmp & B43_PHYVER_VERSION);
3535 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3543 #ifdef CONFIG_B43_NPHY
3553 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3554 "(Analog %u, Type %u, Revision %u)\n",
3555 analog_type, phy_type, phy_rev);
3558 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3559 analog_type, phy_type, phy_rev);
3561 /* Get RADIO versioning */
3562 if (dev->dev->bus->chip_id == 0x4317) {
3563 if (dev->dev->bus->chip_rev == 0)
3565 else if (dev->dev->bus->chip_rev == 1)
3570 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3571 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3572 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3573 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3575 radio_manuf = (tmp & 0x00000FFF);
3576 radio_ver = (tmp & 0x0FFFF000) >> 12;
3577 radio_rev = (tmp & 0xF0000000) >> 28;
3578 if (radio_manuf != 0x17F /* Broadcom */)
3582 if (radio_ver != 0x2060)
3586 if (radio_manuf != 0x17F)
3590 if ((radio_ver & 0xFFF0) != 0x2050)
3594 if (radio_ver != 0x2050)
3598 if (radio_ver != 0x2055)
3605 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3606 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3607 radio_manuf, radio_ver, radio_rev);
3610 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3611 radio_manuf, radio_ver, radio_rev);
3613 phy->radio_manuf = radio_manuf;
3614 phy->radio_ver = radio_ver;
3615 phy->radio_rev = radio_rev;
3617 phy->analog = analog_type;
3618 phy->type = phy_type;
3624 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3625 struct b43_phy *phy)
3627 struct b43_txpower_lo_control *lo;
3630 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3631 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3633 phy->aci_enable = 0;
3634 phy->aci_wlan_automatic = 0;
3635 phy->aci_hw_rssi = 0;
3637 phy->radio_off_context.valid = 0;
3639 lo = phy->lo_control;
3641 memset(lo, 0, sizeof(*(phy->lo_control)));
3643 INIT_LIST_HEAD(&lo->calib_list);
3645 phy->max_lb_gain = 0;
3646 phy->trsw_rx_gain = 0;
3647 phy->txpwr_offset = 0;
3650 phy->nrssislope = 0;
3651 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3652 phy->nrssi[i] = -1000;
3653 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3654 phy->nrssi_lt[i] = i;
3656 phy->lofcal = 0xFFFF;
3657 phy->initval = 0xFFFF;
3659 phy->interfmode = B43_INTERFMODE_NONE;
3660 phy->channel = 0xFF;
3662 phy->hardware_power_control = !!modparam_hwpctl;
3664 /* PHY TX errors counter. */
3665 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3667 /* OFDM-table address caching. */
3668 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3671 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3675 /* Assume the radio is enabled. If it's not enabled, the state will
3676 * immediately get fixed on the first periodic work run. */
3677 dev->radio_hw_enable = 1;
3680 memset(&dev->stats, 0, sizeof(dev->stats));
3682 setup_struct_phy_for_init(dev, &dev->phy);
3684 /* IRQ related flags */
3685 dev->irq_reason = 0;
3686 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3687 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3689 dev->mac_suspended = 1;
3691 /* Noise calculation context */
3692 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3695 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3697 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3700 if (!modparam_btcoex)
3702 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3704 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3707 hf = b43_hf_read(dev);
3708 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3709 hf |= B43_HF_BTCOEXALT;
3711 hf |= B43_HF_BTCOEX;
3712 b43_hf_write(dev, hf);
3715 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3717 if (!modparam_btcoex)
3722 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3724 #ifdef CONFIG_SSB_DRIVER_PCICORE
3725 struct ssb_bus *bus = dev->dev->bus;
3728 if (bus->pcicore.dev &&
3729 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3730 bus->pcicore.dev->id.revision <= 5) {
3731 /* IMCFGLO timeouts workaround. */
3732 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3733 tmp &= ~SSB_IMCFGLO_REQTO;
3734 tmp &= ~SSB_IMCFGLO_SERTO;
3735 switch (bus->bustype) {
3736 case SSB_BUSTYPE_PCI:
3737 case SSB_BUSTYPE_PCMCIA:
3740 case SSB_BUSTYPE_SSB:
3744 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3746 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3749 /* Write the short and long frame retry limit values. */
3750 static void b43_set_retry_limits(struct b43_wldev *dev,
3751 unsigned int short_retry,
3752 unsigned int long_retry)
3754 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3755 * the chip-internal counter. */
3756 short_retry = min(short_retry, (unsigned int)0xF);
3757 long_retry = min(long_retry, (unsigned int)0xF);
3759 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3761 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3765 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3769 /* The time value is in microseconds. */
3770 if (dev->phy.type == B43_PHYTYPE_A)
3774 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
3776 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3777 pu_delay = max(pu_delay, (u16)2400);
3779 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3782 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3783 static void b43_set_pretbtt(struct b43_wldev *dev)
3787 /* The time value is in microseconds. */
3788 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
3791 if (dev->phy.type == B43_PHYTYPE_A)
3796 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3797 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3800 /* Shutdown a wireless core */
3801 /* Locking: wl->mutex */
3802 static void b43_wireless_core_exit(struct b43_wldev *dev)
3804 struct b43_phy *phy = &dev->phy;
3807 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3808 if (b43_status(dev) != B43_STAT_INITIALIZED)
3810 b43_set_status(dev, B43_STAT_UNINIT);
3812 /* Stop the microcode PSM. */
3813 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3814 macctl &= ~B43_MACCTL_PSM_RUN;
3815 macctl |= B43_MACCTL_PSM_JMP0;
3816 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3818 if (!dev->suspend_in_progress) {
3820 b43_rng_exit(dev->wl);
3825 b43_radio_turn_off(dev, 1);
3826 b43_switch_analog(dev, 0);
3827 if (phy->dyn_tssi_tbl)
3828 kfree(phy->tssi2dbm);
3829 kfree(phy->lo_control);
3830 phy->lo_control = NULL;
3831 if (dev->wl->current_beacon) {
3832 dev_kfree_skb_any(dev->wl->current_beacon);
3833 dev->wl->current_beacon = NULL;
3836 ssb_device_disable(dev->dev, 0);
3837 ssb_bus_may_powerdown(dev->dev->bus);
3840 /* Initialize a wireless core */
3841 static int b43_wireless_core_init(struct b43_wldev *dev)
3843 struct b43_wl *wl = dev->wl;
3844 struct ssb_bus *bus = dev->dev->bus;
3845 struct ssb_sprom *sprom = &bus->sprom;
3846 struct b43_phy *phy = &dev->phy;
3851 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3853 err = ssb_bus_powerup(bus, 0);
3856 if (!ssb_device_is_enabled(dev->dev)) {
3857 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3858 b43_wireless_core_reset(dev, tmp);
3861 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3863 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3864 if (!phy->lo_control) {
3869 setup_struct_wldev_for_init(dev);
3871 err = b43_phy_init_tssi2dbm_table(dev);
3873 goto err_kfree_lo_control;
3875 /* Enable IRQ routing to this device. */
3876 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3878 b43_imcfglo_timeouts_workaround(dev);
3879 b43_bluetooth_coext_disable(dev);
3880 b43_phy_early_init(dev);
3881 err = b43_chip_init(dev);
3883 goto err_kfree_tssitbl;
3884 b43_shm_write16(dev, B43_SHM_SHARED,
3885 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3886 hf = b43_hf_read(dev);
3887 if (phy->type == B43_PHYTYPE_G) {
3891 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3892 hf |= B43_HF_OFDMPABOOST;
3893 } else if (phy->type == B43_PHYTYPE_B) {
3895 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3898 b43_hf_write(dev, hf);
3900 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3901 B43_DEFAULT_LONG_RETRY_LIMIT);
3902 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3903 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3905 /* Disable sending probe responses from firmware.
3906 * Setting the MaxTime to one usec will always trigger
3907 * a timeout, so we never send any probe resp.
3908 * A timeout of zero is infinite. */
3909 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3911 b43_rate_memory_init(dev);
3912 b43_set_phytxctl_defaults(dev);
3914 /* Minimum Contention Window */
3915 if (phy->type == B43_PHYTYPE_B) {
3916 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3918 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3920 /* Maximum Contention Window */
3921 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3923 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3924 dev->__using_pio_transfers = 1;
3925 err = b43_pio_init(dev);
3927 dev->__using_pio_transfers = 0;
3928 err = b43_dma_init(dev);
3933 b43_set_synth_pu_delay(dev, 1);
3934 b43_bluetooth_coext_enable(dev);
3936 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3937 b43_upload_card_macaddress(dev);
3938 b43_security_init(dev);
3939 if (!dev->suspend_in_progress)
3942 b43_set_status(dev, B43_STAT_INITIALIZED);
3944 if (!dev->suspend_in_progress)
3952 if (phy->dyn_tssi_tbl)
3953 kfree(phy->tssi2dbm);
3954 err_kfree_lo_control:
3955 kfree(phy->lo_control);
3956 phy->lo_control = NULL;
3958 ssb_bus_may_powerdown(bus);
3959 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3963 static int b43_op_add_interface(struct ieee80211_hw *hw,
3964 struct ieee80211_if_init_conf *conf)
3966 struct b43_wl *wl = hw_to_b43_wl(hw);
3967 struct b43_wldev *dev;
3968 unsigned long flags;
3969 int err = -EOPNOTSUPP;
3971 /* TODO: allow WDS/AP devices to coexist */
3973 if (conf->type != IEEE80211_IF_TYPE_AP &&
3974 conf->type != IEEE80211_IF_TYPE_STA &&
3975 conf->type != IEEE80211_IF_TYPE_WDS &&
3976 conf->type != IEEE80211_IF_TYPE_IBSS)
3979 mutex_lock(&wl->mutex);
3981 goto out_mutex_unlock;
3983 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3985 dev = wl->current_dev;
3987 wl->vif = conf->vif;
3988 wl->if_type = conf->type;
3989 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3991 spin_lock_irqsave(&wl->irq_lock, flags);
3992 b43_adjust_opmode(dev);
3993 b43_set_pretbtt(dev);
3994 b43_set_synth_pu_delay(dev, 0);
3995 b43_upload_card_macaddress(dev);
3996 spin_unlock_irqrestore(&wl->irq_lock, flags);
4000 mutex_unlock(&wl->mutex);
4005 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4006 struct ieee80211_if_init_conf *conf)
4008 struct b43_wl *wl = hw_to_b43_wl(hw);
4009 struct b43_wldev *dev = wl->current_dev;
4010 unsigned long flags;
4012 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4014 mutex_lock(&wl->mutex);
4016 B43_WARN_ON(!wl->operating);
4017 B43_WARN_ON(wl->vif != conf->vif);
4022 spin_lock_irqsave(&wl->irq_lock, flags);
4023 b43_adjust_opmode(dev);
4024 memset(wl->mac_addr, 0, ETH_ALEN);
4025 b43_upload_card_macaddress(dev);
4026 spin_unlock_irqrestore(&wl->irq_lock, flags);
4028 mutex_unlock(&wl->mutex);
4031 static int b43_op_start(struct ieee80211_hw *hw)
4033 struct b43_wl *wl = hw_to_b43_wl(hw);
4034 struct b43_wldev *dev = wl->current_dev;
4037 bool do_rfkill_exit = 0;
4039 /* Kill all old instance specific information to make sure
4040 * the card won't use it in the short timeframe between start
4041 * and mac80211 reconfiguring it. */
4042 memset(wl->bssid, 0, ETH_ALEN);
4043 memset(wl->mac_addr, 0, ETH_ALEN);
4044 wl->filter_flags = 0;
4045 wl->radiotap_enabled = 0;
4048 /* First register RFkill.
4049 * LEDs that are registered later depend on it. */
4050 b43_rfkill_init(dev);
4052 mutex_lock(&wl->mutex);
4054 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4055 err = b43_wireless_core_init(dev);
4058 goto out_mutex_unlock;
4063 if (b43_status(dev) < B43_STAT_STARTED) {
4064 err = b43_wireless_core_start(dev);
4067 b43_wireless_core_exit(dev);
4069 goto out_mutex_unlock;
4074 mutex_unlock(&wl->mutex);
4077 b43_rfkill_exit(dev);
4082 static void b43_op_stop(struct ieee80211_hw *hw)
4084 struct b43_wl *wl = hw_to_b43_wl(hw);
4085 struct b43_wldev *dev = wl->current_dev;
4087 b43_rfkill_exit(dev);
4088 cancel_work_sync(&(wl->qos_update_work));
4089 cancel_work_sync(&(wl->beacon_update_trigger));
4091 mutex_lock(&wl->mutex);
4092 if (b43_status(dev) >= B43_STAT_STARTED)
4093 b43_wireless_core_stop(dev);
4094 b43_wireless_core_exit(dev);
4095 mutex_unlock(&wl->mutex);
4098 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4099 u32 short_retry_limit, u32 long_retry_limit)
4101 struct b43_wl *wl = hw_to_b43_wl(hw);
4102 struct b43_wldev *dev;
4105 mutex_lock(&wl->mutex);
4106 dev = wl->current_dev;
4107 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4111 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4113 mutex_unlock(&wl->mutex);
4118 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4120 struct b43_wl *wl = hw_to_b43_wl(hw);
4121 struct sk_buff *beacon;
4122 unsigned long flags;
4123 struct ieee80211_tx_control txctl;
4125 /* We could modify the existing beacon and set the aid bit in
4126 * the TIM field, but that would probably require resizing and
4127 * moving of data within the beacon template.
4128 * Simply request a new beacon and let mac80211 do the hard work. */
4129 beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
4130 if (unlikely(!beacon))
4132 spin_lock_irqsave(&wl->irq_lock, flags);
4133 b43_update_templates(wl, beacon, &txctl);
4134 spin_unlock_irqrestore(&wl->irq_lock, flags);
4139 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4140 struct sk_buff *beacon,
4141 struct ieee80211_tx_control *ctl)
4143 struct b43_wl *wl = hw_to_b43_wl(hw);
4144 unsigned long flags;
4146 spin_lock_irqsave(&wl->irq_lock, flags);
4147 b43_update_templates(wl, beacon, ctl);
4148 spin_unlock_irqrestore(&wl->irq_lock, flags);
4153 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4154 struct ieee80211_vif *vif,
4155 enum sta_notify_cmd notify_cmd,
4158 struct b43_wl *wl = hw_to_b43_wl(hw);
4160 B43_WARN_ON(!vif || wl->vif != vif);
4163 static const struct ieee80211_ops b43_hw_ops = {
4165 .conf_tx = b43_op_conf_tx,
4166 .add_interface = b43_op_add_interface,
4167 .remove_interface = b43_op_remove_interface,
4168 .config = b43_op_config,
4169 .config_interface = b43_op_config_interface,
4170 .configure_filter = b43_op_configure_filter,
4171 .set_key = b43_op_set_key,
4172 .get_stats = b43_op_get_stats,
4173 .get_tx_stats = b43_op_get_tx_stats,
4174 .start = b43_op_start,
4175 .stop = b43_op_stop,
4176 .set_retry_limit = b43_op_set_retry_limit,
4177 .set_tim = b43_op_beacon_set_tim,
4178 .beacon_update = b43_op_ibss_beacon_update,
4179 .sta_notify = b43_op_sta_notify,
4182 /* Hard-reset the chip. Do not call this directly.
4183 * Use b43_controller_restart()
4185 static void b43_chip_reset(struct work_struct *work)
4187 struct b43_wldev *dev =
4188 container_of(work, struct b43_wldev, restart_work);
4189 struct b43_wl *wl = dev->wl;
4193 mutex_lock(&wl->mutex);
4195 prev_status = b43_status(dev);
4196 /* Bring the device down... */
4197 if (prev_status >= B43_STAT_STARTED)
4198 b43_wireless_core_stop(dev);
4199 if (prev_status >= B43_STAT_INITIALIZED)
4200 b43_wireless_core_exit(dev);
4202 /* ...and up again. */
4203 if (prev_status >= B43_STAT_INITIALIZED) {
4204 err = b43_wireless_core_init(dev);
4208 if (prev_status >= B43_STAT_STARTED) {
4209 err = b43_wireless_core_start(dev);
4211 b43_wireless_core_exit(dev);
4216 mutex_unlock(&wl->mutex);
4218 b43err(wl, "Controller restart FAILED\n");
4220 b43info(wl, "Controller restarted\n");
4223 static int b43_setup_bands(struct b43_wldev *dev,
4224 bool have_2ghz_phy, bool have_5ghz_phy)
4226 struct ieee80211_hw *hw = dev->wl->hw;
4229 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4230 if (dev->phy.type == B43_PHYTYPE_N) {
4232 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4235 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4238 dev->phy.supports_2ghz = have_2ghz_phy;
4239 dev->phy.supports_5ghz = have_5ghz_phy;
4244 static void b43_wireless_core_detach(struct b43_wldev *dev)
4246 /* We release firmware that late to not be required to re-request
4247 * is all the time when we reinit the core. */
4248 b43_release_firmware(dev);
4251 static int b43_wireless_core_attach(struct b43_wldev *dev)
4253 struct b43_wl *wl = dev->wl;
4254 struct ssb_bus *bus = dev->dev->bus;
4255 struct pci_dev *pdev = bus->host_pci;
4257 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4260 /* Do NOT do any device initialization here.
4261 * Do it in wireless_core_init() instead.
4262 * This function is for gathering basic information about the HW, only.
4263 * Also some structs may be set up here. But most likely you want to have
4264 * that in core_init(), too.
4267 err = ssb_bus_powerup(bus, 0);
4269 b43err(wl, "Bus powerup failed\n");
4272 /* Get the PHY type. */
4273 if (dev->dev->id.revision >= 5) {
4276 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4277 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4278 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4282 dev->phy.gmode = have_2ghz_phy;
4283 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4284 b43_wireless_core_reset(dev, tmp);
4286 err = b43_phy_versioning(dev);
4289 /* Check if this device supports multiband. */
4291 (pdev->device != 0x4312 &&
4292 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4293 /* No multiband support. */
4296 switch (dev->phy.type) {
4308 if (dev->phy.type == B43_PHYTYPE_A) {
4310 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4314 if (1 /* disable A-PHY */) {
4315 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4316 if (dev->phy.type != B43_PHYTYPE_N) {
4322 dev->phy.gmode = have_2ghz_phy;
4323 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4324 b43_wireless_core_reset(dev, tmp);
4326 err = b43_validate_chipaccess(dev);
4329 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4333 /* Now set some default "current_dev" */
4334 if (!wl->current_dev)
4335 wl->current_dev = dev;
4336 INIT_WORK(&dev->restart_work, b43_chip_reset);
4338 b43_radio_turn_off(dev, 1);
4339 b43_switch_analog(dev, 0);
4340 ssb_device_disable(dev->dev, 0);
4341 ssb_bus_may_powerdown(bus);
4347 ssb_bus_may_powerdown(bus);
4351 static void b43_one_core_detach(struct ssb_device *dev)
4353 struct b43_wldev *wldev;
4356 wldev = ssb_get_drvdata(dev);
4358 cancel_work_sync(&wldev->restart_work);
4359 b43_debugfs_remove_device(wldev);
4360 b43_wireless_core_detach(wldev);
4361 list_del(&wldev->list);
4363 ssb_set_drvdata(dev, NULL);
4367 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4369 struct b43_wldev *wldev;
4370 struct pci_dev *pdev;
4373 if (!list_empty(&wl->devlist)) {
4374 /* We are not the first core on this chip. */
4375 pdev = dev->bus->host_pci;
4376 /* Only special chips support more than one wireless
4377 * core, although some of the other chips have more than
4378 * one wireless core as well. Check for this and
4382 ((pdev->device != 0x4321) &&
4383 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4384 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4389 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4395 b43_set_status(wldev, B43_STAT_UNINIT);
4396 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4397 tasklet_init(&wldev->isr_tasklet,
4398 (void (*)(unsigned long))b43_interrupt_tasklet,
4399 (unsigned long)wldev);
4400 INIT_LIST_HEAD(&wldev->list);
4402 err = b43_wireless_core_attach(wldev);
4404 goto err_kfree_wldev;
4406 list_add(&wldev->list, &wl->devlist);
4408 ssb_set_drvdata(dev, wldev);
4409 b43_debugfs_add_device(wldev);
4419 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4420 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4421 (pdev->device == _device) && \
4422 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4423 (pdev->subsystem_device == _subdevice) )
4425 static void b43_sprom_fixup(struct ssb_bus *bus)
4427 struct pci_dev *pdev;
4429 /* boardflags workarounds */
4430 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4431 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4432 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4433 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4434 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4435 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4436 if (bus->bustype == SSB_BUSTYPE_PCI) {
4437 pdev = bus->host_pci;
4438 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4439 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4440 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4441 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4445 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4447 struct ieee80211_hw *hw = wl->hw;
4449 ssb_set_devtypedata(dev, NULL);
4450 ieee80211_free_hw(hw);
4453 static int b43_wireless_init(struct ssb_device *dev)
4455 struct ssb_sprom *sprom = &dev->bus->sprom;
4456 struct ieee80211_hw *hw;
4460 b43_sprom_fixup(dev->bus);
4462 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4464 b43err(NULL, "Could not allocate ieee80211 device\n");
4469 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4470 IEEE80211_HW_RX_INCLUDES_FCS;
4471 hw->max_signal = 100;
4472 hw->max_rssi = -110;
4473 hw->max_noise = -110;
4474 hw->queues = b43_modparam_qos ? 4 : 1;
4475 SET_IEEE80211_DEV(hw, dev->dev);
4476 if (is_valid_ether_addr(sprom->et1mac))
4477 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4479 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4481 /* Get and initialize struct b43_wl */
4482 wl = hw_to_b43_wl(hw);
4483 memset(wl, 0, sizeof(*wl));
4485 spin_lock_init(&wl->irq_lock);
4486 rwlock_init(&wl->tx_lock);
4487 spin_lock_init(&wl->leds_lock);
4488 spin_lock_init(&wl->shm_lock);
4489 mutex_init(&wl->mutex);
4490 INIT_LIST_HEAD(&wl->devlist);
4491 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4492 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4494 ssb_set_devtypedata(dev, wl);
4495 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4501 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4507 wl = ssb_get_devtypedata(dev);
4509 /* Probing the first core. Must setup common struct b43_wl */
4511 err = b43_wireless_init(dev);
4514 wl = ssb_get_devtypedata(dev);
4517 err = b43_one_core_attach(dev, wl);
4519 goto err_wireless_exit;
4522 err = ieee80211_register_hw(wl->hw);
4524 goto err_one_core_detach;
4530 err_one_core_detach:
4531 b43_one_core_detach(dev);
4534 b43_wireless_exit(dev, wl);
4538 static void b43_remove(struct ssb_device *dev)
4540 struct b43_wl *wl = ssb_get_devtypedata(dev);
4541 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4544 if (wl->current_dev == wldev)
4545 ieee80211_unregister_hw(wl->hw);
4547 b43_one_core_detach(dev);
4549 if (list_empty(&wl->devlist)) {
4550 /* Last core on the chip unregistered.
4551 * We can destroy common struct b43_wl.
4553 b43_wireless_exit(dev, wl);
4557 /* Perform a hardware reset. This can be called from any context. */
4558 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4560 /* Must avoid requeueing, if we are in shutdown. */
4561 if (b43_status(dev) < B43_STAT_INITIALIZED)
4563 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4564 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4569 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4571 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4572 struct b43_wl *wl = wldev->wl;
4574 b43dbg(wl, "Suspending...\n");
4576 mutex_lock(&wl->mutex);
4577 wldev->suspend_in_progress = true;
4578 wldev->suspend_init_status = b43_status(wldev);
4579 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4580 b43_wireless_core_stop(wldev);
4581 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4582 b43_wireless_core_exit(wldev);
4583 mutex_unlock(&wl->mutex);
4585 b43dbg(wl, "Device suspended.\n");
4590 static int b43_resume(struct ssb_device *dev)
4592 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4593 struct b43_wl *wl = wldev->wl;
4596 b43dbg(wl, "Resuming...\n");
4598 mutex_lock(&wl->mutex);
4599 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4600 err = b43_wireless_core_init(wldev);
4602 b43err(wl, "Resume failed at core init\n");
4606 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4607 err = b43_wireless_core_start(wldev);
4609 b43_leds_exit(wldev);
4610 b43_rng_exit(wldev->wl);
4611 b43_wireless_core_exit(wldev);
4612 b43err(wl, "Resume failed at core start\n");
4616 b43dbg(wl, "Device resumed.\n");
4618 wldev->suspend_in_progress = false;
4619 mutex_unlock(&wl->mutex);
4623 #else /* CONFIG_PM */
4624 # define b43_suspend NULL
4625 # define b43_resume NULL
4626 #endif /* CONFIG_PM */
4628 static struct ssb_driver b43_ssb_driver = {
4629 .name = KBUILD_MODNAME,
4630 .id_table = b43_ssb_tbl,
4632 .remove = b43_remove,
4633 .suspend = b43_suspend,
4634 .resume = b43_resume,
4637 static void b43_print_driverinfo(void)
4639 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4640 *feat_leds = "", *feat_rfkill = "";
4642 #ifdef CONFIG_B43_PCI_AUTOSELECT
4645 #ifdef CONFIG_B43_PCMCIA
4648 #ifdef CONFIG_B43_NPHY
4651 #ifdef CONFIG_B43_LEDS
4654 #ifdef CONFIG_B43_RFKILL
4657 printk(KERN_INFO "Broadcom 43xx driver loaded "
4658 "[ Features: %s%s%s%s%s, Firmware-ID: "
4659 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4660 feat_pci, feat_pcmcia, feat_nphy,
4661 feat_leds, feat_rfkill);
4664 static int __init b43_init(void)
4669 err = b43_pcmcia_init();
4672 err = ssb_driver_register(&b43_ssb_driver);
4674 goto err_pcmcia_exit;
4675 b43_print_driverinfo();
4686 static void __exit b43_exit(void)
4688 ssb_driver_unregister(&b43_ssb_driver);
4693 module_init(b43_init)
4694 module_exit(b43_exit)