drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         u8 i;
  41         u16 routing;
  42
  43         b43_radio_write(dev, 0x16, e->radio_syn16);
  44         b43_radio_write(dev, 0x17, e->radio_syn17);
  45         b43_radio_write(dev, 0x22, e->radio_syn22);
  46         b43_radio_write(dev, 0x25, e->radio_syn25);
  47         b43_radio_write(dev, 0x27, e->radio_syn27);
  48         b43_radio_write(dev, 0x28, e->radio_syn28);
  49         b43_radio_write(dev, 0x29, e->radio_syn29);
  50         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  51         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  52         b43_radio_write(dev, 0x37, e->radio_syn37);
  53         b43_radio_write(dev, 0x41, e->radio_syn41);
  54         b43_radio_write(dev, 0x43, e->radio_syn43);
  55         b43_radio_write(dev, 0x47, e->radio_syn47);
  56         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  57         b43_radio_write(dev, 0x58, e->radio_syn58);
  58         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  59         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  60         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  61         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  62         b43_radio_write(dev, 0x92, e->radio_syn92);
  63         b43_radio_write(dev, 0x98, e->radio_syn98);
  64
  65         for (i = 0; i < 2; i++) {
  66                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  67                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  68                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  69                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  70                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  71                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  72                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  73                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  74                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  75         }
  76
  77         udelay(50);
  78
  79         /* Calibration */
  80         b43_radio_mask(dev, 0x2b, ~0x1);
  81         b43_radio_mask(dev, 0x2e, ~0x4);
  82         b43_radio_set(dev, 0x2e, 0x4);
  83         b43_radio_set(dev, 0x2b, 0x1);
  84
  85         udelay(300);
  86 }
  87
  88 static void b43_radio_2059_init(struct b43_wldev *dev)
  89 {
  90         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  91         const u16 radio_values[3][2] = {
  92                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  93         };
  94         u16 i, j;
  95
  96         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  97         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  98
  99         for (i = 0; i < ARRAY_SIZE(routing); i++)
 100                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
 101
 102         b43_radio_set(dev, 0x2e, 0x0078);
 103         b43_radio_set(dev, 0xc0, 0x0080);
 104         msleep(2);
 105         b43_radio_mask(dev, 0x2e, ~0x0078);
 106         b43_radio_mask(dev, 0xc0, ~0x0080);
 107
 108         if (1) { /* FIXME */
 109                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
 110                 udelay(10);
 111                 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
 112                 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
 113
 114                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
 115                 udelay(100);
 116                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
 117
 118                 for (i = 0; i < 10000; i++) {
 119                         if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
 120                                 i = 0;
 121                                 break;
 122                         }
 123                         udelay(100);
 124                 }
 125                 if (i)
 126                         b43err(dev->wl, "radio 0x945 timeout\n");
 127
 128                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
 129                 b43_radio_set(dev, 0xa, 0x60);
 130
 131                 for (i = 0; i < 3; i++) {
 132                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 133                         b43_radio_write(dev, 0x13D, 0x6E);
 134                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 135                         b43_radio_write(dev, 0x13C, 0x55);
 136
 137                         for (j = 0; j < 10000; j++) {
 138                                 if (b43_radio_read(dev, 0x140) & 2) {
 139                                         j = 0;
 140                                         break;
 141                                 }
 142                                 udelay(500);
 143                         }
 144                         if (j)
 145                                 b43err(dev->wl, "radio 0x140 timeout\n");
 146
 147                         b43_radio_write(dev, 0x13C, 0x15);
 148                 }
 149
 150                 b43_radio_mask(dev, 0x17F, ~0x1);
 151         }
 152
 153         b43_radio_mask(dev, 0x11, ~0x0008);
 154 }
 155
 156 /**************************************************
 157  * RF
 158  **************************************************/
 159
 160 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 161 {
 162         u8 i;
 163
 164         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 165         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 166
 167         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 168         for (i = 0; i < 200; i++) {
 169                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 170                         i = 0;
 171                         break;
 172                 }
 173                 msleep(1);
 174         }
 175         if (i)
 176                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 177
 178         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 179 }
 180
 181 /**************************************************
 182  * Various PHY ops
 183  **************************************************/
 184
 185 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 186 {
 187         u16 tmp;
 188         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 189                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 190                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 191
 192         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 193         tmp &= allowed;
 194         tmp &= ~mask;
 195         tmp |= (val & mask);
 196         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 197
 198         return tmp;
 199 }
 200
 201 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
 202 {
 203         u16 bbcfg;
 204
 205         b43_phy_force_clock(dev, true);
 206         bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 207         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
 208         udelay(1);
 209         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
 210         b43_phy_force_clock(dev, false);
 211
 212         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 213 }
 214
 215 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 216 {
 217         u8 i, j;
 218         u16 base[] = { 0x40, 0x60, 0x80 };
 219
 220         for (i = 0; i < ARRAY_SIZE(base); i++) {
 221                 for (j = 0; j < 4; j++)
 222                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 223         }
 224
 225         for (i = 0; i < ARRAY_SIZE(base); i++)
 226                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 227 }
 228
 229 /* Some unknown AFE (Analog Frondned) op */
 230 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 231 {
 232         u8 i;
 233
 234         static const u16 ctl_regs[3][2] = {
 235                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 236                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 237                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 238         };
 239
 240         for (i = 0; i < 3; i++) {
 241                 /* TODO: verify masks&sets */
 242                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 243                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 244                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 245                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 246                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 247                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 248         }
 249 }
 250
 251 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 252 {
 253         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 254         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 255         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 256 }
 257
 258 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 259 {
 260         unsigned int i;
 261         u16 val;
 262
 263         val = 0x1E1F;
 264         for (i = 0; i < 16; i++) {
 265                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 266                 val -= 0x202;
 267         }
 268         val = 0x3E3F;
 269         for (i = 0; i < 16; i++) {
 270                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 271                 val -= 0x202;
 272         }
 273         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 274 }
 275
 276 /**************************************************
 277  * Tx/Rx
 278  **************************************************/
 279
 280 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 281 {
 282         int i;
 283
 284         for (i = 0; i < 3; i++) {
 285                 u16 mask;
 286                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 287
 288                 if (0) /* FIXME */
 289                         mask = 0x2 << (i * 4);
 290                 else
 291                         mask = 0;
 292                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 293
 294                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 295                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 296                                 tmp & 0xFF);
 297                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 298                                 tmp & 0xFF);
 299         }
 300 }
 301
 302 /**************************************************
 303  * Channel switching ops.
 304  **************************************************/
 305
 306 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 307                                   struct ieee80211_channel *new_channel)
 308 {
 309         struct bcma_device *core = dev->dev->bdev;
 310         int spuravoid = 0;
 311         u16 tmp;
 312
 313         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 314         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 315                 spuravoid = 1;
 316         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 317         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 318         bcma_core_pll_ctl(core,
 319                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 320                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 321                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 322                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 323
 324         /* Values has been taken from wlc_bmac_switch_macfreq comments */
 325         switch (spuravoid) {
 326         case 2: /* 126MHz */
 327                 tmp = 0x2082;
 328                 break;
 329         case 1: /* 123MHz */
 330                 tmp = 0x5341;
 331                 break;
 332         default: /* 120MHz */
 333                 tmp = 0x8889;
 334         }
 335
 336         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
 337         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
 338
 339         /* TODO: reset PLL */
 340
 341         if (spuravoid)
 342                 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
 343         else
 344                 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
 345                                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
 346
 347         b43_phy_ht_reset_cca(dev);
 348 }
 349
 350 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 351                                 const struct b43_phy_ht_channeltab_e_phy *e,
 352                                 struct ieee80211_channel *new_channel)
 353 {
 354         bool old_band_5ghz;
 355
 356         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 357         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 358                 /* TODO */
 359         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 360                 /* TODO */
 361         }
 362
 363         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 364         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 365         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 366         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 367         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 368         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 369
 370         if (new_channel->hw_value == 14) {
 371                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 372                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 373         } else {
 374                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 375                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 376                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 377                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 378         }
 379
 380         if (1) /* TODO: On N it's for early devices only, what about HT? */
 381                 b43_phy_ht_tx_power_fix(dev);
 382
 383         b43_phy_ht_spur_avoid(dev, new_channel);
 384
 385         b43_phy_write(dev, 0x017e, 0x3830);
 386 }
 387
 388 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 389                                   struct ieee80211_channel *channel,
 390                                   enum nl80211_channel_type channel_type)
 391 {
 392         struct b43_phy *phy = &dev->phy;
 393
 394         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 395
 396         if (phy->radio_ver == 0x2059) {
 397                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 398                                                         channel->center_freq);
 399                 if (!chent_r2059)
 400                         return -ESRCH;
 401         } else {
 402                 return -ESRCH;
 403         }
 404
 405         /* TODO: In case of N-PHY some bandwidth switching goes here */
 406
 407         if (phy->radio_ver == 0x2059) {
 408                 b43_radio_2059_channel_setup(dev, chent_r2059);
 409                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 410                                          channel);
 411         } else {
 412                 return -ESRCH;
 413         }
 414
 415         return 0;
 416 }
 417
 418 /**************************************************
 419  * Basic PHY ops.
 420  **************************************************/
 421
 422 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 423 {
 424         struct b43_phy_ht *phy_ht;
 425
 426         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 427         if (!phy_ht)
 428                 return -ENOMEM;
 429         dev->phy.ht = phy_ht;
 430
 431         return 0;
 432 }
 433
 434 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 435 {
 436         struct b43_phy *phy = &dev->phy;
 437         struct b43_phy_ht *phy_ht = phy->ht;
 438
 439         memset(phy_ht, 0, sizeof(*phy_ht));
 440 }
 441
 442 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 443 {
 444         u16 tmp;
 445         u16 clip_state[3];
 446
 447         if (dev->dev->bus_type != B43_BUS_BCMA) {
 448                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 449                 return -EOPNOTSUPP;
 450         }
 451
 452         b43_phy_ht_tables_init(dev);
 453
 454         b43_phy_mask(dev, 0x0be, ~0x2);
 455         b43_phy_set(dev, 0x23f, 0x7ff);
 456         b43_phy_set(dev, 0x240, 0x7ff);
 457         b43_phy_set(dev, 0x241, 0x7ff);
 458
 459         b43_phy_ht_zero_extg(dev);
 460
 461         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 462
 463         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 464         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 465         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 466
 467         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 468         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 469         b43_phy_write(dev, 0x20d, 0xb8);
 470         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 471         b43_phy_write(dev, 0x70, 0x50);
 472         b43_phy_write(dev, 0x1ff, 0x30);
 473
 474         if (0) /* TODO: condition */
 475                 ; /* TODO: PHY op on reg 0x217 */
 476
 477         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 478                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 479         else
 480                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 481                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 482
 483         b43_phy_set(dev, 0xb1, 0x91);
 484         b43_phy_write(dev, 0x32f, 0x0003);
 485         b43_phy_write(dev, 0x077, 0x0010);
 486         b43_phy_write(dev, 0x0b4, 0x0258);
 487         b43_phy_mask(dev, 0x17e, ~0x4000);
 488
 489         b43_phy_write(dev, 0x0b9, 0x0072);
 490
 491         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 492         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 493         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 494
 495         b43_phy_ht_afe_unk1(dev);
 496
 497         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 498                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 499
 500         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 501         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 502
 503         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 504         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 505         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 506
 507         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 508                             0x8e, 0x96, 0x96, 0x96);
 509         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 510                             0x8f, 0x9f, 0x9f, 0x9f);
 511         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 512                             0x8f, 0x9f, 0x9f, 0x9f);
 513
 514         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 515         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 516         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 517
 518         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 519         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 520         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 521         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 522
 523         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 524                             0x09, 0x0e, 0x13, 0x18);
 525         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 526                             0x09, 0x0e, 0x13, 0x18);
 527         /* TODO: Did wl mean 2 instead of 40? */
 528         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 529                             0x09, 0x0e, 0x13, 0x18);
 530
 531         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 532         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 533         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 534
 535         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 536         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 537         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 538         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 539
 540         /* Copy some tables entries */
 541         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 542         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 543         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 544         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 545         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 546         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 547
 548         /* Reset CCA */
 549         b43_phy_force_clock(dev, true);
 550         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 551         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 552         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 553         b43_phy_force_clock(dev, false);
 554
 555         b43_mac_phy_clock_set(dev, true);
 556
 557         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 558         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 559
 560         /* TODO: Should we restore it? Or store it in global PHY info? */
 561         b43_phy_ht_classifier(dev, 0, 0);
 562         b43_phy_ht_read_clip_detection(dev, clip_state);
 563
 564         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 565                 b43_phy_ht_bphy_init(dev);
 566
 567         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 568                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 569
 570         return 0;
 571 }
 572
 573 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 574 {
 575         struct b43_phy *phy = &dev->phy;
 576         struct b43_phy_ht *phy_ht = phy->ht;
 577
 578         kfree(phy_ht);
 579         phy->ht = NULL;
 580 }
 581
 582 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 583 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 584                                         bool blocked)
 585 {
 586         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 587                 b43err(dev->wl, "MAC not suspended\n");
 588
 589         /* In the following PHY ops we copy wl's dummy behaviour.
 590          * TODO: Find out if reads (currently hidden in masks/masksets) are
 591          * needed and replace following ops with just writes or w&r.
 592          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 593          * cause delayed (!) machine lock up. */
 594         if (blocked) {
 595                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 596         } else {
 597                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 598                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 599                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 600                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 601
 602                 if (dev->phy.radio_ver == 0x2059)
 603                         b43_radio_2059_init(dev);
 604                 else
 605                         B43_WARN_ON(1);
 606
 607                 b43_switch_channel(dev, dev->phy.channel);
 608         }
 609 }
 610
 611 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 612 {
 613         if (on) {
 614                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
 615                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
 616                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
 617                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
 618                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
 619                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
 620         } else {
 621                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
 622                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
 623                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
 624                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
 625                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
 626                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
 627         }
 628 }
 629
 630 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 631                                         unsigned int new_channel)
 632 {
 633         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 634         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 635
 636         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 637                 if ((new_channel < 1) || (new_channel > 14))
 638                         return -EINVAL;
 639         } else {
 640                 return -EINVAL;
 641         }
 642
 643         return b43_phy_ht_set_channel(dev, channel, channel_type);
 644 }
 645
 646 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 647 {
 648         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 649                 return 11;
 650         return 36;
 651 }
 652
 653 /**************************************************
 654  * R/W ops.
 655  **************************************************/
 656
 657 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 658 {
 659         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 660         return b43_read16(dev, B43_MMIO_PHY_DATA);
 661 }
 662
 663 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 664 {
 665         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 666         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 667 }
 668
 669 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 670                                  u16 set)
 671 {
 672         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 673         b43_write16(dev, B43_MMIO_PHY_DATA,
 674                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 675 }
 676
 677 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 678 {
 679         /* HT-PHY needs 0x200 for read access */
 680         reg |= 0x200;
 681
 682         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 683         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 684 }
 685
 686 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 687                                       u16 value)
 688 {
 689         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 690         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 691 }
 692
 693 static enum b43_txpwr_result
 694 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 695 {
 696         return B43_TXPWR_RES_DONE;
 697 }
 698
 699 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
 700 {
 701 }
 702
 703 /**************************************************
 704  * PHY ops struct.
 705  **************************************************/
 706
 707 const struct b43_phy_operations b43_phyops_ht = {
 708         .allocate               = b43_phy_ht_op_allocate,
 709         .free                   = b43_phy_ht_op_free,
 710         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 711         .init                   = b43_phy_ht_op_init,
 712         .phy_read               = b43_phy_ht_op_read,
 713         .phy_write              = b43_phy_ht_op_write,
 714         .phy_maskset            = b43_phy_ht_op_maskset,
 715         .radio_read             = b43_phy_ht_op_radio_read,
 716         .radio_write            = b43_phy_ht_op_radio_write,
 717         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 718         .switch_analog          = b43_phy_ht_op_switch_analog,
 719         .switch_channel         = b43_phy_ht_op_switch_channel,
 720         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 721         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 722         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 723 };