drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         u8 i;
  41         u16 routing;
  42
  43         b43_radio_write(dev, 0x16, e->radio_syn16);
  44         b43_radio_write(dev, 0x17, e->radio_syn17);
  45         b43_radio_write(dev, 0x22, e->radio_syn22);
  46         b43_radio_write(dev, 0x25, e->radio_syn25);
  47         b43_radio_write(dev, 0x27, e->radio_syn27);
  48         b43_radio_write(dev, 0x28, e->radio_syn28);
  49         b43_radio_write(dev, 0x29, e->radio_syn29);
  50         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  51         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  52         b43_radio_write(dev, 0x37, e->radio_syn37);
  53         b43_radio_write(dev, 0x41, e->radio_syn41);
  54         b43_radio_write(dev, 0x43, e->radio_syn43);
  55         b43_radio_write(dev, 0x47, e->radio_syn47);
  56         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  57         b43_radio_write(dev, 0x58, e->radio_syn58);
  58         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  59         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  60         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  61         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  62         b43_radio_write(dev, 0x92, e->radio_syn92);
  63         b43_radio_write(dev, 0x98, e->radio_syn98);
  64
  65         for (i = 0; i < 2; i++) {
  66                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  67                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  68                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  69                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  70                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  71                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  72                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  73                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  74                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  75         }
  76
  77         udelay(50);
  78
  79         /* Calibration */
  80         b43_radio_mask(dev, 0x2b, ~0x1);
  81         b43_radio_mask(dev, 0x2e, ~0x4);
  82         b43_radio_set(dev, 0x2e, 0x4);
  83         b43_radio_set(dev, 0x2b, 0x1);
  84
  85         udelay(300);
  86 }
  87
  88 static void b43_radio_2059_init(struct b43_wldev *dev)
  89 {
  90         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  91         const u16 radio_values[3][2] = {
  92                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  93         };
  94         u16 i, j;
  95
  96         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  97         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  98
  99         for (i = 0; i < ARRAY_SIZE(routing); i++)
 100                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
 101
 102         b43_radio_set(dev, 0x2e, 0x0078);
 103         b43_radio_set(dev, 0xc0, 0x0080);
 104         msleep(2);
 105         b43_radio_mask(dev, 0x2e, ~0x0078);
 106         b43_radio_mask(dev, 0xc0, ~0x0080);
 107
 108         if (1) { /* FIXME */
 109                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
 110                 udelay(10);
 111                 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
 112                 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
 113
 114                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
 115                 udelay(100);
 116                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
 117
 118                 for (i = 0; i < 10000; i++) {
 119                         if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
 120                                 i = 0;
 121                                 break;
 122                         }
 123                         udelay(100);
 124                 }
 125                 if (i)
 126                         b43err(dev->wl, "radio 0x945 timeout\n");
 127
 128                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
 129                 b43_radio_set(dev, 0xa, 0x60);
 130
 131                 for (i = 0; i < 3; i++) {
 132                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 133                         b43_radio_write(dev, 0x13D, 0x6E);
 134                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 135                         b43_radio_write(dev, 0x13C, 0x55);
 136
 137                         for (j = 0; j < 10000; j++) {
 138                                 if (b43_radio_read(dev, 0x140) & 2) {
 139                                         j = 0;
 140                                         break;
 141                                 }
 142                                 udelay(500);
 143                         }
 144                         if (j)
 145                                 b43err(dev->wl, "radio 0x140 timeout\n");
 146
 147                         b43_radio_write(dev, 0x13C, 0x15);
 148                 }
 149
 150                 b43_radio_mask(dev, 0x17F, ~0x1);
 151         }
 152
 153         b43_radio_mask(dev, 0x11, ~0x0008);
 154 }
 155
 156 /**************************************************
 157  * RF
 158  **************************************************/
 159
 160 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 161 {
 162         u8 i;
 163
 164         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 165         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 166
 167         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 168         for (i = 0; i < 200; i++) {
 169                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 170                         i = 0;
 171                         break;
 172                 }
 173                 msleep(1);
 174         }
 175         if (i)
 176                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 177
 178         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 179 }
 180
 181 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
 182 {
 183         struct b43_phy_ht *htphy = dev->phy.ht;
 184         static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
 185                                      B43_PHY_HT_RF_CTL_INT_C2,
 186                                      B43_PHY_HT_RF_CTL_INT_C3 };
 187         int i;
 188
 189         if (enable) {
 190                 for (i = 0; i < 3; i++)
 191                         b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
 192         } else {
 193                 for (i = 0; i < 3; i++)
 194                         htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
 195                 /* TODO: Does 5GHz band use different value (not 0x0400)? */
 196                 for (i = 0; i < 3; i++)
 197                         b43_phy_write(dev, regs[i], 0x0400);
 198         }
 199 }
 200
 201 /**************************************************
 202  * Various PHY ops
 203  **************************************************/
 204
 205 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 206 {
 207         u16 tmp;
 208         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 209                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 210                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 211
 212         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 213         tmp &= allowed;
 214         tmp &= ~mask;
 215         tmp |= (val & mask);
 216         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 217
 218         return tmp;
 219 }
 220
 221 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
 222 {
 223         u16 bbcfg;
 224
 225         b43_phy_force_clock(dev, true);
 226         bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 227         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
 228         udelay(1);
 229         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
 230         b43_phy_force_clock(dev, false);
 231
 232         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 233 }
 234
 235 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 236 {
 237         u8 i, j;
 238         u16 base[] = { 0x40, 0x60, 0x80 };
 239
 240         for (i = 0; i < ARRAY_SIZE(base); i++) {
 241                 for (j = 0; j < 4; j++)
 242                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 243         }
 244
 245         for (i = 0; i < ARRAY_SIZE(base); i++)
 246                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 247 }
 248
 249 /* Some unknown AFE (Analog Frondned) op */
 250 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 251 {
 252         u8 i;
 253
 254         static const u16 ctl_regs[3][2] = {
 255                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 256                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 257                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 258         };
 259
 260         for (i = 0; i < 3; i++) {
 261                 /* TODO: verify masks&sets */
 262                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 263                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 264                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 265                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 266                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 267                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 268         }
 269 }
 270
 271 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 272 {
 273         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 274         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 275         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 276 }
 277
 278 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 279 {
 280         unsigned int i;
 281         u16 val;
 282
 283         val = 0x1E1F;
 284         for (i = 0; i < 16; i++) {
 285                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 286                 val -= 0x202;
 287         }
 288         val = 0x3E3F;
 289         for (i = 0; i < 16; i++) {
 290                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 291                 val -= 0x202;
 292         }
 293         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 294 }
 295
 296 /**************************************************
 297  * Tx/Rx
 298  **************************************************/
 299
 300 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 301 {
 302         int i;
 303
 304         for (i = 0; i < 3; i++) {
 305                 u16 mask;
 306                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 307
 308                 if (0) /* FIXME */
 309                         mask = 0x2 << (i * 4);
 310                 else
 311                         mask = 0;
 312                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 313
 314                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 315                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 316                                 tmp & 0xFF);
 317                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 318                                 tmp & 0xFF);
 319         }
 320 }
 321
 322 /**************************************************
 323  * Channel switching ops.
 324  **************************************************/
 325
 326 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 327                                   struct ieee80211_channel *new_channel)
 328 {
 329         struct bcma_device *core = dev->dev->bdev;
 330         int spuravoid = 0;
 331         u16 tmp;
 332
 333         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 334         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 335                 spuravoid = 1;
 336         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 337         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 338         bcma_core_pll_ctl(core,
 339                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 340                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 341                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 342                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 343
 344         /* Values has been taken from wlc_bmac_switch_macfreq comments */
 345         switch (spuravoid) {
 346         case 2: /* 126MHz */
 347                 tmp = 0x2082;
 348                 break;
 349         case 1: /* 123MHz */
 350                 tmp = 0x5341;
 351                 break;
 352         default: /* 120MHz */
 353                 tmp = 0x8889;
 354         }
 355
 356         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
 357         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
 358
 359         /* TODO: reset PLL */
 360
 361         if (spuravoid)
 362                 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
 363         else
 364                 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
 365                                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
 366
 367         b43_phy_ht_reset_cca(dev);
 368 }
 369
 370 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 371                                 const struct b43_phy_ht_channeltab_e_phy *e,
 372                                 struct ieee80211_channel *new_channel)
 373 {
 374         bool old_band_5ghz;
 375
 376         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 377         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 378                 /* TODO */
 379         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 380                 /* TODO */
 381         }
 382
 383         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 384         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 385         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 386         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 387         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 388         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 389
 390         if (new_channel->hw_value == 14) {
 391                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 392                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 393         } else {
 394                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 395                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 396                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 397                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 398         }
 399
 400         if (1) /* TODO: On N it's for early devices only, what about HT? */
 401                 b43_phy_ht_tx_power_fix(dev);
 402
 403         b43_phy_ht_spur_avoid(dev, new_channel);
 404
 405         b43_phy_write(dev, 0x017e, 0x3830);
 406 }
 407
 408 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 409                                   struct ieee80211_channel *channel,
 410                                   enum nl80211_channel_type channel_type)
 411 {
 412         struct b43_phy *phy = &dev->phy;
 413
 414         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 415
 416         if (phy->radio_ver == 0x2059) {
 417                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 418                                                         channel->center_freq);
 419                 if (!chent_r2059)
 420                         return -ESRCH;
 421         } else {
 422                 return -ESRCH;
 423         }
 424
 425         /* TODO: In case of N-PHY some bandwidth switching goes here */
 426
 427         if (phy->radio_ver == 0x2059) {
 428                 b43_radio_2059_channel_setup(dev, chent_r2059);
 429                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 430                                          channel);
 431         } else {
 432                 return -ESRCH;
 433         }
 434
 435         return 0;
 436 }
 437
 438 /**************************************************
 439  * Basic PHY ops.
 440  **************************************************/
 441
 442 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 443 {
 444         struct b43_phy_ht *phy_ht;
 445
 446         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 447         if (!phy_ht)
 448                 return -ENOMEM;
 449         dev->phy.ht = phy_ht;
 450
 451         return 0;
 452 }
 453
 454 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 455 {
 456         struct b43_phy *phy = &dev->phy;
 457         struct b43_phy_ht *phy_ht = phy->ht;
 458
 459         memset(phy_ht, 0, sizeof(*phy_ht));
 460 }
 461
 462 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 463 {
 464         u16 tmp;
 465         u16 clip_state[3];
 466
 467         if (dev->dev->bus_type != B43_BUS_BCMA) {
 468                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 469                 return -EOPNOTSUPP;
 470         }
 471
 472         b43_phy_ht_tables_init(dev);
 473
 474         b43_phy_mask(dev, 0x0be, ~0x2);
 475         b43_phy_set(dev, 0x23f, 0x7ff);
 476         b43_phy_set(dev, 0x240, 0x7ff);
 477         b43_phy_set(dev, 0x241, 0x7ff);
 478
 479         b43_phy_ht_zero_extg(dev);
 480
 481         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 482
 483         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 484         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 485         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 486
 487         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 488         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 489         b43_phy_write(dev, 0x20d, 0xb8);
 490         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 491         b43_phy_write(dev, 0x70, 0x50);
 492         b43_phy_write(dev, 0x1ff, 0x30);
 493
 494         if (0) /* TODO: condition */
 495                 ; /* TODO: PHY op on reg 0x217 */
 496
 497         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 498                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 499         else
 500                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 501                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 502
 503         b43_phy_set(dev, 0xb1, 0x91);
 504         b43_phy_write(dev, 0x32f, 0x0003);
 505         b43_phy_write(dev, 0x077, 0x0010);
 506         b43_phy_write(dev, 0x0b4, 0x0258);
 507         b43_phy_mask(dev, 0x17e, ~0x4000);
 508
 509         b43_phy_write(dev, 0x0b9, 0x0072);
 510
 511         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 512         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 513         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 514
 515         b43_phy_ht_afe_unk1(dev);
 516
 517         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 518                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 519
 520         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 521         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 522
 523         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 524         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 525         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 526
 527         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 528                             0x8e, 0x96, 0x96, 0x96);
 529         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 530                             0x8f, 0x9f, 0x9f, 0x9f);
 531         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 532                             0x8f, 0x9f, 0x9f, 0x9f);
 533
 534         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 535         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 536         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 537
 538         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 539         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 540         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 541         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 542
 543         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 544                             0x09, 0x0e, 0x13, 0x18);
 545         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 546                             0x09, 0x0e, 0x13, 0x18);
 547         /* TODO: Did wl mean 2 instead of 40? */
 548         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 549                             0x09, 0x0e, 0x13, 0x18);
 550
 551         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 552         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 553         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 554
 555         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 556         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 557         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 558         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 559
 560         /* Copy some tables entries */
 561         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 562         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 563         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 564         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 565         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 566         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 567
 568         /* Reset CCA */
 569         b43_phy_force_clock(dev, true);
 570         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 571         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 572         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 573         b43_phy_force_clock(dev, false);
 574
 575         b43_mac_phy_clock_set(dev, true);
 576
 577         b43_phy_ht_pa_override(dev, false);
 578         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 579         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 580         b43_phy_ht_pa_override(dev, true);
 581
 582         /* TODO: Should we restore it? Or store it in global PHY info? */
 583         b43_phy_ht_classifier(dev, 0, 0);
 584         b43_phy_ht_read_clip_detection(dev, clip_state);
 585
 586         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 587                 b43_phy_ht_bphy_init(dev);
 588
 589         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 590                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 591
 592         return 0;
 593 }
 594
 595 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 596 {
 597         struct b43_phy *phy = &dev->phy;
 598         struct b43_phy_ht *phy_ht = phy->ht;
 599
 600         kfree(phy_ht);
 601         phy->ht = NULL;
 602 }
 603
 604 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 605 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 606                                         bool blocked)
 607 {
 608         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 609                 b43err(dev->wl, "MAC not suspended\n");
 610
 611         /* In the following PHY ops we copy wl's dummy behaviour.
 612          * TODO: Find out if reads (currently hidden in masks/masksets) are
 613          * needed and replace following ops with just writes or w&r.
 614          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 615          * cause delayed (!) machine lock up. */
 616         if (blocked) {
 617                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 618         } else {
 619                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 620                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 621                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 622                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 623
 624                 if (dev->phy.radio_ver == 0x2059)
 625                         b43_radio_2059_init(dev);
 626                 else
 627                         B43_WARN_ON(1);
 628
 629                 b43_switch_channel(dev, dev->phy.channel);
 630         }
 631 }
 632
 633 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 634 {
 635         if (on) {
 636                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
 637                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
 638                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
 639                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
 640                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
 641                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
 642         } else {
 643                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
 644                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
 645                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
 646                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
 647                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
 648                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
 649         }
 650 }
 651
 652 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 653                                         unsigned int new_channel)
 654 {
 655         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 656         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 657
 658         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 659                 if ((new_channel < 1) || (new_channel > 14))
 660                         return -EINVAL;
 661         } else {
 662                 return -EINVAL;
 663         }
 664
 665         return b43_phy_ht_set_channel(dev, channel, channel_type);
 666 }
 667
 668 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 669 {
 670         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 671                 return 11;
 672         return 36;
 673 }
 674
 675 /**************************************************
 676  * R/W ops.
 677  **************************************************/
 678
 679 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 680 {
 681         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 682         return b43_read16(dev, B43_MMIO_PHY_DATA);
 683 }
 684
 685 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 686 {
 687         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 688         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 689 }
 690
 691 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 692                                  u16 set)
 693 {
 694         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 695         b43_write16(dev, B43_MMIO_PHY_DATA,
 696                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 697 }
 698
 699 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 700 {
 701         /* HT-PHY needs 0x200 for read access */
 702         reg |= 0x200;
 703
 704         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 705         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 706 }
 707
 708 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 709                                       u16 value)
 710 {
 711         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 712         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 713 }
 714
 715 static enum b43_txpwr_result
 716 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 717 {
 718         return B43_TXPWR_RES_DONE;
 719 }
 720
 721 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
 722 {
 723 }
 724
 725 /**************************************************
 726  * PHY ops struct.
 727  **************************************************/
 728
 729 const struct b43_phy_operations b43_phyops_ht = {
 730         .allocate               = b43_phy_ht_op_allocate,
 731         .free                   = b43_phy_ht_op_free,
 732         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 733         .init                   = b43_phy_ht_op_init,
 734         .phy_read               = b43_phy_ht_op_read,
 735         .phy_write              = b43_phy_ht_op_write,
 736         .phy_maskset            = b43_phy_ht_op_maskset,
 737         .radio_read             = b43_phy_ht_op_radio_read,
 738         .radio_write            = b43_phy_ht_op_radio_write,
 739         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 740         .switch_analog          = b43_phy_ht_op_switch_analog,
 741         .switch_channel         = b43_phy_ht_op_switch_channel,
 742         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 743         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 744         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 745 };