4 #include "phy_common.h"
7 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
8 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
9 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
10 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
11 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
12 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
13 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
14 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
15 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
16 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
17 #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */
18 #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */
19 #define B43_PHY_HT_BW1 0x1CE
20 #define B43_PHY_HT_BW2 0x1CF
21 #define B43_PHY_HT_BW3 0x1D0
22 #define B43_PHY_HT_BW4 0x1D1
23 #define B43_PHY_HT_BW5 0x1D2
24 #define B43_PHY_HT_BW6 0x1D3
26 #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E)
27 #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E)
28 #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E)
30 #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000)
31 #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003)
32 #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */
33 #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */
34 #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */
35 #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */
36 #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */
37 #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */
38 #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004)
39 /* Values for the status are the same as for the trigger */
41 #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
43 #define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c)
44 #define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c)
45 #define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c)
47 #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110)
48 #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111)
49 #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114)
50 #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115)
51 #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118)
52 #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119)
54 #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
57 /* Values for PHY registers used on channel switching */
58 struct b43_phy_ht_channeltab_e_phy {
69 u16 rf_ctl_int_save[3];
73 struct b43_phy_operations;
74 extern const struct b43_phy_operations b43_phyops_ht;
76 #endif /* B43_PHY_HT_H_ */