drivers/net/wireless/b43/phy_ht.h

   1 #ifndef B43_PHY_HT_H_
   2 #define B43_PHY_HT_H_
   3
   4 #include "phy_common.h"
   5
   6
   7 #define B43_PHY_HT_BBCFG                        0x001 /* BB config */
   8 #define  B43_PHY_HT_BBCFG_RSTCCA                0x4000 /* Reset CCA */
   9 #define  B43_PHY_HT_BBCFG_RSTRX                 0x8000 /* Reset RX */
  10 #define B43_PHY_HT_BANDCTL                      0x009 /* Band control */
  11 #define  B43_PHY_HT_BANDCTL_5GHZ                0x0001 /* Use the 5GHz band */
  12 #define B43_PHY_HT_TABLE_ADDR                   0x072 /* Table address */
  13 #define B43_PHY_HT_TABLE_DATALO                 0x073 /* Table data low */
  14 #define B43_PHY_HT_TABLE_DATAHI                 0x074 /* Table data high */
  15 #define B43_PHY_HT_CLASS_CTL                    0x0B0 /* Classifier control */
  16 #define  B43_PHY_HT_CLASS_CTL_CCK_EN            0x0001 /* CCK enable */
  17 #define  B43_PHY_HT_CLASS_CTL_OFDM_EN           0x0002 /* OFDM enable */
  18 #define  B43_PHY_HT_CLASS_CTL_WAITED_EN         0x0004 /* Waited enable */
  19 #define B43_PHY_HT_BW1                          0x1CE
  20 #define B43_PHY_HT_BW2                          0x1CF
  21 #define B43_PHY_HT_BW3                          0x1D0
  22 #define B43_PHY_HT_BW4                          0x1D1
  23 #define B43_PHY_HT_BW5                          0x1D2
  24 #define B43_PHY_HT_BW6                          0x1D3
  25
  26 #define B43_PHY_HT_C1_CLIP1THRES                B43_PHY_OFDM(0x00E)
  27 #define B43_PHY_HT_C2_CLIP1THRES                B43_PHY_OFDM(0x04E)
  28 #define B43_PHY_HT_C3_CLIP1THRES                B43_PHY_OFDM(0x08E)
  29
  30 #define B43_PHY_HT_RF_SEQ_MODE                  B43_PHY_EXTG(0x000)
  31 #define B43_PHY_HT_RF_SEQ_TRIG                  B43_PHY_EXTG(0x003)
  32 #define  B43_PHY_HT_RF_SEQ_TRIG_RX2TX           0x0001 /* RX2TX */
  33 #define  B43_PHY_HT_RF_SEQ_TRIG_TX2RX           0x0002 /* TX2RX */
  34 #define  B43_PHY_HT_RF_SEQ_TRIG_UPGH            0x0004 /* Update gain H */
  35 #define  B43_PHY_HT_RF_SEQ_TRIG_UPGL            0x0008 /* Update gain L */
  36 #define  B43_PHY_HT_RF_SEQ_TRIG_UPGU            0x0010 /* Update gain U */
  37 #define  B43_PHY_HT_RF_SEQ_TRIG_RST2RX          0x0020 /* Reset to RX */
  38 #define B43_PHY_HT_RF_SEQ_STATUS                B43_PHY_EXTG(0x004)
  39 /* Values for the status are the same as for the trigger */
  40
  41 #define B43_PHY_HT_RF_CTL1                      B43_PHY_EXTG(0x010)
  42
  43 #define B43_PHY_HT_AFE_C1_OVER                  B43_PHY_EXTG(0x110)
  44 #define B43_PHY_HT_AFE_C1                       B43_PHY_EXTG(0x111)
  45 #define B43_PHY_HT_AFE_C2_OVER                  B43_PHY_EXTG(0x114)
  46 #define B43_PHY_HT_AFE_C2                       B43_PHY_EXTG(0x115)
  47 #define B43_PHY_HT_AFE_C3_OVER                  B43_PHY_EXTG(0x118)
  48 #define B43_PHY_HT_AFE_C3                       B43_PHY_EXTG(0x119)
  49
  50 #define B43_PHY_HT_TEST                         B43_PHY_N_BMODE(0x00A)
  51
  52
  53 /* Values for PHY registers used on channel switching */
  54 struct b43_phy_ht_channeltab_e_phy {
  55         u16 bw1;
  56         u16 bw2;
  57         u16 bw3;
  58         u16 bw4;
  59         u16 bw5;
  60         u16 bw6;
  61 };
  62
  63
  64 struct b43_phy_ht {
  65 };
  66
  67
  68 struct b43_phy_operations;
  69 extern const struct b43_phy_operations b43_phyops_ht;
  70
  71 #endif /* B43_PHY_HT_H_ */