drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "radio_2057.h"
  36 #include "main.h"
  37
  38 struct nphy_txgains {
  39         u16 txgm[2];
  40         u16 pga[2];
  41         u16 pad[2];
  42         u16 ipa[2];
  43 };
  44
  45 struct nphy_iqcal_params {
  46         u16 txgm;
  47         u16 pga;
  48         u16 pad;
  49         u16 ipa;
  50         u16 cal_gain;
  51         u16 ncorr[5];
  52 };
  53
  54 struct nphy_iq_est {
  55         s32 iq0_prod;
  56         u32 i0_pwr;
  57         u32 q0_pwr;
  58         s32 iq1_prod;
  59         u32 i1_pwr;
  60         u32 q1_pwr;
  61 };
  62
  63 enum b43_nphy_rf_sequence {
  64         B43_RFSEQ_RX2TX,
  65         B43_RFSEQ_TX2RX,
  66         B43_RFSEQ_RESET2RX,
  67         B43_RFSEQ_UPDATE_GAINH,
  68         B43_RFSEQ_UPDATE_GAINL,
  69         B43_RFSEQ_UPDATE_GAINU,
  70 };
  71
  72 enum b43_nphy_rssi_type {
  73         B43_NPHY_RSSI_X = 0,
  74         B43_NPHY_RSSI_Y,
  75         B43_NPHY_RSSI_Z,
  76         B43_NPHY_RSSI_PWRDET,
  77         B43_NPHY_RSSI_TSSI_I,
  78         B43_NPHY_RSSI_TSSI_Q,
  79         B43_NPHY_RSSI_TBD,
  80 };
  81
  82 enum n_rail_type {
  83         N_RAIL_I = 0,
  84         N_RAIL_Q = 1,
  85 };
  86
  87 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  88 {
  89         enum ieee80211_band band = b43_current_band(dev->wl);
  90         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  91                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  92 }
  93
  94 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
  95 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
  96 {
  97         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
  98                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
  99 }
 100
 101 /**************************************************
 102  * RF (just without b43_nphy_rf_control_intc_override)
 103  **************************************************/
 104
 105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 106 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 107                                        enum b43_nphy_rf_sequence seq)
 108 {
 109         static const u16 trigger[] = {
 110                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 111                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 112                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 113                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 114                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 115                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 116         };
 117         int i;
 118         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 119
 120         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 121
 122         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 123                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 124         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 125         for (i = 0; i < 200; i++) {
 126                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 127                         goto ok;
 128                 msleep(1);
 129         }
 130         b43err(dev->wl, "RF sequence status timeout\n");
 131 ok:
 132         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 133 }
 134
 135 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
 136 static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
 137                                               u16 value, u8 core, bool off,
 138                                               u8 override)
 139 {
 140         const struct nphy_rf_control_override_rev7 *e;
 141         u16 en_addrs[3][2] = {
 142                 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
 143         };
 144         u16 en_addr;
 145         u16 en_mask = field;
 146         u16 val_addr;
 147         u8 i;
 148
 149         /* Remember: we can get NULL! */
 150         e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
 151
 152         for (i = 0; i < 2; i++) {
 153                 if (override >= ARRAY_SIZE(en_addrs)) {
 154                         b43err(dev->wl, "Invalid override value %d\n", override);
 155                         return;
 156                 }
 157                 en_addr = en_addrs[override][i];
 158
 159                 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
 160
 161                 if (off) {
 162                         b43_phy_mask(dev, en_addr, ~en_mask);
 163                         if (e) /* Do it safer, better than wl */
 164                                 b43_phy_mask(dev, val_addr, ~e->val_mask);
 165                 } else {
 166                         if (!core || (core & (1 << i))) {
 167                                 b43_phy_set(dev, en_addr, en_mask);
 168                                 if (e)
 169                                         b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
 170                         }
 171                 }
 172         }
 173 }
 174
 175 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 176 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 177                                                 u16 value, u8 core, bool off)
 178 {
 179         int i;
 180         u8 index = fls(field);
 181         u8 addr, en_addr, val_addr;
 182         /* we expect only one bit set */
 183         B43_WARN_ON(field & (~(1 << (index - 1))));
 184
 185         if (dev->phy.rev >= 3) {
 186                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 187                 for (i = 0; i < 2; i++) {
 188                         if (index == 0 || index == 16) {
 189                                 b43err(dev->wl,
 190                                         "Unsupported RF Ctrl Override call\n");
 191                                 return;
 192                         }
 193
 194                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 195                         en_addr = B43_PHY_N((i == 0) ?
 196                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 197                         val_addr = B43_PHY_N((i == 0) ?
 198                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 199
 200                         if (off) {
 201                                 b43_phy_mask(dev, en_addr, ~(field));
 202                                 b43_phy_mask(dev, val_addr,
 203                                                 ~(rf_ctrl->val_mask));
 204                         } else {
 205                                 if (core == 0 || ((1 << i) & core)) {
 206                                         b43_phy_set(dev, en_addr, field);
 207                                         b43_phy_maskset(dev, val_addr,
 208                                                 ~(rf_ctrl->val_mask),
 209                                                 (value << rf_ctrl->val_shift));
 210                                 }
 211                         }
 212                 }
 213         } else {
 214                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 215                 if (off) {
 216                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 217                         value = 0;
 218                 } else {
 219                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 220                 }
 221
 222                 for (i = 0; i < 2; i++) {
 223                         if (index <= 1 || index == 16) {
 224                                 b43err(dev->wl,
 225                                         "Unsupported RF Ctrl Override call\n");
 226                                 return;
 227                         }
 228
 229                         if (index == 2 || index == 10 ||
 230                             (index >= 13 && index <= 15)) {
 231                                 core = 1;
 232                         }
 233
 234                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 235                         addr = B43_PHY_N((i == 0) ?
 236                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 237
 238                         if ((1 << i) & core)
 239                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 240                                                 (value << rf_ctrl->shift));
 241
 242                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 243                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 244                                         B43_NPHY_RFCTL_CMD_START);
 245                         udelay(1);
 246                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 247                 }
 248         }
 249 }
 250
 251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 252 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
 253                                                 u16 value, u8 core)
 254 {
 255         u8 i, j;
 256         u16 reg, tmp, val;
 257
 258         B43_WARN_ON(dev->phy.rev < 3);
 259         B43_WARN_ON(field > 4);
 260
 261         for (i = 0; i < 2; i++) {
 262                 if ((core == 1 && i == 1) || (core == 2 && !i))
 263                         continue;
 264
 265                 reg = (i == 0) ?
 266                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 267                 b43_phy_set(dev, reg, 0x400);
 268
 269                 switch (field) {
 270                 case 0:
 271                         b43_phy_write(dev, reg, 0);
 272                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 273                         break;
 274                 case 1:
 275                         if (!i) {
 276                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 277                                                 0xFC3F, (value << 6));
 278                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 279                                                 0xFFFE, 1);
 280                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 281                                                 B43_NPHY_RFCTL_CMD_START);
 282                                 for (j = 0; j < 100; j++) {
 283                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 284                                                 j = 0;
 285                                                 break;
 286                                         }
 287                                         udelay(10);
 288                                 }
 289                                 if (j)
 290                                         b43err(dev->wl,
 291                                                 "intc override timeout\n");
 292                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 293                                                 0xFFFE);
 294                         } else {
 295                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 296                                                 0xFC3F, (value << 6));
 297                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 298                                                 0xFFFE, 1);
 299                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 300                                                 B43_NPHY_RFCTL_CMD_RXTX);
 301                                 for (j = 0; j < 100; j++) {
 302                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 303                                                 j = 0;
 304                                                 break;
 305                                         }
 306                                         udelay(10);
 307                                 }
 308                                 if (j)
 309                                         b43err(dev->wl,
 310                                                 "intc override timeout\n");
 311                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 312                                                 0xFFFE);
 313                         }
 314                         break;
 315                 case 2:
 316                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 317                                 tmp = 0x0020;
 318                                 val = value << 5;
 319                         } else {
 320                                 tmp = 0x0010;
 321                                 val = value << 4;
 322                         }
 323                         b43_phy_maskset(dev, reg, ~tmp, val);
 324                         break;
 325                 case 3:
 326                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 327                                 tmp = 0x0001;
 328                                 val = value;
 329                         } else {
 330                                 tmp = 0x0004;
 331                                 val = value << 2;
 332                         }
 333                         b43_phy_maskset(dev, reg, ~tmp, val);
 334                         break;
 335                 case 4:
 336                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 337                                 tmp = 0x0002;
 338                                 val = value << 1;
 339                         } else {
 340                                 tmp = 0x0008;
 341                                 val = value << 3;
 342                         }
 343                         b43_phy_maskset(dev, reg, ~tmp, val);
 344                         break;
 345                 }
 346         }
 347 }
 348
 349 /**************************************************
 350  * Various PHY ops
 351  **************************************************/
 352
 353 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 354 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 355                                           const u16 *clip_st)
 356 {
 357         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 358         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 359 }
 360
 361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 362 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 363 {
 364         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 365         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 366 }
 367
 368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 369 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 370 {
 371         u16 tmp;
 372
 373         if (dev->dev->core_rev == 16)
 374                 b43_mac_suspend(dev);
 375
 376         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 377         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 378                 B43_NPHY_CLASSCTL_WAITEDEN);
 379         tmp &= ~mask;
 380         tmp |= (val & mask);
 381         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 382
 383         if (dev->dev->core_rev == 16)
 384                 b43_mac_enable(dev);
 385
 386         return tmp;
 387 }
 388
 389 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 390 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 391 {
 392         u16 bbcfg;
 393
 394         b43_phy_force_clock(dev, 1);
 395         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 396         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 397         udelay(1);
 398         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 399         b43_phy_force_clock(dev, 0);
 400         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 401 }
 402
 403 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 404 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 405 {
 406         struct b43_phy *phy = &dev->phy;
 407         struct b43_phy_n *nphy = phy->n;
 408
 409         if (enable) {
 410                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 411                 if (nphy->deaf_count++ == 0) {
 412                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 413                         b43_nphy_classifier(dev, 0x7, 0);
 414                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 415                         b43_nphy_write_clip_detection(dev, clip);
 416                 }
 417                 b43_nphy_reset_cca(dev);
 418         } else {
 419                 if (--nphy->deaf_count == 0) {
 420                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 421                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 422                 }
 423         }
 424 }
 425
 426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 427 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 428 {
 429         struct b43_phy_n *nphy = dev->phy.n;
 430
 431         u8 i;
 432         s16 tmp;
 433         u16 data[4];
 434         s16 gain[2];
 435         u16 minmax[2];
 436         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 437
 438         if (nphy->hang_avoid)
 439                 b43_nphy_stay_in_carrier_search(dev, 1);
 440
 441         if (nphy->gain_boost) {
 442                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 443                         gain[0] = 6;
 444                         gain[1] = 6;
 445                 } else {
 446                         tmp = 40370 - 315 * dev->phy.channel;
 447                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 448                         tmp = 23242 - 224 * dev->phy.channel;
 449                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 450                 }
 451         } else {
 452                 gain[0] = 0;
 453                 gain[1] = 0;
 454         }
 455
 456         for (i = 0; i < 2; i++) {
 457                 if (nphy->elna_gain_config) {
 458                         data[0] = 19 + gain[i];
 459                         data[1] = 25 + gain[i];
 460                         data[2] = 25 + gain[i];
 461                         data[3] = 25 + gain[i];
 462                 } else {
 463                         data[0] = lna_gain[0] + gain[i];
 464                         data[1] = lna_gain[1] + gain[i];
 465                         data[2] = lna_gain[2] + gain[i];
 466                         data[3] = lna_gain[3] + gain[i];
 467                 }
 468                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 469
 470                 minmax[i] = 23 + gain[i];
 471         }
 472
 473         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 474                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 475         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 476                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 477
 478         if (nphy->hang_avoid)
 479                 b43_nphy_stay_in_carrier_search(dev, 0);
 480 }
 481
 482 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 483 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 484                                         u8 *events, u8 *delays, u8 length)
 485 {
 486         struct b43_phy_n *nphy = dev->phy.n;
 487         u8 i;
 488         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 489         u16 offset1 = cmd << 4;
 490         u16 offset2 = offset1 + 0x80;
 491
 492         if (nphy->hang_avoid)
 493                 b43_nphy_stay_in_carrier_search(dev, true);
 494
 495         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 496         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 497
 498         for (i = length; i < 16; i++) {
 499                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 500                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 501         }
 502
 503         if (nphy->hang_avoid)
 504                 b43_nphy_stay_in_carrier_search(dev, false);
 505 }
 506
 507 /**************************************************
 508  * Radio 0x2057
 509  **************************************************/
 510
 511 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
 512 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
 513 {
 514         struct b43_phy *phy = &dev->phy;
 515         u16 tmp;
 516
 517         if (phy->radio_rev == 5) {
 518                 b43_phy_mask(dev, 0x342, ~0x2);
 519                 udelay(10);
 520                 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
 521                 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
 522         }
 523
 524         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
 525         udelay(10);
 526         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
 527         if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
 528                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 529                 return 0;
 530         }
 531         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
 532         tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
 533         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
 534
 535         if (phy->radio_rev == 5) {
 536                 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
 537                 b43_radio_mask(dev, 0x1ca, ~0x2);
 538         }
 539         if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
 540                 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
 541                 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
 542                                   tmp << 2);
 543         }
 544
 545         return tmp & 0x3e;
 546 }
 547
 548 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
 549 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
 550 {
 551         struct b43_phy *phy = &dev->phy;
 552         bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
 553                         phy->radio_rev == 6);
 554         u16 tmp;
 555
 556         if (special) {
 557                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
 558                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
 559         } else {
 560                 b43_radio_write(dev, 0x1AE, 0x61);
 561                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
 562         }
 563         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 564         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 565         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 566                                   5000000))
 567                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 568         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 569         if (special) {
 570                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
 571                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 572         } else {
 573                 b43_radio_write(dev, 0x1AE, 0x69);
 574                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
 575         }
 576         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 577         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 578         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 579                                   5000000))
 580                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 581         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 582         if (special) {
 583                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
 584                 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
 585                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 586         } else {
 587                 b43_radio_write(dev, 0x1AE, 0x73);
 588                 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 589                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
 590         }
 591         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 592         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 593                                   5000000)) {
 594                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 595                 return 0;
 596         }
 597         tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
 598         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 599         return tmp;
 600 }
 601
 602 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
 603 {
 604         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 605         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 606         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
 607         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 608         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
 609 }
 610
 611 static void b43_radio_2057_init_post(struct b43_wldev *dev)
 612 {
 613         b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
 614
 615         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
 616         b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
 617         mdelay(2);
 618         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
 619         b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
 620
 621         if (dev->phy.n->init_por) {
 622                 b43_radio_2057_rcal(dev);
 623                 b43_radio_2057_rccal(dev);
 624         }
 625         b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
 626
 627         dev->phy.n->init_por = false;
 628 }
 629
 630 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
 631 static void b43_radio_2057_init(struct b43_wldev *dev)
 632 {
 633         b43_radio_2057_init_pre(dev);
 634         r2057_upload_inittabs(dev);
 635         b43_radio_2057_init_post(dev);
 636 }
 637
 638 /**************************************************
 639  * Radio 0x2056
 640  **************************************************/
 641
 642 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 643                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 644 {
 645         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 646         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 647         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 648         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 649         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 650         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 651                                         e->radio_syn_pll_loopfilter1);
 652         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 653                                         e->radio_syn_pll_loopfilter2);
 654         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 655                                         e->radio_syn_pll_loopfilter3);
 656         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 657                                         e->radio_syn_pll_loopfilter4);
 658         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 659                                         e->radio_syn_pll_loopfilter5);
 660         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 661                                         e->radio_syn_reserved_addr27);
 662         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 663                                         e->radio_syn_reserved_addr28);
 664         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 665                                         e->radio_syn_reserved_addr29);
 666         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 667                                         e->radio_syn_logen_vcobuf1);
 668         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 669         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 670         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 671
 672         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 673                                         e->radio_rx0_lnaa_tune);
 674         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 675                                         e->radio_rx0_lnag_tune);
 676
 677         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 678                                         e->radio_tx0_intpaa_boost_tune);
 679         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 680                                         e->radio_tx0_intpag_boost_tune);
 681         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 682                                         e->radio_tx0_pada_boost_tune);
 683         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 684                                         e->radio_tx0_padg_boost_tune);
 685         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 686                                         e->radio_tx0_pgaa_boost_tune);
 687         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 688                                         e->radio_tx0_pgag_boost_tune);
 689         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 690                                         e->radio_tx0_mixa_boost_tune);
 691         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 692                                         e->radio_tx0_mixg_boost_tune);
 693
 694         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 695                                         e->radio_rx1_lnaa_tune);
 696         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 697                                         e->radio_rx1_lnag_tune);
 698
 699         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 700                                         e->radio_tx1_intpaa_boost_tune);
 701         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 702                                         e->radio_tx1_intpag_boost_tune);
 703         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 704                                         e->radio_tx1_pada_boost_tune);
 705         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 706                                         e->radio_tx1_padg_boost_tune);
 707         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 708                                         e->radio_tx1_pgaa_boost_tune);
 709         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 710                                         e->radio_tx1_pgag_boost_tune);
 711         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 712                                         e->radio_tx1_mixa_boost_tune);
 713         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 714                                         e->radio_tx1_mixg_boost_tune);
 715 }
 716
 717 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 718 static void b43_radio_2056_setup(struct b43_wldev *dev,
 719                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 720 {
 721         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 722         enum ieee80211_band band = b43_current_band(dev->wl);
 723         u16 offset;
 724         u8 i;
 725         u16 bias, cbias;
 726         u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
 727         u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
 728
 729         B43_WARN_ON(dev->phy.rev < 3);
 730
 731         b43_chantab_radio_2056_upload(dev, e);
 732         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 733
 734         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 735             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 736                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 737                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 738                 if (dev->dev->chip_id == 0x4716) {
 739                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 740                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 741                 } else {
 742                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 743                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 744                 }
 745         }
 746         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 747             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 748                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 749                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 750                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 751                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 752         }
 753
 754         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 755                 for (i = 0; i < 2; i++) {
 756                         offset = i ? B2056_TX1 : B2056_TX0;
 757                         if (dev->phy.rev >= 5) {
 758                                 b43_radio_write(dev,
 759                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 760
 761                                 if (dev->dev->chip_id == 0x4716) {
 762                                         bias = 0x40;
 763                                         cbias = 0x45;
 764                                         pag_boost = 0x5;
 765                                         pgag_boost = 0x33;
 766                                         mixg_boost = 0x55;
 767                                 } else {
 768                                         bias = 0x25;
 769                                         cbias = 0x20;
 770                                         pag_boost = 0x4;
 771                                         pgag_boost = 0x03;
 772                                         mixg_boost = 0x65;
 773                                 }
 774                                 padg_boost = 0x77;
 775
 776                                 b43_radio_write(dev,
 777                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 778                                         bias);
 779                                 b43_radio_write(dev,
 780                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 781                                         bias);
 782                                 b43_radio_write(dev,
 783                                         offset | B2056_TX_INTPAG_CASCBIAS,
 784                                         cbias);
 785                                 b43_radio_write(dev,
 786                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 787                                         pag_boost);
 788                                 b43_radio_write(dev,
 789                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 790                                         pgag_boost);
 791                                 b43_radio_write(dev,
 792                                         offset | B2056_TX_PADG_BOOST_TUNE,
 793                                         padg_boost);
 794                                 b43_radio_write(dev,
 795                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 796                                         mixg_boost);
 797                         } else {
 798                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 799                                 b43_radio_write(dev,
 800                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 801                                         bias);
 802                                 b43_radio_write(dev,
 803                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 804                                         bias);
 805                                 b43_radio_write(dev,
 806                                         offset | B2056_TX_INTPAG_CASCBIAS,
 807                                         0x30);
 808                         }
 809                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 810                 }
 811         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 812                 u16 freq = dev->phy.channel_freq;
 813                 if (freq < 5100) {
 814                         paa_boost = 0xA;
 815                         pada_boost = 0x77;
 816                         pgaa_boost = 0xF;
 817                         mixa_boost = 0xF;
 818                 } else if (freq < 5340) {
 819                         paa_boost = 0x8;
 820                         pada_boost = 0x77;
 821                         pgaa_boost = 0xFB;
 822                         mixa_boost = 0xF;
 823                 } else if (freq < 5650) {
 824                         paa_boost = 0x0;
 825                         pada_boost = 0x77;
 826                         pgaa_boost = 0xB;
 827                         mixa_boost = 0xF;
 828                 } else {
 829                         paa_boost = 0x0;
 830                         pada_boost = 0x77;
 831                         if (freq != 5825)
 832                                 pgaa_boost = -(freq - 18) / 36 + 168;
 833                         else
 834                                 pgaa_boost = 6;
 835                         mixa_boost = 0xF;
 836                 }
 837
 838                 for (i = 0; i < 2; i++) {
 839                         offset = i ? B2056_TX1 : B2056_TX0;
 840
 841                         b43_radio_write(dev,
 842                                 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
 843                         b43_radio_write(dev,
 844                                 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
 845                         b43_radio_write(dev,
 846                                 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
 847                         b43_radio_write(dev,
 848                                 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
 849                         b43_radio_write(dev,
 850                                 offset | B2056_TX_TXSPARE1, 0x30);
 851                         b43_radio_write(dev,
 852                                 offset | B2056_TX_PA_SPARE2, 0xee);
 853                         b43_radio_write(dev,
 854                                 offset | B2056_TX_PADA_CASCBIAS, 0x03);
 855                         b43_radio_write(dev,
 856                                 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
 857                         b43_radio_write(dev,
 858                                 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
 859                         b43_radio_write(dev,
 860                                 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
 861                 }
 862         }
 863
 864         udelay(50);
 865         /* VCO calibration */
 866         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 867         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 868         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 869         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 870         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 871         udelay(300);
 872 }
 873
 874 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
 875 {
 876         struct b43_phy *phy = &dev->phy;
 877         u16 mast2, tmp;
 878
 879         if (phy->rev != 3)
 880                 return 0;
 881
 882         mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
 883         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
 884
 885         udelay(10);
 886         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 887         udelay(10);
 888         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
 889
 890         if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
 891                                   1000000)) {
 892                 b43err(dev->wl, "Radio recalibration timeout\n");
 893                 return 0;
 894         }
 895
 896         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 897         tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
 898         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
 899
 900         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
 901
 902         return tmp & 0x1f;
 903 }
 904
 905 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 906 {
 907         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 908                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 909         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 910         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 911                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 912         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 913                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 914         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 915                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 916 }
 917
 918 static void b43_radio_init2056_post(struct b43_wldev *dev)
 919 {
 920         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 921         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 922         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 923         msleep(1);
 924         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 925         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 926         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 927         if (dev->phy.n->init_por)
 928                 b43_radio_2056_rcal(dev);
 929 }
 930
 931 /*
 932  * Initialize a Broadcom 2056 N-radio
 933  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 934  */
 935 static void b43_radio_init2056(struct b43_wldev *dev)
 936 {
 937         b43_radio_init2056_pre(dev);
 938         b2056_upload_inittabs(dev, 0, 0);
 939         b43_radio_init2056_post(dev);
 940
 941         dev->phy.n->init_por = false;
 942 }
 943
 944 /**************************************************
 945  * Radio 0x2055
 946  **************************************************/
 947
 948 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 949                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 950 {
 951         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 952         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 953         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 954         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 955         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 956
 957         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 958         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 959         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 960         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 961         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 962
 963         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 964         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 965         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 966         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 967         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 968
 969         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 970         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 971         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 972         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 973         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 974
 975         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 976         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 977         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 978         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 979         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 980
 981         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 982         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 983 }
 984
 985 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 986 static void b43_radio_2055_setup(struct b43_wldev *dev,
 987                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 988 {
 989         B43_WARN_ON(dev->phy.rev >= 3);
 990
 991         b43_chantab_radio_upload(dev, e);
 992         udelay(50);
 993         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 994         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 995         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 996         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 997         udelay(300);
 998 }
 999
1000 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1001 {
1002         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1003                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
1004         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1005                     B43_NPHY_RFCTL_CMD_CHIP0PU |
1006                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
1007         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1008                     B43_NPHY_RFCTL_CMD_PORFORCE);
1009 }
1010
1011 static void b43_radio_init2055_post(struct b43_wldev *dev)
1012 {
1013         struct b43_phy_n *nphy = dev->phy.n;
1014         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1015         bool workaround = false;
1016
1017         if (sprom->revision < 4)
1018                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1019                               && dev->dev->board_type == 0x46D
1020                               && dev->dev->board_rev >= 0x41);
1021         else
1022                 workaround =
1023                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1024
1025         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1026         if (workaround) {
1027                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1028                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1029         }
1030         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1031         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1032         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1033         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1034         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1035         msleep(1);
1036         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1037         if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1038                 b43err(dev->wl, "radio post init timeout\n");
1039         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1040         b43_switch_channel(dev, dev->phy.channel);
1041         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1042         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1043         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1044         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1045         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1046         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1047         if (!nphy->gain_boost) {
1048                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1049                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1050         } else {
1051                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1052                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1053         }
1054         udelay(2);
1055 }
1056
1057 /*
1058  * Initialize a Broadcom 2055 N-radio
1059  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1060  */
1061 static void b43_radio_init2055(struct b43_wldev *dev)
1062 {
1063         b43_radio_init2055_pre(dev);
1064         if (b43_status(dev) < B43_STAT_INITIALIZED) {
1065                 /* Follow wl, not specs. Do not force uploading all regs */
1066                 b2055_upload_inittab(dev, 0, 0);
1067         } else {
1068                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1069                 b2055_upload_inittab(dev, ghz5, 0);
1070         }
1071         b43_radio_init2055_post(dev);
1072 }
1073
1074 /**************************************************
1075  * Samples
1076  **************************************************/
1077
1078 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1079 static int b43_nphy_load_samples(struct b43_wldev *dev,
1080                                         struct b43_c32 *samples, u16 len) {
1081         struct b43_phy_n *nphy = dev->phy.n;
1082         u16 i;
1083         u32 *data;
1084
1085         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1086         if (!data) {
1087                 b43err(dev->wl, "allocation for samples loading failed\n");
1088                 return -ENOMEM;
1089         }
1090         if (nphy->hang_avoid)
1091                 b43_nphy_stay_in_carrier_search(dev, 1);
1092
1093         for (i = 0; i < len; i++) {
1094                 data[i] = (samples[i].i & 0x3FF << 10);
1095                 data[i] |= samples[i].q & 0x3FF;
1096         }
1097         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1098
1099         kfree(data);
1100         if (nphy->hang_avoid)
1101                 b43_nphy_stay_in_carrier_search(dev, 0);
1102         return 0;
1103 }
1104
1105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1106 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1107                                         bool test)
1108 {
1109         int i;
1110         u16 bw, len, rot, angle;
1111         struct b43_c32 *samples;
1112
1113
1114         bw = (dev->phy.is_40mhz) ? 40 : 20;
1115         len = bw << 3;
1116
1117         if (test) {
1118                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1119                         bw = 82;
1120                 else
1121                         bw = 80;
1122
1123                 if (dev->phy.is_40mhz)
1124                         bw <<= 1;
1125
1126                 len = bw << 1;
1127         }
1128
1129         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1130         if (!samples) {
1131                 b43err(dev->wl, "allocation for samples generation failed\n");
1132                 return 0;
1133         }
1134         rot = (((freq * 36) / bw) << 16) / 100;
1135         angle = 0;
1136
1137         for (i = 0; i < len; i++) {
1138                 samples[i] = b43_cordic(angle);
1139                 angle += rot;
1140                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1141                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1142         }
1143
1144         i = b43_nphy_load_samples(dev, samples, len);
1145         kfree(samples);
1146         return (i < 0) ? 0 : len;
1147 }
1148
1149 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1150 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1151                                         u16 wait, bool iqmode, bool dac_test)
1152 {
1153         struct b43_phy_n *nphy = dev->phy.n;
1154         int i;
1155         u16 seq_mode;
1156         u32 tmp;
1157
1158         if (nphy->hang_avoid)
1159                 b43_nphy_stay_in_carrier_search(dev, true);
1160
1161         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1162                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1163                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1164         }
1165
1166         if (!dev->phy.is_40mhz)
1167                 tmp = 0x6464;
1168         else
1169                 tmp = 0x4747;
1170         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1171
1172         if (nphy->hang_avoid)
1173                 b43_nphy_stay_in_carrier_search(dev, false);
1174
1175         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1176
1177         if (loops != 0xFFFF)
1178                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1179         else
1180                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1181
1182         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1183
1184         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1185
1186         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1187         if (iqmode) {
1188                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1189                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1190         } else {
1191                 if (dac_test)
1192                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1193                 else
1194                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1195         }
1196         for (i = 0; i < 100; i++) {
1197                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1198                         i = 0;
1199                         break;
1200                 }
1201                 udelay(10);
1202         }
1203         if (i)
1204                 b43err(dev->wl, "run samples timeout\n");
1205
1206         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1207 }
1208
1209 /**************************************************
1210  * RSSI
1211  **************************************************/
1212
1213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1214 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1215                                         s8 offset, u8 core,
1216                                         enum n_rail_type rail,
1217                                         enum b43_nphy_rssi_type type)
1218 {
1219         u16 tmp;
1220         bool core1or5 = (core == 1) || (core == 5);
1221         bool core2or5 = (core == 2) || (core == 5);
1222
1223         offset = clamp_val(offset, -32, 31);
1224         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1225
1226         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1227                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1228         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1229                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1230         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1231                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1232         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1233                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1234
1235         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1236                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1237         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1238                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1239         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1240                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1241         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1242                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1243
1244         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1245                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1246         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1247                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1248         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1249                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1250         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1251                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1252
1253         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1254                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1255         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1256                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1257         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1258                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1259         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1260                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1261
1262         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1263                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1264         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1265                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1266         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1267                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1268         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1269                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1270
1271         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1272                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1273         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1274                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1275
1276         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1277                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1278         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1279                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1280 }
1281
1282 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1283 {
1284         u8 i;
1285         u16 reg, val;
1286
1287         if (code == 0) {
1288                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1289                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1290                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1291                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1292                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1293                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1294                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1295                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1296         } else {
1297                 for (i = 0; i < 2; i++) {
1298                         if ((code == 1 && i == 1) || (code == 2 && !i))
1299                                 continue;
1300
1301                         reg = (i == 0) ?
1302                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1303                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1304
1305                         if (type < 3) {
1306                                 reg = (i == 0) ?
1307                                         B43_NPHY_AFECTL_C1 :
1308                                         B43_NPHY_AFECTL_C2;
1309                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1310
1311                                 reg = (i == 0) ?
1312                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1313                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1314                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1315
1316                                 if (type == 0)
1317                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1318                                 else if (type == 1)
1319                                         val = 16;
1320                                 else
1321                                         val = 32;
1322                                 b43_phy_set(dev, reg, val);
1323
1324                                 reg = (i == 0) ?
1325                                         B43_NPHY_TXF_40CO_B1S0 :
1326                                         B43_NPHY_TXF_40CO_B32S1;
1327                                 b43_phy_set(dev, reg, 0x0020);
1328                         } else {
1329                                 if (type == 6)
1330                                         val = 0x0100;
1331                                 else if (type == 3)
1332                                         val = 0x0200;
1333                                 else
1334                                         val = 0x0300;
1335
1336                                 reg = (i == 0) ?
1337                                         B43_NPHY_AFECTL_C1 :
1338                                         B43_NPHY_AFECTL_C2;
1339
1340                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1341                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1342
1343                                 if (type != 3 && type != 6) {
1344                                         enum ieee80211_band band =
1345                                                 b43_current_band(dev->wl);
1346
1347                                         if (b43_nphy_ipa(dev))
1348                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1349                                         else
1350                                                 val = 0x11;
1351                                         reg = (i == 0) ? 0x2000 : 0x3000;
1352                                         reg |= B2055_PADDRV;
1353                                         b43_radio_write16(dev, reg, val);
1354
1355                                         reg = (i == 0) ?
1356                                                 B43_NPHY_AFECTL_OVER1 :
1357                                                 B43_NPHY_AFECTL_OVER;
1358                                         b43_phy_set(dev, reg, 0x0200);
1359                                 }
1360                         }
1361                 }
1362         }
1363 }
1364
1365 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1366 {
1367         u16 val;
1368
1369         if (type < 3)
1370                 val = 0;
1371         else if (type == 6)
1372                 val = 1;
1373         else if (type == 3)
1374                 val = 2;
1375         else
1376                 val = 3;
1377
1378         val = (val << 12) | (val << 14);
1379         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1380         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1381
1382         if (type < 3) {
1383                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1384                                 (type + 1) << 4);
1385                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1386                                 (type + 1) << 4);
1387         }
1388
1389         if (code == 0) {
1390                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1391                 if (type < 3) {
1392                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1393                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1394                                   B43_NPHY_RFCTL_CMD_CORESEL));
1395                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1396                                 ~(0x1 << 12 |
1397                                   0x1 << 5 |
1398                                   0x1 << 1 |
1399                                   0x1));
1400                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1401                                 ~B43_NPHY_RFCTL_CMD_START);
1402                         udelay(20);
1403                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1404                 }
1405         } else {
1406                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1407                 if (type < 3) {
1408                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1409                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1410                                   B43_NPHY_RFCTL_CMD_CORESEL),
1411                                 (B43_NPHY_RFCTL_CMD_RXEN |
1412                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1413                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1414                                 (0x1 << 12 |
1415                                   0x1 << 5 |
1416                                   0x1 << 1 |
1417                                   0x1));
1418                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1419                                 B43_NPHY_RFCTL_CMD_START);
1420                         udelay(20);
1421                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1422                 }
1423         }
1424 }
1425
1426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1427 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1428 {
1429         if (dev->phy.rev >= 3)
1430                 b43_nphy_rev3_rssi_select(dev, code, type);
1431         else
1432                 b43_nphy_rev2_rssi_select(dev, code, type);
1433 }
1434
1435 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1436 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1437 {
1438         int i;
1439         for (i = 0; i < 2; i++) {
1440                 if (type == 2) {
1441                         if (i == 0) {
1442                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1443                                                   0xFC, buf[0]);
1444                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1445                                                   0xFC, buf[1]);
1446                         } else {
1447                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1448                                                   0xFC, buf[2 * i]);
1449                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1450                                                   0xFC, buf[2 * i + 1]);
1451                         }
1452                 } else {
1453                         if (i == 0)
1454                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1455                                                   0xF3, buf[0] << 2);
1456                         else
1457                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1458                                                   0xF3, buf[2 * i + 1] << 2);
1459                 }
1460         }
1461 }
1462
1463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1464 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1465                                 u8 nsamp)
1466 {
1467         int i;
1468         int out;
1469         u16 save_regs_phy[9];
1470         u16 s[2];
1471
1472         if (dev->phy.rev >= 3) {
1473                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1474                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1475                 save_regs_phy[2] = b43_phy_read(dev,
1476                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1477                 save_regs_phy[3] = b43_phy_read(dev,
1478                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1479                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1480                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1481                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1482                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1483                 save_regs_phy[8] = 0;
1484         } else {
1485                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1486                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1487                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1488                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1489                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1490                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1491                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1492                 save_regs_phy[7] = 0;
1493                 save_regs_phy[8] = 0;
1494         }
1495
1496         b43_nphy_rssi_select(dev, 5, type);
1497
1498         if (dev->phy.rev < 2) {
1499                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1500                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1501         }
1502
1503         for (i = 0; i < 4; i++)
1504                 buf[i] = 0;
1505
1506         for (i = 0; i < nsamp; i++) {
1507                 if (dev->phy.rev < 2) {
1508                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1509                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1510                 } else {
1511                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1512                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1513                 }
1514
1515                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1516                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1517                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1518                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1519         }
1520         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1521                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1522
1523         if (dev->phy.rev < 2)
1524                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1525
1526         if (dev->phy.rev >= 3) {
1527                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1528                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1529                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1530                                 save_regs_phy[2]);
1531                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1532                                 save_regs_phy[3]);
1533                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1534                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1535                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1536                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1537         } else {
1538                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1539                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1540                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1541                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1542                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1543                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1544                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1545         }
1546
1547         return out;
1548 }
1549
1550 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1551 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1552 {
1553         struct b43_phy_n *nphy = dev->phy.n;
1554
1555         u16 saved_regs_phy_rfctl[2];
1556         u16 saved_regs_phy[13];
1557         u16 regs_to_store[] = {
1558                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1559                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1560                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1561                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1562                 B43_NPHY_RFCTL_CMD,
1563                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1564                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1565         };
1566
1567         u16 class;
1568
1569         u16 clip_state[2];
1570         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1571
1572         u8 vcm_final = 0;
1573         s32 offset[4];
1574         s32 results[8][4] = { };
1575         s32 results_min[4] = { };
1576         s32 poll_results[4] = { };
1577
1578         u16 *rssical_radio_regs = NULL;
1579         u16 *rssical_phy_regs = NULL;
1580
1581         u16 r; /* routing */
1582         u8 rx_core_state;
1583         u8 core, i, j;
1584
1585         class = b43_nphy_classifier(dev, 0, 0);
1586         b43_nphy_classifier(dev, 7, 4);
1587         b43_nphy_read_clip_detection(dev, clip_state);
1588         b43_nphy_write_clip_detection(dev, clip_off);
1589
1590         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1591         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1592         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1593                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1594
1595         b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1596         b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1597         b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1598         b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1599         b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1600         b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1601
1602         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1603                 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1604                 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1605         } else {
1606                 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1607                 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1608         }
1609
1610         rx_core_state = b43_nphy_get_rx_core_state(dev);
1611         for (core = 0; core < 2; core++) {
1612                 if (!(rx_core_state & (1 << core)))
1613                         continue;
1614                 r = core ? B2056_RX1 : B2056_RX0;
1615                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, 2);
1616                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, 2);
1617                 for (i = 0; i < 8; i++) {
1618                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1619                                         i << 2);
1620                         b43_nphy_poll_rssi(dev, 2, results[i], 8);
1621                 }
1622                 for (i = 0; i < 4; i += 2) {
1623                         s32 curr;
1624                         s32 mind = 0x100000;
1625                         s32 minpoll = 249;
1626                         u8 minvcm = 0;
1627                         if (2 * core != i)
1628                                 continue;
1629                         for (j = 0; j < 8; j++) {
1630                                 curr = results[j][i] * results[j][i] +
1631                                         results[j][i + 1] * results[j][i];
1632                                 if (curr < mind) {
1633                                         mind = curr;
1634                                         minvcm = j;
1635                                 }
1636                                 if (results[j][i] < minpoll)
1637                                         minpoll = results[j][i];
1638                         }
1639                         vcm_final = minvcm;
1640                         results_min[i] = minpoll;
1641                 }
1642                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1643                                   vcm_final << 2);
1644                 for (i = 0; i < 4; i++) {
1645                         if (core != i / 2)
1646                                 continue;
1647                         offset[i] = -results[vcm_final][i];
1648                         if (offset[i] < 0)
1649                                 offset[i] = -((abs(offset[i]) + 4) / 8);
1650                         else
1651                                 offset[i] = (offset[i] + 4) / 8;
1652                         if (results_min[i] == 248)
1653                                 offset[i] = -32;
1654                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1655                                                    (i / 2 == 0) ? 1 : 2,
1656                                                    (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1657                                                    2);
1658                 }
1659         }
1660         for (core = 0; core < 2; core++) {
1661                 if (!(rx_core_state & (1 << core)))
1662                         continue;
1663                 for (i = 0; i < 2; i++) {
1664                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1665                                                    N_RAIL_I, i);
1666                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1667                                                    N_RAIL_Q, i);
1668                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
1669                         for (j = 0; j < 4; j++) {
1670                                 if (j / 2 == core) {
1671                                         offset[j] = 232 - poll_results[j];
1672                                         if (offset[j] < 0)
1673                                                 offset[j] = -(abs(offset[j] + 4) / 8);
1674                                         else
1675                                                 offset[j] = (offset[j] + 4) / 8;
1676                                         b43_nphy_scale_offset_rssi(dev, 0,
1677                                                 offset[2 * core], core + 1, j % 2, i);
1678                                 }
1679                         }
1680                 }
1681         }
1682
1683         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1684         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1685
1686         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1687
1688         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1689         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1690         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1691
1692         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1693         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1694         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1695
1696         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1697                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1698
1699         /* Store for future configuration */
1700         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1701                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1702                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1703         } else {
1704                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1705                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1706         }
1707         rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1708         rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1709         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1710         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1711         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1712         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1713         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1714         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1715         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1716         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1717         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1718         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1719         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1720         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1721
1722         /* Remember for which channel we store configuration */
1723         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1724                 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1725         else
1726                 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1727
1728         /* End of calibration, restore configuration */
1729         b43_nphy_classifier(dev, 7, class);
1730         b43_nphy_write_clip_detection(dev, clip_state);
1731 }
1732
1733 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1734 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1735 {
1736         int i, j;
1737         u8 state[4];
1738         u8 code, val;
1739         u16 class, override;
1740         u8 regs_save_radio[2];
1741         u16 regs_save_phy[2];
1742
1743         s32 offset[4];
1744         u8 core;
1745         u8 rail;
1746
1747         u16 clip_state[2];
1748         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1749         s32 results_min[4] = { };
1750         u8 vcm_final[4] = { };
1751         s32 results[4][4] = { };
1752         s32 miniq[4][2] = { };
1753
1754         if (type == 2) {
1755                 code = 0;
1756                 val = 6;
1757         } else if (type < 2) {
1758                 code = 25;
1759                 val = 4;
1760         } else {
1761                 B43_WARN_ON(1);
1762                 return;
1763         }
1764
1765         class = b43_nphy_classifier(dev, 0, 0);
1766         b43_nphy_classifier(dev, 7, 4);
1767         b43_nphy_read_clip_detection(dev, clip_state);
1768         b43_nphy_write_clip_detection(dev, clip_off);
1769
1770         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1771                 override = 0x140;
1772         else
1773                 override = 0x110;
1774
1775         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1776         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1777         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1778         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1779
1780         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1781         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1782         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1783         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1784
1785         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1786         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1787         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1788         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1789         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1790         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1791
1792         b43_nphy_rssi_select(dev, 5, type);
1793         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1794         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1795
1796         for (i = 0; i < 4; i++) {
1797                 u8 tmp[4];
1798                 for (j = 0; j < 4; j++)
1799                         tmp[j] = i;
1800                 if (type != 1)
1801                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1802                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1803                 if (type < 2)
1804                         for (j = 0; j < 2; j++)
1805                                 miniq[i][j] = min(results[i][2 * j],
1806                                                 results[i][2 * j + 1]);
1807         }
1808
1809         for (i = 0; i < 4; i++) {
1810                 s32 mind = 0x100000;
1811                 u8 minvcm = 0;
1812                 s32 minpoll = 249;
1813                 s32 curr;
1814                 for (j = 0; j < 4; j++) {
1815                         if (type == 2)
1816                                 curr = abs(results[j][i]);
1817                         else
1818                                 curr = abs(miniq[j][i / 2] - code * 8);
1819
1820                         if (curr < mind) {
1821                                 mind = curr;
1822                                 minvcm = j;
1823                         }
1824
1825                         if (results[j][i] < minpoll)
1826                                 minpoll = results[j][i];
1827                 }
1828                 results_min[i] = minpoll;
1829                 vcm_final[i] = minvcm;
1830         }
1831
1832         if (type != 1)
1833                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1834
1835         for (i = 0; i < 4; i++) {
1836                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1837
1838                 if (offset[i] < 0)
1839                         offset[i] = -((abs(offset[i]) + 4) / 8);
1840                 else
1841                         offset[i] = (offset[i] + 4) / 8;
1842
1843                 if (results_min[i] == 248)
1844                         offset[i] = code - 32;
1845
1846                 core = (i / 2) ? 2 : 1;
1847                 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1848
1849                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1850                                                 type);
1851         }
1852
1853         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1854         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1855
1856         switch (state[2]) {
1857         case 1:
1858                 b43_nphy_rssi_select(dev, 1, 2);
1859                 break;
1860         case 4:
1861                 b43_nphy_rssi_select(dev, 1, 0);
1862                 break;
1863         case 2:
1864                 b43_nphy_rssi_select(dev, 1, 1);
1865                 break;
1866         default:
1867                 b43_nphy_rssi_select(dev, 1, 1);
1868                 break;
1869         }
1870
1871         switch (state[3]) {
1872         case 1:
1873                 b43_nphy_rssi_select(dev, 2, 2);
1874                 break;
1875         case 4:
1876                 b43_nphy_rssi_select(dev, 2, 0);
1877                 break;
1878         default:
1879                 b43_nphy_rssi_select(dev, 2, 1);
1880                 break;
1881         }
1882
1883         b43_nphy_rssi_select(dev, 0, type);
1884
1885         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1886         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1887         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1888         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1889
1890         b43_nphy_classifier(dev, 7, class);
1891         b43_nphy_write_clip_detection(dev, clip_state);
1892         /* Specs don't say about reset here, but it makes wl and b43 dumps
1893            identical, it really seems wl performs this */
1894         b43_nphy_reset_cca(dev);
1895 }
1896
1897 /*
1898  * RSSI Calibration
1899  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1900  */
1901 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1902 {
1903         if (dev->phy.rev >= 3) {
1904                 b43_nphy_rev3_rssi_cal(dev);
1905         } else {
1906                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1907                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1908                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1909         }
1910 }
1911
1912 /**************************************************
1913  * Workarounds
1914  **************************************************/
1915
1916 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1917 {
1918         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1919
1920         bool ghz5;
1921         bool ext_lna;
1922         u16 rssi_gain;
1923         struct nphy_gain_ctl_workaround_entry *e;
1924         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1925         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1926
1927         /* Prepare values */
1928         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1929                 & B43_NPHY_BANDCTL_5GHZ;
1930         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1931                 sprom->boardflags_lo & B43_BFL_EXTLNA;
1932         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1933         if (ghz5 && dev->phy.rev >= 5)
1934                 rssi_gain = 0x90;
1935         else
1936                 rssi_gain = 0x50;
1937
1938         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1939
1940         /* Set Clip 2 detect */
1941         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1942                         B43_NPHY_C1_CGAINI_CL2DETECT);
1943         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1944                         B43_NPHY_C2_CGAINI_CL2DETECT);
1945
1946         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1947                         0x17);
1948         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1949                         0x17);
1950         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1951         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1952         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1953         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1954         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1955                         rssi_gain);
1956         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1957                         rssi_gain);
1958         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1959                         0x17);
1960         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1961                         0x17);
1962         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1963         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1964
1965         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1966         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1967         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1968         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1969         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1970         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1971         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1972         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1973         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1974         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1975         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1976         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1977
1978         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1979         b43_phy_write(dev, 0x2A7, e->init_gain);
1980         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1981                                 e->rfseq_init);
1982
1983         /* TODO: check defines. Do not match variables names */
1984         b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1985         b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1986         b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1987         b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1988         b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1989         b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1990
1991         b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1992         b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1993         b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1994         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1995         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1996         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1997                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1998         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1999                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2000         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2001 }
2002
2003 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2004 {
2005         struct b43_phy_n *nphy = dev->phy.n;
2006
2007         u8 i, j;
2008         u8 code;
2009         u16 tmp;
2010         u8 rfseq_events[3] = { 6, 8, 7 };
2011         u8 rfseq_delays[3] = { 10, 30, 1 };
2012
2013         /* Set Clip 2 detect */
2014         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2015         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2016
2017         /* Set narrowband clip threshold */
2018         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2019         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2020
2021         if (!dev->phy.is_40mhz) {
2022                 /* Set dwell lengths */
2023                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2024                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2025                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2026                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2027         }
2028
2029         /* Set wideband clip 2 threshold */
2030         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2031                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2032         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2033                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2034
2035         if (!dev->phy.is_40mhz) {
2036                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2037                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2038                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2039                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2040                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2041                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2042                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2043                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2044         }
2045
2046         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2047
2048         if (nphy->gain_boost) {
2049                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2050                         dev->phy.is_40mhz)
2051                         code = 4;
2052                 else
2053                         code = 5;
2054         } else {
2055                 code = dev->phy.is_40mhz ? 6 : 7;
2056         }
2057
2058         /* Set HPVGA2 index */
2059         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2060                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2061         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2062                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2063
2064         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2065         /* specs say about 2 loops, but wl does 4 */
2066         for (i = 0; i < 4; i++)
2067                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2068
2069         b43_nphy_adjust_lna_gain_table(dev);
2070
2071         if (nphy->elna_gain_config) {
2072                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2073                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2074                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2075                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2076                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2077
2078                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2079                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2080                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2081                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2082                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2083
2084                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2085                 /* specs say about 2 loops, but wl does 4 */
2086                 for (i = 0; i < 4; i++)
2087                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2088                                                 (code << 8 | 0x74));
2089         }
2090
2091         if (dev->phy.rev == 2) {
2092                 for (i = 0; i < 4; i++) {
2093                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2094                                         (0x0400 * i) + 0x0020);
2095                         for (j = 0; j < 21; j++) {
2096                                 tmp = j * (i < 2 ? 3 : 1);
2097                                 b43_phy_write(dev,
2098                                         B43_NPHY_TABLE_DATALO, tmp);
2099                         }
2100                 }
2101         }
2102
2103         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2104         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2105                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2106                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2107
2108         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2109                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2110 }
2111
2112 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2113 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2114 {
2115         if (dev->phy.rev >= 7)
2116                 ; /* TODO */
2117         else if (dev->phy.rev >= 3)
2118                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2119         else
2120                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2121 }
2122
2123 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2124 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2125 {
2126         if (!offset)
2127                 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2128         return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2129 }
2130
2131 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2132 {
2133         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2134         struct b43_phy *phy = &dev->phy;
2135
2136         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2137                                         0x1F };
2138         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2139
2140         u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2141         u8 ntab7_138_146[] = { 0x11, 0x11 };
2142         u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2143
2144         u16 lpf_20, lpf_40, lpf_11b;
2145         u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2146         u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2147         bool rccal_ovrd = false;
2148
2149         u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2150         u16 bias, conv, filt;
2151
2152         u32 tmp32;
2153         u8 core;
2154
2155         if (phy->rev == 7) {
2156                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2157                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2158                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2159                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2160                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2161                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2162                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2163                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2164                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2165                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2166                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2167                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2168                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2169                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2170                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2171                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2172                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2173         }
2174         if (phy->rev <= 8) {
2175                 b43_phy_write(dev, 0x23F, 0x1B0);
2176                 b43_phy_write(dev, 0x240, 0x1B0);
2177         }
2178         if (phy->rev >= 8)
2179                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2180
2181         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2182         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2183         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2184         tmp32 &= 0xffffff;
2185         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2186         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2187         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2188
2189         if (b43_nphy_ipa(dev))
2190                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2191                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2192
2193         b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2194         b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2195
2196         lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2197         lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2198         lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2199         if (b43_nphy_ipa(dev)) {
2200                 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2201                     phy->radio_rev == 7 || phy->radio_rev == 8) {
2202                         bcap_val = b43_radio_read(dev, 0x16b);
2203                         scap_val = b43_radio_read(dev, 0x16a);
2204                         scap_val_11b = scap_val;
2205                         bcap_val_11b = bcap_val;
2206                         if (phy->radio_rev == 5 && phy->is_40mhz) {
2207                                 scap_val_11n_20 = scap_val;
2208                                 bcap_val_11n_20 = bcap_val;
2209                                 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2210                                 rccal_ovrd = true;
2211                         } else { /* Rev 7/8 */
2212                                 lpf_20 = 4;
2213                                 lpf_11b = 1;
2214                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2215                                         scap_val_11n_20 = 0xc;
2216                                         bcap_val_11n_20 = 0xc;
2217                                         scap_val_11n_40 = 0xa;
2218                                         bcap_val_11n_40 = 0xa;
2219                                 } else {
2220                                         scap_val_11n_20 = 0x14;
2221                                         bcap_val_11n_20 = 0x14;
2222                                         scap_val_11n_40 = 0xf;
2223                                         bcap_val_11n_40 = 0xf;
2224                                 }
2225                                 rccal_ovrd = true;
2226                         }
2227                 }
2228         } else {
2229                 if (phy->radio_rev == 5) {
2230                         lpf_20 = 1;
2231                         lpf_40 = 3;
2232                         bcap_val = b43_radio_read(dev, 0x16b);
2233                         scap_val = b43_radio_read(dev, 0x16a);
2234                         scap_val_11b = scap_val;
2235                         bcap_val_11b = bcap_val;
2236                         scap_val_11n_20 = 0x11;
2237                         scap_val_11n_40 = 0x11;
2238                         bcap_val_11n_20 = 0x13;
2239                         bcap_val_11n_40 = 0x13;
2240                         rccal_ovrd = true;
2241                 }
2242         }
2243         if (rccal_ovrd) {
2244                 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2245                                    (scap_val_11b << 3) |
2246                                    lpf_11b;
2247                 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2248                                    (scap_val_11n_20 << 3) |
2249                                    lpf_20;
2250                 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2251                                    (scap_val_11n_40 << 3) |
2252                                    lpf_40;
2253                 for (core = 0; core < 2; core++) {
2254                         b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2255                                        rx2tx_lut_20_11b);
2256                         b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2257                                        rx2tx_lut_20_11n);
2258                         b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2259                                        rx2tx_lut_20_11n);
2260                         b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2261                                        rx2tx_lut_40_11n);
2262                         b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2263                                        rx2tx_lut_40_11n);
2264                         b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2265                                        rx2tx_lut_40_11n);
2266                         b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2267                                        rx2tx_lut_40_11n);
2268                         b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2269                                        rx2tx_lut_40_11n);
2270                 }
2271                 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
2272         }
2273         b43_phy_write(dev, 0x32F, 0x3);
2274         if (phy->radio_rev == 4 || phy->radio_rev == 6)
2275                 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
2276
2277         if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2278                 if (sprom->revision &&
2279                     sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2280                         b43_radio_write(dev, 0x5, 0x05);
2281                         b43_radio_write(dev, 0x6, 0x30);
2282                         b43_radio_write(dev, 0x7, 0x00);
2283                         b43_radio_set(dev, 0x4f, 0x1);
2284                         b43_radio_set(dev, 0xd4, 0x1);
2285                         bias = 0x1f;
2286                         conv = 0x6f;
2287                         filt = 0xaa;
2288                 } else {
2289                         bias = 0x2b;
2290                         conv = 0x7f;
2291                         filt = 0xee;
2292                 }
2293                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2294                         for (core = 0; core < 2; core++) {
2295                                 if (core == 0) {
2296                                         b43_radio_write(dev, 0x5F, bias);
2297                                         b43_radio_write(dev, 0x64, conv);
2298                                         b43_radio_write(dev, 0x66, filt);
2299                                 } else {
2300                                         b43_radio_write(dev, 0xE8, bias);
2301                                         b43_radio_write(dev, 0xE9, conv);
2302                                         b43_radio_write(dev, 0xEB, filt);
2303                                 }
2304                         }
2305                 }
2306         }
2307
2308         if (b43_nphy_ipa(dev)) {
2309                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2310                         if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2311                             phy->radio_rev == 6) {
2312                                 for (core = 0; core < 2; core++) {
2313                                         if (core == 0)
2314                                                 b43_radio_write(dev, 0x51,
2315                                                                 0x7f);
2316                                         else
2317                                                 b43_radio_write(dev, 0xd6,
2318                                                                 0x7f);
2319                                 }
2320                         }
2321                         if (phy->radio_rev == 3) {
2322                                 for (core = 0; core < 2; core++) {
2323                                         if (core == 0) {
2324                                                 b43_radio_write(dev, 0x64,
2325                                                                 0x13);
2326                                                 b43_radio_write(dev, 0x5F,
2327                                                                 0x1F);
2328                                                 b43_radio_write(dev, 0x66,
2329                                                                 0xEE);
2330                                                 b43_radio_write(dev, 0x59,
2331                                                                 0x8A);
2332                                                 b43_radio_write(dev, 0x80,
2333                                                                 0x3E);
2334                                         } else {
2335                                                 b43_radio_write(dev, 0x69,
2336                                                                 0x13);
2337                                                 b43_radio_write(dev, 0xE8,
2338                                                                 0x1F);
2339                                                 b43_radio_write(dev, 0xEB,
2340                                                                 0xEE);
2341                                                 b43_radio_write(dev, 0xDE,
2342                                                                 0x8A);
2343                                                 b43_radio_write(dev, 0x105,
2344                                                                 0x3E);
2345                                         }
2346                                 }
2347                         } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2348                                 if (!phy->is_40mhz) {
2349                                         b43_radio_write(dev, 0x5F, 0x14);
2350                                         b43_radio_write(dev, 0xE8, 0x12);
2351                                 } else {
2352                                         b43_radio_write(dev, 0x5F, 0x16);
2353                                         b43_radio_write(dev, 0xE8, 0x16);
2354                                 }
2355                         }
2356                 } else {
2357                         u16 freq = phy->channel_freq;
2358                         if ((freq >= 5180 && freq <= 5230) ||
2359                             (freq >= 5745 && freq <= 5805)) {
2360                                 b43_radio_write(dev, 0x7D, 0xFF);
2361                                 b43_radio_write(dev, 0xFE, 0xFF);
2362                         }
2363                 }
2364         } else {
2365                 if (phy->radio_rev != 5) {
2366                         for (core = 0; core < 2; core++) {
2367                                 if (core == 0) {
2368                                         b43_radio_write(dev, 0x5c, 0x61);
2369                                         b43_radio_write(dev, 0x51, 0x70);
2370                                 } else {
2371                                         b43_radio_write(dev, 0xe1, 0x61);
2372                                         b43_radio_write(dev, 0xd6, 0x70);
2373                                 }
2374                         }
2375                 }
2376         }
2377
2378         if (phy->radio_rev == 4) {
2379                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2380                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2381                 for (core = 0; core < 2; core++) {
2382                         if (core == 0) {
2383                                 b43_radio_write(dev, 0x1a1, 0x00);
2384                                 b43_radio_write(dev, 0x1a2, 0x3f);
2385                                 b43_radio_write(dev, 0x1a6, 0x3f);
2386                         } else {
2387                                 b43_radio_write(dev, 0x1a7, 0x00);
2388                                 b43_radio_write(dev, 0x1ab, 0x3f);
2389                                 b43_radio_write(dev, 0x1ac, 0x3f);
2390                         }
2391                 }
2392         } else {
2393                 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2394                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2395                 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2396                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2397
2398                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2399                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2400                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2401                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2402                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2403                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2404
2405                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2406                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2407                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2408                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2409         }
2410
2411         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2412
2413         b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2414         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2415         b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2416         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2417         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2418         b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2419         b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2420
2421         if (!phy->is_40mhz) {
2422                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2423                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2424         } else {
2425                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2426                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2427         }
2428
2429         b43_nphy_gain_ctl_workarounds(dev);
2430
2431         /* TODO
2432         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2433                             aux_adc_vmid_rev7_core0);
2434         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2435                             aux_adc_vmid_rev7_core1);
2436         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2437                             aux_adc_gain_rev7);
2438         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2439                             aux_adc_gain_rev7);
2440         */
2441 }
2442
2443 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2444 {
2445         struct b43_phy_n *nphy = dev->phy.n;
2446         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2447
2448         /* TX to RX */
2449         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2450         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2451         /* RX to TX */
2452         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2453                                         0x1F };
2454         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2455         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2456         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2457
2458         u16 tmp16;
2459         u32 tmp32;
2460
2461         b43_phy_write(dev, 0x23f, 0x1f8);
2462         b43_phy_write(dev, 0x240, 0x1f8);
2463
2464         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2465         tmp32 &= 0xffffff;
2466         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2467
2468         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2469         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2470         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2471         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2472         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2473         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2474
2475         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2476         b43_phy_write(dev, 0x2AE, 0x000C);
2477
2478         /* TX to RX */
2479         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2480                                  ARRAY_SIZE(tx2rx_events));
2481
2482         /* RX to TX */
2483         if (b43_nphy_ipa(dev))
2484                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2485                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2486         if (nphy->hw_phyrxchain != 3 &&
2487             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2488                 if (b43_nphy_ipa(dev)) {
2489                         rx2tx_delays[5] = 59;
2490                         rx2tx_delays[6] = 1;
2491                         rx2tx_events[7] = 0x1F;
2492                 }
2493                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2494                                          ARRAY_SIZE(rx2tx_events));
2495         }
2496
2497         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2498                 0x2 : 0x9C40;
2499         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2500
2501         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
2502
2503         if (!dev->phy.is_40mhz) {
2504                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2505                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2506         } else {
2507                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2508                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2509         }
2510
2511         b43_nphy_gain_ctl_workarounds(dev);
2512
2513         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2514         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2515
2516         /* TODO */
2517
2518         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2519         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2520         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2521         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2522         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2523         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2524         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2525         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2526         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2527         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2528         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2529         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2530
2531         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2532
2533         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2534              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2535             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2536              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2537                 tmp32 = 0x00088888;
2538         else
2539                 tmp32 = 0x88888888;
2540         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2541         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2542         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2543
2544         if (dev->phy.rev == 4 &&
2545             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2546                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2547                                 0x70);
2548                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2549                                 0x70);
2550         }
2551
2552         /* Dropped probably-always-true condition */
2553         b43_phy_write(dev, 0x224, 0x03eb);
2554         b43_phy_write(dev, 0x225, 0x03eb);
2555         b43_phy_write(dev, 0x226, 0x0341);
2556         b43_phy_write(dev, 0x227, 0x0341);
2557         b43_phy_write(dev, 0x228, 0x042b);
2558         b43_phy_write(dev, 0x229, 0x042b);
2559         b43_phy_write(dev, 0x22a, 0x0381);
2560         b43_phy_write(dev, 0x22b, 0x0381);
2561         b43_phy_write(dev, 0x22c, 0x042b);
2562         b43_phy_write(dev, 0x22d, 0x042b);
2563         b43_phy_write(dev, 0x22e, 0x0381);
2564         b43_phy_write(dev, 0x22f, 0x0381);
2565
2566         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2567                 ; /* TODO: 0x0080000000000000 HF */
2568 }
2569
2570 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2571 {
2572         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2573         struct b43_phy *phy = &dev->phy;
2574         struct b43_phy_n *nphy = phy->n;
2575
2576         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2577         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2578
2579         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2580         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2581
2582         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2583             dev->dev->board_type == 0x8B) {
2584                 delays1[0] = 0x1;
2585                 delays1[5] = 0x14;
2586         }
2587
2588         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2589             nphy->band5g_pwrgain) {
2590                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2591                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2592         } else {
2593                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2594                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2595         }
2596
2597         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2598         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2599         if (dev->phy.rev < 3) {
2600                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2601                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2602         }
2603
2604         if (dev->phy.rev < 2) {
2605                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2606                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2607                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2608                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2609                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2610                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2611         }
2612
2613         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2614         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2615         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2616         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2617
2618         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2619         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2620
2621         b43_nphy_gain_ctl_workarounds(dev);
2622
2623         if (dev->phy.rev < 2) {
2624                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2625                         b43_hf_write(dev, b43_hf_read(dev) |
2626                                         B43_HF_MLADVW);
2627         } else if (dev->phy.rev == 2) {
2628                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2629                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2630         }
2631
2632         if (dev->phy.rev < 2)
2633                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2634                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2635
2636         /* Set phase track alpha and beta */
2637         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2638         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2639         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2640         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2641         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2642         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2643
2644         if (dev->phy.rev < 3) {
2645                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2646                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2647                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2648                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2649                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2650         }
2651
2652         if (dev->phy.rev == 2)
2653                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2654                                 B43_NPHY_FINERX2_CGC_DECGC);
2655 }
2656
2657 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2658 static void b43_nphy_workarounds(struct b43_wldev *dev)
2659 {
2660         struct b43_phy *phy = &dev->phy;
2661         struct b43_phy_n *nphy = phy->n;
2662
2663         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2664                 b43_nphy_classifier(dev, 1, 0);
2665         else
2666                 b43_nphy_classifier(dev, 1, 1);
2667
2668         if (nphy->hang_avoid)
2669                 b43_nphy_stay_in_carrier_search(dev, 1);
2670
2671         b43_phy_set(dev, B43_NPHY_IQFLIP,
2672                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2673
2674         if (dev->phy.rev >= 7)
2675                 b43_nphy_workarounds_rev7plus(dev);
2676         else if (dev->phy.rev >= 3)
2677                 b43_nphy_workarounds_rev3plus(dev);
2678         else
2679                 b43_nphy_workarounds_rev1_2(dev);
2680
2681         if (nphy->hang_avoid)
2682                 b43_nphy_stay_in_carrier_search(dev, 0);
2683 }
2684
2685 /**************************************************
2686  * Tx/Rx common
2687  **************************************************/
2688
2689 /*
2690  * Transmits a known value for LO calibration
2691  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2692  */
2693 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2694                                 bool iqmode, bool dac_test)
2695 {
2696         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2697         if (samp == 0)
2698                 return -1;
2699         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2700         return 0;
2701 }
2702
2703 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2704 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2705 {
2706         struct b43_phy_n *nphy = dev->phy.n;
2707
2708         bool override = false;
2709         u16 chain = 0x33;
2710
2711         if (nphy->txrx_chain == 0) {
2712                 chain = 0x11;
2713                 override = true;
2714         } else if (nphy->txrx_chain == 1) {
2715                 chain = 0x22;
2716                 override = true;
2717         }
2718
2719         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2720                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2721                         chain);
2722
2723         if (override)
2724                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2725                                 B43_NPHY_RFSEQMODE_CAOVER);
2726         else
2727                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2728                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2729 }
2730
2731 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2732 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2733 {
2734         struct b43_phy_n *nphy = dev->phy.n;
2735         u16 tmp;
2736
2737         if (nphy->hang_avoid)
2738                 b43_nphy_stay_in_carrier_search(dev, 1);
2739
2740         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2741         if (tmp & 0x1)
2742                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2743         else if (tmp & 0x2)
2744                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2745
2746         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2747
2748         if (nphy->bb_mult_save & 0x80000000) {
2749                 tmp = nphy->bb_mult_save & 0xFFFF;
2750                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2751                 nphy->bb_mult_save = 0;
2752         }
2753
2754         if (nphy->hang_avoid)
2755                 b43_nphy_stay_in_carrier_search(dev, 0);
2756 }
2757
2758 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2759 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2760                                         struct nphy_txgains target,
2761                                         struct nphy_iqcal_params *params)
2762 {
2763         int i, j, indx;
2764         u16 gain;
2765
2766         if (dev->phy.rev >= 3) {
2767                 params->txgm = target.txgm[core];
2768                 params->pga = target.pga[core];
2769                 params->pad = target.pad[core];
2770                 params->ipa = target.ipa[core];
2771                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2772                                         (params->pad << 4) | (params->ipa);
2773                 for (j = 0; j < 5; j++)
2774                         params->ncorr[j] = 0x79;
2775         } else {
2776                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2777                         (target.txgm[core] << 8);
2778
2779                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2780                         1 : 0;
2781                 for (i = 0; i < 9; i++)
2782                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2783                                 break;
2784                 i = min(i, 8);
2785
2786                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2787                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2788                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2789                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2790                                         (params->pad << 2);
2791                 for (j = 0; j < 4; j++)
2792                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2793         }
2794 }
2795
2796 /**************************************************
2797  * Tx and Rx
2798  **************************************************/
2799
2800 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2801 {//TODO
2802 }
2803
2804 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2805                                                         bool ignore_tssi)
2806 {//TODO
2807         return B43_TXPWR_RES_DONE;
2808 }
2809
2810 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2811 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2812 {
2813         struct b43_phy_n *nphy = dev->phy.n;
2814         u8 i;
2815         u16 bmask, val, tmp;
2816         enum ieee80211_band band = b43_current_band(dev->wl);
2817
2818         if (nphy->hang_avoid)
2819                 b43_nphy_stay_in_carrier_search(dev, 1);
2820
2821         nphy->txpwrctrl = enable;
2822         if (!enable) {
2823                 if (dev->phy.rev >= 3 &&
2824                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2825                      (B43_NPHY_TXPCTL_CMD_COEFF |
2826                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2827                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2828                         /* We disable enabled TX pwr ctl, save it's state */
2829                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2830                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2831                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2832                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2833                 }
2834
2835                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2836                 for (i = 0; i < 84; i++)
2837                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2838
2839                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2840                 for (i = 0; i < 84; i++)
2841                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2842
2843                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2844                 if (dev->phy.rev >= 3)
2845                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2846                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2847
2848                 if (dev->phy.rev >= 3) {
2849                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2850                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2851                 } else {
2852                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2853                 }
2854
2855                 if (dev->phy.rev == 2)
2856                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2857                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2858                 else if (dev->phy.rev < 2)
2859                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2860                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2861
2862                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2863                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2864         } else {
2865                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2866                                     nphy->adj_pwr_tbl);
2867                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2868                                     nphy->adj_pwr_tbl);
2869
2870                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2871                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2872                 /* wl does useless check for "enable" param here */
2873                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2874                 if (dev->phy.rev >= 3) {
2875                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2876                         if (val)
2877                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2878                 }
2879                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2880
2881                 if (band == IEEE80211_BAND_5GHZ) {
2882                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2883                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2884                         if (dev->phy.rev > 1)
2885                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2886                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2887                                                 0x64);
2888                 }
2889
2890                 if (dev->phy.rev >= 3) {
2891                         if (nphy->tx_pwr_idx[0] != 128 &&
2892                             nphy->tx_pwr_idx[1] != 128) {
2893                                 /* Recover TX pwr ctl state */
2894                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2895                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
2896                                                 nphy->tx_pwr_idx[0]);
2897                                 if (dev->phy.rev > 1)
2898                                         b43_phy_maskset(dev,
2899                                                 B43_NPHY_TXPCTL_INIT,
2900                                                 ~0xff, nphy->tx_pwr_idx[1]);
2901                         }
2902                 }
2903
2904                 if (dev->phy.rev >= 3) {
2905                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2906                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2907                 } else {
2908                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2909                 }
2910
2911                 if (dev->phy.rev == 2)
2912                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2913                 else if (dev->phy.rev < 2)
2914                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2915
2916                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2917                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2918
2919                 if (b43_nphy_ipa(dev)) {
2920                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2921                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2922                 }
2923         }
2924
2925         if (nphy->hang_avoid)
2926                 b43_nphy_stay_in_carrier_search(dev, 0);
2927 }
2928
2929 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2930 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2931 {
2932         struct b43_phy_n *nphy = dev->phy.n;
2933         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2934
2935         u8 txpi[2], bbmult, i;
2936         u16 tmp, radio_gain, dac_gain;
2937         u16 freq = dev->phy.channel_freq;
2938         u32 txgain;
2939         /* u32 gaintbl; rev3+ */
2940
2941         if (nphy->hang_avoid)
2942                 b43_nphy_stay_in_carrier_search(dev, 1);
2943
2944         if (dev->phy.rev >= 7) {
2945                 txpi[0] = txpi[1] = 30;
2946         } else if (dev->phy.rev >= 3) {
2947                 txpi[0] = 40;
2948                 txpi[1] = 40;
2949         } else if (sprom->revision < 4) {
2950                 txpi[0] = 72;
2951                 txpi[1] = 72;
2952         } else {
2953                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2954                         txpi[0] = sprom->txpid2g[0];
2955                         txpi[1] = sprom->txpid2g[1];
2956                 } else if (freq >= 4900 && freq < 5100) {
2957                         txpi[0] = sprom->txpid5gl[0];
2958                         txpi[1] = sprom->txpid5gl[1];
2959                 } else if (freq >= 5100 && freq < 5500) {
2960                         txpi[0] = sprom->txpid5g[0];
2961                         txpi[1] = sprom->txpid5g[1];
2962                 } else if (freq >= 5500) {
2963                         txpi[0] = sprom->txpid5gh[0];
2964                         txpi[1] = sprom->txpid5gh[1];
2965                 } else {
2966                         txpi[0] = 91;
2967                         txpi[1] = 91;
2968                 }
2969         }
2970         if (dev->phy.rev < 7 &&
2971             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
2972                 txpi[0] = txpi[1] = 91;
2973
2974         /*
2975         for (i = 0; i < 2; i++) {
2976                 nphy->txpwrindex[i].index_internal = txpi[i];
2977                 nphy->txpwrindex[i].index_internal_save = txpi[i];
2978         }
2979         */
2980
2981         for (i = 0; i < 2; i++) {
2982                 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2983
2984                 if (dev->phy.rev >= 3)
2985                         radio_gain = (txgain >> 16) & 0x1FFFF;
2986                 else
2987                         radio_gain = (txgain >> 16) & 0x1FFF;
2988
2989                 if (dev->phy.rev >= 7)
2990                         dac_gain = (txgain >> 8) & 0x7;
2991                 else
2992                         dac_gain = (txgain >> 8) & 0x3F;
2993                 bbmult = txgain & 0xFF;
2994
2995                 if (dev->phy.rev >= 3) {
2996                         if (i == 0)
2997                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2998                         else
2999                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3000                 } else {
3001                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3002                 }
3003
3004                 if (i == 0)
3005                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3006                 else
3007                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3008
3009                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3010
3011                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3012                 if (i == 0)
3013                         tmp = (tmp & 0x00FF) | (bbmult << 8);
3014                 else
3015                         tmp = (tmp & 0xFF00) | bbmult;
3016                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3017
3018                 if (b43_nphy_ipa(dev)) {
3019                         u32 tmp32;
3020                         u16 reg = (i == 0) ?
3021                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3022                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3023                                                               576 + txpi[i]));
3024                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3025                         b43_phy_set(dev, reg, 0x4);
3026                 }
3027         }
3028
3029         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3030
3031         if (nphy->hang_avoid)
3032                 b43_nphy_stay_in_carrier_search(dev, 0);
3033 }
3034
3035 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3036 {
3037         struct b43_phy *phy = &dev->phy;
3038
3039         u8 core;
3040         u16 r; /* routing */
3041
3042         if (phy->rev >= 7) {
3043                 for (core = 0; core < 2; core++) {
3044                         r = core ? 0x190 : 0x170;
3045                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3046                                 b43_radio_write(dev, r + 0x5, 0x5);
3047                                 b43_radio_write(dev, r + 0x9, 0xE);
3048                                 if (phy->rev != 5)
3049                                         b43_radio_write(dev, r + 0xA, 0);
3050                                 if (phy->rev != 7)
3051                                         b43_radio_write(dev, r + 0xB, 1);
3052                                 else
3053                                         b43_radio_write(dev, r + 0xB, 0x31);
3054                         } else {
3055                                 b43_radio_write(dev, r + 0x5, 0x9);
3056                                 b43_radio_write(dev, r + 0x9, 0xC);
3057                                 b43_radio_write(dev, r + 0xB, 0x0);
3058                                 if (phy->rev != 5)
3059                                         b43_radio_write(dev, r + 0xA, 1);
3060                                 else
3061                                         b43_radio_write(dev, r + 0xA, 0x31);
3062                         }
3063                         b43_radio_write(dev, r + 0x6, 0);
3064                         b43_radio_write(dev, r + 0x7, 0);
3065                         b43_radio_write(dev, r + 0x8, 3);
3066                         b43_radio_write(dev, r + 0xC, 0);
3067                 }
3068         } else {
3069                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3070                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3071                 else
3072                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3073                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3074                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3075
3076                 for (core = 0; core < 2; core++) {
3077                         r = core ? B2056_TX1 : B2056_TX0;
3078
3079                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3080                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3081                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3082                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3083                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3084                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3085                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3086                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3087                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3088                                                 0x5);
3089                                 if (phy->rev != 5)
3090                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
3091                                                         0x00);
3092                                 if (phy->rev >= 5)
3093                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3094                                                         0x31);
3095                                 else
3096                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3097                                                         0x11);
3098                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3099                                                 0xE);
3100                         } else {
3101                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3102                                                 0x9);
3103                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3104                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3105                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3106                                                 0xC);
3107                         }
3108                 }
3109         }
3110 }
3111
3112 /*
3113  * Stop radio and transmit known signal. Then check received signal strength to
3114  * get TSSI (Transmit Signal Strength Indicator).
3115  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3116  */
3117 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3118 {
3119         struct b43_phy *phy = &dev->phy;
3120         struct b43_phy_n *nphy = dev->phy.n;
3121
3122         u32 tmp;
3123         s32 rssi[4] = { };
3124
3125         /* TODO: check if we can transmit */
3126
3127         if (b43_nphy_ipa(dev))
3128                 b43_nphy_ipa_internal_tssi_setup(dev);
3129
3130         if (phy->rev >= 7)
3131                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3132         else if (phy->rev >= 3)
3133                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3134
3135         b43_nphy_stop_playback(dev);
3136         b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3137         udelay(20);
3138         tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
3139         b43_nphy_stop_playback(dev);
3140         b43_nphy_rssi_select(dev, 0, 0);
3141
3142         if (phy->rev >= 7)
3143                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3144         else if (phy->rev >= 3)
3145                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3146
3147         if (phy->rev >= 3) {
3148                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3149                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3150         } else {
3151                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3152                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3153         }
3154         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3155         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3156 }
3157
3158 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3159 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3160 {
3161         struct b43_phy_n *nphy = dev->phy.n;
3162
3163         u8 idx, delta;
3164         u8 i, stf_mode;
3165
3166         for (i = 0; i < 4; i++)
3167                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3168
3169         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3170                 delta = 0;
3171                 switch (stf_mode) {
3172                 case 0:
3173                         if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3174                                 idx = 68;
3175                         } else {
3176                                 delta = 1;
3177                                 idx = dev->phy.is_40mhz ? 52 : 4;
3178                         }
3179                         break;
3180                 case 1:
3181                         idx = dev->phy.is_40mhz ? 76 : 28;
3182                         break;
3183                 case 2:
3184                         idx = dev->phy.is_40mhz ? 84 : 36;
3185                         break;
3186                 case 3:
3187                         idx = dev->phy.is_40mhz ? 92 : 44;
3188                         break;
3189                 }
3190
3191                 for (i = 0; i < 20; i++) {
3192                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3193                                 nphy->tx_power_offset[idx];
3194                         if (i == 0)
3195                                 idx += delta;
3196                         if (i == 14)
3197                                 idx += 1 - delta;
3198                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3199                             i == 13)
3200                                 idx += 1;
3201                 }
3202         }
3203 }
3204
3205 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3206 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3207 {
3208         struct b43_phy_n *nphy = dev->phy.n;
3209         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3210
3211         s16 a1[2], b0[2], b1[2];
3212         u8 idle[2];
3213         s8 target[2];
3214         s32 num, den, pwr;
3215         u32 regval[64];
3216
3217         u16 freq = dev->phy.channel_freq;
3218         u16 tmp;
3219         u16 r; /* routing */
3220         u8 i, c;
3221
3222         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3223                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3224                 b43_read32(dev, B43_MMIO_MACCTL);
3225                 udelay(1);
3226         }
3227
3228         if (nphy->hang_avoid)
3229                 b43_nphy_stay_in_carrier_search(dev, true);
3230
3231         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3232         if (dev->phy.rev >= 3)
3233                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3234                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3235         else
3236                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3237                             B43_NPHY_TXPCTL_CMD_PCTLEN);
3238
3239         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3240                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3241
3242         if (sprom->revision < 4) {
3243                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3244                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3245                 target[0] = target[1] = 52;
3246                 a1[0] = a1[1] = -424;
3247                 b0[0] = b0[1] = 5612;
3248                 b1[0] = b1[1] = -1393;
3249         } else {
3250                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3251                         for (c = 0; c < 2; c++) {
3252                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3253                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3254                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3255                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3256                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3257                         }
3258                 } else if (freq >= 4900 && freq < 5100) {
3259                         for (c = 0; c < 2; c++) {
3260                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3261                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3262                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3263                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3264                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3265                         }
3266                 } else if (freq >= 5100 && freq < 5500) {
3267                         for (c = 0; c < 2; c++) {
3268                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3269                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3270                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3271                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3272                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3273                         }
3274                 } else if (freq >= 5500) {
3275                         for (c = 0; c < 2; c++) {
3276                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3277                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3278                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3279                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3280                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3281                         }
3282                 } else {
3283                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3284                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3285                         target[0] = target[1] = 52;
3286                         a1[0] = a1[1] = -424;
3287                         b0[0] = b0[1] = 5612;
3288                         b1[0] = b1[1] = -1393;
3289                 }
3290         }
3291         /* target[0] = target[1] = nphy->tx_power_max; */
3292
3293         if (dev->phy.rev >= 3) {
3294                 if (sprom->fem.ghz2.tssipos)
3295                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3296                 if (dev->phy.rev >= 7) {
3297                         for (c = 0; c < 2; c++) {
3298                                 r = c ? 0x190 : 0x170;
3299                                 if (b43_nphy_ipa(dev))
3300                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3301                         }
3302                 } else {
3303                         if (b43_nphy_ipa(dev)) {
3304                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3305                                 b43_radio_write(dev,
3306                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3307                                 b43_radio_write(dev,
3308                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3309                         } else {
3310                                 b43_radio_write(dev,
3311                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3312                                 b43_radio_write(dev,
3313                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3314                         }
3315                 }
3316         }
3317
3318         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3319                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3320                 b43_read32(dev, B43_MMIO_MACCTL);
3321                 udelay(1);
3322         }
3323
3324         if (dev->phy.rev >= 7) {
3325                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3326                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3327                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3328                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3329         } else {
3330                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3331                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3332                 if (dev->phy.rev > 1)
3333                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3334                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3335         }
3336
3337         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3338                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3339
3340         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3341                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3342                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3343         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3344                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3345                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3346                       B43_NPHY_TXPCTL_ITSSI_BINF);
3347         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3348                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3349                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3350
3351         for (c = 0; c < 2; c++) {
3352                 for (i = 0; i < 64; i++) {
3353                         num = 8 * (16 * b0[c] + b1[c] * i);
3354                         den = 32768 + a1[c] * i;
3355                         pwr = max((4 * num + den / 2) / den, -8);
3356                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3357                                 pwr = max(pwr, target[c] + 1);
3358                         regval[i] = pwr;
3359                 }
3360                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3361         }
3362
3363         b43_nphy_tx_prepare_adjusted_power_table(dev);
3364         /*
3365         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3366         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3367         */
3368
3369         if (nphy->hang_avoid)
3370                 b43_nphy_stay_in_carrier_search(dev, false);
3371 }
3372
3373 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3374 {
3375         struct b43_phy *phy = &dev->phy;
3376
3377         const u32 *table = NULL;
3378         u32 rfpwr_offset;
3379         u8 pga_gain;
3380         int i;
3381
3382         table = b43_nphy_get_tx_gain_table(dev);
3383         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3384         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3385
3386         if (phy->rev >= 3) {
3387 #if 0
3388                 nphy->gmval = (table[0] >> 16) & 0x7000;
3389 #endif
3390
3391                 for (i = 0; i < 128; i++) {
3392                         pga_gain = (table[i] >> 24) & 0xF;
3393                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3394                                 rfpwr_offset =
3395                                  b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3396                         else
3397                                 rfpwr_offset =
3398                                  0; /* FIXME */
3399                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3400                                        rfpwr_offset);
3401                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3402                                        rfpwr_offset);
3403                 }
3404         }
3405 }
3406
3407 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3408 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3409 {
3410         struct b43_phy_n *nphy = dev->phy.n;
3411         enum ieee80211_band band;
3412         u16 tmp;
3413
3414         if (!enable) {
3415                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3416                                                        B43_NPHY_RFCTL_INTC1);
3417                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3418                                                        B43_NPHY_RFCTL_INTC2);
3419                 band = b43_current_band(dev->wl);
3420                 if (dev->phy.rev >= 3) {
3421                         if (band == IEEE80211_BAND_5GHZ)
3422                                 tmp = 0x600;
3423                         else
3424                                 tmp = 0x480;
3425                 } else {
3426                         if (band == IEEE80211_BAND_5GHZ)
3427                                 tmp = 0x180;
3428                         else
3429                                 tmp = 0x120;
3430                 }
3431                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3432                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3433         } else {
3434                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3435                                 nphy->rfctrl_intc1_save);
3436                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3437                                 nphy->rfctrl_intc2_save);
3438         }
3439 }
3440
3441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3442 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3443 {
3444         u16 tmp;
3445
3446         if (dev->phy.rev >= 3) {
3447                 if (b43_nphy_ipa(dev)) {
3448                         tmp = 4;
3449                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3450                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3451                 }
3452
3453                 tmp = 1;
3454                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3455                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3456         }
3457 }
3458
3459 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3460 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3461                                 u16 samps, u8 time, bool wait)
3462 {
3463         int i;
3464         u16 tmp;
3465
3466         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3467         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3468         if (wait)
3469                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3470         else
3471                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3472
3473         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3474
3475         for (i = 1000; i; i--) {
3476                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3477                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3478                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3479                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3480                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3481                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3482                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3483                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3484
3485                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3486                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3487                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3488                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3489                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3490                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3491                         return;
3492                 }
3493                 udelay(10);
3494         }
3495         memset(est, 0, sizeof(*est));
3496 }
3497
3498 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3499 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3500                                         struct b43_phy_n_iq_comp *pcomp)
3501 {
3502         if (write) {
3503                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3504                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3505                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3506                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3507         } else {
3508                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3509                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3510                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3511                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3512         }
3513 }
3514
3515 #if 0
3516 /* Ready but not used anywhere */
3517 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3518 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3519 {
3520         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3521
3522         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3523         if (core == 0) {
3524                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3525                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3526         } else {
3527                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3528                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3529         }
3530         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3531         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3532         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3533         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3534         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3535         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3536         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3537         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3538 }
3539
3540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3541 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3542 {
3543         u8 rxval, txval;
3544         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3545
3546         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3547         if (core == 0) {
3548                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3549                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3550         } else {
3551                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3552                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3553         }
3554         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3555         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3556         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3557         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3558         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3559         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3560         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3561         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3562
3563         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3564         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3565
3566         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3567                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3568                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3569         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3570                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3571         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3572                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3573         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3574                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3575
3576         if (core == 0) {
3577                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3578                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3579         } else {
3580                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3581                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3582         }
3583
3584         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3585         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3586         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3587
3588         if (core == 0) {
3589                 rxval = 1;
3590                 txval = 8;
3591         } else {
3592                 rxval = 4;
3593                 txval = 2;
3594         }
3595         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3596         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3597 }
3598 #endif
3599
3600 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3601 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3602 {
3603         int i;
3604         s32 iq;
3605         u32 ii;
3606         u32 qq;
3607         int iq_nbits, qq_nbits;
3608         int arsh, brsh;
3609         u16 tmp, a, b;
3610
3611         struct nphy_iq_est est;
3612         struct b43_phy_n_iq_comp old;
3613         struct b43_phy_n_iq_comp new = { };
3614         bool error = false;
3615
3616         if (mask == 0)
3617                 return;
3618
3619         b43_nphy_rx_iq_coeffs(dev, false, &old);
3620         b43_nphy_rx_iq_coeffs(dev, true, &new);
3621         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3622         new = old;
3623
3624         for (i = 0; i < 2; i++) {
3625                 if (i == 0 && (mask & 1)) {
3626                         iq = est.iq0_prod;
3627                         ii = est.i0_pwr;
3628                         qq = est.q0_pwr;
3629                 } else if (i == 1 && (mask & 2)) {
3630                         iq = est.iq1_prod;
3631                         ii = est.i1_pwr;
3632                         qq = est.q1_pwr;
3633                 } else {
3634                         continue;
3635                 }
3636
3637                 if (ii + qq < 2) {
3638                         error = true;
3639                         break;
3640                 }
3641
3642                 iq_nbits = fls(abs(iq));
3643                 qq_nbits = fls(qq);
3644
3645                 arsh = iq_nbits - 20;
3646                 if (arsh >= 0) {
3647                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3648                         tmp = ii >> arsh;
3649                 } else {
3650                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3651                         tmp = ii << -arsh;
3652                 }
3653                 if (tmp == 0) {
3654                         error = true;
3655                         break;
3656                 }
3657                 a /= tmp;
3658
3659                 brsh = qq_nbits - 11;
3660                 if (brsh >= 0) {
3661                         b = (qq << (31 - qq_nbits));
3662                         tmp = ii >> brsh;
3663                 } else {
3664                         b = (qq << (31 - qq_nbits));
3665                         tmp = ii << -brsh;
3666                 }
3667                 if (tmp == 0) {
3668                         error = true;
3669                         break;
3670                 }
3671                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3672
3673                 if (i == 0 && (mask & 0x1)) {
3674                         if (dev->phy.rev >= 3) {
3675                                 new.a0 = a & 0x3FF;
3676                                 new.b0 = b & 0x3FF;
3677                         } else {
3678                                 new.a0 = b & 0x3FF;
3679                                 new.b0 = a & 0x3FF;
3680                         }
3681                 } else if (i == 1 && (mask & 0x2)) {
3682                         if (dev->phy.rev >= 3) {
3683                                 new.a1 = a & 0x3FF;
3684                                 new.b1 = b & 0x3FF;
3685                         } else {
3686                                 new.a1 = b & 0x3FF;
3687                                 new.b1 = a & 0x3FF;
3688                         }
3689                 }
3690         }
3691
3692         if (error)
3693                 new = old;
3694
3695         b43_nphy_rx_iq_coeffs(dev, true, &new);
3696 }
3697
3698 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3699 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3700 {
3701         u16 array[4];
3702         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3703
3704         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3705         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3706         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3707         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3708 }
3709
3710 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3711 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3712 {
3713         struct b43_phy_n *nphy = dev->phy.n;
3714
3715         u8 channel = dev->phy.channel;
3716         int tone[2] = { 57, 58 };
3717         u32 noise[2] = { 0x3FF, 0x3FF };
3718
3719         B43_WARN_ON(dev->phy.rev < 3);
3720
3721         if (nphy->hang_avoid)
3722                 b43_nphy_stay_in_carrier_search(dev, 1);
3723
3724         if (nphy->gband_spurwar_en) {
3725                 /* TODO: N PHY Adjust Analog Pfbw (7) */
3726                 if (channel == 11 && dev->phy.is_40mhz)
3727                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3728                 else
3729                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3730                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3731         }
3732
3733         if (nphy->aband_spurwar_en) {
3734                 if (channel == 54) {
3735                         tone[0] = 0x20;
3736                         noise[0] = 0x25F;
3737                 } else if (channel == 38 || channel == 102 || channel == 118) {
3738                         if (0 /* FIXME */) {
3739                                 tone[0] = 0x20;
3740                                 noise[0] = 0x21F;
3741                         } else {
3742                                 tone[0] = 0;
3743                                 noise[0] = 0;
3744                         }
3745                 } else if (channel == 134) {
3746                         tone[0] = 0x20;
3747                         noise[0] = 0x21F;
3748                 } else if (channel == 151) {
3749                         tone[0] = 0x10;
3750                         noise[0] = 0x23F;
3751                 } else if (channel == 153 || channel == 161) {
3752                         tone[0] = 0x30;
3753                         noise[0] = 0x23F;
3754                 } else {
3755                         tone[0] = 0;
3756                         noise[0] = 0;
3757                 }
3758
3759                 if (!tone[0] && !noise[0])
3760                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3761                 else
3762                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3763         }
3764
3765         if (nphy->hang_avoid)
3766                 b43_nphy_stay_in_carrier_search(dev, 0);
3767 }
3768
3769 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3770 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3771 {
3772         struct b43_phy_n *nphy = dev->phy.n;
3773         int i, j;
3774         u32 tmp;
3775         u32 cur_real, cur_imag, real_part, imag_part;
3776
3777         u16 buffer[7];
3778
3779         if (nphy->hang_avoid)
3780                 b43_nphy_stay_in_carrier_search(dev, true);
3781
3782         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3783
3784         for (i = 0; i < 2; i++) {
3785                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3786                         (buffer[i * 2 + 1] & 0x3FF);
3787                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3788                                 (((i + 26) << 10) | 320));
3789                 for (j = 0; j < 128; j++) {
3790                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3791                                         ((tmp >> 16) & 0xFFFF));
3792                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3793                                         (tmp & 0xFFFF));
3794                 }
3795         }
3796
3797         for (i = 0; i < 2; i++) {
3798                 tmp = buffer[5 + i];
3799                 real_part = (tmp >> 8) & 0xFF;
3800                 imag_part = (tmp & 0xFF);
3801                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3802                                 (((i + 26) << 10) | 448));
3803
3804                 if (dev->phy.rev >= 3) {
3805                         cur_real = real_part;
3806                         cur_imag = imag_part;
3807                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3808                 }
3809
3810                 for (j = 0; j < 128; j++) {
3811                         if (dev->phy.rev < 3) {
3812                                 cur_real = (real_part * loscale[j] + 128) >> 8;
3813                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3814                                 tmp = ((cur_real & 0xFF) << 8) |
3815                                         (cur_imag & 0xFF);
3816                         }
3817                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3818                                         ((tmp >> 16) & 0xFFFF));
3819                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3820                                         (tmp & 0xFFFF));
3821                 }
3822         }
3823
3824         if (dev->phy.rev >= 3) {
3825                 b43_shm_write16(dev, B43_SHM_SHARED,
3826                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3827                 b43_shm_write16(dev, B43_SHM_SHARED,
3828                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3829         }
3830
3831         if (nphy->hang_avoid)
3832                 b43_nphy_stay_in_carrier_search(dev, false);
3833 }
3834
3835 /*
3836  * Restore RSSI Calibration
3837  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3838  */
3839 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3840 {
3841         struct b43_phy_n *nphy = dev->phy.n;
3842
3843         u16 *rssical_radio_regs = NULL;
3844         u16 *rssical_phy_regs = NULL;
3845
3846         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3847                 if (!nphy->rssical_chanspec_2G.center_freq)
3848                         return;
3849                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3850                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3851         } else {
3852                 if (!nphy->rssical_chanspec_5G.center_freq)
3853                         return;
3854                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3855                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3856         }
3857
3858         /* TODO use some definitions */
3859         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3860         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3861
3862         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3863         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3864         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3865         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3866
3867         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3868         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3869         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3870         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3871
3872         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3873         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3874         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3875         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3876 }
3877
3878 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3879 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3880 {
3881         struct b43_phy_n *nphy = dev->phy.n;
3882         u16 *save = nphy->tx_rx_cal_radio_saveregs;
3883         u16 tmp;
3884         u8 offset, i;
3885
3886         if (dev->phy.rev >= 3) {
3887             for (i = 0; i < 2; i++) {
3888                 tmp = (i == 0) ? 0x2000 : 0x3000;
3889                 offset = i * 11;
3890
3891                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3892                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3893                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3894                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3895                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3896                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3897                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3898                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3899                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3900                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3901                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3902
3903                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3904                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3905                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3906                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3907                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3908                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3909                         if (nphy->ipa5g_on) {
3910                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3911                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3912                         } else {
3913                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3914                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3915                         }
3916                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3917                 } else {
3918                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3919                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3920                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3921                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3922                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3923                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3924                         if (nphy->ipa2g_on) {
3925                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3926                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3927                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
3928                         } else {
3929                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3930                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3931                         }
3932                 }
3933                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3934                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3935                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3936             }
3937         } else {
3938                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3939                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3940
3941                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3942                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3943
3944                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3945                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3946
3947                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3948                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3949
3950                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3951                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3952
3953                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3954                     B43_NPHY_BANDCTL_5GHZ)) {
3955                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3956                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3957                 } else {
3958                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3959                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3960                 }
3961
3962                 if (dev->phy.rev < 2) {
3963                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3964                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3965                 } else {
3966                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3967                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3968                 }
3969         }
3970 }
3971
3972 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3973 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3974 {
3975         struct b43_phy_n *nphy = dev->phy.n;
3976         int i;
3977         u16 scale, entry;
3978
3979         u16 tmp = nphy->txcal_bbmult;
3980         if (core == 0)
3981                 tmp >>= 8;
3982         tmp &= 0xff;
3983
3984         for (i = 0; i < 18; i++) {
3985                 scale = (ladder_lo[i].percent * tmp) / 100;
3986                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3987                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3988
3989                 scale = (ladder_iq[i].percent * tmp) / 100;
3990                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3991                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3992         }
3993 }
3994
3995 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3996 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3997 {
3998         int i;
3999         for (i = 0; i < 15; i++)
4000                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4001                                 tbl_tx_filter_coef_rev4[2][i]);
4002 }
4003
4004 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4005 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4006 {
4007         int i, j;
4008         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4009         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4010
4011         for (i = 0; i < 3; i++)
4012                 for (j = 0; j < 15; j++)
4013                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4014                                         tbl_tx_filter_coef_rev4[i][j]);
4015
4016         if (dev->phy.is_40mhz) {
4017                 for (j = 0; j < 15; j++)
4018                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4019                                         tbl_tx_filter_coef_rev4[3][j]);
4020         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4021                 for (j = 0; j < 15; j++)
4022                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4023                                         tbl_tx_filter_coef_rev4[5][j]);
4024         }
4025
4026         if (dev->phy.channel == 14)
4027                 for (j = 0; j < 15; j++)
4028                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4029                                         tbl_tx_filter_coef_rev4[6][j]);
4030 }
4031
4032 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4033 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4034 {
4035         struct b43_phy_n *nphy = dev->phy.n;
4036
4037         u16 curr_gain[2];
4038         struct nphy_txgains target;
4039         const u32 *table = NULL;
4040
4041         if (!nphy->txpwrctrl) {
4042                 int i;
4043
4044                 if (nphy->hang_avoid)
4045                         b43_nphy_stay_in_carrier_search(dev, true);
4046                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4047                 if (nphy->hang_avoid)
4048                         b43_nphy_stay_in_carrier_search(dev, false);
4049
4050                 for (i = 0; i < 2; ++i) {
4051                         if (dev->phy.rev >= 3) {
4052                                 target.ipa[i] = curr_gain[i] & 0x000F;
4053                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4054                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4055                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4056                         } else {
4057                                 target.ipa[i] = curr_gain[i] & 0x0003;
4058                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4059                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4060                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4061                         }
4062                 }
4063         } else {
4064                 int i;
4065                 u16 index[2];
4066                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4067                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4068                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4069                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4070                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4071                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4072
4073                 for (i = 0; i < 2; ++i) {
4074                         table = b43_nphy_get_tx_gain_table(dev);
4075                         if (dev->phy.rev >= 3) {
4076                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4077                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4078                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4079                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4080                         } else {
4081                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4082                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4083                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4084                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4085                         }
4086                 }
4087         }
4088
4089         return target;
4090 }
4091
4092 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4093 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4094 {
4095         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4096
4097         if (dev->phy.rev >= 3) {
4098                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4099                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4100                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4101                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4102                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4103                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4104                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4105                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4106                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4107                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4108                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4109                 b43_nphy_reset_cca(dev);
4110         } else {
4111                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4112                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4113                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4114                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4115                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4116                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4117                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4118         }
4119 }
4120
4121 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4122 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4123 {
4124         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4125         u16 tmp;
4126
4127         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4128         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4129         if (dev->phy.rev >= 3) {
4130                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4131                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4132
4133                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4134                 regs[2] = tmp;
4135                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4136
4137                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4138                 regs[3] = tmp;
4139                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4140
4141                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4142                 b43_phy_mask(dev, B43_NPHY_BBCFG,
4143                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4144
4145                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4146                 regs[5] = tmp;
4147                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4148
4149                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4150                 regs[6] = tmp;
4151                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4152                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4153                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4154
4155                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4156                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4157                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
4158
4159                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4160                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4161                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4162                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4163         } else {
4164                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4165                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4166                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4167                 regs[2] = tmp;
4168                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4169                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4170                 regs[3] = tmp;
4171                 tmp |= 0x2000;
4172                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4173                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4174                 regs[4] = tmp;
4175                 tmp |= 0x2000;
4176                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4177                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4178                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4179                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4180                         tmp = 0x0180;
4181                 else
4182                         tmp = 0x0120;
4183                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4184                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4185         }
4186 }
4187
4188 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4189 static void b43_nphy_save_cal(struct b43_wldev *dev)
4190 {
4191         struct b43_phy_n *nphy = dev->phy.n;
4192
4193         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4194         u16 *txcal_radio_regs = NULL;
4195         struct b43_chanspec *iqcal_chanspec;
4196         u16 *table = NULL;
4197
4198         if (nphy->hang_avoid)
4199                 b43_nphy_stay_in_carrier_search(dev, 1);
4200
4201         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4202                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4203                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4204                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4205                 table = nphy->cal_cache.txcal_coeffs_2G;
4206         } else {
4207                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4208                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4209                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4210                 table = nphy->cal_cache.txcal_coeffs_5G;
4211         }
4212
4213         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4214         /* TODO use some definitions */
4215         if (dev->phy.rev >= 3) {
4216                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4217                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4218                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4219                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4220                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4221                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4222                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4223                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4224         } else {
4225                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4226                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4227                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4228                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4229         }
4230         iqcal_chanspec->center_freq = dev->phy.channel_freq;
4231         iqcal_chanspec->channel_type = dev->phy.channel_type;
4232         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4233
4234         if (nphy->hang_avoid)
4235                 b43_nphy_stay_in_carrier_search(dev, 0);
4236 }
4237
4238 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4239 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4240 {
4241         struct b43_phy_n *nphy = dev->phy.n;
4242
4243         u16 coef[4];
4244         u16 *loft = NULL;
4245         u16 *table = NULL;
4246
4247         int i;
4248         u16 *txcal_radio_regs = NULL;
4249         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4250
4251         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4252                 if (!nphy->iqcal_chanspec_2G.center_freq)
4253                         return;
4254                 table = nphy->cal_cache.txcal_coeffs_2G;
4255                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4256         } else {
4257                 if (!nphy->iqcal_chanspec_5G.center_freq)
4258                         return;
4259                 table = nphy->cal_cache.txcal_coeffs_5G;
4260                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4261         }
4262
4263         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4264
4265         for (i = 0; i < 4; i++) {
4266                 if (dev->phy.rev >= 3)
4267                         table[i] = coef[i];
4268                 else
4269                         coef[i] = 0;
4270         }
4271
4272         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4273         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4274         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4275
4276         if (dev->phy.rev < 2)
4277                 b43_nphy_tx_iq_workaround(dev);
4278
4279         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4280                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4281                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4282         } else {
4283                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4284                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4285         }
4286
4287         /* TODO use some definitions */
4288         if (dev->phy.rev >= 3) {
4289                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4290                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4291                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4292                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4293                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4294                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4295                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4296                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4297         } else {
4298                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4299                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4300                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4301                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4302         }
4303         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4304 }
4305
4306 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4307 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4308                                 struct nphy_txgains target,
4309                                 bool full, bool mphase)
4310 {
4311         struct b43_phy_n *nphy = dev->phy.n;
4312         int i;
4313         int error = 0;
4314         int freq;
4315         bool avoid = false;
4316         u8 length;
4317         u16 tmp, core, type, count, max, numb, last = 0, cmd;
4318         const u16 *table;
4319         bool phy6or5x;
4320
4321         u16 buffer[11];
4322         u16 diq_start = 0;
4323         u16 save[2];
4324         u16 gain[2];
4325         struct nphy_iqcal_params params[2];
4326         bool updated[2] = { };
4327
4328         b43_nphy_stay_in_carrier_search(dev, true);
4329
4330         if (dev->phy.rev >= 4) {
4331                 avoid = nphy->hang_avoid;
4332                 nphy->hang_avoid = false;
4333         }
4334
4335         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4336
4337         for (i = 0; i < 2; i++) {
4338                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4339                 gain[i] = params[i].cal_gain;
4340         }
4341
4342         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4343
4344         b43_nphy_tx_cal_radio_setup(dev);
4345         b43_nphy_tx_cal_phy_setup(dev);
4346
4347         phy6or5x = dev->phy.rev >= 6 ||
4348                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4349                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4350         if (phy6or5x) {
4351                 if (dev->phy.is_40mhz) {
4352                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4353                                         tbl_tx_iqlo_cal_loft_ladder_40);
4354                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4355                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
4356                 } else {
4357                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4358                                         tbl_tx_iqlo_cal_loft_ladder_20);
4359                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4360                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
4361                 }
4362         }
4363
4364         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4365
4366         if (!dev->phy.is_40mhz)
4367                 freq = 2500;
4368         else
4369                 freq = 5000;
4370
4371         if (nphy->mphase_cal_phase_id > 2)
4372                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4373                                         0xFFFF, 0, true, false);
4374         else
4375                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4376
4377         if (error == 0) {
4378                 if (nphy->mphase_cal_phase_id > 2) {
4379                         table = nphy->mphase_txcal_bestcoeffs;
4380                         length = 11;
4381                         if (dev->phy.rev < 3)
4382                                 length -= 2;
4383                 } else {
4384                         if (!full && nphy->txiqlocal_coeffsvalid) {
4385                                 table = nphy->txiqlocal_bestc;
4386                                 length = 11;
4387                                 if (dev->phy.rev < 3)
4388                                         length -= 2;
4389                         } else {
4390                                 full = true;
4391                                 if (dev->phy.rev >= 3) {
4392                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4393                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4394                                 } else {
4395                                         table = tbl_tx_iqlo_cal_startcoefs;
4396                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4397                                 }
4398                         }
4399                 }
4400
4401                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4402
4403                 if (full) {
4404                         if (dev->phy.rev >= 3)
4405                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4406                         else
4407                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4408                 } else {
4409                         if (dev->phy.rev >= 3)
4410                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4411                         else
4412                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4413                 }
4414
4415                 if (mphase) {
4416                         count = nphy->mphase_txcal_cmdidx;
4417                         numb = min(max,
4418                                 (u16)(count + nphy->mphase_txcal_numcmds));
4419                 } else {
4420                         count = 0;
4421                         numb = max;
4422                 }
4423
4424                 for (; count < numb; count++) {
4425                         if (full) {
4426                                 if (dev->phy.rev >= 3)
4427                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4428                                 else
4429                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4430                         } else {
4431                                 if (dev->phy.rev >= 3)
4432                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4433                                 else
4434                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4435                         }
4436
4437                         core = (cmd & 0x3000) >> 12;
4438                         type = (cmd & 0x0F00) >> 8;
4439
4440                         if (phy6or5x && updated[core] == 0) {
4441                                 b43_nphy_update_tx_cal_ladder(dev, core);
4442                                 updated[core] = true;
4443                         }
4444
4445                         tmp = (params[core].ncorr[type] << 8) | 0x66;
4446                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4447
4448                         if (type == 1 || type == 3 || type == 4) {
4449                                 buffer[0] = b43_ntab_read(dev,
4450                                                 B43_NTAB16(15, 69 + core));
4451                                 diq_start = buffer[0];
4452                                 buffer[0] = 0;
4453                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4454                                                 0);
4455                         }
4456
4457                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4458                         for (i = 0; i < 2000; i++) {
4459                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4460                                 if (tmp & 0xC000)
4461                                         break;
4462                                 udelay(10);
4463                         }
4464
4465                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4466                                                 buffer);
4467                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4468                                                 buffer);
4469
4470                         if (type == 1 || type == 3 || type == 4)
4471                                 buffer[0] = diq_start;
4472                 }
4473
4474                 if (mphase)
4475                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4476
4477                 last = (dev->phy.rev < 3) ? 6 : 7;
4478
4479                 if (!mphase || nphy->mphase_cal_phase_id == last) {
4480                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4481                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4482                         if (dev->phy.rev < 3) {
4483                                 buffer[0] = 0;
4484                                 buffer[1] = 0;
4485                                 buffer[2] = 0;
4486                                 buffer[3] = 0;
4487                         }
4488                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4489                                                 buffer);
4490                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4491                                                 buffer);
4492                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4493                                                 buffer);
4494                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4495                                                 buffer);
4496                         length = 11;
4497                         if (dev->phy.rev < 3)
4498                                 length -= 2;
4499                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4500                                                 nphy->txiqlocal_bestc);
4501                         nphy->txiqlocal_coeffsvalid = true;
4502                         nphy->txiqlocal_chanspec.center_freq =
4503                                                         dev->phy.channel_freq;
4504                         nphy->txiqlocal_chanspec.channel_type =
4505                                                         dev->phy.channel_type;
4506                 } else {
4507                         length = 11;
4508                         if (dev->phy.rev < 3)
4509                                 length -= 2;
4510                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4511                                                 nphy->mphase_txcal_bestcoeffs);
4512                 }
4513
4514                 b43_nphy_stop_playback(dev);
4515                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4516         }
4517
4518         b43_nphy_tx_cal_phy_cleanup(dev);
4519         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4520
4521         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4522                 b43_nphy_tx_iq_workaround(dev);
4523
4524         if (dev->phy.rev >= 4)
4525                 nphy->hang_avoid = avoid;
4526
4527         b43_nphy_stay_in_carrier_search(dev, false);
4528
4529         return error;
4530 }
4531
4532 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4533 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4534 {
4535         struct b43_phy_n *nphy = dev->phy.n;
4536         u8 i;
4537         u16 buffer[7];
4538         bool equal = true;
4539
4540         if (!nphy->txiqlocal_coeffsvalid ||
4541             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4542             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4543                 return;
4544
4545         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4546         for (i = 0; i < 4; i++) {
4547                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4548                         equal = false;
4549                         break;
4550                 }
4551         }
4552
4553         if (!equal) {
4554                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4555                                         nphy->txiqlocal_bestc);
4556                 for (i = 0; i < 4; i++)
4557                         buffer[i] = 0;
4558                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4559                                         buffer);
4560                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4561                                         &nphy->txiqlocal_bestc[5]);
4562                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4563                                         &nphy->txiqlocal_bestc[5]);
4564         }
4565 }
4566
4567 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4568 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4569                         struct nphy_txgains target, u8 type, bool debug)
4570 {
4571         struct b43_phy_n *nphy = dev->phy.n;
4572         int i, j, index;
4573         u8 rfctl[2];
4574         u8 afectl_core;
4575         u16 tmp[6];
4576         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4577         u32 real, imag;
4578         enum ieee80211_band band;
4579
4580         u8 use;
4581         u16 cur_hpf;
4582         u16 lna[3] = { 3, 3, 1 };
4583         u16 hpf1[3] = { 7, 2, 0 };
4584         u16 hpf2[3] = { 2, 0, 0 };
4585         u32 power[3] = { };
4586         u16 gain_save[2];
4587         u16 cal_gain[2];
4588         struct nphy_iqcal_params cal_params[2];
4589         struct nphy_iq_est est;
4590         int ret = 0;
4591         bool playtone = true;
4592         int desired = 13;
4593
4594         b43_nphy_stay_in_carrier_search(dev, 1);
4595
4596         if (dev->phy.rev < 2)
4597                 b43_nphy_reapply_tx_cal_coeffs(dev);
4598         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4599         for (i = 0; i < 2; i++) {
4600                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4601                 cal_gain[i] = cal_params[i].cal_gain;
4602         }
4603         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4604
4605         for (i = 0; i < 2; i++) {
4606                 if (i == 0) {
4607                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
4608                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
4609                         afectl_core = B43_NPHY_AFECTL_C1;
4610                 } else {
4611                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
4612                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
4613                         afectl_core = B43_NPHY_AFECTL_C2;
4614                 }
4615
4616                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4617                 tmp[2] = b43_phy_read(dev, afectl_core);
4618                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4619                 tmp[4] = b43_phy_read(dev, rfctl[0]);
4620                 tmp[5] = b43_phy_read(dev, rfctl[1]);
4621
4622                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4623                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4624                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4625                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4626                                 (1 - i));
4627                 b43_phy_set(dev, afectl_core, 0x0006);
4628                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4629
4630                 band = b43_current_band(dev->wl);
4631
4632                 if (nphy->rxcalparams & 0xFF000000) {
4633                         if (band == IEEE80211_BAND_5GHZ)
4634                                 b43_phy_write(dev, rfctl[0], 0x140);
4635                         else
4636                                 b43_phy_write(dev, rfctl[0], 0x110);
4637                 } else {
4638                         if (band == IEEE80211_BAND_5GHZ)
4639                                 b43_phy_write(dev, rfctl[0], 0x180);
4640                         else
4641                                 b43_phy_write(dev, rfctl[0], 0x120);
4642                 }
4643
4644                 if (band == IEEE80211_BAND_5GHZ)
4645                         b43_phy_write(dev, rfctl[1], 0x148);
4646                 else
4647                         b43_phy_write(dev, rfctl[1], 0x114);
4648
4649                 if (nphy->rxcalparams & 0x10000) {
4650                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4651                                         (i + 1));
4652                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4653                                         (2 - i));
4654                 }
4655
4656                 for (j = 0; j < 4; j++) {
4657                         if (j < 3) {
4658                                 cur_lna = lna[j];
4659                                 cur_hpf1 = hpf1[j];
4660                                 cur_hpf2 = hpf2[j];
4661                         } else {
4662                                 if (power[1] > 10000) {
4663                                         use = 1;
4664                                         cur_hpf = cur_hpf1;
4665                                         index = 2;
4666                                 } else {
4667                                         if (power[0] > 10000) {
4668                                                 use = 1;
4669                                                 cur_hpf = cur_hpf1;
4670                                                 index = 1;
4671                                         } else {
4672                                                 index = 0;
4673                                                 use = 2;
4674                                                 cur_hpf = cur_hpf2;
4675                                         }
4676                                 }
4677                                 cur_lna = lna[index];
4678                                 cur_hpf1 = hpf1[index];
4679                                 cur_hpf2 = hpf2[index];
4680                                 cur_hpf += desired - hweight32(power[index]);
4681                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
4682                                 if (use == 1)
4683                                         cur_hpf1 = cur_hpf;
4684                                 else
4685                                         cur_hpf2 = cur_hpf;
4686                         }
4687
4688                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4689                                         (cur_lna << 2));
4690                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4691                                                                         false);
4692                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4693                         b43_nphy_stop_playback(dev);
4694
4695                         if (playtone) {
4696                                 ret = b43_nphy_tx_tone(dev, 4000,
4697                                                 (nphy->rxcalparams & 0xFFFF),
4698                                                 false, false);
4699                                 playtone = false;
4700                         } else {
4701                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4702                                                         false, false);
4703                         }
4704
4705                         if (ret == 0) {
4706                                 if (j < 3) {
4707                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4708                                                                         false);
4709                                         if (i == 0) {
4710                                                 real = est.i0_pwr;
4711                                                 imag = est.q0_pwr;
4712                                         } else {
4713                                                 real = est.i1_pwr;
4714                                                 imag = est.q1_pwr;
4715                                         }
4716                                         power[i] = ((real + imag) / 1024) + 1;
4717                                 } else {
4718                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4719                                 }
4720                                 b43_nphy_stop_playback(dev);
4721                         }
4722
4723                         if (ret != 0)
4724                                 break;
4725                 }
4726
4727                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4728                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4729                 b43_phy_write(dev, rfctl[1], tmp[5]);
4730                 b43_phy_write(dev, rfctl[0], tmp[4]);
4731                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4732                 b43_phy_write(dev, afectl_core, tmp[2]);
4733                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4734
4735                 if (ret != 0)
4736                         break;
4737         }
4738
4739         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4740         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4741         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4742
4743         b43_nphy_stay_in_carrier_search(dev, 0);
4744
4745         return ret;
4746 }
4747
4748 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4749                         struct nphy_txgains target, u8 type, bool debug)
4750 {
4751         return -1;
4752 }
4753
4754 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4755 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4756                         struct nphy_txgains target, u8 type, bool debug)
4757 {
4758         if (dev->phy.rev >= 3)
4759                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4760         else
4761                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4762 }
4763
4764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4765 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4766 {
4767         struct b43_phy *phy = &dev->phy;
4768         struct b43_phy_n *nphy = phy->n;
4769         /* u16 buf[16]; it's rev3+ */
4770
4771         nphy->phyrxchain = mask;
4772
4773         if (0 /* FIXME clk */)
4774                 return;
4775
4776         b43_mac_suspend(dev);
4777
4778         if (nphy->hang_avoid)
4779                 b43_nphy_stay_in_carrier_search(dev, true);
4780
4781         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4782                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4783
4784         if ((mask & 0x3) != 0x3) {
4785                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4786                 if (dev->phy.rev >= 3) {
4787                         /* TODO */
4788                 }
4789         } else {
4790                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4791                 if (dev->phy.rev >= 3) {
4792                         /* TODO */
4793                 }
4794         }
4795
4796         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4797
4798         if (nphy->hang_avoid)
4799                 b43_nphy_stay_in_carrier_search(dev, false);
4800
4801         b43_mac_enable(dev);
4802 }
4803
4804 /**************************************************
4805  * N-PHY init
4806  **************************************************/
4807
4808 /*
4809  * Upload the N-PHY tables.
4810  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4811  */
4812 static void b43_nphy_tables_init(struct b43_wldev *dev)
4813 {
4814         if (dev->phy.rev < 3)
4815                 b43_nphy_rev0_1_2_tables_init(dev);
4816         else
4817                 b43_nphy_rev3plus_tables_init(dev);
4818 }
4819
4820 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4821 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4822 {
4823         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4824
4825         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4826         if (preamble == 1)
4827                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4828         else
4829                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4830
4831         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4832 }
4833
4834 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4835 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4836 {
4837         unsigned int i;
4838         u16 val;
4839
4840         val = 0x1E1F;
4841         for (i = 0; i < 16; i++) {
4842                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4843                 val -= 0x202;
4844         }
4845         val = 0x3E3F;
4846         for (i = 0; i < 16; i++) {
4847                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4848                 val -= 0x202;
4849         }
4850         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4851 }
4852
4853 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4854 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4855 {
4856         if (dev->phy.rev >= 3) {
4857                 if (!init)
4858                         return;
4859                 if (0 /* FIXME */) {
4860                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4861                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4862                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4863                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4864                 }
4865         } else {
4866                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4867                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4868
4869                 switch (dev->dev->bus_type) {
4870 #ifdef CONFIG_B43_BCMA
4871                 case B43_BUS_BCMA:
4872                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4873                                                  0xFC00, 0xFC00);
4874                         break;
4875 #endif
4876 #ifdef CONFIG_B43_SSB
4877                 case B43_BUS_SSB:
4878                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4879                                                 0xFC00, 0xFC00);
4880                         break;
4881 #endif
4882                 }
4883
4884                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4885                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4886                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4887                               0);
4888
4889                 if (init) {
4890                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4891                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4892                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4893                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4894                 }
4895         }
4896 }
4897
4898 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4899 static int b43_phy_initn(struct b43_wldev *dev)
4900 {
4901         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4902         struct b43_phy *phy = &dev->phy;
4903         struct b43_phy_n *nphy = phy->n;
4904         u8 tx_pwr_state;
4905         struct nphy_txgains target;
4906         u16 tmp;
4907         enum ieee80211_band tmp2;
4908         bool do_rssi_cal;
4909
4910         u16 clip[2];
4911         bool do_cal = false;
4912
4913         if ((dev->phy.rev >= 3) &&
4914            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4915            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4916                 switch (dev->dev->bus_type) {
4917 #ifdef CONFIG_B43_BCMA
4918                 case B43_BUS_BCMA:
4919                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4920                                       BCMA_CC_CHIPCTL, 0x40);
4921                         break;
4922 #endif
4923 #ifdef CONFIG_B43_SSB
4924                 case B43_BUS_SSB:
4925                         chipco_set32(&dev->dev->sdev->bus->chipco,
4926                                      SSB_CHIPCO_CHIPCTL, 0x40);
4927                         break;
4928 #endif
4929                 }
4930         }
4931         nphy->deaf_count = 0;
4932         b43_nphy_tables_init(dev);
4933         nphy->crsminpwr_adjusted = false;
4934         nphy->noisevars_adjusted = false;
4935
4936         /* Clear all overrides */
4937         if (dev->phy.rev >= 3) {
4938                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4939                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4940                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4941                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4942         } else {
4943                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4944         }
4945         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4946         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4947         if (dev->phy.rev < 6) {
4948                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4949                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4950         }
4951         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4952                      ~(B43_NPHY_RFSEQMODE_CAOVER |
4953                        B43_NPHY_RFSEQMODE_TROVER));
4954         if (dev->phy.rev >= 3)
4955                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4956         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4957
4958         if (dev->phy.rev <= 2) {
4959                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4960                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4961                                 ~B43_NPHY_BPHY_CTL3_SCALE,
4962                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4963         }
4964         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4965         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4966
4967         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4968             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4969              dev->dev->board_type == 0x8B))
4970                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4971         else
4972                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4973         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4974         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4975         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
4976
4977         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4978         b43_nphy_update_txrx_chain(dev);
4979
4980         if (phy->rev < 2) {
4981                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4982                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4983         }
4984
4985         tmp2 = b43_current_band(dev->wl);
4986         if (b43_nphy_ipa(dev)) {
4987                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4988                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4989                                 nphy->papd_epsilon_offset[0] << 7);
4990                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
4991                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
4992                                 nphy->papd_epsilon_offset[1] << 7);
4993                 b43_nphy_int_pa_set_tx_dig_filters(dev);
4994         } else if (phy->rev >= 5) {
4995                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
4996         }
4997
4998         b43_nphy_workarounds(dev);
4999
5000         /* Reset CCA, in init code it differs a little from standard way */
5001         b43_phy_force_clock(dev, 1);
5002         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5003         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5004         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5005         b43_phy_force_clock(dev, 0);
5006
5007         b43_mac_phy_clock_set(dev, true);
5008
5009         b43_nphy_pa_override(dev, false);
5010         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5011         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5012         b43_nphy_pa_override(dev, true);
5013
5014         b43_nphy_classifier(dev, 0, 0);
5015         b43_nphy_read_clip_detection(dev, clip);
5016         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5017                 b43_nphy_bphy_init(dev);
5018
5019         tx_pwr_state = nphy->txpwrctrl;
5020         b43_nphy_tx_power_ctrl(dev, false);
5021         b43_nphy_tx_power_fix(dev);
5022         b43_nphy_tx_power_ctl_idle_tssi(dev);
5023         b43_nphy_tx_power_ctl_setup(dev);
5024         b43_nphy_tx_gain_table_upload(dev);
5025
5026         if (nphy->phyrxchain != 3)
5027                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5028         if (nphy->mphase_cal_phase_id > 0)
5029                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5030
5031         do_rssi_cal = false;
5032         if (phy->rev >= 3) {
5033                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5034                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5035                 else
5036                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5037
5038                 if (do_rssi_cal)
5039                         b43_nphy_rssi_cal(dev);
5040                 else
5041                         b43_nphy_restore_rssi_cal(dev);
5042         } else {
5043                 b43_nphy_rssi_cal(dev);
5044         }
5045
5046         if (!((nphy->measure_hold & 0x6) != 0)) {
5047                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5048                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5049                 else
5050                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5051
5052                 if (nphy->mute)
5053                         do_cal = false;
5054
5055                 if (do_cal) {
5056                         target = b43_nphy_get_tx_gains(dev);
5057
5058                         if (nphy->antsel_type == 2)
5059                                 b43_nphy_superswitch_init(dev, true);
5060                         if (nphy->perical != 2) {
5061                                 b43_nphy_rssi_cal(dev);
5062                                 if (phy->rev >= 3) {
5063                                         nphy->cal_orig_pwr_idx[0] =
5064                                             nphy->txpwrindex[0].index_internal;
5065                                         nphy->cal_orig_pwr_idx[1] =
5066                                             nphy->txpwrindex[1].index_internal;
5067                                         /* TODO N PHY Pre Calibrate TX Gain */
5068                                         target = b43_nphy_get_tx_gains(dev);
5069                                 }
5070                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5071                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5072                                                 b43_nphy_save_cal(dev);
5073                         } else if (nphy->mphase_cal_phase_id == 0)
5074                                 ;/* N PHY Periodic Calibration with arg 3 */
5075                 } else {
5076                         b43_nphy_restore_cal(dev);
5077                 }
5078         }
5079
5080         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5081         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5082         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5083         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5084         if (phy->rev >= 3 && phy->rev <= 6)
5085                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
5086         b43_nphy_tx_lp_fbw(dev);
5087         if (phy->rev >= 3)
5088                 b43_nphy_spur_workaround(dev);
5089
5090         return 0;
5091 }
5092
5093 /**************************************************
5094  * Channel switching ops.
5095  **************************************************/
5096
5097 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5098                                    const struct b43_phy_n_sfo_cfg *e)
5099 {
5100         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5101         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5102         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5103         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5104         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5105         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5106 }
5107
5108 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5109 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5110 {
5111         switch (dev->dev->bus_type) {
5112 #ifdef CONFIG_B43_BCMA
5113         case B43_BUS_BCMA:
5114                 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5115                                              avoid);
5116                 break;
5117 #endif
5118 #ifdef CONFIG_B43_SSB
5119         case B43_BUS_SSB:
5120                 /* FIXME */
5121                 break;
5122 #endif
5123         }
5124 }
5125
5126 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5127 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5128                                 const struct b43_phy_n_sfo_cfg *e,
5129                                 struct ieee80211_channel *new_channel)
5130 {
5131         struct b43_phy *phy = &dev->phy;
5132         struct b43_phy_n *nphy = dev->phy.n;
5133         int ch = new_channel->hw_value;
5134
5135         u16 old_band_5ghz;
5136         u32 tmp32;
5137
5138         old_band_5ghz =
5139                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5140         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5141                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5142                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5143                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5144                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5145                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5146         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5147                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5148                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5149                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5150                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5151                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5152         }
5153
5154         b43_chantab_phy_upload(dev, e);
5155
5156         if (new_channel->hw_value == 14) {
5157                 b43_nphy_classifier(dev, 2, 0);
5158                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5159         } else {
5160                 b43_nphy_classifier(dev, 2, 2);
5161                 if (new_channel->band == IEEE80211_BAND_2GHZ)
5162                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5163         }
5164
5165         if (!nphy->txpwrctrl)
5166                 b43_nphy_tx_power_fix(dev);
5167
5168         if (dev->phy.rev < 3)
5169                 b43_nphy_adjust_lna_gain_table(dev);
5170
5171         b43_nphy_tx_lp_fbw(dev);
5172
5173         if (dev->phy.rev >= 3 &&
5174             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5175                 bool avoid = false;
5176                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5177                         avoid = true;
5178                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5179                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5180                                 avoid = true;
5181                 } else { /* 40MHz */
5182                         if (nphy->aband_spurwar_en &&
5183                             (ch == 38 || ch == 102 || ch == 118))
5184                                 avoid = dev->dev->chip_id == 0x4716;
5185                 }
5186
5187                 b43_nphy_pmu_spur_avoid(dev, avoid);
5188
5189                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5190                     dev->dev->chip_id == 43225) {
5191                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5192                                     avoid ? 0x5341 : 0x8889);
5193                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5194                 }
5195
5196                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5197                         ; /* TODO: reset PLL */
5198
5199                 if (avoid)
5200                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5201                 else
5202                         b43_phy_mask(dev, B43_NPHY_BBCFG,
5203                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5204
5205                 b43_nphy_reset_cca(dev);
5206
5207                 /* wl sets useless phy_isspuravoid here */
5208         }
5209
5210         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5211
5212         if (phy->rev >= 3)
5213                 b43_nphy_spur_workaround(dev);
5214 }
5215
5216 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5217 static int b43_nphy_set_channel(struct b43_wldev *dev,
5218                                 struct ieee80211_channel *channel,
5219                                 enum nl80211_channel_type channel_type)
5220 {
5221         struct b43_phy *phy = &dev->phy;
5222
5223         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5224         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5225
5226         u8 tmp;
5227
5228         if (dev->phy.rev >= 3) {
5229                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5230                                                         channel->center_freq);
5231                 if (!tabent_r3)
5232                         return -ESRCH;
5233         } else {
5234                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5235                                                         channel->hw_value);
5236                 if (!tabent_r2)
5237                         return -ESRCH;
5238         }
5239
5240         /* Channel is set later in common code, but we need to set it on our
5241            own to let this function's subcalls work properly. */
5242         phy->channel = channel->hw_value;
5243         phy->channel_freq = channel->center_freq;
5244
5245         if (b43_channel_type_is_40mhz(phy->channel_type) !=
5246                 b43_channel_type_is_40mhz(channel_type))
5247                 ; /* TODO: BMAC BW Set (channel_type) */
5248
5249         if (channel_type == NL80211_CHAN_HT40PLUS)
5250                 b43_phy_set(dev, B43_NPHY_RXCTL,
5251                                 B43_NPHY_RXCTL_BSELU20);
5252         else if (channel_type == NL80211_CHAN_HT40MINUS)
5253                 b43_phy_mask(dev, B43_NPHY_RXCTL,
5254                                 ~B43_NPHY_RXCTL_BSELU20);
5255
5256         if (dev->phy.rev >= 3) {
5257                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5258                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5259                 b43_radio_2056_setup(dev, tabent_r3);
5260                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5261         } else {
5262                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5263                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5264                 b43_radio_2055_setup(dev, tabent_r2);
5265                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5266         }
5267
5268         return 0;
5269 }
5270
5271 /**************************************************
5272  * Basic PHY ops.
5273  **************************************************/
5274
5275 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5276 {
5277         struct b43_phy_n *nphy;
5278
5279         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5280         if (!nphy)
5281                 return -ENOMEM;
5282         dev->phy.n = nphy;
5283
5284         return 0;
5285 }
5286
5287 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5288 {
5289         struct b43_phy *phy = &dev->phy;
5290         struct b43_phy_n *nphy = phy->n;
5291         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5292
5293         memset(nphy, 0, sizeof(*nphy));
5294
5295         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5296         nphy->spur_avoid = (phy->rev >= 3) ?
5297                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5298         nphy->init_por = true;
5299         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5300         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5301         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5302         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5303         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5304          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5305         nphy->tx_pwr_idx[0] = 128;
5306         nphy->tx_pwr_idx[1] = 128;
5307
5308         /* Hardware TX power control and 5GHz power gain */
5309         nphy->txpwrctrl = false;
5310         nphy->pwg_gain_5ghz = false;
5311         if (dev->phy.rev >= 3 ||
5312             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5313              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5314                 nphy->txpwrctrl = true;
5315                 nphy->pwg_gain_5ghz = true;
5316         } else if (sprom->revision >= 4) {
5317                 if (dev->phy.rev >= 2 &&
5318                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5319                         nphy->txpwrctrl = true;
5320 #ifdef CONFIG_B43_SSB
5321                         if (dev->dev->bus_type == B43_BUS_SSB &&
5322                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5323                                 struct pci_dev *pdev =
5324                                         dev->dev->sdev->bus->host_pci;
5325                                 if (pdev->device == 0x4328 ||
5326                                     pdev->device == 0x432a)
5327                                         nphy->pwg_gain_5ghz = true;
5328                         }
5329 #endif
5330                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5331                         nphy->pwg_gain_5ghz = true;
5332                 }
5333         }
5334
5335         if (dev->phy.rev >= 3) {
5336                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5337                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5338         }
5339
5340         nphy->init_por = true;
5341 }
5342
5343 static void b43_nphy_op_free(struct b43_wldev *dev)
5344 {
5345         struct b43_phy *phy = &dev->phy;
5346         struct b43_phy_n *nphy = phy->n;
5347
5348         kfree(nphy);
5349         phy->n = NULL;
5350 }
5351
5352 static int b43_nphy_op_init(struct b43_wldev *dev)
5353 {
5354         return b43_phy_initn(dev);
5355 }
5356
5357 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5358 {
5359 #if B43_DEBUG
5360         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5361                 /* OFDM registers are onnly available on A/G-PHYs */
5362                 b43err(dev->wl, "Invalid OFDM PHY access at "
5363                        "0x%04X on N-PHY\n", offset);
5364                 dump_stack();
5365         }
5366         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5367                 /* Ext-G registers are only available on G-PHYs */
5368                 b43err(dev->wl, "Invalid EXT-G PHY access at "
5369                        "0x%04X on N-PHY\n", offset);
5370                 dump_stack();
5371         }
5372 #endif /* B43_DEBUG */
5373 }
5374
5375 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5376 {
5377         check_phyreg(dev, reg);
5378         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5379         return b43_read16(dev, B43_MMIO_PHY_DATA);
5380 }
5381
5382 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5383 {
5384         check_phyreg(dev, reg);
5385         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5386         b43_write16(dev, B43_MMIO_PHY_DATA, value);
5387 }
5388
5389 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5390                                  u16 set)
5391 {
5392         check_phyreg(dev, reg);
5393         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5394         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5395 }
5396
5397 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5398 {
5399         /* Register 1 is a 32-bit register. */
5400         B43_WARN_ON(reg == 1);
5401         /* N-PHY needs 0x100 for read access */
5402         reg |= 0x100;
5403
5404         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5405         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5406 }
5407
5408 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5409 {
5410         /* Register 1 is a 32-bit register. */
5411         B43_WARN_ON(reg == 1);
5412
5413         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5414         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5415 }
5416
5417 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5418 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5419                                         bool blocked)
5420 {
5421         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5422                 b43err(dev->wl, "MAC not suspended\n");
5423
5424         if (blocked) {
5425                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5426                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5427                 if (dev->phy.rev >= 7) {
5428                         /* TODO */
5429                 } else if (dev->phy.rev >= 3) {
5430                         b43_radio_mask(dev, 0x09, ~0x2);
5431
5432                         b43_radio_write(dev, 0x204D, 0);
5433                         b43_radio_write(dev, 0x2053, 0);
5434                         b43_radio_write(dev, 0x2058, 0);
5435                         b43_radio_write(dev, 0x205E, 0);
5436                         b43_radio_mask(dev, 0x2062, ~0xF0);
5437                         b43_radio_write(dev, 0x2064, 0);
5438
5439                         b43_radio_write(dev, 0x304D, 0);
5440                         b43_radio_write(dev, 0x3053, 0);
5441                         b43_radio_write(dev, 0x3058, 0);
5442                         b43_radio_write(dev, 0x305E, 0);
5443                         b43_radio_mask(dev, 0x3062, ~0xF0);
5444                         b43_radio_write(dev, 0x3064, 0);
5445                 }
5446         } else {
5447                 if (dev->phy.rev >= 7) {
5448                         b43_radio_2057_init(dev);
5449                         b43_switch_channel(dev, dev->phy.channel);
5450                 } else if (dev->phy.rev >= 3) {
5451                         b43_radio_init2056(dev);
5452                         b43_switch_channel(dev, dev->phy.channel);
5453                 } else {
5454                         b43_radio_init2055(dev);
5455                 }
5456         }
5457 }
5458
5459 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5460 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5461 {
5462         u16 override = on ? 0x0 : 0x7FFF;
5463         u16 core = on ? 0xD : 0x00FD;
5464
5465         if (dev->phy.rev >= 3) {
5466                 if (on) {
5467                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5468                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5469                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5470                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5471                 } else {
5472                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5473                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5474                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5475                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5476                 }
5477         } else {
5478                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5479         }
5480 }
5481
5482 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5483                                       unsigned int new_channel)
5484 {
5485         struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5486         enum nl80211_channel_type channel_type =
5487                 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5488
5489         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5490                 if ((new_channel < 1) || (new_channel > 14))
5491                         return -EINVAL;
5492         } else {
5493                 if (new_channel > 200)
5494                         return -EINVAL;
5495         }
5496
5497         return b43_nphy_set_channel(dev, channel, channel_type);
5498 }
5499
5500 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5501 {
5502         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5503                 return 1;
5504         return 36;
5505 }
5506
5507 const struct b43_phy_operations b43_phyops_n = {
5508         .allocate               = b43_nphy_op_allocate,
5509         .free                   = b43_nphy_op_free,
5510         .prepare_structs        = b43_nphy_op_prepare_structs,
5511         .init                   = b43_nphy_op_init,
5512         .phy_read               = b43_nphy_op_read,
5513         .phy_write              = b43_nphy_op_write,
5514         .phy_maskset            = b43_nphy_op_maskset,
5515         .radio_read             = b43_nphy_op_radio_read,
5516         .radio_write            = b43_nphy_op_radio_write,
5517         .software_rfkill        = b43_nphy_op_software_rfkill,
5518         .switch_analog          = b43_nphy_op_switch_analog,
5519         .switch_channel         = b43_nphy_op_switch_channel,
5520         .get_default_chan       = b43_nphy_op_get_default_chan,
5521         .recalc_txpower         = b43_nphy_op_recalc_txpower,
5522         .adjust_txpower         = b43_nphy_op_adjust_txpower,
5523 };