2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef BRCMFMAC_SDIO_H
18 #define BRCMFMAC_SDIO_H
20 #include <linux/skbuff.h>
21 #include <linux/firmware.h>
28 #define SDIOD_FBR_SIZE 0x100
31 #define SDIO_FUNC_ENABLE_1 0x02
32 #define SDIO_FUNC_ENABLE_2 0x04
35 #define SDIO_FUNC_READY_1 0x02
36 #define SDIO_FUNC_READY_2 0x04
39 #define INTR_STATUS_FUNC1 0x2
40 #define INTR_STATUS_FUNC2 0x4
42 /* Maximum number of I/O funcs */
43 #define SDIOD_MAX_IOFUNCS 7
45 /* mask of register map */
46 #define REG_F0_REG_MASK 0x7FF
47 #define REG_F1_MISC_MASK 0x1FFFF
49 /* as of sdiod rev 0, supports 3 functions */
50 #define SBSDIO_NUM_FUNCTION 3
52 /* function 0 vendor specific CCCR registers */
53 #define SDIO_CCCR_BRCM_CARDCAP 0xf0
54 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
55 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
56 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
57 #define SDIO_CCCR_BRCM_CARDCTRL 0xf1
58 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
59 #define SDIO_CCCR_BRCM_SEPINT 0xf2
61 #define SDIO_SEPINT_MASK 0x01
62 #define SDIO_SEPINT_OE 0x02
63 #define SDIO_SEPINT_ACT_HI 0x04
65 /* function 1 miscellaneous registers */
67 /* sprom command and status */
68 #define SBSDIO_SPROM_CS 0x10000
69 /* sprom info register */
70 #define SBSDIO_SPROM_INFO 0x10001
71 /* sprom indirect access data byte 0 */
72 #define SBSDIO_SPROM_DATA_LOW 0x10002
73 /* sprom indirect access data byte 1 */
74 #define SBSDIO_SPROM_DATA_HIGH 0x10003
75 /* sprom indirect access addr byte 0 */
76 #define SBSDIO_SPROM_ADDR_LOW 0x10004
78 #define SBSDIO_GPIO_SELECT 0x10005
80 #define SBSDIO_GPIO_OUT 0x10006
82 #define SBSDIO_GPIO_EN 0x10007
83 /* rev < 7, watermark for sdio device */
84 #define SBSDIO_WATERMARK 0x10008
85 /* control busy signal generation */
86 #define SBSDIO_DEVICE_CTL 0x10009
88 /* SB Address Window Low (b15) */
89 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A
90 /* SB Address Window Mid (b23:b16) */
91 #define SBSDIO_FUNC1_SBADDRMID 0x1000B
92 /* SB Address Window High (b31:b24) */
93 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
94 /* Frame Control (frame term/abort) */
95 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D
96 /* ChipClockCSR (ALP/HT ctl/status) */
97 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
98 /* SdioPullUp (on cmd, d0-d2) */
99 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
100 /* Write Frame Byte Count Low */
101 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
102 /* Write Frame Byte Count High */
103 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
104 /* Read Frame Byte Count Low */
105 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
106 /* Read Frame Byte Count High */
107 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
108 /* MesBusyCtl (rev 11) */
109 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
110 /* Sdio Core Rev 12 */
111 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
112 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
113 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
114 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
115 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
116 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F
117 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
118 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
119 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
120 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
121 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
123 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
124 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
126 /* function 1 OCP space */
128 /* sb offset addr is <= 15 bits, 32k */
129 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
130 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
131 /* with b15, maps to 32-bit SB access */
132 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
134 /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
136 #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
137 #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
138 #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
139 /* Address bits from SBADDR regs */
140 #define SBSDIO_SBWINDOW_MASK 0xffff8000
142 #define SDIOH_READ 0 /* Read request */
143 #define SDIOH_WRITE 1 /* Write request */
145 #define SDIOH_DATA_FIX 0 /* Fixed addressing */
146 #define SDIOH_DATA_INC 1 /* Incremental addressing */
148 /* internal return code */
152 /* Packet alignment for most efficient SDIO (can change based on platform) */
153 #define BRCMF_SDALIGN (1 << 6)
155 /* watchdog polling interval in ms */
156 #define BRCMF_WD_POLL_MS 10
158 /* The state of the bus */
159 enum brcmf_sdio_state {
160 BRCMF_STATE_DOWN, /* Device available, still initialising */
161 BRCMF_STATE_DATA, /* Ready for data transfers, DPC enabled */
162 BRCMF_STATE_NOMEDIUM /* No medium access to dongle possible */
173 struct brcmf_sdio_dev {
174 struct sdio_func *func[SDIO_MAX_FUNCS];
175 u8 num_funcs; /* Supported funcs on client */
176 u32 sbwad; /* Save backplane window address */
177 struct brcmf_sdio *bus;
178 atomic_t suspend; /* suspend flag */
180 wait_queue_head_t idle_wait;
182 struct brcmf_bus *bus_if;
183 struct brcmfmac_sdio_platform_data *pdata;
184 bool oob_irq_requested;
185 bool irq_en; /* irq enable flags */
186 spinlock_t irq_en_lock;
187 bool irq_wake; /* irq wake enable flags */
189 uint max_request_size;
190 ushort max_segment_count;
191 uint max_segment_size;
193 struct sg_table sgtable;
194 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
195 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
197 enum brcmf_sdio_state state;
200 /* sdio core registers */
202 u32 corecontrol; /* 0x00, rev8 */
203 u32 corestatus; /* rev8 */
205 u32 biststatus; /* rev8 */
208 u16 pcmciamesportaladdr; /* 0x010, rev8 */
210 u16 pcmciamesportalmask; /* rev8 */
212 u16 pcmciawrframebc; /* rev8 */
214 u16 pcmciaunderflowtimer; /* rev8 */
218 u32 intstatus; /* 0x020, rev8 */
219 u32 hostintmask; /* rev8 */
220 u32 intmask; /* rev8 */
221 u32 sbintstatus; /* rev8 */
222 u32 sbintmask; /* rev8 */
223 u32 funcintmask; /* rev4 */
225 u32 tosbmailbox; /* 0x040, rev8 */
226 u32 tohostmailbox; /* rev8 */
227 u32 tosbmailboxdata; /* rev8 */
228 u32 tohostmailboxdata; /* rev8 */
230 /* synchronized access to registers in SDIO clock domain */
231 u32 sdioaccess; /* 0x050, rev8 */
234 /* PCMCIA frame control */
235 u8 pcmciaframectrl; /* 0x060, rev8 */
237 u8 pcmciawatermark; /* rev8 */
240 /* interrupt batching control */
241 u32 intrcvlazy; /* 0x100, rev8 */
245 u32 cmd52rd; /* 0x110, rev8 */
246 u32 cmd52wr; /* rev8 */
247 u32 cmd53rd; /* rev8 */
248 u32 cmd53wr; /* rev8 */
249 u32 abort; /* rev8 */
250 u32 datacrcerror; /* rev8 */
251 u32 rdoutofsync; /* rev8 */
252 u32 wroutofsync; /* rev8 */
253 u32 writebusy; /* rev8 */
254 u32 readwait; /* rev8 */
255 u32 readterm; /* rev8 */
256 u32 writeterm; /* rev8 */
258 u32 clockctlstatus; /* rev8 */
261 u32 PAD[128]; /* DMA engines */
263 /* SDIO/PCMCIA CIS region */
264 char cis[512]; /* 0x400-0x5ff, rev6 */
266 /* PCMCIA function control registers */
267 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
270 /* PCMCIA backplane access */
271 u16 backplanecsr; /* 0x76E, rev6 */
272 u16 backplaneaddr0; /* rev6 */
273 u16 backplaneaddr1; /* rev6 */
274 u16 backplaneaddr2; /* rev6 */
275 u16 backplaneaddr3; /* rev6 */
276 u16 backplanedata0; /* rev6 */
277 u16 backplanedata1; /* rev6 */
278 u16 backplanedata2; /* rev6 */
279 u16 backplanedata3; /* rev6 */
282 /* sprom "size" & "blank" info */
283 u16 spromstatus; /* 0x7BE, rev2 */
289 /* Register/deregister interrupt handler. */
290 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
291 int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
293 /* sdio device register access interface */
294 u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
295 u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
296 void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
298 void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
301 /* Buffer transfer to/from device (client) core via cmd53.
302 * fn: function number
303 * flags: backplane width, address increment, sync/async
304 * buf: pointer to memory data buffer
305 * nbytes: number of bytes to transfer to/from buf
306 * pkt: pointer to packet associated with buf (if any)
307 * complete: callback function for command completion (async only)
308 * handle: handle for completion callback (first arg in callback)
309 * Returns 0 or error code.
310 * NOTE: Async operation is not currently supported.
312 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
313 struct sk_buff_head *pktq);
314 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
316 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
317 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
318 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
319 struct sk_buff_head *pktq, uint totlen);
323 /* Four-byte target (backplane) width (vs. two-byte) */
324 #define SDIO_REQ_4BYTE 0x1
325 /* Fixed address (FIFO) (vs. incrementing address) */
326 #define SDIO_REQ_FIXED 0x2
328 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
329 * rw: read or write (0/1)
330 * addr: direct SDIO address
331 * buf: pointer to memory data buffer
332 * nbytes: number of bytes to transfer to/from buf
333 * Returns 0 or error code.
335 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
336 u8 *data, uint size);
338 /* Issue an abort to the specified function */
339 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
341 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
342 void brcmf_sdio_remove(struct brcmf_sdio *bus);
343 void brcmf_sdio_isr(struct brcmf_sdio *bus);
345 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
346 void brcmf_sdio_wowl_config(struct device *dev, bool enabled);
348 #endif /* BRCMFMAC_SDIO_H */