2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
39 #include "brcms_trace_events.h"
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG 1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK 800
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT 100
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52 * control it independently
58 #define EDCF_ACI_MASK 0x60
59 #define EDCF_ACI_SHIFT 5
60 #define EDCF_ECWMIN_MASK 0x0f
61 #define EDCF_ECWMAX_SHIFT 4
62 #define EDCF_AIFSN_MASK 0x0f
63 #define EDCF_AIFSN_MAX 15
64 #define EDCF_ECWMAX_MASK 0xf0
66 #define EDCF_AC_BE_TXOP_STA 0x0000
67 #define EDCF_AC_BK_TXOP_STA 0x0000
68 #define EDCF_AC_VO_ACI_STA 0x62
69 #define EDCF_AC_VO_ECW_STA 0x32
70 #define EDCF_AC_VI_ACI_STA 0x42
71 #define EDCF_AC_VI_ECW_STA 0x43
72 #define EDCF_AC_BK_ECW_STA 0xA4
73 #define EDCF_AC_VI_TXOP_STA 0x005e
74 #define EDCF_AC_VO_TXOP_STA 0x002f
75 #define EDCF_AC_BE_ACI_STA 0x03
76 #define EDCF_AC_BE_ECW_STA 0xA4
77 #define EDCF_AC_BK_ACI_STA 0x27
78 #define EDCF_AC_VO_TXOP_AP 0x002f
80 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
81 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83 #define APHY_SYMBOL_TIME 4
84 #define APHY_PREAMBLE_TIME 16
85 #define APHY_SIGNAL_TIME 4
86 #define APHY_SIFS_TIME 16
87 #define APHY_SERVICE_NBITS 16
88 #define APHY_TAIL_NBITS 6
89 #define BPHY_SIFS_TIME 10
90 #define BPHY_PLCP_SHORT_TIME 96
92 #define PREN_PREAMBLE 24
93 #define PREN_MM_EXT 12
94 #define PREN_PREAMBLE_EXT 4
96 #define DOT11_MAC_HDR_LEN 24
97 #define DOT11_ACK_LEN 10
98 #define DOT11_BA_LEN 4
99 #define DOT11_OFDM_SIGNAL_EXTENSION 6
100 #define DOT11_MIN_FRAG_LEN 256
101 #define DOT11_RTS_LEN 16
102 #define DOT11_CTS_LEN 10
103 #define DOT11_BA_BITMAP_LEN 128
104 #define DOT11_MIN_BEACON_PERIOD 1
105 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
106 #define DOT11_MAXNUMFRAGS 16
107 #define DOT11_MAX_FRAG_LEN 2346
109 #define BPHY_PLCP_TIME 192
110 #define RIFS_11N_TIME 2
112 /* length of the BCN template area */
113 #define BCN_TMPL_LEN 512
115 /* brcms_bss_info flag bit values */
116 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
118 /* chip rx buffer offset */
119 #define BRCMS_HWRXOFF 38
121 /* rfdisable delay timer 500 ms, runs of ALP clock */
122 #define RFDISABLE_DEFAULT 10000000
124 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
126 /* synthpu_dly times in us */
127 #define SYNTHPU_DLY_APHY_US 3700
128 #define SYNTHPU_DLY_BPHY_US 1050
129 #define SYNTHPU_DLY_NPHY_US 2048
130 #define SYNTHPU_DLY_LPPHY_US 300
132 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
134 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
135 #define EDCF_SHORT_S 0
137 #define EDCF_LONG_S 8
138 #define EDCF_LFB_S 12
139 #define EDCF_SHORT_M BITFIELD_MASK(4)
140 #define EDCF_SFB_M BITFIELD_MASK(4)
141 #define EDCF_LONG_M BITFIELD_MASK(4)
142 #define EDCF_LFB_M BITFIELD_MASK(4)
144 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
145 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
146 #define RETRY_LONG_DEF 4 /* Default Long retry count */
147 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
148 #define RETRY_LONG_FB 2 /* Long count for fb rate */
150 #define APHY_CWMIN 15
151 #define PHY_CWMAX 1023
153 #define EDCF_AIFSN_MIN 1
155 #define FRAGNUM_MASK 0xF
157 #define APHY_SLOT_TIME 9
158 #define BPHY_SLOT_TIME 20
160 #define WL_SPURAVOID_OFF 0
161 #define WL_SPURAVOID_ON1 1
162 #define WL_SPURAVOID_ON2 2
164 /* invalid core flags, use the saved coreflags */
165 #define BRCMS_USE_COREFLAGS 0xffffffff
167 /* values for PLCPHdr_override */
168 #define BRCMS_PLCP_AUTO -1
169 #define BRCMS_PLCP_SHORT 0
170 #define BRCMS_PLCP_LONG 1
172 /* values for g_protection_override and n_protection_override */
173 #define BRCMS_PROTECTION_AUTO -1
174 #define BRCMS_PROTECTION_OFF 0
175 #define BRCMS_PROTECTION_ON 1
176 #define BRCMS_PROTECTION_MMHDR_ONLY 2
177 #define BRCMS_PROTECTION_CTS_ONLY 3
179 /* values for g_protection_control and n_protection_control */
180 #define BRCMS_PROTECTION_CTL_OFF 0
181 #define BRCMS_PROTECTION_CTL_LOCAL 1
182 #define BRCMS_PROTECTION_CTL_OVERLAP 2
184 /* values for n_protection */
185 #define BRCMS_N_PROTECTION_OFF 0
186 #define BRCMS_N_PROTECTION_OPTIONAL 1
187 #define BRCMS_N_PROTECTION_20IN40 2
188 #define BRCMS_N_PROTECTION_MIXEDMODE 3
190 /* values for band specific 40MHz capabilities */
191 #define BRCMS_N_BW_20ALL 0
192 #define BRCMS_N_BW_40ALL 1
193 #define BRCMS_N_BW_20IN2G_40IN5G 2
195 /* bitflags for SGI support (sgi_rx iovar) */
196 #define BRCMS_N_SGI_20 0x01
197 #define BRCMS_N_SGI_40 0x02
199 /* defines used by the nrate iovar */
200 /* MSC in use,indicates b0-6 holds an mcs */
201 #define NRATE_MCS_INUSE 0x00000080
203 #define NRATE_RATE_MASK 0x0000007f
204 /* stf mode mask: siso, cdd, stbc, sdm */
205 #define NRATE_STF_MASK 0x0000ff00
207 #define NRATE_STF_SHIFT 8
208 /* bit indicate to override mcs only */
209 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
210 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
211 #define NRATE_SGI_SHIFT 23 /* sgi mode */
212 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
213 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
215 #define NRATE_STF_SISO 0 /* stf mode SISO */
216 #define NRATE_STF_CDD 1 /* stf mode CDD */
217 #define NRATE_STF_STBC 2 /* stf mode STBC */
218 #define NRATE_STF_SDM 3 /* stf mode SDM */
220 #define MAX_DMA_SEGS 4
222 /* # of entries in Tx FIFO */
224 /* Max # of entries in Rx FIFO based on 4kb page size */
227 /* Amount of headroom to leave in Tx FIFO */
228 #define TX_HEADROOM 4
230 /* try to keep this # rbufs posted to the chip */
231 #define NRXBUFPOST 32
233 /* max # frames to process in brcms_c_recv() */
235 /* max # tx status to process in wlc_txstatus() */
238 /* brcmu_format_flags() bit description structure */
239 struct brcms_c_bit_desc {
245 * The following table lists the buffer memory allocated to xmt fifos in HW.
246 * the size is in units of 256bytes(one block), total size is HW dependent
247 * ucode has default fifo partition, sw can overwrite if necessary
249 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
250 * the twiki is updated before making changes.
253 /* Starting corerev for the fifo size table */
254 #define XMTFIFOTBL_STARTREV 17
262 struct edcf_acparam {
271 /* TX FIFO number to WME/802.1E Access Category */
272 static const u8 wme_fifo2ac[] = {
281 /* ieee80211 Access Category to TX FIFO number */
282 static const u8 wme_ac2fifo[] = {
289 static const u16 xmtfifo_sz[][NFIFO] = {
290 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291 {20, 192, 192, 21, 17, 5},
296 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297 {20, 192, 192, 21, 17, 5},
298 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299 {9, 58, 22, 14, 14, 5},
300 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301 {20, 192, 192, 21, 17, 5},
302 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303 {20, 192, 192, 21, 17, 5},
304 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305 {9, 58, 22, 14, 14, 5},
312 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
313 {9, 58, 22, 14, 14, 5},
317 static const char * const fifo_names[] = {
318 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
320 static const char fifo_names[6][0];
324 /* pointer to most recently allocated wl/wlc */
325 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
328 /* Mapping of ieee80211 AC numbers to tx fifos */
329 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
330 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
331 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
332 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
333 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
336 /* Mapping of tx fifos to ieee80211 AC numbers */
337 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
338 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
339 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
340 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
341 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
344 static u8 brcms_ac_to_fifo(u8 ac)
346 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
347 return TX_AC_BE_FIFO;
348 return ac_to_fifo_mapping[ac];
351 static u8 brcms_fifo_to_ac(u8 fifo)
353 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
354 return IEEE80211_AC_BE;
355 return fifo_to_ac_mapping[fifo];
358 /* Find basic rate for a given rate */
359 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
361 if (is_mcs_rate(rspec))
362 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
364 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
367 static u16 frametype(u32 rspec, u8 mimoframe)
369 if (is_mcs_rate(rspec))
371 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
374 /* currently the best mechanism for determining SIFS is the band in use */
375 static u16 get_sifs(struct brcms_band *band)
377 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
382 * Detect Card removed.
383 * Even checking an sbconfig register read will not false trigger when the core
384 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
385 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
386 * reg with fixed 0/1 pattern (some platforms return all 0).
387 * If clocks are present, call the sb routine which will figure out if the
390 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
395 return ai_deviceremoved(wlc->hw->sih);
396 macctrl = bcma_read32(wlc->hw->d11core,
397 D11REGOFFS(maccontrol));
398 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
401 /* sum the individual fifo tx pending packet counts */
402 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
407 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
409 pending += dma_txpending(wlc->hw->di[i]);
413 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
415 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
418 static int brcms_chspec_bw(u16 chanspec)
420 if (CHSPEC_IS40(chanspec))
422 if (CHSPEC_IS20(chanspec))
428 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
433 kfree(cfg->current_bss);
437 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
442 brcms_c_bsscfg_mfree(wlc->bsscfg);
444 kfree(wlc->modulecb);
445 kfree(wlc->default_bss);
446 kfree(wlc->protection);
448 kfree(wlc->bandstate[0]);
449 kfree(wlc->corestate->macstat_snapshot);
450 kfree(wlc->corestate);
451 kfree(wlc->hw->bandstate[0]);
459 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
461 struct brcms_bss_cfg *cfg;
463 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
467 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
468 if (cfg->current_bss == NULL)
474 brcms_c_bsscfg_mfree(cfg);
478 static struct brcms_c_info *
479 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
481 struct brcms_c_info *wlc;
483 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
489 /* allocate struct brcms_c_pub state structure */
490 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
491 if (wlc->pub == NULL) {
497 /* allocate struct brcms_hardware state structure */
499 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
500 if (wlc->hw == NULL) {
506 wlc->hw->bandstate[0] =
507 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
508 if (wlc->hw->bandstate[0] == NULL) {
514 for (i = 1; i < MAXBANDS; i++)
515 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
516 ((unsigned long)wlc->hw->bandstate[0] +
517 (sizeof(struct brcms_hw_band) * i));
521 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
522 if (wlc->modulecb == NULL) {
527 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
528 if (wlc->default_bss == NULL) {
533 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
534 if (wlc->bsscfg == NULL) {
539 wlc->protection = kzalloc(sizeof(struct brcms_protection),
541 if (wlc->protection == NULL) {
546 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
547 if (wlc->stf == NULL) {
553 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
554 if (wlc->bandstate[0] == NULL) {
560 for (i = 1; i < MAXBANDS; i++)
561 wlc->bandstate[i] = (struct brcms_band *)
562 ((unsigned long)wlc->bandstate[0]
563 + (sizeof(struct brcms_band)*i));
566 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
567 if (wlc->corestate == NULL) {
572 wlc->corestate->macstat_snapshot =
573 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
574 if (wlc->corestate->macstat_snapshot == NULL) {
582 brcms_c_detach_mfree(wlc);
587 * Update the slot timing for standard 11b/g (20us slots)
588 * or shortslot 11g (9us slots)
589 * The PSM needs to be suspended for this call.
591 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
594 struct bcma_device *core = wlc_hw->d11core;
597 /* 11g short slot: 11a timing */
598 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
599 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
601 /* 11g long slot: 11b timing */
602 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
603 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
608 * calculate frame duration of a given rate and length, return
611 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
612 u8 preamble_type, uint mac_len)
614 uint nsyms, dur = 0, Ndps, kNdps;
615 uint rate = rspec2rate(ratespec);
618 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
623 if (is_mcs_rate(ratespec)) {
624 uint mcs = ratespec & RSPEC_RATE_MASK;
625 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
627 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
628 if (preamble_type == BRCMS_MM_PREAMBLE)
630 /* 1000Ndbps = kbps * 4 */
631 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
632 rspec_issgi(ratespec)) * 4;
634 if (rspec_stc(ratespec) == 0)
636 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
637 APHY_TAIL_NBITS) * 1000, kNdps);
639 /* STBC needs to have even number of symbols */
642 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
643 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
645 dur += APHY_SYMBOL_TIME * nsyms;
646 if (wlc->band->bandtype == BRCM_BAND_2G)
647 dur += DOT11_OFDM_SIGNAL_EXTENSION;
648 } else if (is_ofdm_rate(rate)) {
649 dur = APHY_PREAMBLE_TIME;
650 dur += APHY_SIGNAL_TIME;
651 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
653 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
655 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
657 dur += APHY_SYMBOL_TIME * nsyms;
658 if (wlc->band->bandtype == BRCM_BAND_2G)
659 dur += DOT11_OFDM_SIGNAL_EXTENSION;
662 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
665 mac_len = mac_len * 8 * 2;
666 /* calc ceiling of bits/rate = microseconds of air time */
667 dur = (mac_len + rate - 1) / rate;
668 if (preamble_type & BRCMS_SHORT_PREAMBLE)
669 dur += BPHY_PLCP_SHORT_TIME;
671 dur += BPHY_PLCP_TIME;
676 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
677 const struct d11init *inits)
679 struct bcma_device *core = wlc_hw->d11core;
685 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
687 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
688 size = le16_to_cpu(inits[i].size);
689 offset = le16_to_cpu(inits[i].addr);
690 value = le32_to_cpu(inits[i].value);
692 bcma_write16(core, offset, value);
694 bcma_write32(core, offset, value);
700 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
704 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
708 for (idx = 0; idx < MHFMAX; idx++)
709 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
712 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
714 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
716 /* init microcode host flags */
717 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
719 /* do band-specific ucode IHR, SHM, and SCR inits */
720 if (D11REV_IS(wlc_hw->corerev, 23)) {
721 if (BRCMS_ISNPHY(wlc_hw->band))
722 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
724 brcms_err(wlc_hw->d11core,
725 "%s: wl%d: unsupported phy in corerev %d\n",
726 __func__, wlc_hw->unit,
729 if (D11REV_IS(wlc_hw->corerev, 24)) {
730 if (BRCMS_ISLCNPHY(wlc_hw->band))
731 brcms_c_write_inits(wlc_hw,
732 ucode->d11lcn0bsinitvals24);
734 brcms_err(wlc_hw->d11core,
735 "%s: wl%d: unsupported phy in core rev %d\n",
736 __func__, wlc_hw->unit,
739 brcms_err(wlc_hw->d11core,
740 "%s: wl%d: unsupported corerev %d\n",
741 __func__, wlc_hw->unit, wlc_hw->corerev);
746 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
748 struct bcma_device *core = wlc_hw->d11core;
749 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
751 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
754 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
756 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
758 wlc_hw->phyclk = clk;
760 if (OFF == clk) { /* clear gmode bit, put phy into reset */
762 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
763 (SICF_PRST | SICF_FGC));
765 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
768 } else { /* take phy out of reset */
770 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
772 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
778 /* low-level band switch utility routine */
779 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
781 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
784 wlc_hw->band = wlc_hw->bandstate[bandunit];
788 * until we eliminate need for wlc->band refs in low level code
790 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
792 /* set gmode core flag */
793 if (wlc_hw->sbclk && !wlc_hw->noreset) {
799 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
803 /* switch to new band but leave it inactive */
804 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
806 struct brcms_hardware *wlc_hw = wlc->hw;
810 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
811 macctrl = bcma_read32(wlc_hw->d11core,
812 D11REGOFFS(maccontrol));
813 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
815 /* disable interrupts */
816 macintmask = brcms_intrsoff(wlc->wl);
819 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
821 brcms_b_core_phy_clk(wlc_hw, OFF);
823 brcms_c_setxband(wlc_hw, bandunit);
828 /* process an individual struct tx_status */
830 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
832 struct sk_buff *p = NULL;
834 struct dma_pub *dma = NULL;
835 struct d11txh *txh = NULL;
836 struct scb *scb = NULL;
838 int tx_rts, tx_frame_count, tx_rts_count;
839 uint totlen, supr_status;
841 struct ieee80211_hdr *h;
843 struct ieee80211_tx_info *tx_info;
844 struct ieee80211_tx_rate *txrate;
848 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
849 txs->frameid, txs->status, txs->lasttxtime,
850 txs->sequence, txs->phyerr, txs->ackphyrxsh);
852 /* discard intermediate indications for ucode with one legitimate case:
853 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
854 * but the subsequent tx of DATA failed. so it will start rts/cts
855 * from the beginning (resetting the rts transmission count)
857 if (!(txs->status & TX_STATUS_AMPDU)
858 && (txs->status & TX_STATUS_INTERMEDIATE)) {
859 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
864 queue = txs->frameid & TXFID_QUEUE_MASK;
865 if (queue >= NFIFO) {
866 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
870 dma = wlc->hw->di[queue];
872 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
874 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
878 txh = (struct d11txh *) (p->data);
879 mcl = le16_to_cpu(txh->MacTxControlLow);
882 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
883 txs->phyerr, txh->MainRates);
885 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
886 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
889 tx_info = IEEE80211_SKB_CB(p);
890 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
892 if (tx_info->rate_driver_data[0])
895 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
896 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
902 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
903 * frames; this traces them for the rest.
905 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
907 supr_status = txs->status & TX_STATUS_SUPR_MASK;
908 if (supr_status == TX_STATUS_SUPR_BADCH) {
909 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
910 brcms_dbg_tx(wlc->hw->d11core,
911 "Pkt tx suppressed, dest chan %u, current %d\n",
912 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
913 CHSPEC_CHANNEL(wlc->default_bss->chanspec));
916 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
918 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
920 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
922 lastframe = !ieee80211_has_morefrags(h->frame_control);
925 brcms_err(wlc->hw->d11core, "Not last frame!\n");
928 * Set information to be consumed by Minstrel ht.
930 * The "fallback limit" is the number of tx attempts a given
931 * MPDU is sent at the "primary" rate. Tx attempts beyond that
932 * limit are sent at the "secondary" rate.
933 * A 'short frame' does not exceed RTS treshold.
935 u16 sfbl, /* Short Frame Rate Fallback Limit */
936 lfbl, /* Long Frame Rate Fallback Limit */
939 if (queue < IEEE80211_NUM_ACS) {
940 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
942 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
949 txrate = tx_info->status.rates;
950 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
955 ieee80211_tx_info_clear_status(tx_info);
957 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
959 * rate selection requested a fallback rate
962 txrate[0].count = fbl;
963 txrate[1].count = tx_frame_count - fbl;
966 * rate selection did not request fallback rate, or
969 txrate[0].count = tx_frame_count;
971 * rc80211_minstrel.c:minstrel_tx_status() expects
972 * unused rates to be marked with idx = -1
978 /* clear the rest of the rates */
979 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
984 if (txs->status & TX_STATUS_ACK_RCV)
985 tx_info->flags |= IEEE80211_TX_STAT_ACK;
992 /* remove PLCP & Broadcom tx descriptor header */
993 skb_pull(p, D11_PHY_HDR_LEN);
994 skb_pull(p, D11_TXH_LEN);
995 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
997 brcms_err(wlc->hw->d11core,
998 "%s: Not last frame => not calling tx_status\n",
1007 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1010 brcmu_pkt_buf_free_skb(p);
1013 if (dma && queue < NFIFO) {
1014 u16 ac_queue = brcms_fifo_to_ac(queue);
1015 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1016 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1017 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1024 /* process tx completion events in BMAC
1025 * Return true if more tx status need to be processed. false otherwise.
1028 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1030 bool morepending = false;
1031 struct bcma_device *core;
1032 struct tx_status txstatus, *txs;
1036 * Param 'max_tx_num' indicates max. # tx status to process before
1039 uint max_tx_num = bound ? TXSBND : -1;
1042 core = wlc_hw->d11core;
1044 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1048 if (s1 == 0xffffffff) {
1049 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1053 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1055 txs->status = s1 & TXS_STATUS_MASK;
1056 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1057 txs->sequence = s2 & TXS_SEQ_MASK;
1058 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1059 txs->lasttxtime = 0;
1061 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1063 /* !give others some time to run! */
1064 if (++n >= max_tx_num)
1066 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1072 if (n >= max_tx_num)
1078 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1080 if (!wlc->bsscfg->BSS)
1082 * DirFrmQ is now valid...defer setting until end
1085 wlc->qvalid |= MCMD_DIRFRMQVAL;
1088 /* set initial host flags value */
1090 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1092 struct brcms_hardware *wlc_hw = wlc->hw;
1094 memset(mhfs, 0, MHFMAX * sizeof(u16));
1096 mhfs[MHF2] |= mhf2_init;
1098 /* prohibit use of slowclock on multifunction boards */
1099 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1100 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1102 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1103 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1104 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1109 dmareg(uint direction, uint fifonum)
1111 if (direction == DMA_TX)
1112 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1113 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1116 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1121 * ucode host flag 2 needed for pio mode, independent of band and fifo
1124 struct brcms_hardware *wlc_hw = wlc->hw;
1125 uint unit = wlc_hw->unit;
1127 /* name and offsets for dma_attach */
1128 snprintf(name, sizeof(name), "wl%d", unit);
1130 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1131 int dma_attach_err = 0;
1135 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1136 * RX: RX_FIFO (RX data packets)
1138 wlc_hw->di[0] = dma_attach(name, wlc,
1139 (wme ? dmareg(DMA_TX, 0) : 0),
1141 (wme ? NTXD : 0), NRXD,
1142 RXBUFSZ, -1, NRXBUFPOST,
1144 dma_attach_err |= (NULL == wlc_hw->di[0]);
1148 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1149 * (legacy) TX_DATA_FIFO (TX data packets)
1152 wlc_hw->di[1] = dma_attach(name, wlc,
1153 dmareg(DMA_TX, 1), 0,
1154 NTXD, 0, 0, -1, 0, 0);
1155 dma_attach_err |= (NULL == wlc_hw->di[1]);
1159 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1162 wlc_hw->di[2] = dma_attach(name, wlc,
1163 dmareg(DMA_TX, 2), 0,
1164 NTXD, 0, 0, -1, 0, 0);
1165 dma_attach_err |= (NULL == wlc_hw->di[2]);
1168 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1169 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1171 wlc_hw->di[3] = dma_attach(name, wlc,
1175 dma_attach_err |= (NULL == wlc_hw->di[3]);
1176 /* Cleaner to leave this as if with AP defined */
1178 if (dma_attach_err) {
1179 brcms_err(wlc_hw->d11core,
1180 "wl%d: wlc_attach: dma_attach failed\n",
1185 /* get pointer to dma engine tx flow control variable */
1186 for (i = 0; i < NFIFO; i++)
1188 wlc_hw->txavail[i] =
1189 (uint *) dma_getvar(wlc_hw->di[i],
1193 /* initial ucode host flags */
1194 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1199 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1203 for (j = 0; j < NFIFO; j++) {
1204 if (wlc_hw->di[j]) {
1205 dma_detach(wlc_hw->di[j]);
1206 wlc_hw->di[j] = NULL;
1212 * Initialize brcms_c_info default values ...
1213 * may get overrides later in this function
1214 * BMAC_NOTES, move low out and resolve the dangling ones
1216 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1218 struct brcms_c_info *wlc = wlc_hw->wlc;
1220 /* set default sw macintmask value */
1221 wlc->defmacintmask = DEF_MACINTMASK;
1223 /* various 802.11g modes */
1224 wlc_hw->shortslot = false;
1226 wlc_hw->SFBL = RETRY_SHORT_FB;
1227 wlc_hw->LFBL = RETRY_LONG_FB;
1229 /* default mac retry limits */
1230 wlc_hw->SRL = RETRY_SHORT_DEF;
1231 wlc_hw->LRL = RETRY_LONG_DEF;
1232 wlc_hw->chanspec = ch20mhz_chspec(1);
1235 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1237 /* delay before first read of ucode state */
1240 /* wait until ucode is no longer asleep */
1241 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1242 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1245 /* control chip clock to save power, enable dynamic clock or force fast clock */
1246 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1248 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1249 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1250 * on backplane, but mac core will still run on ALP(not HT) when
1251 * it enters powersave mode, which means the FCA bit may not be
1252 * set. Should wakeup mac if driver wants it to run on HT.
1256 if (mode == BCMA_CLKMODE_FAST) {
1257 bcma_set32(wlc_hw->d11core,
1258 D11REGOFFS(clk_ctl_st),
1264 ((bcma_read32(wlc_hw->d11core,
1265 D11REGOFFS(clk_ctl_st)) &
1267 PMU_MAX_TRANSITION_DLY);
1268 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1269 D11REGOFFS(clk_ctl_st)) &
1272 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1273 (bcma_read32(wlc_hw->d11core,
1274 D11REGOFFS(clk_ctl_st)) &
1275 (CCS_FORCEHT | CCS_HTAREQ)))
1277 ((bcma_read32(wlc_hw->d11core,
1278 offsetof(struct d11regs,
1281 PMU_MAX_TRANSITION_DLY);
1282 bcma_mask32(wlc_hw->d11core,
1283 D11REGOFFS(clk_ctl_st),
1287 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1290 /* old chips w/o PMU, force HT through cc,
1291 * then use FCA to verify mac is running fast clock
1294 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1296 /* check fast clock is available (if core is not in reset) */
1297 if (wlc_hw->forcefastclk && wlc_hw->clk)
1298 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1302 * keep the ucode wake bit on if forcefastclk is on since we
1303 * do not want ucode to put us back to slow clock when it dozes
1304 * for PM mode. Code below matches the wake override bit with
1305 * current forcefastclk state. Only setting bit in wake_override
1306 * instead of waking ucode immediately since old code had this
1307 * behavior. Older code set wlc->forcefastclk but only had the
1308 * wake happen if the wakup_ucode work (protected by an up
1309 * check) was executed just below.
1311 if (wlc_hw->forcefastclk)
1312 mboolset(wlc_hw->wake_override,
1313 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1315 mboolclr(wlc_hw->wake_override,
1316 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1320 /* set or clear ucode host flag bits
1321 * it has an optimization for no-change write
1322 * it only writes through shared memory when the core has clock;
1323 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1326 * bands values are: BRCM_BAND_AUTO <--- Current band only
1327 * BRCM_BAND_5G <--- 5G band only
1328 * BRCM_BAND_2G <--- 2G band only
1329 * BRCM_BAND_ALL <--- All bands
1332 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1336 u16 addr[MHFMAX] = {
1337 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1340 struct brcms_hw_band *band;
1342 if ((val & ~mask) || idx >= MHFMAX)
1343 return; /* error condition */
1346 /* Current band only or all bands,
1347 * then set the band to current band
1349 case BRCM_BAND_AUTO:
1351 band = wlc_hw->band;
1354 band = wlc_hw->bandstate[BAND_5G_INDEX];
1357 band = wlc_hw->bandstate[BAND_2G_INDEX];
1360 band = NULL; /* error condition */
1364 save = band->mhfs[idx];
1365 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1367 /* optimization: only write through if changed, and
1368 * changed band is the current band
1370 if (wlc_hw->clk && (band->mhfs[idx] != save)
1371 && (band == wlc_hw->band))
1372 brcms_b_write_shm(wlc_hw, addr[idx],
1373 (u16) band->mhfs[idx]);
1376 if (bands == BRCM_BAND_ALL) {
1377 wlc_hw->bandstate[0]->mhfs[idx] =
1378 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1379 wlc_hw->bandstate[1]->mhfs[idx] =
1380 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1384 /* set the maccontrol register to desired reset state and
1385 * initialize the sw cache of the register
1387 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1389 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1390 wlc_hw->maccontrol = 0;
1391 wlc_hw->suspended_fifos = 0;
1392 wlc_hw->wake_override = 0;
1393 wlc_hw->mute_override = 0;
1394 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1398 * write the software state of maccontrol and
1399 * overrides to the maccontrol register
1401 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1403 u32 maccontrol = wlc_hw->maccontrol;
1405 /* OR in the wake bit if overridden */
1406 if (wlc_hw->wake_override)
1407 maccontrol |= MCTL_WAKE;
1409 /* set AP and INFRA bits for mute if needed */
1410 if (wlc_hw->mute_override) {
1411 maccontrol &= ~(MCTL_AP);
1412 maccontrol |= MCTL_INFRA;
1415 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1419 /* set or clear maccontrol bits */
1420 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1426 return; /* error condition */
1427 maccontrol = wlc_hw->maccontrol;
1428 new_maccontrol = (maccontrol & ~mask) | val;
1430 /* if the new maccontrol value is the same as the old, nothing to do */
1431 if (new_maccontrol == maccontrol)
1434 /* something changed, cache the new value */
1435 wlc_hw->maccontrol = new_maccontrol;
1437 /* write the new values with overrides applied */
1438 brcms_c_mctrl_write(wlc_hw);
1441 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1444 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1445 mboolset(wlc_hw->wake_override, override_bit);
1449 mboolset(wlc_hw->wake_override, override_bit);
1451 brcms_c_mctrl_write(wlc_hw);
1452 brcms_b_wait_for_wake(wlc_hw);
1455 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1458 mboolclr(wlc_hw->wake_override, override_bit);
1460 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1463 brcms_c_mctrl_write(wlc_hw);
1466 /* When driver needs ucode to stop beaconing, it has to make sure that
1467 * MCTL_AP is clear and MCTL_INFRA is set
1468 * Mode MCTL_AP MCTL_INFRA
1470 * STA 0 1 <--- This will ensure no beacons
1473 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1475 wlc_hw->mute_override = 1;
1477 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1478 * override, then there is no change to write
1480 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1483 brcms_c_mctrl_write(wlc_hw);
1486 /* Clear the override on AP and INFRA bits */
1487 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1489 if (wlc_hw->mute_override == 0)
1492 wlc_hw->mute_override = 0;
1494 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1495 * override, then there is no change to write
1497 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1500 brcms_c_mctrl_write(wlc_hw);
1504 * Write a MAC address to the given match reg offset in the RXE match engine.
1507 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1510 struct bcma_device *core = wlc_hw->d11core;
1515 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1517 mac_l = addr[0] | (addr[1] << 8);
1518 mac_m = addr[2] | (addr[3] << 8);
1519 mac_h = addr[4] | (addr[5] << 8);
1521 /* enter the MAC addr into the RXE match registers */
1522 bcma_write16(core, D11REGOFFS(rcm_ctl),
1523 RCM_INC_DATA | match_reg_offset);
1524 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1525 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1526 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1530 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1533 struct bcma_device *core = wlc_hw->d11core;
1538 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1540 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1542 /* if MCTL_BIGEND bit set in mac control register,
1543 * the chip swaps data in fifo, as well as data in
1546 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1549 memcpy(&word, buf, sizeof(u32));
1552 word_be = cpu_to_be32(word);
1553 word = *(u32 *)&word_be;
1555 word_le = cpu_to_le32(word);
1556 word = *(u32 *)&word_le;
1559 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1561 buf = (u8 *) buf + sizeof(u32);
1566 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1568 wlc_hw->band->CWmin = newmin;
1570 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1571 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1572 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1573 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1576 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1578 wlc_hw->band->CWmax = newmax;
1580 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1581 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1582 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1583 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1586 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1590 /* request FAST clock if not on */
1591 fastclk = wlc_hw->forcefastclk;
1593 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1595 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1597 brcms_b_phy_reset(wlc_hw);
1598 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1600 /* restore the clk */
1602 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1605 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1608 struct brcms_c_info *wlc = wlc_hw->wlc;
1609 /* update SYNTHPU_DLY */
1611 if (BRCMS_ISLCNPHY(wlc->band))
1612 v = SYNTHPU_DLY_LPPHY_US;
1613 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1614 v = SYNTHPU_DLY_NPHY_US;
1616 v = SYNTHPU_DLY_BPHY_US;
1618 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1621 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1624 u16 phytxant = wlc_hw->bmac_phytxant;
1625 u16 mask = PHY_TXC_ANT_MASK;
1627 /* set the Probe Response frame phy control word */
1628 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1629 phyctl = (phyctl & ~mask) | phytxant;
1630 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1632 /* set the Response (ACK/CTS) frame phy control word */
1633 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1634 phyctl = (phyctl & ~mask) | phytxant;
1635 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1638 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1643 struct plcp_signal_rate_lookup {
1647 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1648 const struct plcp_signal_rate_lookup rate_lookup[] = {
1649 {BRCM_RATE_6M, 0xB},
1650 {BRCM_RATE_9M, 0xF},
1651 {BRCM_RATE_12M, 0xA},
1652 {BRCM_RATE_18M, 0xE},
1653 {BRCM_RATE_24M, 0x9},
1654 {BRCM_RATE_36M, 0xD},
1655 {BRCM_RATE_48M, 0x8},
1656 {BRCM_RATE_54M, 0xC}
1659 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1660 if (rate == rate_lookup[i].rate) {
1661 plcp_rate = rate_lookup[i].signal_rate;
1666 /* Find the SHM pointer to the rate table entry by looking in the
1669 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1672 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1676 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1677 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1683 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1686 /* walk the phy rate table and update the entries */
1687 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1690 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1692 /* read the SHM Rate Table entry OFDM PCTL1 values */
1694 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1696 /* modify the value */
1697 pctl1 &= ~PHY_TXC1_MODE_MASK;
1698 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1700 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1701 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1706 /* band-specific init */
1707 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1709 struct brcms_hardware *wlc_hw = wlc->hw;
1711 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1712 wlc_hw->band->bandunit);
1714 brcms_c_ucode_bsinit(wlc_hw);
1716 wlc_phy_init(wlc_hw->band->pi, chanspec);
1718 brcms_c_ucode_txant_set(wlc_hw);
1721 * cwmin is band-specific, update hardware
1722 * with value for current band
1724 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1725 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1727 brcms_b_update_slot_timing(wlc_hw,
1728 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1729 true : wlc_hw->shortslot);
1731 /* write phytype and phyvers */
1732 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1733 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1736 * initialize the txphyctl1 rate table since
1737 * shmem is shared between bands
1739 brcms_upd_ofdm_pctl1_table(wlc_hw);
1741 brcms_b_upd_synthpu(wlc_hw);
1744 /* Perform a soft reset of the PHY PLL */
1745 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1747 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1750 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1753 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1756 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1761 /* light way to turn on phy clock without reset for NPHY only
1762 * refer to brcms_b_core_phy_clk for full version
1764 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1766 /* support(necessary for NPHY and HYPHY) only */
1767 if (!BRCMS_ISNPHY(wlc_hw->band))
1771 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1773 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1777 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1780 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1782 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1785 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1787 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1789 bool phy_in_reset = false;
1791 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1796 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1798 /* Specific reset sequence required for NPHY rev 3 and 4 */
1799 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1800 NREV_LE(wlc_hw->band->phyrev, 4)) {
1801 /* Set the PHY bandwidth */
1802 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1806 /* Perform a soft reset of the PHY PLL */
1807 brcms_b_core_phypll_reset(wlc_hw);
1810 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1811 (SICF_PRST | SICF_PCLKE));
1812 phy_in_reset = true;
1814 brcms_b_core_ioctl(wlc_hw,
1815 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1816 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1820 brcms_b_core_phy_clk(wlc_hw, ON);
1823 wlc_phy_anacore(pih, ON);
1826 /* switch to and initialize new band */
1827 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1829 struct brcms_c_info *wlc = wlc_hw->wlc;
1832 /* Enable the d11 core before accessing it */
1833 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1834 bcma_core_enable(wlc_hw->d11core, 0);
1835 brcms_c_mctrl_reset(wlc_hw);
1838 macintmask = brcms_c_setband_inact(wlc, bandunit);
1843 brcms_b_core_phy_clk(wlc_hw, ON);
1845 /* band-specific initializations */
1846 brcms_b_bsinit(wlc, chanspec);
1849 * If there are any pending software interrupt bits,
1850 * then replace these with a harmless nonzero value
1851 * so brcms_c_dpc() will re-enable interrupts when done.
1853 if (wlc->macintstatus)
1854 wlc->macintstatus = MI_DMAINT;
1856 /* restore macintmask */
1857 brcms_intrsrestore(wlc->wl, macintmask);
1859 /* ucode should still be suspended.. */
1860 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1864 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1867 /* reject unsupported corerev */
1868 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1869 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1877 /* Validate some board info parameters */
1878 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1880 uint boardrev = wlc_hw->boardrev;
1882 /* 4 bits each for board type, major, minor, and tiny version */
1883 uint brt = (boardrev & 0xf000) >> 12;
1884 uint b0 = (boardrev & 0xf00) >> 8;
1885 uint b1 = (boardrev & 0xf0) >> 4;
1886 uint b2 = boardrev & 0xf;
1888 /* voards from other vendors are always considered valid */
1889 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1892 /* do some boardrev sanity checks when boardvendor is Broadcom */
1896 if (boardrev <= 0xff)
1899 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1906 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1908 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1910 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1911 if (!is_zero_ether_addr(sprom->il0mac)) {
1912 memcpy(etheraddr, sprom->il0mac, 6);
1916 if (wlc_hw->_nbands > 1)
1917 memcpy(etheraddr, sprom->et1mac, 6);
1919 memcpy(etheraddr, sprom->il0mac, 6);
1922 /* power both the pll and external oscillator on/off */
1923 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1925 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1928 * dont power down if plldown is false or
1929 * we must poll hw radio disable
1931 if (!want && wlc_hw->pllreq)
1934 wlc_hw->sbclk = want;
1935 if (!wlc_hw->sbclk) {
1936 wlc_hw->clk = false;
1937 if (wlc_hw->band && wlc_hw->band->pi)
1938 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1943 * Return true if radio is disabled, otherwise false.
1944 * hw radio disable signal is an external pin, users activate it asynchronously
1945 * this function could be called when driver is down and w/o clock
1946 * it operates on different registers depending on corerev and boardflag.
1948 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1953 xtal = wlc_hw->sbclk;
1955 brcms_b_xtal(wlc_hw, ON);
1957 /* may need to take core out of reset first */
1961 * mac no longer enables phyclk automatically when driver
1962 * accesses phyreg throughput mac. This can be skipped since
1963 * only mac reg is accessed below
1965 if (D11REV_GE(wlc_hw->corerev, 18))
1966 flags |= SICF_PCLKE;
1969 * TODO: test suspend/resume
1971 * AI chip doesn't restore bar0win2 on
1972 * hibernation/resume, need sw fixup
1975 bcma_core_enable(wlc_hw->d11core, flags);
1976 brcms_c_mctrl_reset(wlc_hw);
1979 v = ((bcma_read32(wlc_hw->d11core,
1980 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1982 /* put core back into reset */
1984 bcma_core_disable(wlc_hw->d11core, 0);
1987 brcms_b_xtal(wlc_hw, OFF);
1992 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1994 struct dma_pub *di = wlc_hw->di[fifo];
1995 return dma_rxreset(di);
1999 * ensure fask clock during reset
2001 * reset d11(out of reset)
2002 * reset phy(out of reset)
2003 * clear software macintstatus for fresh new start
2004 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2006 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2011 if (flags == BRCMS_USE_COREFLAGS)
2012 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2014 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2016 /* request FAST clock if not on */
2017 fastclk = wlc_hw->forcefastclk;
2019 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2021 /* reset the dma engines except first time thru */
2022 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2023 for (i = 0; i < NFIFO; i++)
2024 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2025 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2026 "dma_txreset[%d]: cannot stop dma\n",
2027 wlc_hw->unit, __func__, i);
2029 if ((wlc_hw->di[RX_FIFO])
2030 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2031 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2032 "[%d]: cannot stop dma\n",
2033 wlc_hw->unit, __func__, RX_FIFO);
2035 /* if noreset, just stop the psm and return */
2036 if (wlc_hw->noreset) {
2037 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2038 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2043 * mac no longer enables phyclk automatically when driver accesses
2044 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2045 * band->pi is invalid. need to enable PHY CLK
2047 if (D11REV_GE(wlc_hw->corerev, 18))
2048 flags |= SICF_PCLKE;
2052 * In chips with PMU, the fastclk request goes through d11 core
2053 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2055 * This adds some delay and we can optimize it by also requesting
2056 * fastclk through chipcommon during this period if necessary. But
2057 * that has to work coordinate with other driver like mips/arm since
2058 * they may touch chipcommon as well.
2060 wlc_hw->clk = false;
2061 bcma_core_enable(wlc_hw->d11core, flags);
2063 if (wlc_hw->band && wlc_hw->band->pi)
2064 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2066 brcms_c_mctrl_reset(wlc_hw);
2068 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2069 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2071 brcms_b_phy_reset(wlc_hw);
2073 /* turn on PHY_PLL */
2074 brcms_b_core_phypll_ctl(wlc_hw, true);
2076 /* clear sw intstatus */
2077 wlc_hw->wlc->macintstatus = 0;
2079 /* restore the clk setting */
2081 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2084 /* txfifo sizes needs to be modified(increased) since the newer cores
2087 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2089 struct bcma_device *core = wlc_hw->d11core;
2091 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2092 u16 txfifo_def, txfifo_def1;
2095 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2096 txfifo_startblk = TXFIFO_START_BLK;
2098 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2099 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2101 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2102 txfifo_def = (txfifo_startblk & 0xff) |
2103 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2104 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2106 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2108 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2110 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2111 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2112 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2114 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2116 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2119 * need to propagate to shm location to be in sync since ucode/hw won't
2122 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2123 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2124 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2125 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2126 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2127 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2128 xmtfifo_sz[TX_AC_BK_FIFO]));
2129 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2130 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2131 xmtfifo_sz[TX_BCMC_FIFO]));
2134 /* This function is used for changing the tsf frac register
2135 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2136 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2137 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2138 * HTPHY Formula is 2^26/freq(MHz) e.g.
2139 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2140 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2141 * For spuron: 123MHz -> 2^26/123 = 545600.5
2142 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2143 * For spur off: 120MHz -> 2^26/120 = 559240.5
2144 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2147 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2149 struct bcma_device *core = wlc_hw->d11core;
2151 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2152 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2153 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2154 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2155 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2156 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2157 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2158 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2159 } else { /* 120Mhz */
2160 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2161 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2163 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2164 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2165 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2166 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2167 } else { /* 80Mhz */
2168 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2169 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2174 /* Initialize GPIOs that are controlled by D11 core */
2175 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2177 struct brcms_hardware *wlc_hw = wlc->hw;
2180 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2181 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2184 * Common GPIO setup:
2185 * G0 = LED 0 = WLAN Activity
2186 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2187 * G2 = LED 2 = WLAN 5 GHz Radio State
2188 * G4 = radio disable input (HI enabled, LO disabled)
2193 /* Allocate GPIOs for mimo antenna diversity feature */
2194 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2195 /* Enable antenna diversity, use 2x3 mode */
2196 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2197 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2198 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2199 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2201 /* init superswitch control */
2202 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2204 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2205 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2207 * The board itself is powered by these GPIOs
2208 * (when not sending pattern) so set them high
2210 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2211 (BOARD_GPIO_12 | BOARD_GPIO_13));
2212 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2213 (BOARD_GPIO_12 | BOARD_GPIO_13));
2215 /* Enable antenna diversity, use 2x4 mode */
2216 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2217 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2218 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2221 /* Configure the desired clock to be 4Mhz */
2222 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2223 ANTSEL_CLKDIV_4MHZ);
2227 * gpio 9 controls the PA. ucode is responsible
2228 * for wiggling out and oe
2230 if (wlc_hw->boardflags & BFL_PACTRL)
2231 gm |= gc |= BOARD_GPIO_PACTRL;
2233 /* apply to gpiocontrol register */
2234 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2237 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2238 const __le32 ucode[], const size_t nbytes)
2240 struct bcma_device *core = wlc_hw->d11core;
2244 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2246 count = (nbytes / sizeof(u32));
2248 bcma_write32(core, D11REGOFFS(objaddr),
2249 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2250 (void)bcma_read32(core, D11REGOFFS(objaddr));
2251 for (i = 0; i < count; i++)
2252 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2256 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2258 struct brcms_c_info *wlc;
2259 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2263 if (wlc_hw->ucode_loaded)
2266 if (D11REV_IS(wlc_hw->corerev, 23)) {
2267 if (BRCMS_ISNPHY(wlc_hw->band)) {
2268 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2269 ucode->bcm43xx_16_mimosz);
2270 wlc_hw->ucode_loaded = true;
2272 brcms_err(wlc_hw->d11core,
2273 "%s: wl%d: unsupported phy in corerev %d\n",
2274 __func__, wlc_hw->unit, wlc_hw->corerev);
2275 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2276 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2277 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2278 ucode->bcm43xx_24_lcnsz);
2279 wlc_hw->ucode_loaded = true;
2281 brcms_err(wlc_hw->d11core,
2282 "%s: wl%d: unsupported phy in corerev %d\n",
2283 __func__, wlc_hw->unit, wlc_hw->corerev);
2288 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2290 /* update sw state */
2291 wlc_hw->bmac_phytxant = phytxant;
2293 /* push to ucode if up */
2296 brcms_c_ucode_txant_set(wlc_hw);
2300 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2302 return (u16) wlc_hw->wlc->stf->txant;
2305 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2307 wlc_hw->antsel_type = antsel_type;
2309 /* Update the antsel type for phy module to use */
2310 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2313 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2317 uint intstatus, idx;
2318 struct bcma_device *core = wlc_hw->d11core;
2320 unit = wlc_hw->unit;
2322 for (idx = 0; idx < NFIFO; idx++) {
2323 /* read intstatus register and ignore any non-error bits */
2326 D11REGOFFS(intctrlregs[idx].intstatus)) &
2331 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2332 unit, idx, intstatus);
2334 if (intstatus & I_RO) {
2335 brcms_err(core, "wl%d: fifo %d: receive fifo "
2336 "overflow\n", unit, idx);
2340 if (intstatus & I_PC) {
2341 brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2346 if (intstatus & I_PD) {
2347 brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2352 if (intstatus & I_DE) {
2353 brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2354 "error\n", unit, idx);
2358 if (intstatus & I_RU)
2359 brcms_err(core, "wl%d: fifo %d: receive descriptor "
2360 "underflow\n", idx, unit);
2362 if (intstatus & I_XU) {
2363 brcms_err(core, "wl%d: fifo %d: transmit fifo "
2364 "underflow\n", idx, unit);
2369 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2373 D11REGOFFS(intctrlregs[idx].intstatus),
2378 void brcms_c_intrson(struct brcms_c_info *wlc)
2380 struct brcms_hardware *wlc_hw = wlc->hw;
2381 wlc->macintmask = wlc->defmacintmask;
2382 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2385 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2387 struct brcms_hardware *wlc_hw = wlc->hw;
2393 macintmask = wlc->macintmask; /* isr can still happen */
2395 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2396 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2397 udelay(1); /* ensure int line is no longer driven */
2398 wlc->macintmask = 0;
2400 /* return previous macintmask; resolve race between us and our isr */
2401 return wlc->macintstatus ? 0 : macintmask;
2404 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2406 struct brcms_hardware *wlc_hw = wlc->hw;
2410 wlc->macintmask = macintmask;
2411 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2414 /* assumes that the d11 MAC is enabled */
2415 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2418 u8 fifo = 1 << tx_fifo;
2420 /* Two clients of this code, 11h Quiet period and scanning. */
2422 /* only suspend if not already suspended */
2423 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2426 /* force the core awake only if not already */
2427 if (wlc_hw->suspended_fifos == 0)
2428 brcms_c_ucode_wake_override_set(wlc_hw,
2429 BRCMS_WAKE_OVERRIDE_TXFIFO);
2431 wlc_hw->suspended_fifos |= fifo;
2433 if (wlc_hw->di[tx_fifo]) {
2435 * Suspending AMPDU transmissions in the middle can cause
2436 * underflow which may result in mismatch between ucode and
2437 * driver so suspend the mac before suspending the FIFO
2439 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2440 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2442 dma_txsuspend(wlc_hw->di[tx_fifo]);
2444 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2445 brcms_c_enable_mac(wlc_hw->wlc);
2449 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2452 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2453 * but need to be done here for PIO otherwise the watchdog will catch
2454 * the inconsistency and fire
2456 /* Two clients of this code, 11h Quiet period and scanning. */
2457 if (wlc_hw->di[tx_fifo])
2458 dma_txresume(wlc_hw->di[tx_fifo]);
2460 /* allow core to sleep again */
2461 if (wlc_hw->suspended_fifos == 0)
2464 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2465 if (wlc_hw->suspended_fifos == 0)
2466 brcms_c_ucode_wake_override_clear(wlc_hw,
2467 BRCMS_WAKE_OVERRIDE_TXFIFO);
2471 /* precondition: requires the mac core to be enabled */
2472 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2474 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2477 /* suspend tx fifos */
2478 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2479 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2480 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2481 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2483 /* zero the address match register so we do not send ACKs */
2484 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2487 /* resume tx fifos */
2488 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2489 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2490 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2491 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2493 /* Restore address */
2494 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2498 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2501 brcms_c_ucode_mute_override_set(wlc_hw);
2503 brcms_c_ucode_mute_override_clear(wlc_hw);
2507 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2509 brcms_b_mute(wlc->hw, mute_tx);
2513 * Read and clear macintmask and macintstatus and intstatus registers.
2514 * This routine should be called with interrupts off
2516 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2517 * 0 if the interrupt is not for us, or we are in some special cases;
2518 * device interrupt status bits otherwise.
2520 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2522 struct brcms_hardware *wlc_hw = wlc->hw;
2523 struct bcma_device *core = wlc_hw->d11core;
2524 u32 macintstatus, mask;
2526 /* macintstatus includes a DMA interrupt summary bit */
2527 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2528 mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2530 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2532 /* detect cardbus removed, in power down(suspend) and in reset */
2533 if (brcms_deviceremoved(wlc))
2536 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2537 * handle that case here.
2539 if (macintstatus == 0xffffffff)
2542 /* defer unsolicited interrupts */
2543 macintstatus &= mask;
2546 if (macintstatus == 0)
2549 /* turn off the interrupts */
2550 bcma_write32(core, D11REGOFFS(macintmask), 0);
2551 (void)bcma_read32(core, D11REGOFFS(macintmask));
2552 wlc->macintmask = 0;
2554 /* clear device interrupts */
2555 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2557 /* MI_DMAINT is indication of non-zero intstatus */
2558 if (macintstatus & MI_DMAINT)
2560 * only fifo interrupt enabled is I_RI in
2561 * RX_FIFO. If MI_DMAINT is set, assume it
2562 * is set and clear the interrupt.
2564 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2567 return macintstatus;
2570 /* Update wlc->macintstatus and wlc->intstatus[]. */
2571 /* Return true if they are updated successfully. false otherwise */
2572 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2576 /* read and clear macintstatus and intstatus registers */
2577 macintstatus = wlc_intstatus(wlc, false);
2579 /* device is removed */
2580 if (macintstatus == 0xffffffff)
2583 /* update interrupt status in software */
2584 wlc->macintstatus |= macintstatus;
2590 * First-level interrupt processing.
2591 * Return true if this was our interrupt
2592 * and if further brcms_c_dpc() processing is required,
2595 bool brcms_c_isr(struct brcms_c_info *wlc)
2597 struct brcms_hardware *wlc_hw = wlc->hw;
2600 if (!wlc_hw->up || !wlc->macintmask)
2603 /* read and clear macintstatus and intstatus registers */
2604 macintstatus = wlc_intstatus(wlc, true);
2606 if (macintstatus == 0xffffffff) {
2607 brcms_err(wlc_hw->d11core,
2608 "DEVICEREMOVED detected in the ISR code path\n");
2612 /* it is not for us */
2613 if (macintstatus == 0)
2616 /* save interrupt status bits */
2617 wlc->macintstatus = macintstatus;
2623 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2625 struct brcms_hardware *wlc_hw = wlc->hw;
2626 struct bcma_device *core = wlc_hw->d11core;
2629 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2630 wlc_hw->band->bandunit);
2633 * Track overlapping suspend requests
2635 wlc_hw->mac_suspend_depth++;
2636 if (wlc_hw->mac_suspend_depth > 1)
2639 /* force the core awake */
2640 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2642 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2644 if (mc == 0xffffffff) {
2645 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2647 brcms_down(wlc->wl);
2650 WARN_ON(mc & MCTL_PSM_JMP_0);
2651 WARN_ON(!(mc & MCTL_PSM_RUN));
2652 WARN_ON(!(mc & MCTL_EN_MAC));
2654 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2655 if (mi == 0xffffffff) {
2656 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2658 brcms_down(wlc->wl);
2661 WARN_ON(mi & MI_MACSSPNDD);
2663 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2665 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2666 BRCMS_MAX_MAC_SUSPEND);
2668 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2669 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2670 " and MI_MACSSPNDD is still not on.\n",
2671 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2672 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2673 "psm_brc 0x%04x\n", wlc_hw->unit,
2674 bcma_read32(core, D11REGOFFS(psmdebug)),
2675 bcma_read32(core, D11REGOFFS(phydebug)),
2676 bcma_read16(core, D11REGOFFS(psm_brc)));
2679 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2680 if (mc == 0xffffffff) {
2681 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2683 brcms_down(wlc->wl);
2686 WARN_ON(mc & MCTL_PSM_JMP_0);
2687 WARN_ON(!(mc & MCTL_PSM_RUN));
2688 WARN_ON(mc & MCTL_EN_MAC);
2691 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2693 struct brcms_hardware *wlc_hw = wlc->hw;
2694 struct bcma_device *core = wlc_hw->d11core;
2697 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2698 wlc->band->bandunit);
2701 * Track overlapping suspend requests
2703 wlc_hw->mac_suspend_depth--;
2704 if (wlc_hw->mac_suspend_depth > 0)
2707 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2708 WARN_ON(mc & MCTL_PSM_JMP_0);
2709 WARN_ON(mc & MCTL_EN_MAC);
2710 WARN_ON(!(mc & MCTL_PSM_RUN));
2712 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2713 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2715 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2716 WARN_ON(mc & MCTL_PSM_JMP_0);
2717 WARN_ON(!(mc & MCTL_EN_MAC));
2718 WARN_ON(!(mc & MCTL_PSM_RUN));
2720 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2721 WARN_ON(mi & MI_MACSSPNDD);
2723 brcms_c_ucode_wake_override_clear(wlc_hw,
2724 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2727 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2729 wlc_hw->hw_stf_ss_opmode = stf_mode;
2732 brcms_upd_ofdm_pctl1_table(wlc_hw);
2735 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2737 struct bcma_device *core = wlc_hw->d11core;
2739 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2741 /* Validate dchip register access */
2743 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2744 (void)bcma_read32(core, D11REGOFFS(objaddr));
2745 w = bcma_read32(core, D11REGOFFS(objdata));
2747 /* Can we write and read back a 32bit register? */
2748 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2749 (void)bcma_read32(core, D11REGOFFS(objaddr));
2750 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2752 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753 (void)bcma_read32(core, D11REGOFFS(objaddr));
2754 val = bcma_read32(core, D11REGOFFS(objdata));
2755 if (val != (u32) 0xaa5555aa) {
2756 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2757 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2761 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2762 (void)bcma_read32(core, D11REGOFFS(objaddr));
2763 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2765 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766 (void)bcma_read32(core, D11REGOFFS(objaddr));
2767 val = bcma_read32(core, D11REGOFFS(objdata));
2768 if (val != (u32) 0x55aaaa55) {
2769 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2770 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2774 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2775 (void)bcma_read32(core, D11REGOFFS(objaddr));
2776 bcma_write32(core, D11REGOFFS(objdata), w);
2778 /* clear CFPStart */
2779 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2781 w = bcma_read32(core, D11REGOFFS(maccontrol));
2782 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2783 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2784 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2785 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2786 (MCTL_IHR_EN | MCTL_WAKE),
2787 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2794 #define PHYPLL_WAIT_US 100000
2796 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2798 struct bcma_device *core = wlc_hw->d11core;
2801 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2806 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2807 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2809 CCS_ERSRC_REQ_D11PLL |
2810 CCS_ERSRC_REQ_PHYPLL);
2811 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2812 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2815 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2816 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2817 brcms_err(core, "%s: turn on PHY PLL failed\n",
2820 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2821 tmp | CCS_ERSRC_REQ_D11PLL |
2822 CCS_ERSRC_REQ_PHYPLL);
2823 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2824 (CCS_ERSRC_AVAIL_D11PLL |
2825 CCS_ERSRC_AVAIL_PHYPLL)) !=
2826 (CCS_ERSRC_AVAIL_D11PLL |
2827 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2829 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2831 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2833 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2834 brcms_err(core, "%s: turn on PHY PLL failed\n",
2839 * Since the PLL may be shared, other cores can still
2840 * be requesting it; so we'll deassert the request but
2841 * not wait for status to comply.
2843 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2844 ~CCS_ERSRC_REQ_PHYPLL);
2845 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2849 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2853 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2855 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2860 if (wlc_hw->noreset)
2864 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2866 /* turn off analog core */
2867 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2869 /* turn off PHYPLL to save power */
2870 brcms_b_core_phypll_ctl(wlc_hw, false);
2872 wlc_hw->clk = false;
2873 bcma_core_disable(wlc_hw->d11core, 0);
2874 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2877 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2879 struct brcms_hardware *wlc_hw = wlc->hw;
2882 /* free any posted tx packets */
2883 for (i = 0; i < NFIFO; i++) {
2884 if (wlc_hw->di[i]) {
2885 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2886 if (i < TX_BCMC_FIFO)
2887 ieee80211_wake_queue(wlc->pub->ieee_hw,
2888 brcms_fifo_to_ac(i));
2892 /* free any posted rx packets */
2893 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2897 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2899 struct bcma_device *core = wlc_hw->d11core;
2900 u16 objoff = D11REGOFFS(objdata);
2902 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2903 (void)bcma_read32(core, D11REGOFFS(objaddr));
2907 return bcma_read16(core, objoff);
2911 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2914 struct bcma_device *core = wlc_hw->d11core;
2915 u16 objoff = D11REGOFFS(objdata);
2917 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2918 (void)bcma_read32(core, D11REGOFFS(objaddr));
2922 bcma_write16(core, objoff, v);
2926 * Read a single u16 from shared memory.
2927 * SHM 'offset' needs to be an even address
2929 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2931 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2935 * Write a single u16 to shared memory.
2936 * SHM 'offset' needs to be an even address
2938 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2940 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2944 * Copy a buffer to shared memory of specified type .
2945 * SHM 'offset' needs to be an even address and
2946 * Buffer length 'len' must be an even number of bytes
2947 * 'sel' selects the type of memory
2950 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2951 const void *buf, int len, u32 sel)
2954 const u8 *p = (const u8 *)buf;
2957 if (len <= 0 || (offset & 1) || (len & 1))
2960 for (i = 0; i < len; i += 2) {
2961 v = p[i] | (p[i + 1] << 8);
2962 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2967 * Copy a piece of shared memory of specified type to a buffer .
2968 * SHM 'offset' needs to be an even address and
2969 * Buffer length 'len' must be an even number of bytes
2970 * 'sel' selects the type of memory
2973 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2980 if (len <= 0 || (offset & 1) || (len & 1))
2983 for (i = 0; i < len; i += 2) {
2984 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2986 p[i + 1] = (v >> 8) & 0xFF;
2990 /* Copy a buffer to shared memory.
2991 * SHM 'offset' needs to be an even address and
2992 * Buffer length 'len' must be an even number of bytes
2994 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2995 const void *buf, int len)
2997 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3000 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3006 /* write retry limit to SCR, shouldn't need to suspend */
3008 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3009 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3010 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3011 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3012 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3013 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3014 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3015 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3019 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3022 if (mboolisset(wlc_hw->pllreq, req_bit))
3025 mboolset(wlc_hw->pllreq, req_bit);
3027 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3029 brcms_b_xtal(wlc_hw, ON);
3032 if (!mboolisset(wlc_hw->pllreq, req_bit))
3035 mboolclr(wlc_hw->pllreq, req_bit);
3037 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3039 brcms_b_xtal(wlc_hw, OFF);
3044 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3046 wlc_hw->antsel_avail = antsel_avail;
3050 * conditions under which the PM bit should be set in outgoing frames
3051 * and STAY_AWAKE is meaningful
3053 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3055 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3057 /* disallow PS when one of the following global conditions meets */
3058 if (!wlc->pub->associated)
3061 /* disallow PS when one of these meets when not scanning */
3062 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3065 if (cfg->associated) {
3067 * disallow PS when one of the following
3068 * bsscfg specific conditions meets
3079 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3082 struct macstat macstats;
3089 /* if driver down, make no sense to update stats */
3094 /* save last rx fifo 0 overflow count */
3095 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3097 /* save last tx fifo underflow count */
3098 for (i = 0; i < NFIFO; i++)
3099 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3102 /* Read mac stats from contiguous shared memory */
3103 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3104 sizeof(struct macstat), OBJADDR_SHM_SEL);
3107 /* check for rx fifo 0 overflow */
3108 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3110 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3111 wlc->pub->unit, delta);
3113 /* check for tx fifo underflows */
3114 for (i = 0; i < NFIFO; i++) {
3116 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3119 brcms_err(wlc->hw->d11core,
3120 "wl%d: %u tx fifo %d underflows!\n",
3121 wlc->pub->unit, delta, i);
3125 /* merge counters from dma module */
3126 for (i = 0; i < NFIFO; i++) {
3128 dma_counterreset(wlc->hw->di[i]);
3132 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3134 /* reset the core */
3135 if (!brcms_deviceremoved(wlc_hw->wlc))
3136 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3138 /* purge the dma rings */
3139 brcms_c_flushqueues(wlc_hw->wlc);
3142 void brcms_c_reset(struct brcms_c_info *wlc)
3144 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3146 /* slurp up hw mac counters before core reset */
3147 brcms_c_statsupd(wlc);
3149 /* reset our snapshot of macstat counters */
3150 memset((char *)wlc->core->macstat_snapshot, 0,
3151 sizeof(struct macstat));
3153 brcms_b_reset(wlc->hw);
3156 void brcms_c_init_scb(struct scb *scb)
3160 memset(scb, 0, sizeof(struct scb));
3161 scb->flags = SCB_WMECAP | SCB_HTCAP;
3162 for (i = 0; i < NUMPRIO; i++) {
3164 scb->seqctl[i] = 0xFFFF;
3167 scb->seqctl_nonqos = 0xFFFF;
3168 scb->magic = SCB_MAGIC;
3173 * download ucode/PCM
3174 * let ucode run to suspended
3175 * download ucode inits
3176 * config other core registers
3179 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3181 struct brcms_hardware *wlc_hw = wlc->hw;
3182 struct bcma_device *core = wlc_hw->d11core;
3186 bool fifosz_fixup = false;
3189 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3191 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3194 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3196 brcms_ucode_download(wlc_hw);
3198 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3200 fifosz_fixup = true;
3202 /* let the PSM run to the suspended state, set mode to BSS STA */
3203 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3204 brcms_b_mctrl(wlc_hw, ~0,
3205 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3207 /* wait for ucode to self-suspend after auto-init */
3208 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3209 MI_MACSSPNDD) == 0), 1000 * 1000);
3210 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3211 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3212 "suspend!\n", wlc_hw->unit);
3214 brcms_c_gpio_init(wlc);
3216 sflags = bcma_aread32(core, BCMA_IOST);
3218 if (D11REV_IS(wlc_hw->corerev, 23)) {
3219 if (BRCMS_ISNPHY(wlc_hw->band))
3220 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3222 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3223 " %d\n", __func__, wlc_hw->unit,
3225 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3226 if (BRCMS_ISLCNPHY(wlc_hw->band))
3227 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3229 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3230 " %d\n", __func__, wlc_hw->unit,
3233 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3234 __func__, wlc_hw->unit, wlc_hw->corerev);
3237 /* For old ucode, txfifo sizes needs to be modified(increased) */
3239 brcms_b_corerev_fifofixup(wlc_hw);
3241 /* check txfifo allocations match between ucode and driver */
3242 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3243 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3247 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3248 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3252 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3253 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3254 buf[TX_AC_BK_FIFO] &= 0xff;
3255 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3259 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3263 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3264 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3265 buf[TX_BCMC_FIFO] &= 0xff;
3266 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3270 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3275 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3276 " driver size %d index %d\n", buf[i],
3277 wlc_hw->xmtfifo_sz[i], i);
3279 /* make sure we can still talk to the mac */
3280 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3282 /* band-specific inits done by wlc_bsinit() */
3284 /* Set up frame burst size and antenna swap threshold init values */
3285 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3286 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3288 /* enable one rx interrupt per received frame */
3289 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3291 /* set the station mode (BSS STA) */
3292 brcms_b_mctrl(wlc_hw,
3293 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3294 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3296 /* set up Beacon interval */
3297 bcnint_us = 0x8000 << 10;
3298 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3299 (bcnint_us << CFPREP_CBI_SHIFT));
3300 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3301 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3303 /* write interrupt mask */
3304 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3307 /* allow the MAC to control the PHY clock (dynamic on/off) */
3308 brcms_b_macphyclk_set(wlc_hw, ON);
3310 /* program dynamic clock control fast powerup delay register */
3311 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3312 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3314 /* tell the ucode the corerev */
3315 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3317 /* tell the ucode MAC capabilities */
3318 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3319 (u16) (wlc_hw->machwcap & 0xffff));
3320 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3322 machwcap >> 16) & 0xffff));
3324 /* write retry limits to SCR, this done after PSM init */
3325 bcma_write32(core, D11REGOFFS(objaddr),
3326 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3327 (void)bcma_read32(core, D11REGOFFS(objaddr));
3328 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3329 bcma_write32(core, D11REGOFFS(objaddr),
3330 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3331 (void)bcma_read32(core, D11REGOFFS(objaddr));
3332 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3334 /* write rate fallback retry limits */
3335 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3336 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3338 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3339 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3341 /* init the tx dma engines */
3342 for (i = 0; i < NFIFO; i++) {
3344 dma_txinit(wlc_hw->di[i]);
3347 /* init the rx dma engine(s) and post receive buffers */
3348 dma_rxinit(wlc_hw->di[RX_FIFO]);
3349 dma_rxfill(wlc_hw->di[RX_FIFO]);
3353 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3356 struct brcms_c_info *wlc = wlc_hw->wlc;
3358 /* request FAST clock if not on */
3359 fastclk = wlc_hw->forcefastclk;
3361 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3363 /* disable interrupts */
3364 macintmask = brcms_intrsoff(wlc->wl);
3366 /* set up the specified band and chanspec */
3367 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3368 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3370 /* do one-time phy inits and calibration */
3371 wlc_phy_cal_init(wlc_hw->band->pi);
3373 /* core-specific initialization */
3374 brcms_b_coreinit(wlc);
3376 /* band-specific inits */
3377 brcms_b_bsinit(wlc, chanspec);
3379 /* restore macintmask */
3380 brcms_intrsrestore(wlc->wl, macintmask);
3382 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3383 * is suspended and brcms_c_enable_mac() will clear this override bit.
3385 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3388 * initialize mac_suspend_depth to 1 to match ucode
3389 * initial suspended state
3391 wlc_hw->mac_suspend_depth = 1;
3393 /* restore the clk */
3395 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3398 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3401 /* Save our copy of the chanspec */
3402 wlc->chanspec = chanspec;
3404 /* Set the chanspec and power limits for this locale */
3405 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3407 if (wlc->stf->ss_algosel_auto)
3408 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3411 brcms_c_stf_ss_update(wlc, wlc->band);
3415 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3417 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3418 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3419 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3420 brcms_chspec_bw(wlc->default_bss->chanspec),
3421 wlc->stf->txstreams);
3424 /* derive wlc->band->basic_rate[] table from 'rateset' */
3425 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3426 struct brcms_c_rateset *rateset)
3432 u8 *br = wlc->band->basic_rate;
3435 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3436 memset(br, 0, BRCM_MAXRATE + 1);
3438 /* For each basic rate in the rates list, make an entry in the
3439 * best basic lookup.
3441 for (i = 0; i < rateset->count; i++) {
3442 /* only make an entry for a basic rate */
3443 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3446 /* mask off basic bit */
3447 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3449 if (rate > BRCM_MAXRATE) {
3450 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3451 "invalid rate 0x%X in rate set\n",
3459 /* The rate lookup table now has non-zero entries for each
3460 * basic rate, equal to the basic rate: br[basicN] = basicN
3462 * To look up the best basic rate corresponding to any
3463 * particular rate, code can use the basic_rate table
3466 * basic_rate = wlc->band->basic_rate[tx_rate]
3468 * Make sure there is a best basic rate entry for
3469 * every rate by walking up the table from low rates
3470 * to high, filling in holes in the lookup table
3473 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3474 rate = wlc->band->hw_rateset.rates[i];
3476 if (br[rate] != 0) {
3477 /* This rate is a basic rate.
3478 * Keep track of the best basic rate so far by
3481 if (is_ofdm_rate(rate))
3489 /* This rate is not a basic rate so figure out the
3490 * best basic rate less than this rate and fill in
3491 * the hole in the table
3494 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3499 if (is_ofdm_rate(rate)) {
3501 * In 11g and 11a, the OFDM mandatory rates
3502 * are 6, 12, and 24 Mbps
3504 if (rate >= BRCM_RATE_24M)
3505 mandatory = BRCM_RATE_24M;
3506 else if (rate >= BRCM_RATE_12M)
3507 mandatory = BRCM_RATE_12M;
3509 mandatory = BRCM_RATE_6M;
3511 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3515 br[rate] = mandatory;
3519 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3522 struct brcms_c_rateset default_rateset;
3524 uint i, band_order[2];
3527 * We might have been bandlocked during down and the chip
3528 * power-cycled (hibernate). Figure out the right band to park on
3530 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3531 /* updated in brcms_c_bandlock() */
3532 parkband = wlc->band->bandunit;
3533 band_order[0] = band_order[1] = parkband;
3535 /* park on the band of the specified chanspec */
3536 parkband = chspec_bandunit(chanspec);
3538 /* order so that parkband initialize last */
3539 band_order[0] = parkband ^ 1;
3540 band_order[1] = parkband;
3543 /* make each band operational, software state init */
3544 for (i = 0; i < wlc->pub->_nbands; i++) {
3545 uint j = band_order[i];
3547 wlc->band = wlc->bandstate[j];
3549 brcms_default_rateset(wlc, &default_rateset);
3551 /* fill in hw_rate */
3552 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3553 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3554 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3556 /* init basic rate lookup */
3557 brcms_c_rate_lookup_init(wlc, &default_rateset);
3560 /* sync up phy/radio chanspec */
3561 brcms_c_set_phy_chanspec(wlc, chanspec);
3565 * Set or clear filtering related maccontrol bits based on
3566 * specified filter flags
3568 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3570 u32 promisc_bits = 0;
3572 wlc->filter_flags = filter_flags;
3574 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3575 promisc_bits |= MCTL_PROMISC;
3577 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3578 promisc_bits |= MCTL_BCNS_PROMISC;
3580 if (filter_flags & FIF_FCSFAIL)
3581 promisc_bits |= MCTL_KEEPBADFCS;
3583 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3584 promisc_bits |= MCTL_KEEPCONTROL;
3586 brcms_b_mctrl(wlc->hw,
3587 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3588 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3593 * ucode, hwmac update
3594 * Channel dependent updates for ucode and hw
3596 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3598 /* enable or disable any active IBSSs depending on whether or not
3599 * we are on the home channel
3601 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3602 if (wlc->pub->associated) {
3604 * BMAC_NOTE: This is something that should be fixed
3605 * in ucode inits. I think that the ucode inits set
3606 * up the bcn templates and shm values with a bogus
3607 * beacon. This should not be done in the inits. If
3608 * ucode needs to set up a beacon for testing, the
3609 * test routines should write it down, not expect the
3610 * inits to populate a bogus beacon.
3612 if (BRCMS_PHY_11N_CAP(wlc->band))
3613 brcms_b_write_shm(wlc->hw,
3614 M_BCN_TXTSF_OFFSET, 0);
3617 /* disable an active IBSS if we are not on the home channel */
3621 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3625 u8 basic_phy_rate, basic_index;
3626 u16 dir_table, basic_table;
3629 /* Shared memory address for the table we are reading */
3630 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3632 /* Shared memory address for the table we are writing */
3633 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3636 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3637 * the index into the rate table.
3639 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3640 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3641 index = phy_rate & 0xf;
3642 basic_index = basic_phy_rate & 0xf;
3644 /* Find the SHM pointer to the ACK rate entry by looking in the
3647 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3649 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3650 * to the correct basic rate for the given incoming rate
3652 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3655 static const struct brcms_c_rateset *
3656 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3658 const struct brcms_c_rateset *rs_dflt;
3660 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3661 if (wlc->band->bandtype == BRCM_BAND_5G)
3662 rs_dflt = &ofdm_mimo_rates;
3664 rs_dflt = &cck_ofdm_mimo_rates;
3665 } else if (wlc->band->gmode)
3666 rs_dflt = &cck_ofdm_rates;
3668 rs_dflt = &cck_rates;
3673 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3675 const struct brcms_c_rateset *rs_dflt;
3676 struct brcms_c_rateset rs;
3677 u8 rate, basic_rate;
3680 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3682 brcms_c_rateset_copy(rs_dflt, &rs);
3683 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3685 /* walk the phy rate table and update SHM basic rate lookup table */
3686 for (i = 0; i < rs.count; i++) {
3687 rate = rs.rates[i] & BRCMS_RATE_MASK;
3689 /* for a given rate brcms_basic_rate returns the rate at
3690 * which a response ACK/CTS should be sent.
3692 basic_rate = brcms_basic_rate(wlc, rate);
3693 if (basic_rate == 0)
3694 /* This should only happen if we are using a
3695 * restricted rateset.
3697 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3699 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3703 /* band-specific init */
3704 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3706 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3707 wlc->pub->unit, wlc->band->bandunit);
3709 /* write ucode ACK/CTS rate table */
3710 brcms_c_set_ratetable(wlc);
3712 /* update some band specific mac configuration */
3713 brcms_c_ucode_mac_upd(wlc);
3715 /* init antenna selection */
3716 brcms_c_antsel_init(wlc->asi);
3720 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3722 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3725 int idle_busy_ratio_x_16 = 0;
3727 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3728 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3729 if (duty_cycle > 100 || duty_cycle < 0) {
3730 brcms_err(wlc->hw->d11core,
3731 "wl%d: duty cycle value off limit\n",
3736 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3737 /* Only write to shared memory when wl is up */
3739 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3742 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3744 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3749 /* push sw hps and wake state through hardware */
3750 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3756 hps = brcms_c_ps_allowed(wlc);
3758 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3761 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3766 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3768 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3771 brcms_b_wait_for_wake(wlc->hw);
3775 * Write this BSS config's MAC address to core.
3776 * Updates RXE match engine.
3778 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3781 struct brcms_c_info *wlc = bsscfg->wlc;
3783 /* enter the MAC addr into the RXE match registers */
3784 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3786 brcms_c_ampdu_macaddr_upd(wlc);
3791 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3792 * Updates RXE match engine.
3794 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3796 /* we need to update BSSID in RXE match registers */
3797 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3800 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3802 wlc_hw->shortslot = shortslot;
3804 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3805 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3806 brcms_b_update_slot_timing(wlc_hw, shortslot);
3807 brcms_c_enable_mac(wlc_hw->wlc);
3812 * Suspend the the MAC and update the slot timing
3813 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3815 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3817 /* use the override if it is set */
3818 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3819 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3821 if (wlc->shortslot == shortslot)
3824 wlc->shortslot = shortslot;
3826 brcms_b_set_shortslot(wlc->hw, shortslot);
3829 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3831 if (wlc->home_chanspec != chanspec) {
3832 wlc->home_chanspec = chanspec;
3834 if (wlc->bsscfg->associated)
3835 wlc->bsscfg->current_bss->chanspec = chanspec;
3840 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3841 bool mute_tx, struct txpwr_limits *txpwr)
3845 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3848 wlc_hw->chanspec = chanspec;
3850 /* Switch bands if necessary */
3851 if (wlc_hw->_nbands > 1) {
3852 bandunit = chspec_bandunit(chanspec);
3853 if (wlc_hw->band->bandunit != bandunit) {
3854 /* brcms_b_setband disables other bandunit,
3855 * use light band switch if not up yet
3858 wlc_phy_chanspec_radio_set(wlc_hw->
3859 bandstate[bandunit]->
3861 brcms_b_setband(wlc_hw, bandunit, chanspec);
3863 brcms_c_setxband(wlc_hw, bandunit);
3868 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3872 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3874 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3876 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3877 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3879 /* Update muting of the channel */
3880 brcms_b_mute(wlc_hw, mute_tx);
3884 /* switch to and initialize new band */
3885 static void brcms_c_setband(struct brcms_c_info *wlc,
3888 wlc->band = wlc->bandstate[bandunit];
3893 /* wait for at least one beacon before entering sleeping state */
3894 brcms_c_set_ps_ctrl(wlc);
3896 /* band-specific initializations */
3897 brcms_c_bsinit(wlc);
3900 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3903 bool switchband = false;
3904 u16 old_chanspec = wlc->chanspec;
3906 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3907 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3908 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3912 /* Switch bands if necessary */
3913 if (wlc->pub->_nbands > 1) {
3914 bandunit = chspec_bandunit(chanspec);
3915 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3917 if (wlc->bandlocked) {
3918 brcms_err(wlc->hw->d11core,
3919 "wl%d: %s: chspec %d band is locked!\n",
3920 wlc->pub->unit, __func__,
3921 CHSPEC_CHANNEL(chanspec));
3925 * should the setband call come after the
3926 * brcms_b_chanspec() ? if the setband updates
3927 * (brcms_c_bsinit) use low level calls to inspect and
3928 * set state, the state inspected may be from the wrong
3929 * band, or the following brcms_b_set_chanspec() may
3932 brcms_c_setband(wlc, bandunit);
3936 /* sync up phy/radio chanspec */
3937 brcms_c_set_phy_chanspec(wlc, chanspec);
3939 /* init antenna selection */
3940 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3941 brcms_c_antsel_init(wlc->asi);
3943 /* Fix the hardware rateset based on bw.
3944 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3946 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3947 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3950 /* update some mac configuration since chanspec changed */
3951 brcms_c_ucode_mac_upd(wlc);
3955 * This function changes the phytxctl for beacon based on current
3956 * beacon ratespec AND txant setting as per this table:
3957 * ratespec CCK ant = wlc->stf->txant
3960 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3964 u16 phytxant = wlc->stf->phytxant;
3965 u16 mask = PHY_TXC_ANT_MASK;
3967 /* for non-siso rates or default setting, use the available chains */
3968 if (BRCMS_PHY_11N_CAP(wlc->band))
3969 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3971 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3972 phyctl = (phyctl & ~mask) | phytxant;
3973 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3977 * centralized protection config change function to simplify debugging, no
3978 * consistency checking this should be called only on changes to avoid overhead
3979 * in periodic function
3981 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3984 * Cannot use brcms_dbg_* here because this function is called
3985 * before wlc is sufficiently initialized.
3987 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3990 case BRCMS_PROT_G_SPEC:
3991 wlc->protection->_g = (bool) val;
3993 case BRCMS_PROT_G_OVR:
3994 wlc->protection->g_override = (s8) val;
3996 case BRCMS_PROT_G_USER:
3997 wlc->protection->gmode_user = (u8) val;
3999 case BRCMS_PROT_OVERLAP:
4000 wlc->protection->overlap = (s8) val;
4002 case BRCMS_PROT_N_USER:
4003 wlc->protection->nmode_user = (s8) val;
4005 case BRCMS_PROT_N_CFG:
4006 wlc->protection->n_cfg = (s8) val;
4008 case BRCMS_PROT_N_CFG_OVR:
4009 wlc->protection->n_cfg_override = (s8) val;
4011 case BRCMS_PROT_N_NONGF:
4012 wlc->protection->nongf = (bool) val;
4014 case BRCMS_PROT_N_NONGF_OVR:
4015 wlc->protection->nongf_override = (s8) val;
4017 case BRCMS_PROT_N_PAM_OVR:
4018 wlc->protection->n_pam_override = (s8) val;
4020 case BRCMS_PROT_N_OBSS:
4021 wlc->protection->n_obss = (bool) val;
4030 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4033 brcms_c_update_beacon(wlc);
4034 brcms_c_update_probe_resp(wlc, true);
4038 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4040 wlc->stf->ldpc = val;
4043 brcms_c_update_beacon(wlc);
4044 brcms_c_update_probe_resp(wlc, true);
4045 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4049 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4050 const struct ieee80211_tx_queue_params *params,
4054 struct shm_acparams acp_shm;
4057 /* Only apply params if the core is out of reset and has clocks */
4059 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4060 wlc->pub->unit, __func__);
4064 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4065 /* fill in shm ac params struct */
4066 acp_shm.txop = params->txop;
4067 /* convert from units of 32us to us for ucode */
4068 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4069 EDCF_TXOP2USEC(acp_shm.txop);
4070 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4072 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4073 && acp_shm.aifs < EDCF_AIFSN_MAX)
4076 if (acp_shm.aifs < EDCF_AIFSN_MIN
4077 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4078 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4079 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4081 acp_shm.cwmin = params->cw_min;
4082 acp_shm.cwmax = params->cw_max;
4083 acp_shm.cwcur = acp_shm.cwmin;
4085 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4087 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4088 /* Indicate the new params to the ucode */
4089 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4092 M_EDCF_STATUS_OFF));
4093 acp_shm.status |= WME_STATUS_NEWAC;
4095 /* Fill in shm acparam table */
4096 shm_entry = (u16 *) &acp_shm;
4097 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4098 brcms_b_write_shm(wlc->hw,
4100 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4105 brcms_c_suspend_mac_and_wait(wlc);
4106 brcms_c_enable_mac(wlc);
4110 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4114 struct ieee80211_tx_queue_params txq_pars;
4115 static const struct edcf_acparam default_edcf_acparams[] = {
4116 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4117 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4118 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4119 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4120 }; /* ucode needs these parameters during its initialization */
4121 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4123 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4124 /* find out which ac this set of params applies to */
4125 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4127 /* fill in shm ac params struct */
4128 txq_pars.txop = edcf_acp->TXOP;
4129 txq_pars.aifs = edcf_acp->ACI;
4131 /* CWmin = 2^(ECWmin) - 1 */
4132 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4133 /* CWmax = 2^(ECWmax) - 1 */
4134 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4135 >> EDCF_ECWMAX_SHIFT);
4136 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4140 brcms_c_suspend_mac_and_wait(wlc);
4141 brcms_c_enable_mac(wlc);
4145 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4147 /* Don't start the timer if HWRADIO feature is disabled */
4148 if (wlc->radio_monitor)
4151 wlc->radio_monitor = true;
4152 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4153 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4156 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4158 if (!wlc->radio_monitor)
4161 wlc->radio_monitor = false;
4162 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4163 return brcms_del_timer(wlc->radio_timer);
4166 /* read hwdisable state and propagate to wlc flag */
4167 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4169 if (wlc->pub->hw_off)
4172 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4173 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4175 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4178 /* update hwradio status and return it */
4179 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4181 brcms_c_radio_hwdisable_upd(wlc);
4183 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4187 /* periodical query hw radio button while driver is "down" */
4188 static void brcms_c_radio_timer(void *arg)
4190 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4192 if (brcms_deviceremoved(wlc)) {
4193 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4194 wlc->pub->unit, __func__);
4195 brcms_down(wlc->wl);
4199 brcms_c_radio_hwdisable_upd(wlc);
4202 /* common low-level watchdog code */
4203 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4205 struct brcms_hardware *wlc_hw = wlc->hw;
4210 /* increment second count */
4213 /* Check for FIFO error interrupts */
4214 brcms_b_fifoerrors(wlc_hw);
4216 /* make sure RX dma has buffers */
4217 dma_rxfill(wlc->hw->di[RX_FIFO]);
4219 wlc_phy_watchdog(wlc_hw->band->pi);
4222 /* common watchdog code */
4223 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4225 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4230 if (brcms_deviceremoved(wlc)) {
4231 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4232 wlc->pub->unit, __func__);
4233 brcms_down(wlc->wl);
4237 /* increment second count */
4240 brcms_c_radio_hwdisable_upd(wlc);
4241 /* if radio is disable, driver may be down, quit here */
4242 if (wlc->pub->radio_disabled)
4245 brcms_b_watchdog(wlc);
4248 * occasionally sample mac stat counters to
4249 * detect 16-bit counter wrap
4251 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4252 brcms_c_statsupd(wlc);
4254 if (BRCMS_ISNPHY(wlc->band) &&
4255 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4256 BRCMS_TEMPSENSE_PERIOD)) {
4257 wlc->tempsense_lasttime = wlc->pub->now;
4258 brcms_c_tempsense_upd(wlc);
4262 static void brcms_c_watchdog_by_timer(void *arg)
4264 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4266 brcms_c_watchdog(wlc);
4269 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4271 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4273 if (!wlc->wdtimer) {
4274 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4279 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4281 if (!wlc->radio_timer) {
4282 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4294 * Initialize brcms_c_info default values ...
4295 * may get overrides later in this function
4297 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4301 /* Save our copy of the chanspec */
4302 wlc->chanspec = ch20mhz_chspec(1);
4304 /* various 802.11g modes */
4305 wlc->shortslot = false;
4306 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4308 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4309 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4311 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4312 BRCMS_PROTECTION_AUTO);
4313 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4314 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4315 BRCMS_PROTECTION_AUTO);
4316 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4317 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4319 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4320 BRCMS_PROTECTION_CTL_OVERLAP);
4322 /* 802.11g draft 4.0 NonERP elt advertisement */
4323 wlc->include_legacy_erp = true;
4325 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4326 wlc->stf->txant = ANT_TX_DEF;
4328 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4330 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4331 for (i = 0; i < NFIFO; i++)
4332 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4333 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4335 /* default rate fallback retry limits */
4336 wlc->SFBL = RETRY_SHORT_FB;
4337 wlc->LFBL = RETRY_LONG_FB;
4339 /* default mac retry limits */
4340 wlc->SRL = RETRY_SHORT_DEF;
4341 wlc->LRL = RETRY_LONG_DEF;
4343 /* WME QoS mode is Auto by default */
4344 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4345 wlc->pub->bcmerror = 0;
4348 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4352 unit = wlc->pub->unit;
4354 wlc->asi = brcms_c_antsel_attach(wlc);
4355 if (wlc->asi == NULL) {
4356 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4362 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4363 if (wlc->ampdu == NULL) {
4364 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4370 if ((brcms_c_stf_attach(wlc) != 0)) {
4371 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4380 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4386 * run backplane attach, init nvram
4388 * initialize software state for each core and band
4389 * put the whole chip in reset(driver down state), no clock
4391 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4392 uint unit, bool piomode)
4394 struct brcms_hardware *wlc_hw;
4398 struct shared_phy_params sha_params;
4399 struct wiphy *wiphy = wlc->wiphy;
4400 struct pci_dev *pcidev = core->bus->host_pci;
4401 struct ssb_sprom *sprom = &core->bus->sprom;
4403 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4404 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4408 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4409 core->bus->boardinfo.vendor,
4410 core->bus->boardinfo.type);
4416 wlc_hw->unit = unit;
4417 wlc_hw->band = wlc_hw->bandstate[0];
4418 wlc_hw->_piomode = piomode;
4420 /* populate struct brcms_hardware with default values */
4421 brcms_b_info_init(wlc_hw);
4424 * Do the hardware portion of the attach. Also initialize software
4425 * state that depends on the particular hardware we are running.
4427 wlc_hw->sih = ai_attach(core->bus);
4428 if (wlc_hw->sih == NULL) {
4429 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4435 /* verify again the device is supported */
4436 if (!brcms_c_chipmatch(core)) {
4437 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4443 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4444 wlc_hw->vendorid = pcidev->vendor;
4445 wlc_hw->deviceid = pcidev->device;
4447 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4448 wlc_hw->deviceid = core->bus->boardinfo.type;
4451 wlc_hw->d11core = core;
4452 wlc_hw->corerev = core->id.rev;
4454 /* validate chip, chiprev and corerev */
4455 if (!brcms_c_isgoodchip(wlc_hw)) {
4460 /* initialize power control registers */
4461 ai_clkctl_init(wlc_hw->sih);
4463 /* request fastclock and force fastclock for the rest of attach
4464 * bring the d11 core out of reset.
4465 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4466 * is still false; But it will be called again inside wlc_corereset,
4467 * after d11 is out of reset.
4469 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4470 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4472 if (!brcms_b_validate_chip_access(wlc_hw)) {
4473 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4479 /* get the board rev, used just below */
4480 j = sprom->board_rev;
4481 /* promote srom boardrev of 0xFF to 1 */
4482 if (j == BOARDREV_PROMOTABLE)
4483 j = BOARDREV_PROMOTED;
4484 wlc_hw->boardrev = (u16) j;
4485 if (!brcms_c_validboardtype(wlc_hw)) {
4486 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4487 "board type (0x%x)" " or revision level (0x%x)\n",
4488 unit, ai_get_boardtype(wlc_hw->sih),
4493 wlc_hw->sromrev = sprom->revision;
4494 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4495 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4497 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4498 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4500 /* check device id(srom, nvram etc.) to set bands */
4501 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4502 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4503 /* Dualband boards */
4504 wlc_hw->_nbands = 2;
4506 wlc_hw->_nbands = 1;
4508 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4509 wlc_hw->_nbands = 1;
4511 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4512 * unconditionally does the init of these values
4514 wlc->vendorid = wlc_hw->vendorid;
4515 wlc->deviceid = wlc_hw->deviceid;
4516 wlc->pub->sih = wlc_hw->sih;
4517 wlc->pub->corerev = wlc_hw->corerev;
4518 wlc->pub->sromrev = wlc_hw->sromrev;
4519 wlc->pub->boardrev = wlc_hw->boardrev;
4520 wlc->pub->boardflags = wlc_hw->boardflags;
4521 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4522 wlc->pub->_nbands = wlc_hw->_nbands;
4524 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4526 if (wlc_hw->physhim == NULL) {
4527 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4533 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4534 sha_params.sih = wlc_hw->sih;
4535 sha_params.physhim = wlc_hw->physhim;
4536 sha_params.unit = unit;
4537 sha_params.corerev = wlc_hw->corerev;
4538 sha_params.vid = wlc_hw->vendorid;
4539 sha_params.did = wlc_hw->deviceid;
4540 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4541 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4542 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4543 sha_params.sromrev = wlc_hw->sromrev;
4544 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4545 sha_params.boardrev = wlc_hw->boardrev;
4546 sha_params.boardflags = wlc_hw->boardflags;
4547 sha_params.boardflags2 = wlc_hw->boardflags2;
4549 /* alloc and save pointer to shared phy state area */
4550 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4551 if (!wlc_hw->phy_sh) {
4556 /* initialize software state for each core and band */
4557 for (j = 0; j < wlc_hw->_nbands; j++) {
4559 * band0 is always 2.4Ghz
4560 * band1, if present, is 5Ghz
4563 brcms_c_setxband(wlc_hw, j);
4565 wlc_hw->band->bandunit = j;
4566 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4567 wlc->band->bandunit = j;
4568 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4569 wlc->core->coreidx = core->core_index;
4571 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4572 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4574 /* init tx fifo size */
4575 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4576 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4577 ARRAY_SIZE(xmtfifo_sz));
4578 wlc_hw->xmtfifo_sz =
4579 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4580 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4582 /* Get a phy for this band */
4584 wlc_phy_attach(wlc_hw->phy_sh, core,
4585 wlc_hw->band->bandtype,
4587 if (wlc_hw->band->pi == NULL) {
4588 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4589 "attach failed\n", unit);
4594 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4596 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4597 &wlc_hw->band->phyrev,
4598 &wlc_hw->band->radioid,
4599 &wlc_hw->band->radiorev);
4600 wlc_hw->band->abgphy_encore =
4601 wlc_phy_get_encore(wlc_hw->band->pi);
4602 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4603 wlc_hw->band->core_flags =
4604 wlc_phy_get_coreflags(wlc_hw->band->pi);
4606 /* verify good phy_type & supported phy revision */
4607 if (BRCMS_ISNPHY(wlc_hw->band)) {
4608 if (NCONF_HAS(wlc_hw->band->phyrev))
4612 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4613 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4619 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4620 "phy type/rev (%d/%d)\n", unit,
4621 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4628 * BMAC_NOTE: wlc->band->pi should not be set below and should
4629 * be done in the high level attach. However we can not make
4630 * that change until all low level access is changed to
4631 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4632 * keeping wlc_hw->band->pi as well for incremental update of
4633 * low level fns, and cut over low only init when all fns
4636 wlc->band->pi = wlc_hw->band->pi;
4637 wlc->band->phytype = wlc_hw->band->phytype;
4638 wlc->band->phyrev = wlc_hw->band->phyrev;
4639 wlc->band->radioid = wlc_hw->band->radioid;
4640 wlc->band->radiorev = wlc_hw->band->radiorev;
4642 /* default contention windows size limits */
4643 wlc_hw->band->CWmin = APHY_CWMIN;
4644 wlc_hw->band->CWmax = PHY_CWMAX;
4646 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4652 /* disable core to match driver "down" state */
4653 brcms_c_coredisable(wlc_hw);
4655 /* Match driver "down" state */
4656 ai_pci_down(wlc_hw->sih);
4658 /* turn off pll and xtal to match driver "down" state */
4659 brcms_b_xtal(wlc_hw, OFF);
4661 /* *******************************************************************
4662 * The hardware is in the DOWN state at this point. D11 core
4663 * or cores are in reset with clocks off, and the board PLLs
4664 * are off if possible.
4666 * Beyond this point, wlc->sbclk == false and chip registers
4667 * should not be touched.
4668 *********************************************************************
4671 /* init etheraddr state variables */
4672 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4674 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4675 is_zero_ether_addr(wlc_hw->etheraddr)) {
4676 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4682 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4683 wlc_hw->deviceid, wlc_hw->_nbands,
4684 ai_get_boardtype(wlc_hw->sih));
4689 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4694 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4697 unit = wlc->pub->unit;
4699 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4700 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4701 wlc->band->antgain = 8;
4702 } else if (wlc->band->antgain == -1) {
4703 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4704 " srom, using 2dB\n", unit, __func__);
4705 wlc->band->antgain = 8;
4708 /* Older sroms specified gain in whole dbm only. In order
4709 * be able to specify qdbm granularity and remain backward
4710 * compatible the whole dbms are now encoded in only
4711 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4712 * 6 bit signed number ranges from -32 - 31.
4716 * 0xc1 = 1.75 db (1 + 3 quarters),
4717 * 0x3f = -1 (-1 + 0 quarters),
4718 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4719 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4721 gain = wlc->band->antgain & 0x3f;
4722 gain <<= 2; /* Sign extend */
4724 fract = (wlc->band->antgain & 0xc0) >> 6;
4725 wlc->band->antgain = 4 * gain + fract;
4729 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4734 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4736 unit = wlc->pub->unit;
4737 bandtype = wlc->band->bandtype;
4739 /* get antennas available */
4740 if (bandtype == BRCM_BAND_5G)
4741 aa = sprom->ant_available_a;
4743 aa = sprom->ant_available_bg;
4745 if ((aa < 1) || (aa > 15)) {
4746 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4747 " srom (0x%x), using 3\n", unit, __func__, aa);
4751 /* reset the defaults if we have a single antenna */
4753 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4754 wlc->stf->txant = ANT_TX_FORCE_0;
4755 } else if (aa == 2) {
4756 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4757 wlc->stf->txant = ANT_TX_FORCE_1;
4761 /* Compute Antenna Gain */
4762 if (bandtype == BRCM_BAND_5G)
4763 wlc->band->antgain = sprom->antenna_gain.a1;
4765 wlc->band->antgain = sprom->antenna_gain.a0;
4767 brcms_c_attach_antgain_init(wlc);
4772 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4775 struct brcms_band *band;
4776 struct brcms_bss_info *bi = wlc->default_bss;
4778 /* init default and target BSS with some sane initial values */
4779 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4780 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4782 /* fill the default channel as the first valid channel
4783 * starting from the 2G channels
4785 chanspec = ch20mhz_chspec(1);
4786 wlc->home_chanspec = bi->chanspec = chanspec;
4788 /* find the band of our default channel */
4790 if (wlc->pub->_nbands > 1 &&
4791 band->bandunit != chspec_bandunit(chanspec))
4792 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4794 /* init bss rates to the band specific default rate set */
4795 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4796 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4797 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4798 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4800 if (wlc->pub->_n_enab & SUPPORT_11N)
4801 bi->flags |= BRCMS_BSS_HT;
4804 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4807 struct brcms_band *band;
4809 for (i = 0; i < wlc->pub->_nbands; i++) {
4810 band = wlc->bandstate[i];
4811 if (band->bandtype == BRCM_BAND_5G) {
4812 if ((bwcap == BRCMS_N_BW_40ALL)
4813 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4814 band->mimo_cap_40 = true;
4816 band->mimo_cap_40 = false;
4818 if (bwcap == BRCMS_N_BW_40ALL)
4819 band->mimo_cap_40 = true;
4821 band->mimo_cap_40 = false;
4826 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4828 /* free timer state */
4830 brcms_free_timer(wlc->wdtimer);
4831 wlc->wdtimer = NULL;
4833 if (wlc->radio_timer) {
4834 brcms_free_timer(wlc->radio_timer);
4835 wlc->radio_timer = NULL;
4839 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4842 brcms_c_antsel_detach(wlc->asi);
4847 brcms_c_ampdu_detach(wlc->ampdu);
4851 brcms_c_stf_detach(wlc);
4857 static int brcms_b_detach(struct brcms_c_info *wlc)
4860 struct brcms_hw_band *band;
4861 struct brcms_hardware *wlc_hw = wlc->hw;
4866 brcms_b_detach_dmapio(wlc_hw);
4868 band = wlc_hw->band;
4869 for (i = 0; i < wlc_hw->_nbands; i++) {
4871 /* Detach this band's phy */
4872 wlc_phy_detach(band->pi);
4875 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4878 /* Free shared phy state */
4879 kfree(wlc_hw->phy_sh);
4881 wlc_phy_shim_detach(wlc_hw->physhim);
4884 ai_detach(wlc_hw->sih);
4893 * Return a count of the number of driver callbacks still pending.
4895 * General policy is that brcms_c_detach can only dealloc/free software states.
4896 * It can NOT touch hardware registers since the d11core may be in reset and
4897 * clock may not be available.
4898 * One exception is sb register access, which is possible if crystal is turned
4899 * on after "down" state, driver should avoid software timer with the exception
4902 uint brcms_c_detach(struct brcms_c_info *wlc)
4909 callbacks += brcms_b_detach(wlc);
4911 /* delete software timers */
4912 if (!brcms_c_radio_monitor_stop(wlc))
4915 brcms_c_channel_mgr_detach(wlc->cmi);
4917 brcms_c_timers_deinit(wlc);
4919 brcms_c_detach_module(wlc);
4921 brcms_c_detach_mfree(wlc);
4925 /* update state that depends on the current value of "ap" */
4926 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4928 /* STA-BSS; short capable */
4929 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4932 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4933 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4935 if (wlc_hw->wlc->pub->hw_up)
4938 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4941 * Enable pll and xtal, initialize the power control registers,
4942 * and force fastclock for the remainder of brcms_c_up().
4944 brcms_b_xtal(wlc_hw, ON);
4945 ai_clkctl_init(wlc_hw->sih);
4946 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4949 * TODO: test suspend/resume
4951 * AI chip doesn't restore bar0win2 on
4952 * hibernation/resume, need sw fixup
4956 * Inform phy that a POR reset has occurred so
4957 * it does a complete phy init
4959 wlc_phy_por_inform(wlc_hw->band->pi);
4961 wlc_hw->ucode_loaded = false;
4962 wlc_hw->wlc->pub->hw_up = true;
4964 if ((wlc_hw->boardflags & BFL_FEM)
4965 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4967 (wlc_hw->boardrev >= 0x1250
4968 && (wlc_hw->boardflags & BFL_FEM_BT)))
4969 ai_epa_4313war(wlc_hw->sih);
4973 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4975 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4978 * Enable pll and xtal, initialize the power control registers,
4979 * and force fastclock for the remainder of brcms_c_up().
4981 brcms_b_xtal(wlc_hw, ON);
4982 ai_clkctl_init(wlc_hw->sih);
4983 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4986 * Configure pci/pcmcia here instead of in brcms_c_attach()
4987 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
4989 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4993 * Need to read the hwradio status here to cover the case where the
4994 * system is loaded with the hw radio disabled. We do not want to
4995 * bring the driver up in this case.
4997 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4998 /* put SB PCI in down state again */
4999 ai_pci_down(wlc_hw->sih);
5000 brcms_b_xtal(wlc_hw, OFF);
5004 ai_pci_up(wlc_hw->sih);
5006 /* reset the d11 core */
5007 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5012 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5015 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5017 /* FULLY enable dynamic power control and d11 core interrupt */
5018 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5019 brcms_intrson(wlc_hw->wlc->wl);
5024 * Write WME tunable parameters for retransmit/max rate
5025 * from wlc struct to ucode
5027 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5031 /* Need clock to do this */
5035 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5036 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5037 wlc->wme_retries[ac]);
5040 /* make interface operational */
5041 int brcms_c_up(struct brcms_c_info *wlc)
5043 struct ieee80211_channel *ch;
5045 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5047 /* HW is turned off so don't try to access it */
5048 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5051 if (!wlc->pub->hw_up) {
5052 brcms_b_hw_up(wlc->hw);
5053 wlc->pub->hw_up = true;
5056 if ((wlc->pub->boardflags & BFL_FEM)
5057 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5058 if (wlc->pub->boardrev >= 0x1250
5059 && (wlc->pub->boardflags & BFL_FEM_BT))
5060 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5061 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5063 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5064 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5068 * Need to read the hwradio status here to cover the case where the
5069 * system is loaded with the hw radio disabled. We do not want to bring
5070 * the driver up in this case. If radio is disabled, abort up, lower
5071 * power, start radio timer and return 0(for NDIS) don't call
5072 * radio_update to avoid looping brcms_c_up.
5074 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5076 if (!wlc->pub->radio_disabled) {
5077 int status = brcms_b_up_prep(wlc->hw);
5078 if (status == -ENOMEDIUM) {
5080 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5081 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5082 mboolset(wlc->pub->radio_disabled,
5083 WL_RADIO_HW_DISABLE);
5085 if (bsscfg->enable && bsscfg->BSS)
5086 brcms_err(wlc->hw->d11core,
5087 "wl%d: up: rfdisable -> "
5088 "bsscfg_disable()\n",
5094 if (wlc->pub->radio_disabled) {
5095 brcms_c_radio_monitor_start(wlc);
5099 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5102 brcms_c_radio_monitor_stop(wlc);
5104 /* Set EDCF hostflags */
5105 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5107 brcms_init(wlc->wl);
5108 wlc->pub->up = true;
5110 if (wlc->bandinit_pending) {
5111 ch = wlc->pub->ieee_hw->conf.channel;
5112 brcms_c_suspend_mac_and_wait(wlc);
5113 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5114 wlc->bandinit_pending = false;
5115 brcms_c_enable_mac(wlc);
5118 brcms_b_up_finish(wlc->hw);
5120 /* Program the TX wme params with the current settings */
5121 brcms_c_wme_retries_write(wlc);
5123 /* start one second watchdog timer */
5124 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5125 wlc->WDarmed = true;
5127 /* ensure antenna config is up to date */
5128 brcms_c_stf_phy_txant_upd(wlc);
5129 /* ensure LDPC config is in sync */
5130 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5135 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5142 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5150 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5152 /* disable interrupts */
5154 wlc_hw->wlc->macintmask = 0;
5156 /* now disable interrupts */
5157 brcms_intrsoff(wlc_hw->wlc->wl);
5159 /* ensure we're running on the pll clock again */
5160 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5162 /* down phy at the last of this stage */
5163 callbacks += wlc_phy_down(wlc_hw->band->pi);
5168 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5177 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5179 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5182 wlc_hw->sbclk = false;
5183 wlc_hw->clk = false;
5184 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5186 /* reclaim any posted packets */
5187 brcms_c_flushqueues(wlc_hw->wlc);
5190 /* Reset and disable the core */
5191 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5192 if (bcma_read32(wlc_hw->d11core,
5193 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5194 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5195 callbacks += brcms_reset(wlc_hw->wlc->wl);
5196 brcms_c_coredisable(wlc_hw);
5199 /* turn off primary xtal and pll */
5200 if (!wlc_hw->noreset) {
5201 ai_pci_down(wlc_hw->sih);
5202 brcms_b_xtal(wlc_hw, OFF);
5210 * Mark the interface nonoperational, stop the software mechanisms,
5211 * disable the hardware, free any transient buffer state.
5212 * Return a count of the number of driver callbacks still pending.
5214 uint brcms_c_down(struct brcms_c_info *wlc)
5219 bool dev_gone = false;
5221 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5223 /* check if we are already in the going down path */
5224 if (wlc->going_down) {
5225 brcms_err(wlc->hw->d11core,
5226 "wl%d: %s: Driver going down so return\n",
5227 wlc->pub->unit, __func__);
5233 wlc->going_down = true;
5235 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5237 dev_gone = brcms_deviceremoved(wlc);
5239 /* Call any registered down handlers */
5240 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5241 if (wlc->modulecb[i].down_fn)
5243 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5246 /* cancel the watchdog timer */
5248 if (!brcms_del_timer(wlc->wdtimer))
5250 wlc->WDarmed = false;
5252 /* cancel all other timers */
5253 callbacks += brcms_c_down_del_timer(wlc);
5255 wlc->pub->up = false;
5257 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5259 callbacks += brcms_b_down_finish(wlc->hw);
5261 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5264 wlc->going_down = false;
5268 /* Set the current gmode configuration */
5269 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5273 struct brcms_c_rateset rs;
5274 /* Default to 54g Auto */
5275 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5276 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5277 bool shortslot_restrict = false; /* Restrict association to stations
5278 * that support shortslot
5280 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5281 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5282 int preamble = BRCMS_PLCP_LONG;
5283 bool preamble_restrict = false; /* Restrict association to stations
5284 * that support short preambles
5286 struct brcms_band *band;
5288 /* if N-support is enabled, allow Gmode set as long as requested
5289 * Gmode is not GMODE_LEGACY_B
5291 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5294 /* verify that we are dealing with 2G band and grab the band pointer */
5295 if (wlc->band->bandtype == BRCM_BAND_2G)
5297 else if ((wlc->pub->_nbands > 1) &&
5298 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5299 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5303 /* update configuration value */
5305 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5307 /* Clear rateset override */
5308 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5311 case GMODE_LEGACY_B:
5312 shortslot = BRCMS_SHORTSLOT_OFF;
5313 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5321 /* Accept defaults */
5326 preamble = BRCMS_PLCP_SHORT;
5327 preamble_restrict = true;
5330 case GMODE_PERFORMANCE:
5331 shortslot = BRCMS_SHORTSLOT_ON;
5332 shortslot_restrict = true;
5334 preamble = BRCMS_PLCP_SHORT;
5335 preamble_restrict = true;
5340 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5341 wlc->pub->unit, __func__, gmode);
5345 band->gmode = gmode;
5347 wlc->shortslot_override = shortslot;
5349 /* Use the default 11g rateset */
5351 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5354 for (i = 0; i < rs.count; i++) {
5355 if (rs.rates[i] == BRCM_RATE_6M
5356 || rs.rates[i] == BRCM_RATE_12M
5357 || rs.rates[i] == BRCM_RATE_24M)
5358 rs.rates[i] |= BRCMS_RATE_FLAG;
5362 /* Set default bss rateset */
5363 wlc->default_bss->rateset.count = rs.count;
5364 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5365 sizeof(wlc->default_bss->rateset.rates));
5370 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5375 if (wlc->stf->txstreams == WL_11N_3x3)
5380 /* force GMODE_AUTO if NMODE is ON */
5381 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5382 if (nmode == WL_11N_3x3)
5383 wlc->pub->_n_enab = SUPPORT_HT;
5385 wlc->pub->_n_enab = SUPPORT_11N;
5386 wlc->default_bss->flags |= BRCMS_BSS_HT;
5387 /* add the mcs rates to the default and hw ratesets */
5388 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5389 wlc->stf->txstreams);
5390 for (i = 0; i < wlc->pub->_nbands; i++)
5391 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5392 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5398 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5399 struct brcms_c_rateset *rs_arg)
5401 struct brcms_c_rateset rs, new;
5404 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5406 /* check for bad count value */
5407 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5410 /* try the current band */
5411 bandunit = wlc->band->bandunit;
5412 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5413 if (brcms_c_rate_hwrs_filter_sort_validate
5414 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5415 wlc->stf->txstreams))
5418 /* try the other band */
5419 if (brcms_is_mband_unlocked(wlc)) {
5420 bandunit = OTHERBANDUNIT(wlc);
5421 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5422 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5424 bandstate[bandunit]->
5426 wlc->stf->txstreams))
5433 /* apply new rateset */
5434 memcpy(&wlc->default_bss->rateset, &new,
5435 sizeof(struct brcms_c_rateset));
5436 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5437 sizeof(struct brcms_c_rateset));
5441 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5446 if (wlc->bsscfg->associated)
5447 r = wlc->bsscfg->current_bss->rateset.rates[0];
5449 r = wlc->default_bss->rateset.rates[0];
5451 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5454 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5456 u16 chspec = ch20mhz_chspec(channel);
5458 if (channel < 0 || channel > MAXCHANNEL)
5461 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5465 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5466 if (wlc->band->bandunit != chspec_bandunit(chspec))
5467 wlc->bandinit_pending = true;
5469 wlc->bandinit_pending = false;
5472 wlc->default_bss->chanspec = chspec;
5473 /* brcms_c_BSSinit() will sanitize the rateset before
5475 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5476 brcms_c_set_home_chanspec(wlc, chspec);
5477 brcms_c_suspend_mac_and_wait(wlc);
5478 brcms_c_set_chanspec(wlc, chspec);
5479 brcms_c_enable_mac(wlc);
5484 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5488 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5489 lrl < 1 || lrl > RETRY_SHORT_MAX)
5495 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5497 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5498 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5499 EDCF_SHORT, wlc->SRL);
5500 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5501 EDCF_LONG, wlc->LRL);
5503 brcms_c_wme_retries_write(wlc);
5508 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5509 struct brcm_rateset *currs)
5511 struct brcms_c_rateset *rs;
5513 if (wlc->pub->associated)
5514 rs = &wlc->bsscfg->current_bss->rateset;
5516 rs = &wlc->default_bss->rateset;
5518 /* Copy only legacy rateset section */
5519 currs->count = rs->count;
5520 memcpy(&currs->rates, &rs->rates, rs->count);
5523 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5525 struct brcms_c_rateset internal_rs;
5528 if (rs->count > BRCMS_NUMRATES)
5531 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5533 /* Copy only legacy rateset section */
5534 internal_rs.count = rs->count;
5535 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5537 /* merge rateset coming in with the current mcsset */
5538 if (wlc->pub->_n_enab & SUPPORT_11N) {
5539 struct brcms_bss_info *mcsset_bss;
5540 if (wlc->bsscfg->associated)
5541 mcsset_bss = wlc->bsscfg->current_bss;
5543 mcsset_bss = wlc->default_bss;
5544 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5548 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5550 brcms_c_ofdm_rateset_war(wlc);
5555 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5557 if (period < DOT11_MIN_BEACON_PERIOD ||
5558 period > DOT11_MAX_BEACON_PERIOD)
5561 wlc->default_bss->beacon_period = period;
5565 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5567 return wlc->band->phytype;
5570 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5572 wlc->shortslot_override = sslot_override;
5575 * shortslot is an 11g feature, so no more work if we are
5576 * currently on the 5G band
5578 if (wlc->band->bandtype == BRCM_BAND_5G)
5581 if (wlc->pub->up && wlc->pub->associated) {
5582 /* let watchdog or beacon processing update shortslot */
5583 } else if (wlc->pub->up) {
5584 /* unassociated shortslot is off */
5585 brcms_c_switch_shortslot(wlc, false);
5587 /* driver is down, so just update the brcms_c_info
5589 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5590 wlc->shortslot = false;
5593 (wlc->shortslot_override ==
5594 BRCMS_SHORTSLOT_ON);
5599 * register watchdog and down handlers.
5601 int brcms_c_module_register(struct brcms_pub *pub,
5602 const char *name, struct brcms_info *hdl,
5603 int (*d_fn)(void *handle))
5605 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5608 /* find an empty entry and just add, no duplication check! */
5609 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5610 if (wlc->modulecb[i].name[0] == '\0') {
5611 strncpy(wlc->modulecb[i].name, name,
5612 sizeof(wlc->modulecb[i].name) - 1);
5613 wlc->modulecb[i].hdl = hdl;
5614 wlc->modulecb[i].down_fn = d_fn;
5622 /* unregister module callbacks */
5623 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5624 struct brcms_info *hdl)
5626 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5632 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5633 if (!strcmp(wlc->modulecb[i].name, name) &&
5634 (wlc->modulecb[i].hdl == hdl)) {
5635 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5640 /* table not found! */
5644 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5646 struct pci_dev *pcidev = core->bus->host_pci;
5647 u16 vendor = pcidev->vendor;
5648 u16 device = pcidev->device;
5650 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5651 pr_err("unknown vendor id %04x\n", vendor);
5655 if (device == BCM43224_D11N_ID_VEN1)
5657 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5659 if (device == BCM4313_D11N2G_ID)
5661 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5664 pr_err("unknown device id %04x\n", device);
5668 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5670 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5672 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5675 pr_err("unknown chip id %04x\n", chipinfo->id);
5679 bool brcms_c_chipmatch(struct bcma_device *core)
5681 switch (core->bus->hosttype) {
5682 case BCMA_HOSTTYPE_PCI:
5683 return brcms_c_chipmatch_pci(core);
5684 case BCMA_HOSTTYPE_SOC:
5685 return brcms_c_chipmatch_soc(core);
5687 pr_err("unknown host type: %i\n", core->bus->hosttype);
5692 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5697 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5698 if (is_ofdm_rate(rate))
5699 table_ptr = M_RT_DIRMAP_A;
5701 table_ptr = M_RT_DIRMAP_B;
5703 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5704 * the index into the rate table.
5706 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5707 index = phy_rate & 0xf;
5709 /* Find the SHM pointer to the rate table entry by looking in the
5712 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5716 * bcmc_fid_generate:
5717 * Generate frame ID for a BCMC packet. The frag field is not used
5718 * for MC frames so is used as part of the sequence number.
5721 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5726 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5730 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5737 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5743 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5744 * is less than or equal to the rate of the immediately previous
5747 rspec = brcms_basic_rate(wlc, rspec);
5748 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5750 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5751 (DOT11_ACK_LEN + FCS_LEN));
5756 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5759 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5763 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5767 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5768 * is less than or equal to the rate of the immediately previous
5771 rspec = brcms_basic_rate(wlc, rspec);
5772 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5773 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5774 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5778 /* brcms_c_compute_frame_dur()
5780 * Calculate the 802.11 MAC header DUR field for MPDU
5781 * DUR for a single frame = 1 SIFS + 1 ACK
5782 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5784 * rate MPDU rate in unit of 500kbps
5785 * next_frag_len next MPDU length in bytes
5786 * preamble_type use short/GF or long/MM PLCP header
5789 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5790 u8 preamble_type, uint next_frag_len)
5794 sifs = get_sifs(wlc->band);
5797 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5799 if (next_frag_len) {
5800 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5802 /* add another SIFS and the frag time */
5805 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5811 /* The opposite of brcms_c_calc_frame_time */
5813 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5814 u8 preamble_type, uint dur)
5816 uint nsyms, mac_len, Ndps, kNdps;
5817 uint rate = rspec2rate(ratespec);
5819 if (is_mcs_rate(ratespec)) {
5820 uint mcs = ratespec & RSPEC_RATE_MASK;
5821 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5822 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5823 /* payload calculation matches that of regular ofdm */
5824 if (wlc->band->bandtype == BRCM_BAND_2G)
5825 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5826 /* kNdbps = kbps * 4 */
5827 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5828 rspec_issgi(ratespec)) * 4;
5829 nsyms = dur / APHY_SYMBOL_TIME;
5832 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5833 } else if (is_ofdm_rate(ratespec)) {
5834 dur -= APHY_PREAMBLE_TIME;
5835 dur -= APHY_SIGNAL_TIME;
5836 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5838 nsyms = dur / APHY_SYMBOL_TIME;
5841 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5843 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5844 dur -= BPHY_PLCP_SHORT_TIME;
5846 dur -= BPHY_PLCP_TIME;
5847 mac_len = dur * rate;
5848 /* divide out factor of 2 in rate (1/2 mbps) */
5849 mac_len = mac_len / 8 / 2;
5855 * Return true if the specified rate is supported by the specified band.
5856 * BRCM_BAND_AUTO indicates the current band.
5858 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5861 struct brcms_c_rateset *hw_rateset;
5864 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5865 hw_rateset = &wlc->band->hw_rateset;
5866 else if (wlc->pub->_nbands > 1)
5867 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5869 /* other band specified and we are a single band device */
5872 /* check if this is a mimo rate */
5873 if (is_mcs_rate(rspec)) {
5874 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5877 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5880 for (i = 0; i < hw_rateset->count; i++)
5881 if (hw_rateset->rates[i] == rspec2rate(rspec))
5885 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5886 "not in hw_rateset\n", wlc->pub->unit, rspec);
5892 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5895 struct bcma_device *core = wlc->hw->d11core;
5896 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5897 u8 rate = int_val & NRATE_RATE_MASK;
5899 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5900 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5901 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5902 == NRATE_OVERRIDE_MCS_ONLY);
5908 /* validate the combination of rate/mcs/stf is allowed */
5909 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5910 /* mcs only allowed when nmode */
5911 if (stf > PHY_TXC1_MODE_SDM) {
5912 brcms_err(core, "wl%d: %s: Invalid stf\n",
5913 wlc->pub->unit, __func__);
5918 /* mcs 32 is a special case, DUP mode 40 only */
5920 if (!CHSPEC_IS40(wlc->home_chanspec) ||
5921 ((stf != PHY_TXC1_MODE_SISO)
5922 && (stf != PHY_TXC1_MODE_CDD))) {
5923 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5924 wlc->pub->unit, __func__);
5928 /* mcs > 7 must use stf SDM */
5929 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5930 /* mcs > 7 must use stf SDM */
5931 if (stf != PHY_TXC1_MODE_SDM) {
5932 brcms_dbg_mac80211(core, "wl%d: enabling "
5933 "SDM mode for mcs %d\n",
5934 wlc->pub->unit, rate);
5935 stf = PHY_TXC1_MODE_SDM;
5939 * MCS 0-7 may use SISO, CDD, and for
5942 if ((stf > PHY_TXC1_MODE_STBC) ||
5943 (!BRCMS_STBC_CAP_PHY(wlc)
5944 && (stf == PHY_TXC1_MODE_STBC))) {
5945 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5946 wlc->pub->unit, __func__);
5951 } else if (is_ofdm_rate(rate)) {
5952 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5953 brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5954 wlc->pub->unit, __func__);
5958 } else if (is_cck_rate(rate)) {
5959 if ((cur_band->bandtype != BRCM_BAND_2G)
5960 || (stf != PHY_TXC1_MODE_SISO)) {
5961 brcms_err(core, "wl%d: %s: Invalid CCK\n",
5962 wlc->pub->unit, __func__);
5967 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5968 wlc->pub->unit, __func__);
5972 /* make sure multiple antennae are available for non-siso rates */
5973 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5974 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5975 "request\n", wlc->pub->unit, __func__);
5982 rspec |= RSPEC_MIMORATE;
5983 /* For STBC populate the STC field of the ratespec */
5984 if (stf == PHY_TXC1_MODE_STBC) {
5986 stc = 1; /* Nss for single stream is always 1 */
5987 rspec |= (stc << RSPEC_STC_SHIFT);
5991 rspec |= (stf << RSPEC_STF_SHIFT);
5993 if (override_mcs_only)
5994 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5997 rspec |= RSPEC_SHORT_GI;
6000 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6009 * Compute PLCP, but only requires actual rate and length of pkt.
6010 * Rate is given in the driver standard multiple of 500 kbps.
6011 * le is set for 11 Mbps rate if necessary.
6012 * Broken out for PRQ.
6015 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6016 uint length, u8 *plcp)
6029 usec = (length << 4) / 11;
6030 if ((length << 4) - (usec * 11) > 0)
6034 usec = (length << 3) / 11;
6035 if ((length << 3) - (usec * 11) > 0) {
6037 if ((usec * 11) - (length << 3) >= 8)
6038 le = D11B_PLCP_SIGNAL_LE;
6043 brcms_err(wlc->hw->d11core,
6044 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6046 rate_500 = BRCM_RATE_1M;
6050 /* PLCP signal byte */
6051 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6052 /* PLCP service byte */
6053 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6054 /* PLCP length u16, little endian */
6055 plcp[2] = usec & 0xff;
6056 plcp[3] = (usec >> 8) & 0xff;
6062 /* Rate: 802.11 rate code, length: PSDU length in octets */
6063 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6065 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6067 if (rspec_is40mhz(rspec) || (mcs == 32))
6068 plcp[0] |= MIMO_PLCP_40MHZ;
6069 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6070 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6071 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6072 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6076 /* Rate: 802.11 rate code, length: PSDU length in octets */
6078 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6082 int rate = rspec2rate(rspec);
6085 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6088 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6089 memset(plcp, 0, D11_PHY_HDR_LEN);
6090 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6092 tmp = (length & 0xfff) << 5;
6093 plcp[2] |= (tmp >> 16) & 0xff;
6094 plcp[1] |= (tmp >> 8) & 0xff;
6095 plcp[0] |= tmp & 0xff;
6098 /* Rate: 802.11 rate code, length: PSDU length in octets */
6099 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6100 uint length, u8 *plcp)
6102 int rate = rspec2rate(rspec);
6104 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6108 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6109 uint length, u8 *plcp)
6111 if (is_mcs_rate(rspec))
6112 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6113 else if (is_ofdm_rate(rspec))
6114 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6116 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6119 /* brcms_c_compute_rtscts_dur()
6121 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6122 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6123 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6125 * cts cts-to-self or rts/cts
6126 * rts_rate rts or cts rate in unit of 500kbps
6127 * rate next MPDU rate in unit of 500kbps
6128 * frame_len next MPDU frame length in bytes
6131 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6133 u32 frame_rate, u8 rts_preamble_type,
6134 u8 frame_preamble_type, uint frame_len, bool ba)
6138 sifs = get_sifs(wlc->band);
6144 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6152 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6156 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6157 BRCMS_SHORT_PREAMBLE);
6160 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6161 frame_preamble_type);
6165 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6170 if (BRCMS_ISLCNPHY(wlc->band)) {
6171 bw = PHY_TXC1_BW_20MHZ;
6173 bw = rspec_get_bw(rspec);
6174 /* 10Mhz is not supported yet */
6175 if (bw < PHY_TXC1_BW_20MHZ) {
6176 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6177 "not supported yet, set to 20L\n", bw);
6178 bw = PHY_TXC1_BW_20MHZ;
6182 if (is_mcs_rate(rspec)) {
6183 uint mcs = rspec & RSPEC_RATE_MASK;
6185 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6186 phyctl1 = rspec_phytxbyte2(rspec);
6187 /* set the upper byte of phyctl1 */
6188 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6189 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6190 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6192 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6193 * Data Rate. Eventually MIMOPHY would also be converted to
6196 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6197 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6198 } else { /* legacy OFDM/CCK */
6200 /* get the phyctl byte from rate phycfg table */
6201 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6203 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6204 "legacy OFDM/CCK rate\n");
6207 /* set the upper byte of phyctl1 */
6209 (bw | (phycfg << 8) |
6210 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6216 * Add struct d11txh, struct cck_phy_hdr.
6218 * 'p' data must start with 802.11 MAC header
6219 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6221 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6225 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6226 struct sk_buff *p, struct scb *scb, uint frag,
6227 uint nfrags, uint queue, uint next_frag_len)
6229 struct ieee80211_hdr *h;
6231 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6232 int len, phylen, rts_phylen;
6233 u16 mch, phyctl, xfts, mainrates;
6234 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6235 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6236 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6237 bool use_rts = false;
6238 bool use_cts = false;
6239 bool use_rifs = false;
6240 bool short_preamble[2] = { false, false };
6241 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6242 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6243 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6244 struct ieee80211_rts *rts = NULL;
6247 bool hwtkmic = false;
6248 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6249 #define ANTCFG_NONE 0xFF
6250 u8 antcfg = ANTCFG_NONE;
6251 u8 fbantcfg = ANTCFG_NONE;
6252 uint phyctl1_stf = 0;
6254 struct ieee80211_tx_rate *txrate[2];
6256 struct ieee80211_tx_info *tx_info;
6259 u8 mimo_preamble_type;
6261 /* locate 802.11 MAC header */
6262 h = (struct ieee80211_hdr *)(p->data);
6263 qos = ieee80211_is_data_qos(h->frame_control);
6265 /* compute length of frame in bytes for use in PLCP computations */
6267 phylen = len + FCS_LEN;
6270 tx_info = IEEE80211_SKB_CB(p);
6273 plcp = skb_push(p, D11_PHY_HDR_LEN);
6275 /* add Broadcom tx descriptor header */
6276 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6277 memset(txh, 0, D11_TXH_LEN);
6280 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6281 /* non-AP STA should never use BCMC queue */
6282 if (queue == TX_BCMC_FIFO) {
6283 brcms_err(wlc->hw->d11core,
6284 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6285 wlc->pub->unit, __func__);
6286 frameid = bcmc_fid_generate(wlc, NULL, txh);
6288 /* Increment the counter for first fragment */
6289 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6290 scb->seqnum[p->priority]++;
6292 /* extract fragment number from frame first */
6293 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6294 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6295 h->seq_ctrl = cpu_to_le16(seq);
6297 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6298 (queue & TXFID_QUEUE_MASK);
6301 frameid |= queue & TXFID_QUEUE_MASK;
6303 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6304 if (ieee80211_is_beacon(h->frame_control))
6305 mcl |= TXC_IGNOREPMQ;
6307 txrate[0] = tx_info->control.rates;
6308 txrate[1] = txrate[0] + 1;
6311 * if rate control algorithm didn't give us a fallback
6312 * rate, use the primary rate
6314 if (txrate[1]->idx < 0)
6315 txrate[1] = txrate[0];
6317 for (k = 0; k < hw->max_rates; k++) {
6318 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6320 if ((txrate[k]->idx >= 0)
6321 && (txrate[k]->idx <
6322 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6324 hw->wiphy->bands[tx_info->band]->
6325 bitrates[txrate[k]->idx].hw_value;
6328 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6331 rspec[k] = BRCM_RATE_1M;
6334 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6335 NRATE_MCS_INUSE | txrate[k]->idx);
6339 * Currently only support same setting for primay and
6340 * fallback rates. Unify flags for each rate into a
6341 * single value for the frame
6345 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6348 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6353 * determine and validate primary rate
6354 * and fallback rates
6356 if (!rspec_active(rspec[k])) {
6357 rspec[k] = BRCM_RATE_1M;
6359 if (!is_multicast_ether_addr(h->addr1)) {
6360 /* set tx antenna config */
6361 brcms_c_antsel_antcfg_get(wlc->asi, false,
6362 false, 0, 0, &antcfg, &fbantcfg);
6367 phyctl1_stf = wlc->stf->ss_opmode;
6369 if (wlc->pub->_n_enab & SUPPORT_11N) {
6370 for (k = 0; k < hw->max_rates; k++) {
6372 * apply siso/cdd to single stream mcs's or ofdm
6373 * if rspec is auto selected
6375 if (((is_mcs_rate(rspec[k]) &&
6376 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6377 is_ofdm_rate(rspec[k]))
6378 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6379 || !(rspec[k] & RSPEC_OVERRIDE))) {
6380 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6382 /* For SISO MCS use STBC if possible */
6383 if (is_mcs_rate(rspec[k])
6384 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6387 /* Nss for single stream is always 1 */
6389 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6391 (stc << RSPEC_STC_SHIFT);
6394 (phyctl1_stf << RSPEC_STF_SHIFT);
6398 * Is the phy configured to use 40MHZ frames? If
6399 * so then pick the desired txbw
6401 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6402 /* default txbw is 20in40 SB */
6403 mimo_ctlchbw = mimo_txbw =
6404 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6406 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6408 if (is_mcs_rate(rspec[k])) {
6409 /* mcs 32 must be 40b/w DUP */
6410 if ((rspec[k] & RSPEC_RATE_MASK)
6413 PHY_TXC1_BW_40MHZ_DUP;
6415 } else if (wlc->mimo_40txbw != AUTO)
6416 mimo_txbw = wlc->mimo_40txbw;
6417 /* else check if dst is using 40 Mhz */
6418 else if (scb->flags & SCB_IS40)
6419 mimo_txbw = PHY_TXC1_BW_40MHZ;
6420 } else if (is_ofdm_rate(rspec[k])) {
6421 if (wlc->ofdm_40txbw != AUTO)
6422 mimo_txbw = wlc->ofdm_40txbw;
6423 } else if (wlc->cck_40txbw != AUTO) {
6424 mimo_txbw = wlc->cck_40txbw;
6428 * mcs32 is 40 b/w only.
6429 * This is possible for probe packets on
6432 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6434 rspec[k] = RSPEC_MIMORATE;
6436 mimo_txbw = PHY_TXC1_BW_20MHZ;
6439 /* Set channel width */
6440 rspec[k] &= ~RSPEC_BW_MASK;
6441 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6442 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6444 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6446 /* Disable short GI, not supported yet */
6447 rspec[k] &= ~RSPEC_SHORT_GI;
6449 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6450 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6451 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6453 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6454 && (!is_mcs_rate(rspec[k]))) {
6455 brcms_err(wlc->hw->d11core,
6456 "wl%d: %s: IEEE80211_TX_"
6457 "RC_MCS != is_mcs_rate(rspec)\n",
6458 wlc->pub->unit, __func__);
6461 if (is_mcs_rate(rspec[k])) {
6462 preamble_type[k] = mimo_preamble_type;
6465 * if SGI is selected, then forced mm
6468 if ((rspec[k] & RSPEC_SHORT_GI)
6469 && is_single_stream(rspec[k] &
6471 preamble_type[k] = BRCMS_MM_PREAMBLE;
6474 /* should be better conditionalized */
6475 if (!is_mcs_rate(rspec[0])
6476 && (tx_info->control.rates[0].
6477 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6478 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6481 for (k = 0; k < hw->max_rates; k++) {
6482 /* Set ctrlchbw as 20Mhz */
6483 rspec[k] &= ~RSPEC_BW_MASK;
6484 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6486 /* for nphy, stf of ofdm frames must follow policies */
6487 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6488 rspec[k] &= ~RSPEC_STF_MASK;
6489 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6494 /* Reset these for use with AMPDU's */
6495 txrate[0]->count = 0;
6496 txrate[1]->count = 0;
6498 /* (2) PROTECTION, may change rspec */
6499 if ((ieee80211_is_data(h->frame_control) ||
6500 ieee80211_is_mgmt(h->frame_control)) &&
6501 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6504 /* (3) PLCP: determine PLCP header and MAC duration,
6505 * fill struct d11txh */
6506 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6507 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6508 memcpy(&txh->FragPLCPFallback,
6509 plcp_fallback, sizeof(txh->FragPLCPFallback));
6511 /* Length field now put in CCK FBR CRC field */
6512 if (is_cck_rate(rspec[1])) {
6513 txh->FragPLCPFallback[4] = phylen & 0xff;
6514 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6517 /* MIMO-RATE: need validation ?? */
6518 mainrates = is_ofdm_rate(rspec[0]) ?
6519 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6522 /* DUR field for main rate */
6523 if (!ieee80211_is_pspoll(h->frame_control) &&
6524 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6526 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6528 h->duration_id = cpu_to_le16(durid);
6529 } else if (use_rifs) {
6530 /* NAV protect to end of next max packet size */
6532 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6534 DOT11_MAX_FRAG_LEN);
6535 durid += RIFS_11N_TIME;
6536 h->duration_id = cpu_to_le16(durid);
6539 /* DUR field for fallback rate */
6540 if (ieee80211_is_pspoll(h->frame_control))
6541 txh->FragDurFallback = h->duration_id;
6542 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6543 txh->FragDurFallback = 0;
6545 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6546 preamble_type[1], next_frag_len);
6547 txh->FragDurFallback = cpu_to_le16(durid);
6550 /* (4) MAC-HDR: MacTxControlLow */
6552 mcl |= TXC_STARTMSDU;
6554 if (!is_multicast_ether_addr(h->addr1))
6555 mcl |= TXC_IMMEDACK;
6557 if (wlc->band->bandtype == BRCM_BAND_5G)
6558 mcl |= TXC_FREQBAND_5G;
6560 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6563 /* set AMIC bit if using hardware TKIP MIC */
6567 txh->MacTxControlLow = cpu_to_le16(mcl);
6569 /* MacTxControlHigh */
6572 /* Set fallback rate preamble type */
6573 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6574 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6575 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6576 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6579 /* MacFrameControl */
6580 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6581 txh->TxFesTimeNormal = cpu_to_le16(0);
6583 txh->TxFesTimeFallback = cpu_to_le16(0);
6586 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6589 txh->TxFrameID = cpu_to_le16(frameid);
6592 * TxStatus, Note the case of recreating the first frag of a suppressed
6593 * frame then we may need to reset the retry cnt's via the status reg
6595 txh->TxStatus = cpu_to_le16(status);
6598 * extra fields for ucode AMPDU aggregation, the new fields are added to
6599 * the END of previous structure so that it's compatible in driver.
6601 txh->MaxNMpdus = cpu_to_le16(0);
6602 txh->MaxABytes_MRT = cpu_to_le16(0);
6603 txh->MaxABytes_FBR = cpu_to_le16(0);
6604 txh->MinMBytes = cpu_to_le16(0);
6606 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6607 * furnish struct d11txh */
6608 /* RTS PLCP header and RTS frame */
6609 if (use_rts || use_cts) {
6610 if (use_rts && use_cts)
6613 for (k = 0; k < 2; k++) {
6614 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6619 if (!is_ofdm_rate(rts_rspec[0]) &&
6620 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6621 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6622 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6623 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6626 if (!is_ofdm_rate(rts_rspec[1]) &&
6627 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6628 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6629 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6630 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6633 /* RTS/CTS additions to MacTxControlLow */
6635 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6637 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6638 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6641 /* RTS PLCP header */
6642 rts_plcp = txh->RTSPhyHeader;
6644 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6646 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6648 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6650 /* fallback rate version of RTS PLCP header */
6651 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6653 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6654 sizeof(txh->RTSPLCPFallback));
6656 /* RTS frame fields... */
6657 rts = (struct ieee80211_rts *)&txh->rts_frame;
6659 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6660 rspec[0], rts_preamble_type[0],
6661 preamble_type[0], phylen, false);
6662 rts->duration = cpu_to_le16(durid);
6663 /* fallback rate version of RTS DUR field */
6664 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6665 rts_rspec[1], rspec[1],
6666 rts_preamble_type[1],
6667 preamble_type[1], phylen, false);
6668 txh->RTSDurFallback = cpu_to_le16(durid);
6671 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6672 IEEE80211_STYPE_CTS);
6674 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6676 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6677 IEEE80211_STYPE_RTS);
6679 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6683 * low 8 bits: main frag rate/mcs,
6684 * high 8 bits: rts/cts rate/mcs
6686 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6688 (struct ofdm_phy_hdr *) rts_plcp) :
6691 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6692 memset((char *)&txh->rts_frame, 0,
6693 sizeof(struct ieee80211_rts));
6694 memset((char *)txh->RTSPLCPFallback, 0,
6695 sizeof(txh->RTSPLCPFallback));
6696 txh->RTSDurFallback = 0;
6699 #ifdef SUPPORT_40MHZ
6700 /* add null delimiter count */
6701 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6702 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6703 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6708 * Now that RTS/RTS FB preamble types are updated, write
6711 txh->MacTxControlHigh = cpu_to_le16(mch);
6714 * MainRates (both the rts and frag plcp rates have
6715 * been calculated now)
6717 txh->MainRates = cpu_to_le16(mainrates);
6719 /* XtraFrameTypes */
6720 xfts = frametype(rspec[1], wlc->mimoft);
6721 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6722 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6723 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6725 txh->XtraFrameTypes = cpu_to_le16(xfts);
6727 /* PhyTxControlWord */
6728 phyctl = frametype(rspec[0], wlc->mimoft);
6729 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6730 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6731 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6732 phyctl |= PHY_TXC_SHORT_HDR;
6735 /* phytxant is properly bit shifted */
6736 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6737 txh->PhyTxControlWord = cpu_to_le16(phyctl);
6739 /* PhyTxControlWord_1 */
6740 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6743 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6744 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6745 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6746 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6748 if (use_rts || use_cts) {
6749 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6750 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6751 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6752 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6756 * For mcs frames, if mixedmode(overloaded with long preamble)
6757 * is going to be set, fill in non-zero MModeLen and/or
6758 * MModeFbrLen it will be unnecessary if they are separated
6760 if (is_mcs_rate(rspec[0]) &&
6761 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6763 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6764 txh->MModeLen = cpu_to_le16(mmodelen);
6767 if (is_mcs_rate(rspec[1]) &&
6768 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6770 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6771 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6775 ac = skb_get_queue_mapping(p);
6776 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6777 uint frag_dur, dur, dur_fallback;
6779 /* WME: Update TXOP threshold */
6780 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6782 brcms_c_calc_frame_time(wlc, rspec[0],
6783 preamble_type[0], phylen);
6786 /* 1 RTS or CTS-to-self frame */
6788 brcms_c_calc_cts_time(wlc, rts_rspec[0],
6789 rts_preamble_type[0]);
6791 brcms_c_calc_cts_time(wlc, rts_rspec[1],
6792 rts_preamble_type[1]);
6793 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6794 dur += le16_to_cpu(rts->duration);
6796 le16_to_cpu(txh->RTSDurFallback);
6797 } else if (use_rifs) {
6801 /* frame + SIFS + ACK */
6804 brcms_c_compute_frame_dur(wlc, rspec[0],
6805 preamble_type[0], 0);
6808 brcms_c_calc_frame_time(wlc, rspec[1],
6812 brcms_c_compute_frame_dur(wlc, rspec[1],
6813 preamble_type[1], 0);
6815 /* NEED to set TxFesTimeNormal (hard) */
6816 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6818 * NEED to set fallback rate version of
6819 * TxFesTimeNormal (hard)
6821 txh->TxFesTimeFallback =
6822 cpu_to_le16((u16) dur_fallback);
6825 * update txop byte threshold (txop minus intraframe
6828 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6832 brcms_c_calc_frame_len(wlc,
6833 rspec[0], preamble_type[0],
6834 (wlc->edcf_txop[ac] -
6836 /* range bound the fragthreshold */
6837 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6840 else if (newfragthresh >
6841 wlc->usr_fragthresh)
6843 wlc->usr_fragthresh;
6844 /* update the fragthresh and do txc update */
6845 if (wlc->fragthresh[queue] !=
6846 (u16) newfragthresh)
6847 wlc->fragthresh[queue] =
6848 (u16) newfragthresh;
6850 brcms_err(wlc->hw->d11core,
6851 "wl%d: %s txop invalid "
6853 wlc->pub->unit, fifo_names[queue],
6854 rspec2rate(rspec[0]));
6857 if (dur > wlc->edcf_txop[ac])
6858 brcms_err(wlc->hw->d11core,
6859 "wl%d: %s: %s txop "
6860 "exceeded phylen %d/%d dur %d/%d\n",
6861 wlc->pub->unit, __func__,
6863 phylen, wlc->fragthresh[queue],
6864 dur, wlc->edcf_txop[ac]);
6871 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6873 struct dma_pub *dma;
6874 int fifo, ret = -ENOSPC;
6876 u16 frameid = INVALIDFID;
6878 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6879 dma = wlc->hw->di[fifo];
6880 txh = (struct d11txh *)(skb->data);
6882 if (dma->txavail == 0) {
6884 * We sometimes get a frame from mac80211 after stopping
6885 * the queues. This only ever seems to be a single frame
6886 * and is seems likely to be a race. TX_HEADROOM should
6887 * ensure that we have enough space to handle these stray
6888 * packets, so warn if there isn't. If we're out of space
6889 * in the tx ring and the tx queue isn't stopped then
6890 * we've really got a bug; warn loudly if that happens.
6892 brcms_warn(wlc->hw->d11core,
6893 "Received frame for tx with no space in DMA ring\n");
6894 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6895 skb_get_queue_mapping(skb)));
6899 /* When a BC/MC frame is being committed to the BCMC fifo
6900 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6902 if (fifo == TX_BCMC_FIFO)
6903 frameid = le16_to_cpu(txh->TxFrameID);
6905 /* Commit BCMC sequence number in the SHM frame ID location */
6906 if (frameid != INVALIDFID) {
6908 * To inform the ucode of the last mcast frame posted
6909 * so that it can clear moredata bit
6911 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6914 ret = brcms_c_txfifo(wlc, fifo, skb);
6916 * The only reason for brcms_c_txfifo to fail is because
6917 * there weren't any DMA descriptors, but we've already
6918 * checked for that. So if it does fail yell loudly.
6925 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6926 struct ieee80211_hw *hw)
6929 struct scb *scb = &wlc->pri_scb;
6931 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6932 brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6933 if (!brcms_c_tx(wlc, sdu))
6936 /* packet discarded */
6937 dev_kfree_skb_any(sdu);
6942 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6944 struct dma_pub *dma = wlc->hw->di[fifo];
6948 ret = dma_txfast(wlc, dma, p);
6950 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6953 * Stop queue if DMA ring is full. Reserve some free descriptors,
6954 * as we sometimes receive a frame from mac80211 after the queues
6957 queue = skb_get_queue_mapping(p);
6958 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6959 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6960 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6966 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6967 bool use_rspec, u16 mimo_ctlchbw)
6972 /* use frame rate as rts rate */
6974 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6975 /* Use 11Mbps as the g protection RTS target rate and fallback.
6976 * Use the brcms_basic_rate() lookup to find the best basic rate
6977 * under the target in case 11 Mbps is not Basic.
6978 * 6 and 9 Mbps are not usually selected by rate selection, but
6979 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6982 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6984 /* calculate RTS rate and fallback rate based on the frame rate
6985 * RTS must be sent at a basic rate since it is a
6986 * control frame, sec 9.6 of 802.11 spec
6988 rts_rspec = brcms_basic_rate(wlc, rspec);
6990 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6991 /* set rts txbw to correct side band */
6992 rts_rspec &= ~RSPEC_BW_MASK;
6995 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6996 * 20MHz channel (DUP), otherwise send RTS on control channel
6998 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
6999 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7001 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7003 /* pick siso/cdd as default for ofdm */
7004 if (is_ofdm_rate(rts_rspec)) {
7005 rts_rspec &= ~RSPEC_STF_MASK;
7006 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7012 /* Update beacon listen interval in shared memory */
7013 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7015 /* wake up every DTIM is the default */
7016 if (wlc->bcn_li_dtim == 1)
7017 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7019 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7020 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7024 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7027 struct bcma_device *core = wlc_hw->d11core;
7029 /* read the tsf timer low, then high to get an atomic read */
7030 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7031 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7035 * recover 64bit TSF value from the 16bit TSF value in the rx header
7036 * given the assumption that the TSF passed in header is within 65ms
7037 * of the current tsf.
7040 * 3.......6.......8.......0.......2.......4.......6.......8......0
7041 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7043 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7044 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7045 * receive call sequence after rx interrupt. Only the higher 16 bits
7046 * are used. Finally, the tsf_h is read from the tsf register.
7048 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7049 struct d11rxhdr *rxh)
7052 u16 rx_tsf_0_15, rx_tsf_16_31;
7054 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7056 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7057 rx_tsf_0_15 = rxh->RxTSFTime;
7060 * a greater tsf time indicates the low 16 bits of
7061 * tsf_l wrapped, so decrement the high 16 bits.
7063 if ((u16)tsf_l < rx_tsf_0_15) {
7065 if (rx_tsf_16_31 == 0xffff)
7069 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7073 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7075 struct ieee80211_rx_status *rx_status)
7080 unsigned char *plcp;
7082 /* fill in TSF and flag its presence */
7083 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7084 rx_status->flag |= RX_FLAG_MACTIME_START;
7086 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7089 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7091 ieee80211_channel_to_frequency(channel, rx_status->band);
7093 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7097 rx_status->antenna =
7098 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7102 rspec = brcms_c_compute_rspec(rxh, plcp);
7103 if (is_mcs_rate(rspec)) {
7104 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7105 rx_status->flag |= RX_FLAG_HT;
7106 if (rspec_is40mhz(rspec))
7107 rx_status->flag |= RX_FLAG_40MHZ;
7109 switch (rspec2rate(rspec)) {
7111 rx_status->rate_idx = 0;
7114 rx_status->rate_idx = 1;
7117 rx_status->rate_idx = 2;
7120 rx_status->rate_idx = 3;
7123 rx_status->rate_idx = 4;
7126 rx_status->rate_idx = 5;
7129 rx_status->rate_idx = 6;
7132 rx_status->rate_idx = 7;
7135 rx_status->rate_idx = 8;
7138 rx_status->rate_idx = 9;
7141 rx_status->rate_idx = 10;
7144 rx_status->rate_idx = 11;
7147 brcms_err(wlc->hw->d11core,
7148 "%s: Unknown rate\n", __func__);
7152 * For 5GHz, we should decrease the index as it is
7153 * a subset of the 2.4G rates. See bitrates field
7154 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7156 if (rx_status->band == IEEE80211_BAND_5GHZ)
7157 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7159 /* Determine short preamble and rate_idx */
7161 if (is_cck_rate(rspec)) {
7162 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7163 rx_status->flag |= RX_FLAG_SHORTPRE;
7164 } else if (is_ofdm_rate(rspec)) {
7165 rx_status->flag |= RX_FLAG_SHORTPRE;
7167 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7172 if (plcp3_issgi(plcp[3]))
7173 rx_status->flag |= RX_FLAG_SHORT_GI;
7175 if (rxh->RxStatus1 & RXS_DECERR) {
7176 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7177 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7180 if (rxh->RxStatus1 & RXS_FCSERR) {
7181 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7182 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7188 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7192 struct ieee80211_rx_status rx_status;
7193 struct ieee80211_hdr *hdr;
7195 memset(&rx_status, 0, sizeof(rx_status));
7196 prep_mac80211_status(wlc, rxh, p, &rx_status);
7198 /* mac header+body length, exclude CRC and plcp header */
7199 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7200 skb_pull(p, D11_PHY_HDR_LEN);
7201 __skb_trim(p, len_mpdu);
7203 /* unmute transmit */
7204 if (wlc->hw->suspended_fifos) {
7205 hdr = (struct ieee80211_hdr *)p->data;
7206 if (ieee80211_is_beacon(hdr->frame_control))
7207 brcms_b_mute(wlc->hw, false);
7210 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7211 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7214 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7215 * number of bytes goes in the length field
7217 * Formula given by HT PHY Spec v 1.13
7218 * len = 3(nsyms + nstream + 3) - 3
7221 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7224 uint nsyms, len = 0, kNdps;
7226 if (is_mcs_rate(ratespec)) {
7227 uint mcs = ratespec & RSPEC_RATE_MASK;
7228 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7229 rspec_stc(ratespec);
7232 * the payload duration calculation matches that
7235 /* 1000Ndbps = kbps * 4 */
7236 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7237 rspec_issgi(ratespec)) * 4;
7239 if (rspec_stc(ratespec) == 0)
7241 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7242 APHY_TAIL_NBITS) * 1000, kNdps);
7244 /* STBC needs to have even number of symbols */
7247 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7248 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7250 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7251 nsyms += (tot_streams + 3);
7253 * 3 bytes/symbol @ legacy 6Mbps rate
7254 * (-3) excluding service bits and tail bits
7256 len = (3 * nsyms) - 3;
7263 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7265 const struct brcms_c_rateset *rs_dflt;
7266 struct brcms_c_rateset rs;
7269 u8 plcp[D11_PHY_HDR_LEN];
7273 sifs = get_sifs(wlc->band);
7275 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7277 brcms_c_rateset_copy(rs_dflt, &rs);
7278 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7281 * walk the phy rate table and update MAC core SHM
7282 * basic rate table entries
7284 for (i = 0; i < rs.count; i++) {
7285 rate = rs.rates[i] & BRCMS_RATE_MASK;
7287 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7289 /* Calculate the Probe Response PLCP for the given rate */
7290 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7293 * Calculate the duration of the Probe Response
7294 * frame plus SIFS for the MAC
7296 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7297 BRCMS_LONG_PREAMBLE, frame_len);
7300 /* Update the SHM Rate Table entry Probe Response values */
7301 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7302 (u16) (plcp[0] + (plcp[1] << 8)));
7303 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7304 (u16) (plcp[2] + (plcp[3] << 8)));
7305 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7309 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7311 * PLCP header is 6 bytes.
7312 * 802.11 A3 header is 24 bytes.
7313 * Max beacon frame body template length is 112 bytes.
7314 * Max probe resp frame body template length is 110 bytes.
7316 * *len on input contains the max length of the packet available.
7318 * The *len value is set to the number of bytes in buf used, and starts
7319 * with the PLCP and included up to, but not including, the 4 byte FCS.
7322 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7324 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7326 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7327 struct cck_phy_hdr *plcp;
7328 struct ieee80211_mgmt *h;
7329 int hdr_len, body_len;
7331 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7333 /* calc buffer size provided for frame body */
7334 body_len = *len - hdr_len;
7335 /* return actual size */
7336 *len = hdr_len + body_len;
7338 /* format PHY and MAC headers */
7339 memset((char *)buf, 0, hdr_len);
7341 plcp = (struct cck_phy_hdr *) buf;
7344 * PLCP for Probe Response frames are filled in from
7347 if (type == IEEE80211_STYPE_BEACON)
7349 brcms_c_compute_plcp(wlc, bcn_rspec,
7350 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7353 /* "Regular" and 16 MBSS but not for 4 MBSS */
7354 /* Update the phytxctl for the beacon based on the rspec */
7355 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7357 h = (struct ieee80211_mgmt *)&plcp[1];
7359 /* fill in 802.11 header */
7360 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7362 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7363 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7364 if (type == IEEE80211_STYPE_BEACON)
7365 memcpy(&h->da, ðer_bcast, ETH_ALEN);
7366 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7367 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7369 /* SEQ filled in by MAC */
7372 int brcms_c_get_header_len(void)
7378 * Update all beacons for the system.
7380 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7382 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7384 if (bsscfg->up && !bsscfg->BSS)
7385 /* Clear the soft intmask */
7386 wlc->defmacintmask &= ~MI_BCNTPL;
7389 /* Write ssid into shared memory */
7391 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7393 u8 *ssidptr = cfg->SSID;
7395 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7397 /* padding the ssid with zero and copy it into shm */
7398 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7399 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7401 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7402 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7406 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7407 struct brcms_bss_cfg *cfg,
7410 u16 prb_resp[BCN_TMPL_LEN / 2];
7411 int len = BCN_TMPL_LEN;
7414 * write the probe response to hardware, or save in
7415 * the config structure
7418 /* create the probe response template */
7419 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7420 cfg, prb_resp, &len);
7423 brcms_c_suspend_mac_and_wait(wlc);
7425 /* write the probe response into the template region */
7426 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7427 (len + 3) & ~3, prb_resp);
7429 /* write the length of the probe response frame (+PLCP/-FCS) */
7430 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7432 /* write the SSID and SSID length */
7433 brcms_c_shm_ssid_upd(wlc, cfg);
7436 * Write PLCP headers and durations for probe response frames
7437 * at all rates. Use the actual frame length covered by the
7438 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7439 * by subtracting the PLCP len and adding the FCS.
7441 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7442 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7445 brcms_c_enable_mac(wlc);
7448 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7450 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7452 /* update AP or IBSS probe responses */
7453 if (bsscfg->up && !bsscfg->BSS)
7454 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7457 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7463 *blocks = wlc_hw->xmtfifo_sz[fifo];
7469 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7472 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7473 if (match_reg_offset == RCM_BSSID_OFFSET)
7474 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7478 * Flag 'scan in progress' to withhold dynamic phy calibration
7480 void brcms_c_scan_start(struct brcms_c_info *wlc)
7482 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7485 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7487 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7490 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7492 wlc->pub->associated = state;
7493 wlc->bsscfg->associated = state;
7497 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7498 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7499 * when later on hardware releases them, they can be handled appropriately.
7501 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7502 struct ieee80211_sta *sta,
7503 void (*dma_callback_fn))
7505 struct dma_pub *dmah;
7507 for (i = 0; i < NFIFO; i++) {
7510 dma_walk_packets(dmah, dma_callback_fn, sta);
7514 int brcms_c_get_curband(struct brcms_c_info *wlc)
7516 return wlc->band->bandunit;
7519 void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7524 /* Kick DMA to send any pending AMPDU */
7525 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7527 dma_txflush(wlc->hw->di[i]);
7529 /* wait for queue and DMA fifos to run dry */
7530 while (brcms_txpktpendtot(wlc) > 0) {
7531 brcms_msleep(wlc->wl, 1);
7537 WARN_ON_ONCE(timeout == 0);
7540 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7542 wlc->bcn_li_bcn = interval;
7544 brcms_c_bcn_li_upd(wlc);
7547 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7551 /* Remove override bit and clip to max qdbm value */
7552 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7553 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7556 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7561 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7563 /* Return qdbm units */
7564 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7567 /* Process received frames */
7569 * Return true if more frames need to be processed. false otherwise.
7570 * Param 'bound' indicates max. # frames to process before break out.
7572 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7574 struct d11rxhdr *rxh;
7575 struct ieee80211_hdr *h;
7579 /* frame starts with rxhdr */
7580 rxh = (struct d11rxhdr *) (p->data);
7582 /* strip off rxhdr */
7583 skb_pull(p, BRCMS_HWRXOFF);
7585 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7586 if (rxh->RxStatus1 & RXS_PBPRES) {
7588 brcms_err(wlc->hw->d11core,
7589 "wl%d: recv: rcvd runt of len %d\n",
7590 wlc->pub->unit, p->len);
7596 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7599 if (rxh->RxStatus1 & RXS_FCSERR) {
7600 if (!(wlc->filter_flags & FIF_FCSFAIL))
7604 /* check received pkt has at least frame control field */
7605 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7608 /* not supporting A-MSDU */
7609 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7613 brcms_c_recvctl(wlc, rxh, p);
7617 brcmu_pkt_buf_free_skb(p);
7620 /* Process received frames */
7622 * Return true if more frames need to be processed. false otherwise.
7623 * Param 'bound' indicates max. # frames to process before break out.
7626 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7629 struct sk_buff *next = NULL;
7630 struct sk_buff_head recv_frames;
7633 uint bound_limit = bound ? RXBND : -1;
7635 skb_queue_head_init(&recv_frames);
7637 /* gather received frames */
7638 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
7640 /* !give others some time to run! */
7641 if (++n >= bound_limit)
7645 /* post more rbufs */
7646 dma_rxfill(wlc_hw->di[fifo]);
7648 /* process each frame */
7649 skb_queue_walk_safe(&recv_frames, p, next) {
7650 struct d11rxhdr_le *rxh_le;
7651 struct d11rxhdr *rxh;
7653 skb_unlink(p, &recv_frames);
7654 rxh_le = (struct d11rxhdr_le *)p->data;
7655 rxh = (struct d11rxhdr *)p->data;
7657 /* fixup rx header endianness */
7658 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7659 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7660 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7661 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7662 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7663 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7664 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7665 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7666 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7667 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7668 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7670 brcms_c_recv(wlc_hw->wlc, p);
7673 return n >= bound_limit;
7676 /* second-level interrupt processing
7677 * Return true if another dpc needs to be re-scheduled. false otherwise.
7678 * Param 'bounded' indicates if applicable loops should be bounded.
7680 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7683 struct brcms_hardware *wlc_hw = wlc->hw;
7684 struct bcma_device *core = wlc_hw->d11core;
7686 if (brcms_deviceremoved(wlc)) {
7687 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7689 brcms_down(wlc->wl);
7693 /* grab and clear the saved software intstatus bits */
7694 macintstatus = wlc->macintstatus;
7695 wlc->macintstatus = 0;
7697 brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7698 wlc_hw->unit, macintstatus);
7700 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7703 if (macintstatus & MI_TFS) {
7705 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7706 wlc->macintstatus |= MI_TFS;
7708 brcms_err(core, "MI_TFS: fatal\n");
7713 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7716 /* ATIM window end */
7717 if (macintstatus & MI_ATIMWINEND) {
7718 brcms_dbg_info(core, "end of ATIM window\n");
7719 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7724 * received data or control frame, MI_DMAINT is
7725 * indication of RX_FIFO interrupt
7727 if (macintstatus & MI_DMAINT)
7728 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7729 wlc->macintstatus |= MI_DMAINT;
7731 /* noise sample collected */
7732 if (macintstatus & MI_BG_NOISE)
7733 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7735 if (macintstatus & MI_GP0) {
7736 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7737 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7739 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7740 __func__, ai_get_chip_id(wlc_hw->sih),
7741 ai_get_chiprev(wlc_hw->sih));
7742 brcms_fatal_error(wlc_hw->wlc->wl);
7745 /* gptimer timeout */
7746 if (macintstatus & MI_TO)
7747 bcma_write32(core, D11REGOFFS(gptimer), 0);
7749 if (macintstatus & MI_RFDISABLE) {
7750 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7751 " RF Disable Input\n", wlc_hw->unit);
7752 brcms_rfkill_set_hw_state(wlc->wl);
7755 /* it isn't done and needs to be resched if macintstatus is non-zero */
7756 return wlc->macintstatus != 0;
7759 brcms_fatal_error(wlc_hw->wlc->wl);
7760 return wlc->macintstatus != 0;
7763 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7765 struct bcma_device *core = wlc->hw->d11core;
7766 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7769 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7771 chanspec = ch20mhz_chspec(ch->hw_value);
7773 brcms_b_init(wlc->hw, chanspec);
7775 /* update beacon listen interval */
7776 brcms_c_bcn_li_upd(wlc);
7778 /* write ethernet address to core */
7779 brcms_c_set_mac(wlc->bsscfg);
7780 brcms_c_set_bssid(wlc->bsscfg);
7782 /* Update tsf_cfprep if associated and up */
7783 if (wlc->pub->associated && wlc->bsscfg->up) {
7786 /* get beacon period and convert to uS */
7787 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7789 * update since init path would reset
7792 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7793 bi << CFPREP_CBI_SHIFT);
7795 /* Update maccontrol PM related bits */
7796 brcms_c_set_ps_ctrl(wlc);
7799 brcms_c_bandinit_ordered(wlc, chanspec);
7801 /* init probe response timeout */
7802 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7804 /* init max burst txop (framebursting) */
7805 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7807 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7809 /* initialize maximum allowed duty cycle */
7810 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7811 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7814 * Update some shared memory locations related to
7815 * max AMPDU size allowed to received
7817 brcms_c_ampdu_shm_upd(wlc->ampdu);
7819 /* band-specific inits */
7820 brcms_c_bsinit(wlc);
7822 /* Enable EDCF mode (while the MAC is suspended) */
7823 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7824 brcms_c_edcf_setparams(wlc, false);
7826 /* read the ucode version if we have not yet done so */
7827 if (wlc->ucode_rev == 0) {
7829 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
7830 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7833 /* ..now really unleash hell (allow the MAC out of suspend) */
7834 brcms_c_enable_mac(wlc);
7836 /* suspend the tx fifos and mute the phy for preism cac time */
7838 brcms_b_mute(wlc->hw, true);
7840 /* enable the RF Disable Delay timer */
7841 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7844 * Initialize WME parameters; if they haven't been set by some other
7845 * mechanism (IOVar, etc) then read them from the hardware.
7847 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7848 /* Uninitialized; read from HW */
7851 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7852 wlc->wme_retries[ac] =
7853 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7858 * The common driver entry routine. Error codes should be unique
7860 struct brcms_c_info *
7861 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7862 bool piomode, uint *perr)
7864 struct brcms_c_info *wlc;
7867 struct brcms_pub *pub;
7869 /* allocate struct brcms_c_info state and its substructures */
7870 wlc = brcms_c_attach_malloc(unit, &err, 0);
7873 wlc->wiphy = wl->wiphy;
7880 wlc->band = wlc->bandstate[0];
7881 wlc->core = wlc->corestate;
7884 pub->_piomode = piomode;
7885 wlc->bandinit_pending = false;
7887 /* populate struct brcms_c_info with default values */
7888 brcms_c_info_init(wlc, unit);
7890 /* update sta/ap related parameters */
7891 brcms_c_ap_upd(wlc);
7894 * low level attach steps(all hw accesses go
7895 * inside, no more in rest of the attach)
7897 err = brcms_b_attach(wlc, core, unit, piomode);
7901 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7903 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7905 /* disable allowed duty cycle */
7906 wlc->tx_duty_cycle_ofdm = 0;
7907 wlc->tx_duty_cycle_cck = 0;
7909 brcms_c_stf_phy_chain_calc(wlc);
7911 /* txchain 1: txant 0, txchain 2: txant 1 */
7912 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7913 wlc->stf->txant = wlc->stf->hw_txchain - 1;
7915 /* push to BMAC driver */
7916 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7917 wlc->stf->hw_rxchain);
7919 /* pull up some info resulting from the low attach */
7920 for (i = 0; i < NFIFO; i++)
7921 wlc->core->txavail[i] = wlc->hw->txavail[i];
7923 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7924 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7926 for (j = 0; j < wlc->pub->_nbands; j++) {
7927 wlc->band = wlc->bandstate[j];
7929 if (!brcms_c_attach_stf_ant_init(wlc)) {
7934 /* default contention windows size limits */
7935 wlc->band->CWmin = APHY_CWMIN;
7936 wlc->band->CWmax = PHY_CWMAX;
7938 /* init gmode value */
7939 if (wlc->band->bandtype == BRCM_BAND_2G) {
7940 wlc->band->gmode = GMODE_AUTO;
7941 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7945 /* init _n_enab supported mode */
7946 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7947 pub->_n_enab = SUPPORT_11N;
7948 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7950 SUPPORT_11N) ? WL_11N_2x2 :
7954 /* init per-band default rateset, depend on band->gmode */
7955 brcms_default_rateset(wlc, &wlc->band->defrateset);
7957 /* fill in hw_rateset */
7958 brcms_c_rateset_filter(&wlc->band->defrateset,
7959 &wlc->band->hw_rateset, false,
7960 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
7961 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
7965 * update antenna config due to
7966 * wlc->stf->txant/txchain/ant_rx_ovr change
7968 brcms_c_stf_phy_txant_upd(wlc);
7970 /* attach each modules */
7971 err = brcms_c_attach_module(wlc);
7975 if (!brcms_c_timers_init(wlc, unit)) {
7976 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
7982 /* depend on rateset, gmode */
7983 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
7985 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
7986 "\n", unit, __func__);
7991 /* init default when all parameters are ready, i.e. ->rateset */
7992 brcms_c_bss_default_init(wlc);
7995 * Complete the wlc default state initializations..
7998 wlc->bsscfg->wlc = wlc;
8000 wlc->mimoft = FT_HT;
8001 wlc->mimo_40txbw = AUTO;
8002 wlc->ofdm_40txbw = AUTO;
8003 wlc->cck_40txbw = AUTO;
8004 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8006 /* Set default values of SGI */
8007 if (BRCMS_SGI_CAP_PHY(wlc)) {
8008 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8010 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8011 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8014 brcms_c_ht_update_sgi_rx(wlc, 0);
8017 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8025 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8026 unit, __func__, err);
8028 brcms_c_detach(wlc);