2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
39 #include "brcms_trace_events.h"
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG 1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK 800
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT 100
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52 * control it independently
58 #define EDCF_ACI_MASK 0x60
59 #define EDCF_ACI_SHIFT 5
60 #define EDCF_ECWMIN_MASK 0x0f
61 #define EDCF_ECWMAX_SHIFT 4
62 #define EDCF_AIFSN_MASK 0x0f
63 #define EDCF_AIFSN_MAX 15
64 #define EDCF_ECWMAX_MASK 0xf0
66 #define EDCF_AC_BE_TXOP_STA 0x0000
67 #define EDCF_AC_BK_TXOP_STA 0x0000
68 #define EDCF_AC_VO_ACI_STA 0x62
69 #define EDCF_AC_VO_ECW_STA 0x32
70 #define EDCF_AC_VI_ACI_STA 0x42
71 #define EDCF_AC_VI_ECW_STA 0x43
72 #define EDCF_AC_BK_ECW_STA 0xA4
73 #define EDCF_AC_VI_TXOP_STA 0x005e
74 #define EDCF_AC_VO_TXOP_STA 0x002f
75 #define EDCF_AC_BE_ACI_STA 0x03
76 #define EDCF_AC_BE_ECW_STA 0xA4
77 #define EDCF_AC_BK_ACI_STA 0x27
78 #define EDCF_AC_VO_TXOP_AP 0x002f
80 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
81 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83 #define APHY_SYMBOL_TIME 4
84 #define APHY_PREAMBLE_TIME 16
85 #define APHY_SIGNAL_TIME 4
86 #define APHY_SIFS_TIME 16
87 #define APHY_SERVICE_NBITS 16
88 #define APHY_TAIL_NBITS 6
89 #define BPHY_SIFS_TIME 10
90 #define BPHY_PLCP_SHORT_TIME 96
92 #define PREN_PREAMBLE 24
93 #define PREN_MM_EXT 12
94 #define PREN_PREAMBLE_EXT 4
96 #define DOT11_MAC_HDR_LEN 24
97 #define DOT11_ACK_LEN 10
98 #define DOT11_BA_LEN 4
99 #define DOT11_OFDM_SIGNAL_EXTENSION 6
100 #define DOT11_MIN_FRAG_LEN 256
101 #define DOT11_RTS_LEN 16
102 #define DOT11_CTS_LEN 10
103 #define DOT11_BA_BITMAP_LEN 128
104 #define DOT11_MAXNUMFRAGS 16
105 #define DOT11_MAX_FRAG_LEN 2346
107 #define BPHY_PLCP_TIME 192
108 #define RIFS_11N_TIME 2
110 /* length of the BCN template area */
111 #define BCN_TMPL_LEN 512
113 /* brcms_bss_info flag bit values */
114 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
116 /* chip rx buffer offset */
117 #define BRCMS_HWRXOFF 38
119 /* rfdisable delay timer 500 ms, runs of ALP clock */
120 #define RFDISABLE_DEFAULT 10000000
122 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
124 /* synthpu_dly times in us */
125 #define SYNTHPU_DLY_APHY_US 3700
126 #define SYNTHPU_DLY_BPHY_US 1050
127 #define SYNTHPU_DLY_NPHY_US 2048
128 #define SYNTHPU_DLY_LPPHY_US 300
130 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
132 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
133 #define EDCF_SHORT_S 0
135 #define EDCF_LONG_S 8
136 #define EDCF_LFB_S 12
137 #define EDCF_SHORT_M BITFIELD_MASK(4)
138 #define EDCF_SFB_M BITFIELD_MASK(4)
139 #define EDCF_LONG_M BITFIELD_MASK(4)
140 #define EDCF_LFB_M BITFIELD_MASK(4)
142 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
143 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
144 #define RETRY_LONG_DEF 4 /* Default Long retry count */
145 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
146 #define RETRY_LONG_FB 2 /* Long count for fb rate */
148 #define APHY_CWMIN 15
149 #define PHY_CWMAX 1023
151 #define EDCF_AIFSN_MIN 1
153 #define FRAGNUM_MASK 0xF
155 #define APHY_SLOT_TIME 9
156 #define BPHY_SLOT_TIME 20
158 #define WL_SPURAVOID_OFF 0
159 #define WL_SPURAVOID_ON1 1
160 #define WL_SPURAVOID_ON2 2
162 /* invalid core flags, use the saved coreflags */
163 #define BRCMS_USE_COREFLAGS 0xffffffff
165 /* values for PLCPHdr_override */
166 #define BRCMS_PLCP_AUTO -1
167 #define BRCMS_PLCP_SHORT 0
168 #define BRCMS_PLCP_LONG 1
170 /* values for g_protection_override and n_protection_override */
171 #define BRCMS_PROTECTION_AUTO -1
172 #define BRCMS_PROTECTION_OFF 0
173 #define BRCMS_PROTECTION_ON 1
174 #define BRCMS_PROTECTION_MMHDR_ONLY 2
175 #define BRCMS_PROTECTION_CTS_ONLY 3
177 /* values for g_protection_control and n_protection_control */
178 #define BRCMS_PROTECTION_CTL_OFF 0
179 #define BRCMS_PROTECTION_CTL_LOCAL 1
180 #define BRCMS_PROTECTION_CTL_OVERLAP 2
182 /* values for n_protection */
183 #define BRCMS_N_PROTECTION_OFF 0
184 #define BRCMS_N_PROTECTION_OPTIONAL 1
185 #define BRCMS_N_PROTECTION_20IN40 2
186 #define BRCMS_N_PROTECTION_MIXEDMODE 3
188 /* values for band specific 40MHz capabilities */
189 #define BRCMS_N_BW_20ALL 0
190 #define BRCMS_N_BW_40ALL 1
191 #define BRCMS_N_BW_20IN2G_40IN5G 2
193 /* bitflags for SGI support (sgi_rx iovar) */
194 #define BRCMS_N_SGI_20 0x01
195 #define BRCMS_N_SGI_40 0x02
197 /* defines used by the nrate iovar */
198 /* MSC in use,indicates b0-6 holds an mcs */
199 #define NRATE_MCS_INUSE 0x00000080
201 #define NRATE_RATE_MASK 0x0000007f
202 /* stf mode mask: siso, cdd, stbc, sdm */
203 #define NRATE_STF_MASK 0x0000ff00
205 #define NRATE_STF_SHIFT 8
206 /* bit indicate to override mcs only */
207 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
208 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
209 #define NRATE_SGI_SHIFT 23 /* sgi mode */
210 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
211 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
213 #define NRATE_STF_SISO 0 /* stf mode SISO */
214 #define NRATE_STF_CDD 1 /* stf mode CDD */
215 #define NRATE_STF_STBC 2 /* stf mode STBC */
216 #define NRATE_STF_SDM 3 /* stf mode SDM */
218 #define MAX_DMA_SEGS 4
220 /* # of entries in Tx FIFO */
222 /* Max # of entries in Rx FIFO based on 4kb page size */
225 /* Amount of headroom to leave in Tx FIFO */
226 #define TX_HEADROOM 4
228 /* try to keep this # rbufs posted to the chip */
229 #define NRXBUFPOST 32
231 /* max # frames to process in brcms_c_recv() */
233 /* max # tx status to process in wlc_txstatus() */
236 /* brcmu_format_flags() bit description structure */
237 struct brcms_c_bit_desc {
243 * The following table lists the buffer memory allocated to xmt fifos in HW.
244 * the size is in units of 256bytes(one block), total size is HW dependent
245 * ucode has default fifo partition, sw can overwrite if necessary
247 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
248 * the twiki is updated before making changes.
251 /* Starting corerev for the fifo size table */
252 #define XMTFIFOTBL_STARTREV 17
260 struct edcf_acparam {
269 /* TX FIFO number to WME/802.1E Access Category */
270 static const u8 wme_fifo2ac[] = {
279 /* ieee80211 Access Category to TX FIFO number */
280 static const u8 wme_ac2fifo[] = {
287 static const u16 xmtfifo_sz[][NFIFO] = {
288 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
289 {20, 192, 192, 21, 17, 5},
294 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
295 {20, 192, 192, 21, 17, 5},
296 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
297 {9, 58, 22, 14, 14, 5},
298 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
299 {20, 192, 192, 21, 17, 5},
300 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
301 {20, 192, 192, 21, 17, 5},
302 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
303 {9, 58, 22, 14, 14, 5},
310 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
311 {9, 58, 22, 14, 14, 5},
315 static const char * const fifo_names[] = {
316 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
318 static const char fifo_names[6][0];
322 /* pointer to most recently allocated wl/wlc */
323 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
326 /* Mapping of ieee80211 AC numbers to tx fifos */
327 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
328 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
329 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
330 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
331 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
334 /* Mapping of tx fifos to ieee80211 AC numbers */
335 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
336 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
337 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
338 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
339 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
342 static u8 brcms_ac_to_fifo(u8 ac)
344 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
345 return TX_AC_BE_FIFO;
346 return ac_to_fifo_mapping[ac];
349 static u8 brcms_fifo_to_ac(u8 fifo)
351 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
352 return IEEE80211_AC_BE;
353 return fifo_to_ac_mapping[fifo];
356 /* Find basic rate for a given rate */
357 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
359 if (is_mcs_rate(rspec))
360 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
362 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
365 static u16 frametype(u32 rspec, u8 mimoframe)
367 if (is_mcs_rate(rspec))
369 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
372 /* currently the best mechanism for determining SIFS is the band in use */
373 static u16 get_sifs(struct brcms_band *band)
375 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
380 * Detect Card removed.
381 * Even checking an sbconfig register read will not false trigger when the core
382 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
383 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
384 * reg with fixed 0/1 pattern (some platforms return all 0).
385 * If clocks are present, call the sb routine which will figure out if the
388 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
393 return ai_deviceremoved(wlc->hw->sih);
394 macctrl = bcma_read32(wlc->hw->d11core,
395 D11REGOFFS(maccontrol));
396 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
399 /* sum the individual fifo tx pending packet counts */
400 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
405 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
407 pending += dma_txpending(wlc->hw->di[i]);
411 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
413 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
416 static int brcms_chspec_bw(u16 chanspec)
418 if (CHSPEC_IS40(chanspec))
420 if (CHSPEC_IS20(chanspec))
426 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
431 kfree(cfg->current_bss);
435 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
440 brcms_c_bsscfg_mfree(wlc->bsscfg);
442 kfree(wlc->modulecb);
443 kfree(wlc->default_bss);
444 kfree(wlc->protection);
446 kfree(wlc->bandstate[0]);
447 kfree(wlc->corestate->macstat_snapshot);
448 kfree(wlc->corestate);
449 kfree(wlc->hw->bandstate[0]);
457 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
459 struct brcms_bss_cfg *cfg;
461 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
465 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
466 if (cfg->current_bss == NULL)
472 brcms_c_bsscfg_mfree(cfg);
476 static struct brcms_c_info *
477 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
479 struct brcms_c_info *wlc;
481 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
487 /* allocate struct brcms_c_pub state structure */
488 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
489 if (wlc->pub == NULL) {
495 /* allocate struct brcms_hardware state structure */
497 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
498 if (wlc->hw == NULL) {
504 wlc->hw->bandstate[0] =
505 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
506 if (wlc->hw->bandstate[0] == NULL) {
512 for (i = 1; i < MAXBANDS; i++)
513 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
514 ((unsigned long)wlc->hw->bandstate[0] +
515 (sizeof(struct brcms_hw_band) * i));
519 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
520 if (wlc->modulecb == NULL) {
525 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
526 if (wlc->default_bss == NULL) {
531 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
532 if (wlc->bsscfg == NULL) {
537 wlc->protection = kzalloc(sizeof(struct brcms_protection),
539 if (wlc->protection == NULL) {
544 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
545 if (wlc->stf == NULL) {
551 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
552 if (wlc->bandstate[0] == NULL) {
558 for (i = 1; i < MAXBANDS; i++)
559 wlc->bandstate[i] = (struct brcms_band *)
560 ((unsigned long)wlc->bandstate[0]
561 + (sizeof(struct brcms_band)*i));
564 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
565 if (wlc->corestate == NULL) {
570 wlc->corestate->macstat_snapshot =
571 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
572 if (wlc->corestate->macstat_snapshot == NULL) {
580 brcms_c_detach_mfree(wlc);
585 * Update the slot timing for standard 11b/g (20us slots)
586 * or shortslot 11g (9us slots)
587 * The PSM needs to be suspended for this call.
589 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
592 struct bcma_device *core = wlc_hw->d11core;
595 /* 11g short slot: 11a timing */
596 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
597 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
599 /* 11g long slot: 11b timing */
600 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
601 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
606 * calculate frame duration of a given rate and length, return
609 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
610 u8 preamble_type, uint mac_len)
612 uint nsyms, dur = 0, Ndps, kNdps;
613 uint rate = rspec2rate(ratespec);
616 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
621 if (is_mcs_rate(ratespec)) {
622 uint mcs = ratespec & RSPEC_RATE_MASK;
623 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
625 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
626 if (preamble_type == BRCMS_MM_PREAMBLE)
628 /* 1000Ndbps = kbps * 4 */
629 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
630 rspec_issgi(ratespec)) * 4;
632 if (rspec_stc(ratespec) == 0)
634 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
635 APHY_TAIL_NBITS) * 1000, kNdps);
637 /* STBC needs to have even number of symbols */
640 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
641 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
643 dur += APHY_SYMBOL_TIME * nsyms;
644 if (wlc->band->bandtype == BRCM_BAND_2G)
645 dur += DOT11_OFDM_SIGNAL_EXTENSION;
646 } else if (is_ofdm_rate(rate)) {
647 dur = APHY_PREAMBLE_TIME;
648 dur += APHY_SIGNAL_TIME;
649 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
651 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
653 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
655 dur += APHY_SYMBOL_TIME * nsyms;
656 if (wlc->band->bandtype == BRCM_BAND_2G)
657 dur += DOT11_OFDM_SIGNAL_EXTENSION;
660 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
663 mac_len = mac_len * 8 * 2;
664 /* calc ceiling of bits/rate = microseconds of air time */
665 dur = (mac_len + rate - 1) / rate;
666 if (preamble_type & BRCMS_SHORT_PREAMBLE)
667 dur += BPHY_PLCP_SHORT_TIME;
669 dur += BPHY_PLCP_TIME;
674 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
675 const struct d11init *inits)
677 struct bcma_device *core = wlc_hw->d11core;
683 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
685 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
686 size = le16_to_cpu(inits[i].size);
687 offset = le16_to_cpu(inits[i].addr);
688 value = le32_to_cpu(inits[i].value);
690 bcma_write16(core, offset, value);
692 bcma_write32(core, offset, value);
698 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
702 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
706 for (idx = 0; idx < MHFMAX; idx++)
707 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
710 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
712 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
714 /* init microcode host flags */
715 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
717 /* do band-specific ucode IHR, SHM, and SCR inits */
718 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
719 if (BRCMS_ISNPHY(wlc_hw->band))
720 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
722 brcms_err(wlc_hw->d11core,
723 "%s: wl%d: unsupported phy in corerev %d\n",
724 __func__, wlc_hw->unit,
727 if (D11REV_IS(wlc_hw->corerev, 24)) {
728 if (BRCMS_ISLCNPHY(wlc_hw->band))
729 brcms_c_write_inits(wlc_hw,
730 ucode->d11lcn0bsinitvals24);
732 brcms_err(wlc_hw->d11core,
733 "%s: wl%d: unsupported phy in core rev %d\n",
734 __func__, wlc_hw->unit,
737 brcms_err(wlc_hw->d11core,
738 "%s: wl%d: unsupported corerev %d\n",
739 __func__, wlc_hw->unit, wlc_hw->corerev);
744 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
746 struct bcma_device *core = wlc_hw->d11core;
747 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
749 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
752 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
754 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
756 wlc_hw->phyclk = clk;
758 if (OFF == clk) { /* clear gmode bit, put phy into reset */
760 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
761 (SICF_PRST | SICF_FGC));
763 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
766 } else { /* take phy out of reset */
768 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
770 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
776 /* low-level band switch utility routine */
777 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
779 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
782 wlc_hw->band = wlc_hw->bandstate[bandunit];
786 * until we eliminate need for wlc->band refs in low level code
788 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
790 /* set gmode core flag */
791 if (wlc_hw->sbclk && !wlc_hw->noreset) {
797 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
801 /* switch to new band but leave it inactive */
802 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
804 struct brcms_hardware *wlc_hw = wlc->hw;
808 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
809 macctrl = bcma_read32(wlc_hw->d11core,
810 D11REGOFFS(maccontrol));
811 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
813 /* disable interrupts */
814 macintmask = brcms_intrsoff(wlc->wl);
817 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
819 brcms_b_core_phy_clk(wlc_hw, OFF);
821 brcms_c_setxband(wlc_hw, bandunit);
826 /* process an individual struct tx_status */
828 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
830 struct sk_buff *p = NULL;
832 struct dma_pub *dma = NULL;
833 struct d11txh *txh = NULL;
834 struct scb *scb = NULL;
836 int tx_rts, tx_frame_count, tx_rts_count;
837 uint totlen, supr_status;
839 struct ieee80211_hdr *h;
841 struct ieee80211_tx_info *tx_info;
842 struct ieee80211_tx_rate *txrate;
846 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
847 txs->frameid, txs->status, txs->lasttxtime,
848 txs->sequence, txs->phyerr, txs->ackphyrxsh);
850 /* discard intermediate indications for ucode with one legitimate case:
851 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
852 * but the subsequent tx of DATA failed. so it will start rts/cts
853 * from the beginning (resetting the rts transmission count)
855 if (!(txs->status & TX_STATUS_AMPDU)
856 && (txs->status & TX_STATUS_INTERMEDIATE)) {
857 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
862 queue = txs->frameid & TXFID_QUEUE_MASK;
863 if (queue >= NFIFO) {
864 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
868 dma = wlc->hw->di[queue];
870 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
872 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
876 txh = (struct d11txh *) (p->data);
877 mcl = le16_to_cpu(txh->MacTxControlLow);
880 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
881 txs->phyerr, txh->MainRates);
883 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
884 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
887 tx_info = IEEE80211_SKB_CB(p);
888 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
890 if (tx_info->rate_driver_data[0])
893 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
894 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
900 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
901 * frames; this traces them for the rest.
903 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
905 supr_status = txs->status & TX_STATUS_SUPR_MASK;
906 if (supr_status == TX_STATUS_SUPR_BADCH) {
907 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
908 brcms_dbg_tx(wlc->hw->d11core,
909 "Pkt tx suppressed, dest chan %u, current %d\n",
910 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
911 CHSPEC_CHANNEL(wlc->default_bss->chanspec));
914 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
916 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
918 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
920 lastframe = !ieee80211_has_morefrags(h->frame_control);
923 brcms_err(wlc->hw->d11core, "Not last frame!\n");
926 * Set information to be consumed by Minstrel ht.
928 * The "fallback limit" is the number of tx attempts a given
929 * MPDU is sent at the "primary" rate. Tx attempts beyond that
930 * limit are sent at the "secondary" rate.
931 * A 'short frame' does not exceed RTS treshold.
933 u16 sfbl, /* Short Frame Rate Fallback Limit */
934 lfbl, /* Long Frame Rate Fallback Limit */
937 if (queue < IEEE80211_NUM_ACS) {
938 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
940 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
947 txrate = tx_info->status.rates;
948 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
953 ieee80211_tx_info_clear_status(tx_info);
955 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
957 * rate selection requested a fallback rate
960 txrate[0].count = fbl;
961 txrate[1].count = tx_frame_count - fbl;
964 * rate selection did not request fallback rate, or
967 txrate[0].count = tx_frame_count;
969 * rc80211_minstrel.c:minstrel_tx_status() expects
970 * unused rates to be marked with idx = -1
976 /* clear the rest of the rates */
977 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
982 if (txs->status & TX_STATUS_ACK_RCV)
983 tx_info->flags |= IEEE80211_TX_STAT_ACK;
990 /* remove PLCP & Broadcom tx descriptor header */
991 skb_pull(p, D11_PHY_HDR_LEN);
992 skb_pull(p, D11_TXH_LEN);
993 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
995 brcms_err(wlc->hw->d11core,
996 "%s: Not last frame => not calling tx_status\n",
1005 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1008 brcmu_pkt_buf_free_skb(p);
1011 if (dma && queue < NFIFO) {
1012 u16 ac_queue = brcms_fifo_to_ac(queue);
1013 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1014 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1015 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1022 /* process tx completion events in BMAC
1023 * Return true if more tx status need to be processed. false otherwise.
1026 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1028 struct bcma_device *core;
1029 struct tx_status txstatus, *txs;
1033 * Param 'max_tx_num' indicates max. # tx status to process before
1036 uint max_tx_num = bound ? TXSBND : -1;
1039 core = wlc_hw->d11core;
1042 while (n < max_tx_num) {
1043 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1044 if (s1 == 0xffffffff) {
1045 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1050 /* only process when valid */
1054 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1055 txs->status = s1 & TXS_STATUS_MASK;
1056 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1057 txs->sequence = s2 & TXS_SEQ_MASK;
1058 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1059 txs->lasttxtime = 0;
1061 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1067 return n >= max_tx_num;
1070 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1072 if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1074 * DirFrmQ is now valid...defer setting until end
1077 wlc->qvalid |= MCMD_DIRFRMQVAL;
1080 /* set initial host flags value */
1082 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1084 struct brcms_hardware *wlc_hw = wlc->hw;
1086 memset(mhfs, 0, MHFMAX * sizeof(u16));
1088 mhfs[MHF2] |= mhf2_init;
1090 /* prohibit use of slowclock on multifunction boards */
1091 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1092 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1094 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1095 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1096 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1101 dmareg(uint direction, uint fifonum)
1103 if (direction == DMA_TX)
1104 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1105 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1108 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1113 * ucode host flag 2 needed for pio mode, independent of band and fifo
1116 struct brcms_hardware *wlc_hw = wlc->hw;
1117 uint unit = wlc_hw->unit;
1119 /* name and offsets for dma_attach */
1120 snprintf(name, sizeof(name), "wl%d", unit);
1122 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1123 int dma_attach_err = 0;
1127 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1128 * RX: RX_FIFO (RX data packets)
1130 wlc_hw->di[0] = dma_attach(name, wlc,
1131 (wme ? dmareg(DMA_TX, 0) : 0),
1133 (wme ? NTXD : 0), NRXD,
1134 RXBUFSZ, -1, NRXBUFPOST,
1136 dma_attach_err |= (NULL == wlc_hw->di[0]);
1140 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1141 * (legacy) TX_DATA_FIFO (TX data packets)
1144 wlc_hw->di[1] = dma_attach(name, wlc,
1145 dmareg(DMA_TX, 1), 0,
1146 NTXD, 0, 0, -1, 0, 0);
1147 dma_attach_err |= (NULL == wlc_hw->di[1]);
1151 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1154 wlc_hw->di[2] = dma_attach(name, wlc,
1155 dmareg(DMA_TX, 2), 0,
1156 NTXD, 0, 0, -1, 0, 0);
1157 dma_attach_err |= (NULL == wlc_hw->di[2]);
1160 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1161 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1163 wlc_hw->di[3] = dma_attach(name, wlc,
1167 dma_attach_err |= (NULL == wlc_hw->di[3]);
1168 /* Cleaner to leave this as if with AP defined */
1170 if (dma_attach_err) {
1171 brcms_err(wlc_hw->d11core,
1172 "wl%d: wlc_attach: dma_attach failed\n",
1177 /* get pointer to dma engine tx flow control variable */
1178 for (i = 0; i < NFIFO; i++)
1180 wlc_hw->txavail[i] =
1181 (uint *) dma_getvar(wlc_hw->di[i],
1185 /* initial ucode host flags */
1186 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1191 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1195 for (j = 0; j < NFIFO; j++) {
1196 if (wlc_hw->di[j]) {
1197 dma_detach(wlc_hw->di[j]);
1198 wlc_hw->di[j] = NULL;
1204 * Initialize brcms_c_info default values ...
1205 * may get overrides later in this function
1206 * BMAC_NOTES, move low out and resolve the dangling ones
1208 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1210 struct brcms_c_info *wlc = wlc_hw->wlc;
1212 /* set default sw macintmask value */
1213 wlc->defmacintmask = DEF_MACINTMASK;
1215 /* various 802.11g modes */
1216 wlc_hw->shortslot = false;
1218 wlc_hw->SFBL = RETRY_SHORT_FB;
1219 wlc_hw->LFBL = RETRY_LONG_FB;
1221 /* default mac retry limits */
1222 wlc_hw->SRL = RETRY_SHORT_DEF;
1223 wlc_hw->LRL = RETRY_LONG_DEF;
1224 wlc_hw->chanspec = ch20mhz_chspec(1);
1227 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1229 /* delay before first read of ucode state */
1232 /* wait until ucode is no longer asleep */
1233 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1234 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1237 /* control chip clock to save power, enable dynamic clock or force fast clock */
1238 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1240 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1241 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1242 * on backplane, but mac core will still run on ALP(not HT) when
1243 * it enters powersave mode, which means the FCA bit may not be
1244 * set. Should wakeup mac if driver wants it to run on HT.
1248 if (mode == BCMA_CLKMODE_FAST) {
1249 bcma_set32(wlc_hw->d11core,
1250 D11REGOFFS(clk_ctl_st),
1256 ((bcma_read32(wlc_hw->d11core,
1257 D11REGOFFS(clk_ctl_st)) &
1259 PMU_MAX_TRANSITION_DLY);
1260 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1261 D11REGOFFS(clk_ctl_st)) &
1264 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1265 (bcma_read32(wlc_hw->d11core,
1266 D11REGOFFS(clk_ctl_st)) &
1267 (CCS_FORCEHT | CCS_HTAREQ)))
1269 ((bcma_read32(wlc_hw->d11core,
1270 offsetof(struct d11regs,
1273 PMU_MAX_TRANSITION_DLY);
1274 bcma_mask32(wlc_hw->d11core,
1275 D11REGOFFS(clk_ctl_st),
1279 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1282 /* old chips w/o PMU, force HT through cc,
1283 * then use FCA to verify mac is running fast clock
1286 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1288 /* check fast clock is available (if core is not in reset) */
1289 if (wlc_hw->forcefastclk && wlc_hw->clk)
1290 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1294 * keep the ucode wake bit on if forcefastclk is on since we
1295 * do not want ucode to put us back to slow clock when it dozes
1296 * for PM mode. Code below matches the wake override bit with
1297 * current forcefastclk state. Only setting bit in wake_override
1298 * instead of waking ucode immediately since old code had this
1299 * behavior. Older code set wlc->forcefastclk but only had the
1300 * wake happen if the wakup_ucode work (protected by an up
1301 * check) was executed just below.
1303 if (wlc_hw->forcefastclk)
1304 mboolset(wlc_hw->wake_override,
1305 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1307 mboolclr(wlc_hw->wake_override,
1308 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1312 /* set or clear ucode host flag bits
1313 * it has an optimization for no-change write
1314 * it only writes through shared memory when the core has clock;
1315 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1318 * bands values are: BRCM_BAND_AUTO <--- Current band only
1319 * BRCM_BAND_5G <--- 5G band only
1320 * BRCM_BAND_2G <--- 2G band only
1321 * BRCM_BAND_ALL <--- All bands
1324 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1328 u16 addr[MHFMAX] = {
1329 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1332 struct brcms_hw_band *band;
1334 if ((val & ~mask) || idx >= MHFMAX)
1335 return; /* error condition */
1338 /* Current band only or all bands,
1339 * then set the band to current band
1341 case BRCM_BAND_AUTO:
1343 band = wlc_hw->band;
1346 band = wlc_hw->bandstate[BAND_5G_INDEX];
1349 band = wlc_hw->bandstate[BAND_2G_INDEX];
1352 band = NULL; /* error condition */
1356 save = band->mhfs[idx];
1357 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1359 /* optimization: only write through if changed, and
1360 * changed band is the current band
1362 if (wlc_hw->clk && (band->mhfs[idx] != save)
1363 && (band == wlc_hw->band))
1364 brcms_b_write_shm(wlc_hw, addr[idx],
1365 (u16) band->mhfs[idx]);
1368 if (bands == BRCM_BAND_ALL) {
1369 wlc_hw->bandstate[0]->mhfs[idx] =
1370 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1371 wlc_hw->bandstate[1]->mhfs[idx] =
1372 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1376 /* set the maccontrol register to desired reset state and
1377 * initialize the sw cache of the register
1379 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1381 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1382 wlc_hw->maccontrol = 0;
1383 wlc_hw->suspended_fifos = 0;
1384 wlc_hw->wake_override = 0;
1385 wlc_hw->mute_override = 0;
1386 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1390 * write the software state of maccontrol and
1391 * overrides to the maccontrol register
1393 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1395 u32 maccontrol = wlc_hw->maccontrol;
1397 /* OR in the wake bit if overridden */
1398 if (wlc_hw->wake_override)
1399 maccontrol |= MCTL_WAKE;
1401 /* set AP and INFRA bits for mute if needed */
1402 if (wlc_hw->mute_override) {
1403 maccontrol &= ~(MCTL_AP);
1404 maccontrol |= MCTL_INFRA;
1407 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1411 /* set or clear maccontrol bits */
1412 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1418 return; /* error condition */
1419 maccontrol = wlc_hw->maccontrol;
1420 new_maccontrol = (maccontrol & ~mask) | val;
1422 /* if the new maccontrol value is the same as the old, nothing to do */
1423 if (new_maccontrol == maccontrol)
1426 /* something changed, cache the new value */
1427 wlc_hw->maccontrol = new_maccontrol;
1429 /* write the new values with overrides applied */
1430 brcms_c_mctrl_write(wlc_hw);
1433 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1436 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1437 mboolset(wlc_hw->wake_override, override_bit);
1441 mboolset(wlc_hw->wake_override, override_bit);
1443 brcms_c_mctrl_write(wlc_hw);
1444 brcms_b_wait_for_wake(wlc_hw);
1447 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1450 mboolclr(wlc_hw->wake_override, override_bit);
1452 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1455 brcms_c_mctrl_write(wlc_hw);
1458 /* When driver needs ucode to stop beaconing, it has to make sure that
1459 * MCTL_AP is clear and MCTL_INFRA is set
1460 * Mode MCTL_AP MCTL_INFRA
1462 * STA 0 1 <--- This will ensure no beacons
1465 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1467 wlc_hw->mute_override = 1;
1469 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1470 * override, then there is no change to write
1472 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1475 brcms_c_mctrl_write(wlc_hw);
1478 /* Clear the override on AP and INFRA bits */
1479 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1481 if (wlc_hw->mute_override == 0)
1484 wlc_hw->mute_override = 0;
1486 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1487 * override, then there is no change to write
1489 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1492 brcms_c_mctrl_write(wlc_hw);
1496 * Write a MAC address to the given match reg offset in the RXE match engine.
1499 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1502 struct bcma_device *core = wlc_hw->d11core;
1507 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1509 mac_l = addr[0] | (addr[1] << 8);
1510 mac_m = addr[2] | (addr[3] << 8);
1511 mac_h = addr[4] | (addr[5] << 8);
1513 /* enter the MAC addr into the RXE match registers */
1514 bcma_write16(core, D11REGOFFS(rcm_ctl),
1515 RCM_INC_DATA | match_reg_offset);
1516 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1517 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1518 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1522 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1525 struct bcma_device *core = wlc_hw->d11core;
1530 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1532 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1534 /* if MCTL_BIGEND bit set in mac control register,
1535 * the chip swaps data in fifo, as well as data in
1538 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1541 memcpy(&word, buf, sizeof(u32));
1544 word_be = cpu_to_be32(word);
1545 word = *(u32 *)&word_be;
1547 word_le = cpu_to_le32(word);
1548 word = *(u32 *)&word_le;
1551 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1553 buf = (u8 *) buf + sizeof(u32);
1558 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1560 wlc_hw->band->CWmin = newmin;
1562 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1563 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1564 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1565 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1568 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1570 wlc_hw->band->CWmax = newmax;
1572 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1573 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1574 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1575 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1578 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1582 /* request FAST clock if not on */
1583 fastclk = wlc_hw->forcefastclk;
1585 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1587 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1589 brcms_b_phy_reset(wlc_hw);
1590 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1592 /* restore the clk */
1594 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1597 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1600 struct brcms_c_info *wlc = wlc_hw->wlc;
1601 /* update SYNTHPU_DLY */
1603 if (BRCMS_ISLCNPHY(wlc->band))
1604 v = SYNTHPU_DLY_LPPHY_US;
1605 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1606 v = SYNTHPU_DLY_NPHY_US;
1608 v = SYNTHPU_DLY_BPHY_US;
1610 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1613 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1616 u16 phytxant = wlc_hw->bmac_phytxant;
1617 u16 mask = PHY_TXC_ANT_MASK;
1619 /* set the Probe Response frame phy control word */
1620 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1621 phyctl = (phyctl & ~mask) | phytxant;
1622 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1624 /* set the Response (ACK/CTS) frame phy control word */
1625 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1626 phyctl = (phyctl & ~mask) | phytxant;
1627 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1630 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1635 struct plcp_signal_rate_lookup {
1639 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1640 const struct plcp_signal_rate_lookup rate_lookup[] = {
1641 {BRCM_RATE_6M, 0xB},
1642 {BRCM_RATE_9M, 0xF},
1643 {BRCM_RATE_12M, 0xA},
1644 {BRCM_RATE_18M, 0xE},
1645 {BRCM_RATE_24M, 0x9},
1646 {BRCM_RATE_36M, 0xD},
1647 {BRCM_RATE_48M, 0x8},
1648 {BRCM_RATE_54M, 0xC}
1651 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1652 if (rate == rate_lookup[i].rate) {
1653 plcp_rate = rate_lookup[i].signal_rate;
1658 /* Find the SHM pointer to the rate table entry by looking in the
1661 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1664 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1668 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1669 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1675 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1678 /* walk the phy rate table and update the entries */
1679 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1682 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1684 /* read the SHM Rate Table entry OFDM PCTL1 values */
1686 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1688 /* modify the value */
1689 pctl1 &= ~PHY_TXC1_MODE_MASK;
1690 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1692 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1693 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1698 /* band-specific init */
1699 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1701 struct brcms_hardware *wlc_hw = wlc->hw;
1703 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1704 wlc_hw->band->bandunit);
1706 brcms_c_ucode_bsinit(wlc_hw);
1708 wlc_phy_init(wlc_hw->band->pi, chanspec);
1710 brcms_c_ucode_txant_set(wlc_hw);
1713 * cwmin is band-specific, update hardware
1714 * with value for current band
1716 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1717 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1719 brcms_b_update_slot_timing(wlc_hw,
1720 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1721 true : wlc_hw->shortslot);
1723 /* write phytype and phyvers */
1724 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1725 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1728 * initialize the txphyctl1 rate table since
1729 * shmem is shared between bands
1731 brcms_upd_ofdm_pctl1_table(wlc_hw);
1733 brcms_b_upd_synthpu(wlc_hw);
1736 /* Perform a soft reset of the PHY PLL */
1737 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1739 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1742 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1748 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1753 /* light way to turn on phy clock without reset for NPHY only
1754 * refer to brcms_b_core_phy_clk for full version
1756 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1758 /* support(necessary for NPHY and HYPHY) only */
1759 if (!BRCMS_ISNPHY(wlc_hw->band))
1763 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1765 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1769 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1772 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1774 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1777 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1779 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1781 bool phy_in_reset = false;
1783 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1788 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1790 /* Specific reset sequence required for NPHY rev 3 and 4 */
1791 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1792 NREV_LE(wlc_hw->band->phyrev, 4)) {
1793 /* Set the PHY bandwidth */
1794 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1798 /* Perform a soft reset of the PHY PLL */
1799 brcms_b_core_phypll_reset(wlc_hw);
1802 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1803 (SICF_PRST | SICF_PCLKE));
1804 phy_in_reset = true;
1806 brcms_b_core_ioctl(wlc_hw,
1807 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1808 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1812 brcms_b_core_phy_clk(wlc_hw, ON);
1815 wlc_phy_anacore(pih, ON);
1818 /* switch to and initialize new band */
1819 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1821 struct brcms_c_info *wlc = wlc_hw->wlc;
1824 /* Enable the d11 core before accessing it */
1825 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1826 bcma_core_enable(wlc_hw->d11core, 0);
1827 brcms_c_mctrl_reset(wlc_hw);
1830 macintmask = brcms_c_setband_inact(wlc, bandunit);
1835 brcms_b_core_phy_clk(wlc_hw, ON);
1837 /* band-specific initializations */
1838 brcms_b_bsinit(wlc, chanspec);
1841 * If there are any pending software interrupt bits,
1842 * then replace these with a harmless nonzero value
1843 * so brcms_c_dpc() will re-enable interrupts when done.
1845 if (wlc->macintstatus)
1846 wlc->macintstatus = MI_DMAINT;
1848 /* restore macintmask */
1849 brcms_intrsrestore(wlc->wl, macintmask);
1851 /* ucode should still be suspended.. */
1852 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1856 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1859 /* reject unsupported corerev */
1860 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1861 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1869 /* Validate some board info parameters */
1870 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1872 uint boardrev = wlc_hw->boardrev;
1874 /* 4 bits each for board type, major, minor, and tiny version */
1875 uint brt = (boardrev & 0xf000) >> 12;
1876 uint b0 = (boardrev & 0xf00) >> 8;
1877 uint b1 = (boardrev & 0xf0) >> 4;
1878 uint b2 = boardrev & 0xf;
1880 /* voards from other vendors are always considered valid */
1881 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1884 /* do some boardrev sanity checks when boardvendor is Broadcom */
1888 if (boardrev <= 0xff)
1891 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1898 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1900 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1902 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1903 if (!is_zero_ether_addr(sprom->il0mac)) {
1904 memcpy(etheraddr, sprom->il0mac, 6);
1908 if (wlc_hw->_nbands > 1)
1909 memcpy(etheraddr, sprom->et1mac, 6);
1911 memcpy(etheraddr, sprom->il0mac, 6);
1914 /* power both the pll and external oscillator on/off */
1915 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1917 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1920 * dont power down if plldown is false or
1921 * we must poll hw radio disable
1923 if (!want && wlc_hw->pllreq)
1926 wlc_hw->sbclk = want;
1927 if (!wlc_hw->sbclk) {
1928 wlc_hw->clk = false;
1929 if (wlc_hw->band && wlc_hw->band->pi)
1930 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1935 * Return true if radio is disabled, otherwise false.
1936 * hw radio disable signal is an external pin, users activate it asynchronously
1937 * this function could be called when driver is down and w/o clock
1938 * it operates on different registers depending on corerev and boardflag.
1940 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1945 xtal = wlc_hw->sbclk;
1947 brcms_b_xtal(wlc_hw, ON);
1949 /* may need to take core out of reset first */
1953 * mac no longer enables phyclk automatically when driver
1954 * accesses phyreg throughput mac. This can be skipped since
1955 * only mac reg is accessed below
1957 if (D11REV_GE(wlc_hw->corerev, 18))
1958 flags |= SICF_PCLKE;
1961 * TODO: test suspend/resume
1963 * AI chip doesn't restore bar0win2 on
1964 * hibernation/resume, need sw fixup
1967 bcma_core_enable(wlc_hw->d11core, flags);
1968 brcms_c_mctrl_reset(wlc_hw);
1971 v = ((bcma_read32(wlc_hw->d11core,
1972 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1974 /* put core back into reset */
1976 bcma_core_disable(wlc_hw->d11core, 0);
1979 brcms_b_xtal(wlc_hw, OFF);
1984 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1986 struct dma_pub *di = wlc_hw->di[fifo];
1987 return dma_rxreset(di);
1991 * ensure fask clock during reset
1993 * reset d11(out of reset)
1994 * reset phy(out of reset)
1995 * clear software macintstatus for fresh new start
1996 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1998 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2003 if (flags == BRCMS_USE_COREFLAGS)
2004 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2006 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2008 /* request FAST clock if not on */
2009 fastclk = wlc_hw->forcefastclk;
2011 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2013 /* reset the dma engines except first time thru */
2014 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2015 for (i = 0; i < NFIFO; i++)
2016 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2017 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2018 "dma_txreset[%d]: cannot stop dma\n",
2019 wlc_hw->unit, __func__, i);
2021 if ((wlc_hw->di[RX_FIFO])
2022 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2023 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2024 "[%d]: cannot stop dma\n",
2025 wlc_hw->unit, __func__, RX_FIFO);
2027 /* if noreset, just stop the psm and return */
2028 if (wlc_hw->noreset) {
2029 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2030 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2035 * mac no longer enables phyclk automatically when driver accesses
2036 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2037 * band->pi is invalid. need to enable PHY CLK
2039 if (D11REV_GE(wlc_hw->corerev, 18))
2040 flags |= SICF_PCLKE;
2044 * In chips with PMU, the fastclk request goes through d11 core
2045 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2047 * This adds some delay and we can optimize it by also requesting
2048 * fastclk through chipcommon during this period if necessary. But
2049 * that has to work coordinate with other driver like mips/arm since
2050 * they may touch chipcommon as well.
2052 wlc_hw->clk = false;
2053 bcma_core_enable(wlc_hw->d11core, flags);
2055 if (wlc_hw->band && wlc_hw->band->pi)
2056 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2058 brcms_c_mctrl_reset(wlc_hw);
2060 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2061 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2063 brcms_b_phy_reset(wlc_hw);
2065 /* turn on PHY_PLL */
2066 brcms_b_core_phypll_ctl(wlc_hw, true);
2068 /* clear sw intstatus */
2069 wlc_hw->wlc->macintstatus = 0;
2071 /* restore the clk setting */
2073 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2076 /* txfifo sizes needs to be modified(increased) since the newer cores
2079 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2081 struct bcma_device *core = wlc_hw->d11core;
2083 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2084 u16 txfifo_def, txfifo_def1;
2087 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2088 txfifo_startblk = TXFIFO_START_BLK;
2090 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2091 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2093 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2094 txfifo_def = (txfifo_startblk & 0xff) |
2095 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2096 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2098 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2100 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2102 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2103 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2104 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2106 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2108 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2111 * need to propagate to shm location to be in sync since ucode/hw won't
2114 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2115 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2116 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2117 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2118 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2119 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2120 xmtfifo_sz[TX_AC_BK_FIFO]));
2121 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2122 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2123 xmtfifo_sz[TX_BCMC_FIFO]));
2126 /* This function is used for changing the tsf frac register
2127 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2128 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2129 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2130 * HTPHY Formula is 2^26/freq(MHz) e.g.
2131 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2132 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2133 * For spuron: 123MHz -> 2^26/123 = 545600.5
2134 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2135 * For spur off: 120MHz -> 2^26/120 = 559240.5
2136 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2139 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2141 struct bcma_device *core = wlc_hw->d11core;
2143 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2144 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2145 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2147 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2148 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2149 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2150 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2151 } else { /* 120Mhz */
2152 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2153 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2155 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2156 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2157 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2158 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2159 } else { /* 80Mhz */
2160 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2161 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2166 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2168 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2169 wlc->bsscfg->type = BRCMS_TYPE_STATION;
2172 /* Initialize GPIOs that are controlled by D11 core */
2173 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2175 struct brcms_hardware *wlc_hw = wlc->hw;
2178 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2179 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2182 * Common GPIO setup:
2183 * G0 = LED 0 = WLAN Activity
2184 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2185 * G2 = LED 2 = WLAN 5 GHz Radio State
2186 * G4 = radio disable input (HI enabled, LO disabled)
2191 /* Allocate GPIOs for mimo antenna diversity feature */
2192 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2193 /* Enable antenna diversity, use 2x3 mode */
2194 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2195 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2196 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2197 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2199 /* init superswitch control */
2200 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2202 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2203 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2205 * The board itself is powered by these GPIOs
2206 * (when not sending pattern) so set them high
2208 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2209 (BOARD_GPIO_12 | BOARD_GPIO_13));
2210 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2211 (BOARD_GPIO_12 | BOARD_GPIO_13));
2213 /* Enable antenna diversity, use 2x4 mode */
2214 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2215 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2216 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2219 /* Configure the desired clock to be 4Mhz */
2220 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2221 ANTSEL_CLKDIV_4MHZ);
2225 * gpio 9 controls the PA. ucode is responsible
2226 * for wiggling out and oe
2228 if (wlc_hw->boardflags & BFL_PACTRL)
2229 gm |= gc |= BOARD_GPIO_PACTRL;
2231 /* apply to gpiocontrol register */
2232 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2235 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2236 const __le32 ucode[], const size_t nbytes)
2238 struct bcma_device *core = wlc_hw->d11core;
2242 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2244 count = (nbytes / sizeof(u32));
2246 bcma_write32(core, D11REGOFFS(objaddr),
2247 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2248 (void)bcma_read32(core, D11REGOFFS(objaddr));
2249 for (i = 0; i < count; i++)
2250 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2254 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2256 struct brcms_c_info *wlc;
2257 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2261 if (wlc_hw->ucode_loaded)
2264 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2265 if (BRCMS_ISNPHY(wlc_hw->band)) {
2266 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2267 ucode->bcm43xx_16_mimosz);
2268 wlc_hw->ucode_loaded = true;
2270 brcms_err(wlc_hw->d11core,
2271 "%s: wl%d: unsupported phy in corerev %d\n",
2272 __func__, wlc_hw->unit, wlc_hw->corerev);
2273 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2274 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2275 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2276 ucode->bcm43xx_24_lcnsz);
2277 wlc_hw->ucode_loaded = true;
2279 brcms_err(wlc_hw->d11core,
2280 "%s: wl%d: unsupported phy in corerev %d\n",
2281 __func__, wlc_hw->unit, wlc_hw->corerev);
2286 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2288 /* update sw state */
2289 wlc_hw->bmac_phytxant = phytxant;
2291 /* push to ucode if up */
2294 brcms_c_ucode_txant_set(wlc_hw);
2298 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2300 return (u16) wlc_hw->wlc->stf->txant;
2303 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2305 wlc_hw->antsel_type = antsel_type;
2307 /* Update the antsel type for phy module to use */
2308 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2311 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2315 uint intstatus, idx;
2316 struct bcma_device *core = wlc_hw->d11core;
2318 unit = wlc_hw->unit;
2320 for (idx = 0; idx < NFIFO; idx++) {
2321 /* read intstatus register and ignore any non-error bits */
2324 D11REGOFFS(intctrlregs[idx].intstatus)) &
2329 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2330 unit, idx, intstatus);
2332 if (intstatus & I_RO) {
2333 brcms_err(core, "wl%d: fifo %d: receive fifo "
2334 "overflow\n", unit, idx);
2338 if (intstatus & I_PC) {
2339 brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2344 if (intstatus & I_PD) {
2345 brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2350 if (intstatus & I_DE) {
2351 brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2352 "error\n", unit, idx);
2356 if (intstatus & I_RU)
2357 brcms_err(core, "wl%d: fifo %d: receive descriptor "
2358 "underflow\n", idx, unit);
2360 if (intstatus & I_XU) {
2361 brcms_err(core, "wl%d: fifo %d: transmit fifo "
2362 "underflow\n", idx, unit);
2367 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2371 D11REGOFFS(intctrlregs[idx].intstatus),
2376 void brcms_c_intrson(struct brcms_c_info *wlc)
2378 struct brcms_hardware *wlc_hw = wlc->hw;
2379 wlc->macintmask = wlc->defmacintmask;
2380 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2383 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2385 struct brcms_hardware *wlc_hw = wlc->hw;
2391 macintmask = wlc->macintmask; /* isr can still happen */
2393 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2394 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2395 udelay(1); /* ensure int line is no longer driven */
2396 wlc->macintmask = 0;
2398 /* return previous macintmask; resolve race between us and our isr */
2399 return wlc->macintstatus ? 0 : macintmask;
2402 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2404 struct brcms_hardware *wlc_hw = wlc->hw;
2408 wlc->macintmask = macintmask;
2409 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2412 /* assumes that the d11 MAC is enabled */
2413 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2416 u8 fifo = 1 << tx_fifo;
2418 /* Two clients of this code, 11h Quiet period and scanning. */
2420 /* only suspend if not already suspended */
2421 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2424 /* force the core awake only if not already */
2425 if (wlc_hw->suspended_fifos == 0)
2426 brcms_c_ucode_wake_override_set(wlc_hw,
2427 BRCMS_WAKE_OVERRIDE_TXFIFO);
2429 wlc_hw->suspended_fifos |= fifo;
2431 if (wlc_hw->di[tx_fifo]) {
2433 * Suspending AMPDU transmissions in the middle can cause
2434 * underflow which may result in mismatch between ucode and
2435 * driver so suspend the mac before suspending the FIFO
2437 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2438 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2440 dma_txsuspend(wlc_hw->di[tx_fifo]);
2442 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2443 brcms_c_enable_mac(wlc_hw->wlc);
2447 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2450 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2451 * but need to be done here for PIO otherwise the watchdog will catch
2452 * the inconsistency and fire
2454 /* Two clients of this code, 11h Quiet period and scanning. */
2455 if (wlc_hw->di[tx_fifo])
2456 dma_txresume(wlc_hw->di[tx_fifo]);
2458 /* allow core to sleep again */
2459 if (wlc_hw->suspended_fifos == 0)
2462 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2463 if (wlc_hw->suspended_fifos == 0)
2464 brcms_c_ucode_wake_override_clear(wlc_hw,
2465 BRCMS_WAKE_OVERRIDE_TXFIFO);
2469 /* precondition: requires the mac core to be enabled */
2470 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2472 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2473 u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2476 /* suspend tx fifos */
2477 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2478 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2479 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2480 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2482 /* zero the address match register so we do not send ACKs */
2483 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2485 /* resume tx fifos */
2486 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2487 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2488 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2489 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2491 /* Restore address */
2492 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2495 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2498 brcms_c_ucode_mute_override_set(wlc_hw);
2500 brcms_c_ucode_mute_override_clear(wlc_hw);
2504 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2506 brcms_b_mute(wlc->hw, mute_tx);
2510 * Read and clear macintmask and macintstatus and intstatus registers.
2511 * This routine should be called with interrupts off
2513 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2514 * 0 if the interrupt is not for us, or we are in some special cases;
2515 * device interrupt status bits otherwise.
2517 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2519 struct brcms_hardware *wlc_hw = wlc->hw;
2520 struct bcma_device *core = wlc_hw->d11core;
2521 u32 macintstatus, mask;
2523 /* macintstatus includes a DMA interrupt summary bit */
2524 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2525 mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2527 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2529 /* detect cardbus removed, in power down(suspend) and in reset */
2530 if (brcms_deviceremoved(wlc))
2533 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2534 * handle that case here.
2536 if (macintstatus == 0xffffffff)
2539 /* defer unsolicited interrupts */
2540 macintstatus &= mask;
2543 if (macintstatus == 0)
2546 /* turn off the interrupts */
2547 bcma_write32(core, D11REGOFFS(macintmask), 0);
2548 (void)bcma_read32(core, D11REGOFFS(macintmask));
2549 wlc->macintmask = 0;
2551 /* clear device interrupts */
2552 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2554 /* MI_DMAINT is indication of non-zero intstatus */
2555 if (macintstatus & MI_DMAINT)
2557 * only fifo interrupt enabled is I_RI in
2558 * RX_FIFO. If MI_DMAINT is set, assume it
2559 * is set and clear the interrupt.
2561 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2564 return macintstatus;
2567 /* Update wlc->macintstatus and wlc->intstatus[]. */
2568 /* Return true if they are updated successfully. false otherwise */
2569 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2573 /* read and clear macintstatus and intstatus registers */
2574 macintstatus = wlc_intstatus(wlc, false);
2576 /* device is removed */
2577 if (macintstatus == 0xffffffff)
2580 /* update interrupt status in software */
2581 wlc->macintstatus |= macintstatus;
2587 * First-level interrupt processing.
2588 * Return true if this was our interrupt
2589 * and if further brcms_c_dpc() processing is required,
2592 bool brcms_c_isr(struct brcms_c_info *wlc)
2594 struct brcms_hardware *wlc_hw = wlc->hw;
2597 if (!wlc_hw->up || !wlc->macintmask)
2600 /* read and clear macintstatus and intstatus registers */
2601 macintstatus = wlc_intstatus(wlc, true);
2603 if (macintstatus == 0xffffffff) {
2604 brcms_err(wlc_hw->d11core,
2605 "DEVICEREMOVED detected in the ISR code path\n");
2609 /* it is not for us */
2610 if (macintstatus == 0)
2613 /* save interrupt status bits */
2614 wlc->macintstatus = macintstatus;
2620 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2622 struct brcms_hardware *wlc_hw = wlc->hw;
2623 struct bcma_device *core = wlc_hw->d11core;
2626 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2627 wlc_hw->band->bandunit);
2630 * Track overlapping suspend requests
2632 wlc_hw->mac_suspend_depth++;
2633 if (wlc_hw->mac_suspend_depth > 1)
2636 /* force the core awake */
2637 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2639 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2641 if (mc == 0xffffffff) {
2642 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2644 brcms_down(wlc->wl);
2647 WARN_ON(mc & MCTL_PSM_JMP_0);
2648 WARN_ON(!(mc & MCTL_PSM_RUN));
2649 WARN_ON(!(mc & MCTL_EN_MAC));
2651 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2652 if (mi == 0xffffffff) {
2653 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2655 brcms_down(wlc->wl);
2658 WARN_ON(mi & MI_MACSSPNDD);
2660 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2662 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2663 BRCMS_MAX_MAC_SUSPEND);
2665 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2666 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2667 " and MI_MACSSPNDD is still not on.\n",
2668 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2669 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2670 "psm_brc 0x%04x\n", wlc_hw->unit,
2671 bcma_read32(core, D11REGOFFS(psmdebug)),
2672 bcma_read32(core, D11REGOFFS(phydebug)),
2673 bcma_read16(core, D11REGOFFS(psm_brc)));
2676 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2677 if (mc == 0xffffffff) {
2678 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2680 brcms_down(wlc->wl);
2683 WARN_ON(mc & MCTL_PSM_JMP_0);
2684 WARN_ON(!(mc & MCTL_PSM_RUN));
2685 WARN_ON(mc & MCTL_EN_MAC);
2688 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2690 struct brcms_hardware *wlc_hw = wlc->hw;
2691 struct bcma_device *core = wlc_hw->d11core;
2694 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2695 wlc->band->bandunit);
2698 * Track overlapping suspend requests
2700 wlc_hw->mac_suspend_depth--;
2701 if (wlc_hw->mac_suspend_depth > 0)
2704 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2705 WARN_ON(mc & MCTL_PSM_JMP_0);
2706 WARN_ON(mc & MCTL_EN_MAC);
2707 WARN_ON(!(mc & MCTL_PSM_RUN));
2709 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2710 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2712 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2713 WARN_ON(mc & MCTL_PSM_JMP_0);
2714 WARN_ON(!(mc & MCTL_EN_MAC));
2715 WARN_ON(!(mc & MCTL_PSM_RUN));
2717 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2718 WARN_ON(mi & MI_MACSSPNDD);
2720 brcms_c_ucode_wake_override_clear(wlc_hw,
2721 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2724 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2726 wlc_hw->hw_stf_ss_opmode = stf_mode;
2729 brcms_upd_ofdm_pctl1_table(wlc_hw);
2732 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2734 struct bcma_device *core = wlc_hw->d11core;
2736 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2738 /* Validate dchip register access */
2740 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2741 (void)bcma_read32(core, D11REGOFFS(objaddr));
2742 w = bcma_read32(core, D11REGOFFS(objdata));
2744 /* Can we write and read back a 32bit register? */
2745 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2746 (void)bcma_read32(core, D11REGOFFS(objaddr));
2747 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2749 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2750 (void)bcma_read32(core, D11REGOFFS(objaddr));
2751 val = bcma_read32(core, D11REGOFFS(objdata));
2752 if (val != (u32) 0xaa5555aa) {
2753 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2754 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2758 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2759 (void)bcma_read32(core, D11REGOFFS(objaddr));
2760 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2762 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2763 (void)bcma_read32(core, D11REGOFFS(objaddr));
2764 val = bcma_read32(core, D11REGOFFS(objdata));
2765 if (val != (u32) 0x55aaaa55) {
2766 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2767 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2771 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2772 (void)bcma_read32(core, D11REGOFFS(objaddr));
2773 bcma_write32(core, D11REGOFFS(objdata), w);
2775 /* clear CFPStart */
2776 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2778 w = bcma_read32(core, D11REGOFFS(maccontrol));
2779 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2780 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2781 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2782 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2783 (MCTL_IHR_EN | MCTL_WAKE),
2784 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2791 #define PHYPLL_WAIT_US 100000
2793 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2795 struct bcma_device *core = wlc_hw->d11core;
2798 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2803 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2804 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2806 CCS_ERSRC_REQ_D11PLL |
2807 CCS_ERSRC_REQ_PHYPLL);
2808 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2809 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2812 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2813 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2814 brcms_err(core, "%s: turn on PHY PLL failed\n",
2817 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2818 tmp | CCS_ERSRC_REQ_D11PLL |
2819 CCS_ERSRC_REQ_PHYPLL);
2820 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2821 (CCS_ERSRC_AVAIL_D11PLL |
2822 CCS_ERSRC_AVAIL_PHYPLL)) !=
2823 (CCS_ERSRC_AVAIL_D11PLL |
2824 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2826 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2828 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2830 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2831 brcms_err(core, "%s: turn on PHY PLL failed\n",
2836 * Since the PLL may be shared, other cores can still
2837 * be requesting it; so we'll deassert the request but
2838 * not wait for status to comply.
2840 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2841 ~CCS_ERSRC_REQ_PHYPLL);
2842 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2846 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2850 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2852 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2857 if (wlc_hw->noreset)
2861 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2863 /* turn off analog core */
2864 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2866 /* turn off PHYPLL to save power */
2867 brcms_b_core_phypll_ctl(wlc_hw, false);
2869 wlc_hw->clk = false;
2870 bcma_core_disable(wlc_hw->d11core, 0);
2871 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2874 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2876 struct brcms_hardware *wlc_hw = wlc->hw;
2879 /* free any posted tx packets */
2880 for (i = 0; i < NFIFO; i++) {
2881 if (wlc_hw->di[i]) {
2882 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2883 if (i < TX_BCMC_FIFO)
2884 ieee80211_wake_queue(wlc->pub->ieee_hw,
2885 brcms_fifo_to_ac(i));
2889 /* free any posted rx packets */
2890 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2894 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2896 struct bcma_device *core = wlc_hw->d11core;
2897 u16 objoff = D11REGOFFS(objdata);
2899 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2900 (void)bcma_read32(core, D11REGOFFS(objaddr));
2904 return bcma_read16(core, objoff);
2908 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2911 struct bcma_device *core = wlc_hw->d11core;
2912 u16 objoff = D11REGOFFS(objdata);
2914 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2915 (void)bcma_read32(core, D11REGOFFS(objaddr));
2919 bcma_wflush16(core, objoff, v);
2923 * Read a single u16 from shared memory.
2924 * SHM 'offset' needs to be an even address
2926 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2928 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2932 * Write a single u16 to shared memory.
2933 * SHM 'offset' needs to be an even address
2935 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2937 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2941 * Copy a buffer to shared memory of specified type .
2942 * SHM 'offset' needs to be an even address and
2943 * Buffer length 'len' must be an even number of bytes
2944 * 'sel' selects the type of memory
2947 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2948 const void *buf, int len, u32 sel)
2951 const u8 *p = (const u8 *)buf;
2954 if (len <= 0 || (offset & 1) || (len & 1))
2957 for (i = 0; i < len; i += 2) {
2958 v = p[i] | (p[i + 1] << 8);
2959 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2964 * Copy a piece of shared memory of specified type to a buffer .
2965 * SHM 'offset' needs to be an even address and
2966 * Buffer length 'len' must be an even number of bytes
2967 * 'sel' selects the type of memory
2970 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2977 if (len <= 0 || (offset & 1) || (len & 1))
2980 for (i = 0; i < len; i += 2) {
2981 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2983 p[i + 1] = (v >> 8) & 0xFF;
2987 /* Copy a buffer to shared memory.
2988 * SHM 'offset' needs to be an even address and
2989 * Buffer length 'len' must be an even number of bytes
2991 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2992 const void *buf, int len)
2994 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2997 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3003 /* write retry limit to SCR, shouldn't need to suspend */
3005 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3006 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3007 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3008 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3009 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3010 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3011 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3012 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3016 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3019 if (mboolisset(wlc_hw->pllreq, req_bit))
3022 mboolset(wlc_hw->pllreq, req_bit);
3024 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3026 brcms_b_xtal(wlc_hw, ON);
3029 if (!mboolisset(wlc_hw->pllreq, req_bit))
3032 mboolclr(wlc_hw->pllreq, req_bit);
3034 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3036 brcms_b_xtal(wlc_hw, OFF);
3041 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3043 wlc_hw->antsel_avail = antsel_avail;
3047 * conditions under which the PM bit should be set in outgoing frames
3048 * and STAY_AWAKE is meaningful
3050 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3052 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3054 /* disallow PS when one of the following global conditions meets */
3055 if (!wlc->pub->associated)
3058 /* disallow PS when one of these meets when not scanning */
3059 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3062 if (cfg->associated)
3068 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3071 struct macstat macstats;
3078 /* if driver down, make no sense to update stats */
3083 /* save last rx fifo 0 overflow count */
3084 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3086 /* save last tx fifo underflow count */
3087 for (i = 0; i < NFIFO; i++)
3088 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3091 /* Read mac stats from contiguous shared memory */
3092 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3093 sizeof(struct macstat), OBJADDR_SHM_SEL);
3096 /* check for rx fifo 0 overflow */
3097 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3099 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3100 wlc->pub->unit, delta);
3102 /* check for tx fifo underflows */
3103 for (i = 0; i < NFIFO; i++) {
3105 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3108 brcms_err(wlc->hw->d11core,
3109 "wl%d: %u tx fifo %d underflows!\n",
3110 wlc->pub->unit, delta, i);
3114 /* merge counters from dma module */
3115 for (i = 0; i < NFIFO; i++) {
3117 dma_counterreset(wlc->hw->di[i]);
3121 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3123 /* reset the core */
3124 if (!brcms_deviceremoved(wlc_hw->wlc))
3125 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3127 /* purge the dma rings */
3128 brcms_c_flushqueues(wlc_hw->wlc);
3131 void brcms_c_reset(struct brcms_c_info *wlc)
3133 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3135 /* slurp up hw mac counters before core reset */
3136 brcms_c_statsupd(wlc);
3138 /* reset our snapshot of macstat counters */
3139 memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3141 brcms_b_reset(wlc->hw);
3144 void brcms_c_init_scb(struct scb *scb)
3148 memset(scb, 0, sizeof(struct scb));
3149 scb->flags = SCB_WMECAP | SCB_HTCAP;
3150 for (i = 0; i < NUMPRIO; i++) {
3152 scb->seqctl[i] = 0xFFFF;
3155 scb->seqctl_nonqos = 0xFFFF;
3156 scb->magic = SCB_MAGIC;
3161 * download ucode/PCM
3162 * let ucode run to suspended
3163 * download ucode inits
3164 * config other core registers
3167 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3169 struct brcms_hardware *wlc_hw = wlc->hw;
3170 struct bcma_device *core = wlc_hw->d11core;
3174 bool fifosz_fixup = false;
3177 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3179 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3182 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3184 brcms_ucode_download(wlc_hw);
3186 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3188 fifosz_fixup = true;
3190 /* let the PSM run to the suspended state, set mode to BSS STA */
3191 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3192 brcms_b_mctrl(wlc_hw, ~0,
3193 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3195 /* wait for ucode to self-suspend after auto-init */
3196 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3197 MI_MACSSPNDD) == 0), 1000 * 1000);
3198 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3199 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3200 "suspend!\n", wlc_hw->unit);
3202 brcms_c_gpio_init(wlc);
3204 sflags = bcma_aread32(core, BCMA_IOST);
3206 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3207 if (BRCMS_ISNPHY(wlc_hw->band))
3208 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3210 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3211 " %d\n", __func__, wlc_hw->unit,
3213 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3214 if (BRCMS_ISLCNPHY(wlc_hw->band))
3215 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3217 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3218 " %d\n", __func__, wlc_hw->unit,
3221 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3222 __func__, wlc_hw->unit, wlc_hw->corerev);
3225 /* For old ucode, txfifo sizes needs to be modified(increased) */
3227 brcms_b_corerev_fifofixup(wlc_hw);
3229 /* check txfifo allocations match between ucode and driver */
3230 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3231 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3235 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3236 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3240 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3241 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3242 buf[TX_AC_BK_FIFO] &= 0xff;
3243 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3247 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3251 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3252 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3253 buf[TX_BCMC_FIFO] &= 0xff;
3254 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3258 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3263 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3264 " driver size %d index %d\n", buf[i],
3265 wlc_hw->xmtfifo_sz[i], i);
3267 /* make sure we can still talk to the mac */
3268 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3270 /* band-specific inits done by wlc_bsinit() */
3272 /* Set up frame burst size and antenna swap threshold init values */
3273 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3274 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3276 /* enable one rx interrupt per received frame */
3277 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3279 /* set the station mode (BSS STA) */
3280 brcms_b_mctrl(wlc_hw,
3281 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3282 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3284 /* set up Beacon interval */
3285 bcnint_us = 0x8000 << 10;
3286 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3287 (bcnint_us << CFPREP_CBI_SHIFT));
3288 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3289 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3291 /* write interrupt mask */
3292 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3295 /* allow the MAC to control the PHY clock (dynamic on/off) */
3296 brcms_b_macphyclk_set(wlc_hw, ON);
3298 /* program dynamic clock control fast powerup delay register */
3299 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3300 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3302 /* tell the ucode the corerev */
3303 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3305 /* tell the ucode MAC capabilities */
3306 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3307 (u16) (wlc_hw->machwcap & 0xffff));
3308 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3310 machwcap >> 16) & 0xffff));
3312 /* write retry limits to SCR, this done after PSM init */
3313 bcma_write32(core, D11REGOFFS(objaddr),
3314 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3315 (void)bcma_read32(core, D11REGOFFS(objaddr));
3316 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3317 bcma_write32(core, D11REGOFFS(objaddr),
3318 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3319 (void)bcma_read32(core, D11REGOFFS(objaddr));
3320 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3322 /* write rate fallback retry limits */
3323 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3324 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3326 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3327 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3329 /* init the tx dma engines */
3330 for (i = 0; i < NFIFO; i++) {
3332 dma_txinit(wlc_hw->di[i]);
3335 /* init the rx dma engine(s) and post receive buffers */
3336 dma_rxinit(wlc_hw->di[RX_FIFO]);
3337 dma_rxfill(wlc_hw->di[RX_FIFO]);
3341 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3344 struct brcms_c_info *wlc = wlc_hw->wlc;
3346 /* request FAST clock if not on */
3347 fastclk = wlc_hw->forcefastclk;
3349 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3351 /* disable interrupts */
3352 macintmask = brcms_intrsoff(wlc->wl);
3354 /* set up the specified band and chanspec */
3355 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3356 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3358 /* do one-time phy inits and calibration */
3359 wlc_phy_cal_init(wlc_hw->band->pi);
3361 /* core-specific initialization */
3362 brcms_b_coreinit(wlc);
3364 /* band-specific inits */
3365 brcms_b_bsinit(wlc, chanspec);
3367 /* restore macintmask */
3368 brcms_intrsrestore(wlc->wl, macintmask);
3370 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3371 * is suspended and brcms_c_enable_mac() will clear this override bit.
3373 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3376 * initialize mac_suspend_depth to 1 to match ucode
3377 * initial suspended state
3379 wlc_hw->mac_suspend_depth = 1;
3381 /* restore the clk */
3383 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3386 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3389 /* Save our copy of the chanspec */
3390 wlc->chanspec = chanspec;
3392 /* Set the chanspec and power limits for this locale */
3393 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3395 if (wlc->stf->ss_algosel_auto)
3396 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3399 brcms_c_stf_ss_update(wlc, wlc->band);
3403 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3405 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3406 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3407 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3408 brcms_chspec_bw(wlc->default_bss->chanspec),
3409 wlc->stf->txstreams);
3412 /* derive wlc->band->basic_rate[] table from 'rateset' */
3413 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3414 struct brcms_c_rateset *rateset)
3420 u8 *br = wlc->band->basic_rate;
3423 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3424 memset(br, 0, BRCM_MAXRATE + 1);
3426 /* For each basic rate in the rates list, make an entry in the
3427 * best basic lookup.
3429 for (i = 0; i < rateset->count; i++) {
3430 /* only make an entry for a basic rate */
3431 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3434 /* mask off basic bit */
3435 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3437 if (rate > BRCM_MAXRATE) {
3438 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3439 "invalid rate 0x%X in rate set\n",
3447 /* The rate lookup table now has non-zero entries for each
3448 * basic rate, equal to the basic rate: br[basicN] = basicN
3450 * To look up the best basic rate corresponding to any
3451 * particular rate, code can use the basic_rate table
3454 * basic_rate = wlc->band->basic_rate[tx_rate]
3456 * Make sure there is a best basic rate entry for
3457 * every rate by walking up the table from low rates
3458 * to high, filling in holes in the lookup table
3461 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3462 rate = wlc->band->hw_rateset.rates[i];
3464 if (br[rate] != 0) {
3465 /* This rate is a basic rate.
3466 * Keep track of the best basic rate so far by
3469 if (is_ofdm_rate(rate))
3477 /* This rate is not a basic rate so figure out the
3478 * best basic rate less than this rate and fill in
3479 * the hole in the table
3482 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3487 if (is_ofdm_rate(rate)) {
3489 * In 11g and 11a, the OFDM mandatory rates
3490 * are 6, 12, and 24 Mbps
3492 if (rate >= BRCM_RATE_24M)
3493 mandatory = BRCM_RATE_24M;
3494 else if (rate >= BRCM_RATE_12M)
3495 mandatory = BRCM_RATE_12M;
3497 mandatory = BRCM_RATE_6M;
3499 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3503 br[rate] = mandatory;
3507 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3510 struct brcms_c_rateset default_rateset;
3512 uint i, band_order[2];
3515 * We might have been bandlocked during down and the chip
3516 * power-cycled (hibernate). Figure out the right band to park on
3518 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3519 /* updated in brcms_c_bandlock() */
3520 parkband = wlc->band->bandunit;
3521 band_order[0] = band_order[1] = parkband;
3523 /* park on the band of the specified chanspec */
3524 parkband = chspec_bandunit(chanspec);
3526 /* order so that parkband initialize last */
3527 band_order[0] = parkband ^ 1;
3528 band_order[1] = parkband;
3531 /* make each band operational, software state init */
3532 for (i = 0; i < wlc->pub->_nbands; i++) {
3533 uint j = band_order[i];
3535 wlc->band = wlc->bandstate[j];
3537 brcms_default_rateset(wlc, &default_rateset);
3539 /* fill in hw_rate */
3540 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3541 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3542 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3544 /* init basic rate lookup */
3545 brcms_c_rate_lookup_init(wlc, &default_rateset);
3548 /* sync up phy/radio chanspec */
3549 brcms_c_set_phy_chanspec(wlc, chanspec);
3553 * Set or clear filtering related maccontrol bits based on
3554 * specified filter flags
3556 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3558 u32 promisc_bits = 0;
3560 wlc->filter_flags = filter_flags;
3562 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3563 promisc_bits |= MCTL_PROMISC;
3565 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3566 promisc_bits |= MCTL_BCNS_PROMISC;
3568 if (filter_flags & FIF_FCSFAIL)
3569 promisc_bits |= MCTL_KEEPBADFCS;
3571 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3572 promisc_bits |= MCTL_KEEPCONTROL;
3574 brcms_b_mctrl(wlc->hw,
3575 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3576 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3581 * ucode, hwmac update
3582 * Channel dependent updates for ucode and hw
3584 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3586 /* enable or disable any active IBSSs depending on whether or not
3587 * we are on the home channel
3589 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3590 if (wlc->pub->associated) {
3592 * BMAC_NOTE: This is something that should be fixed
3593 * in ucode inits. I think that the ucode inits set
3594 * up the bcn templates and shm values with a bogus
3595 * beacon. This should not be done in the inits. If
3596 * ucode needs to set up a beacon for testing, the
3597 * test routines should write it down, not expect the
3598 * inits to populate a bogus beacon.
3600 if (BRCMS_PHY_11N_CAP(wlc->band))
3601 brcms_b_write_shm(wlc->hw,
3602 M_BCN_TXTSF_OFFSET, 0);
3605 /* disable an active IBSS if we are not on the home channel */
3609 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3613 u8 basic_phy_rate, basic_index;
3614 u16 dir_table, basic_table;
3617 /* Shared memory address for the table we are reading */
3618 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3620 /* Shared memory address for the table we are writing */
3621 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3624 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3625 * the index into the rate table.
3627 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3628 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3629 index = phy_rate & 0xf;
3630 basic_index = basic_phy_rate & 0xf;
3632 /* Find the SHM pointer to the ACK rate entry by looking in the
3635 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3637 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3638 * to the correct basic rate for the given incoming rate
3640 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3643 static const struct brcms_c_rateset *
3644 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3646 const struct brcms_c_rateset *rs_dflt;
3648 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3649 if (wlc->band->bandtype == BRCM_BAND_5G)
3650 rs_dflt = &ofdm_mimo_rates;
3652 rs_dflt = &cck_ofdm_mimo_rates;
3653 } else if (wlc->band->gmode)
3654 rs_dflt = &cck_ofdm_rates;
3656 rs_dflt = &cck_rates;
3661 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3663 const struct brcms_c_rateset *rs_dflt;
3664 struct brcms_c_rateset rs;
3665 u8 rate, basic_rate;
3668 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3670 brcms_c_rateset_copy(rs_dflt, &rs);
3671 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3673 /* walk the phy rate table and update SHM basic rate lookup table */
3674 for (i = 0; i < rs.count; i++) {
3675 rate = rs.rates[i] & BRCMS_RATE_MASK;
3677 /* for a given rate brcms_basic_rate returns the rate at
3678 * which a response ACK/CTS should be sent.
3680 basic_rate = brcms_basic_rate(wlc, rate);
3681 if (basic_rate == 0)
3682 /* This should only happen if we are using a
3683 * restricted rateset.
3685 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3687 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3691 /* band-specific init */
3692 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3694 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3695 wlc->pub->unit, wlc->band->bandunit);
3697 /* write ucode ACK/CTS rate table */
3698 brcms_c_set_ratetable(wlc);
3700 /* update some band specific mac configuration */
3701 brcms_c_ucode_mac_upd(wlc);
3703 /* init antenna selection */
3704 brcms_c_antsel_init(wlc->asi);
3708 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3710 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3713 int idle_busy_ratio_x_16 = 0;
3715 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3716 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3717 if (duty_cycle > 100 || duty_cycle < 0) {
3718 brcms_err(wlc->hw->d11core,
3719 "wl%d: duty cycle value off limit\n",
3724 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3725 /* Only write to shared memory when wl is up */
3727 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3730 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3732 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3737 /* push sw hps and wake state through hardware */
3738 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3744 hps = brcms_c_ps_allowed(wlc);
3746 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3749 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3754 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3756 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3759 brcms_b_wait_for_wake(wlc->hw);
3763 * Write this BSS config's MAC address to core.
3764 * Updates RXE match engine.
3766 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3769 struct brcms_c_info *wlc = bsscfg->wlc;
3771 /* enter the MAC addr into the RXE match registers */
3772 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3774 brcms_c_ampdu_macaddr_upd(wlc);
3779 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3780 * Updates RXE match engine.
3782 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3784 /* we need to update BSSID in RXE match registers */
3785 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3788 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3790 wlc_hw->shortslot = shortslot;
3792 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3793 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3794 brcms_b_update_slot_timing(wlc_hw, shortslot);
3795 brcms_c_enable_mac(wlc_hw->wlc);
3800 * Suspend the the MAC and update the slot timing
3801 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3803 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3805 /* use the override if it is set */
3806 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3807 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3809 if (wlc->shortslot == shortslot)
3812 wlc->shortslot = shortslot;
3814 brcms_b_set_shortslot(wlc->hw, shortslot);
3817 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3819 if (wlc->home_chanspec != chanspec) {
3820 wlc->home_chanspec = chanspec;
3822 if (wlc->bsscfg->associated)
3823 wlc->bsscfg->current_bss->chanspec = chanspec;
3828 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3829 bool mute_tx, struct txpwr_limits *txpwr)
3833 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3836 wlc_hw->chanspec = chanspec;
3838 /* Switch bands if necessary */
3839 if (wlc_hw->_nbands > 1) {
3840 bandunit = chspec_bandunit(chanspec);
3841 if (wlc_hw->band->bandunit != bandunit) {
3842 /* brcms_b_setband disables other bandunit,
3843 * use light band switch if not up yet
3846 wlc_phy_chanspec_radio_set(wlc_hw->
3847 bandstate[bandunit]->
3849 brcms_b_setband(wlc_hw, bandunit, chanspec);
3851 brcms_c_setxband(wlc_hw, bandunit);
3856 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3860 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3862 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3864 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3865 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3867 /* Update muting of the channel */
3868 brcms_b_mute(wlc_hw, mute_tx);
3872 /* switch to and initialize new band */
3873 static void brcms_c_setband(struct brcms_c_info *wlc,
3876 wlc->band = wlc->bandstate[bandunit];
3881 /* wait for at least one beacon before entering sleeping state */
3882 brcms_c_set_ps_ctrl(wlc);
3884 /* band-specific initializations */
3885 brcms_c_bsinit(wlc);
3888 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3891 bool switchband = false;
3892 u16 old_chanspec = wlc->chanspec;
3894 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3895 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3896 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3900 /* Switch bands if necessary */
3901 if (wlc->pub->_nbands > 1) {
3902 bandunit = chspec_bandunit(chanspec);
3903 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3905 if (wlc->bandlocked) {
3906 brcms_err(wlc->hw->d11core,
3907 "wl%d: %s: chspec %d band is locked!\n",
3908 wlc->pub->unit, __func__,
3909 CHSPEC_CHANNEL(chanspec));
3913 * should the setband call come after the
3914 * brcms_b_chanspec() ? if the setband updates
3915 * (brcms_c_bsinit) use low level calls to inspect and
3916 * set state, the state inspected may be from the wrong
3917 * band, or the following brcms_b_set_chanspec() may
3920 brcms_c_setband(wlc, bandunit);
3924 /* sync up phy/radio chanspec */
3925 brcms_c_set_phy_chanspec(wlc, chanspec);
3927 /* init antenna selection */
3928 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3929 brcms_c_antsel_init(wlc->asi);
3931 /* Fix the hardware rateset based on bw.
3932 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3934 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3935 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3938 /* update some mac configuration since chanspec changed */
3939 brcms_c_ucode_mac_upd(wlc);
3943 * This function changes the phytxctl for beacon based on current
3944 * beacon ratespec AND txant setting as per this table:
3945 * ratespec CCK ant = wlc->stf->txant
3948 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3952 u16 phytxant = wlc->stf->phytxant;
3953 u16 mask = PHY_TXC_ANT_MASK;
3955 /* for non-siso rates or default setting, use the available chains */
3956 if (BRCMS_PHY_11N_CAP(wlc->band))
3957 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3959 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3960 phyctl = (phyctl & ~mask) | phytxant;
3961 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3965 * centralized protection config change function to simplify debugging, no
3966 * consistency checking this should be called only on changes to avoid overhead
3967 * in periodic function
3969 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3972 * Cannot use brcms_dbg_* here because this function is called
3973 * before wlc is sufficiently initialized.
3975 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3978 case BRCMS_PROT_G_SPEC:
3979 wlc->protection->_g = (bool) val;
3981 case BRCMS_PROT_G_OVR:
3982 wlc->protection->g_override = (s8) val;
3984 case BRCMS_PROT_G_USER:
3985 wlc->protection->gmode_user = (u8) val;
3987 case BRCMS_PROT_OVERLAP:
3988 wlc->protection->overlap = (s8) val;
3990 case BRCMS_PROT_N_USER:
3991 wlc->protection->nmode_user = (s8) val;
3993 case BRCMS_PROT_N_CFG:
3994 wlc->protection->n_cfg = (s8) val;
3996 case BRCMS_PROT_N_CFG_OVR:
3997 wlc->protection->n_cfg_override = (s8) val;
3999 case BRCMS_PROT_N_NONGF:
4000 wlc->protection->nongf = (bool) val;
4002 case BRCMS_PROT_N_NONGF_OVR:
4003 wlc->protection->nongf_override = (s8) val;
4005 case BRCMS_PROT_N_PAM_OVR:
4006 wlc->protection->n_pam_override = (s8) val;
4008 case BRCMS_PROT_N_OBSS:
4009 wlc->protection->n_obss = (bool) val;
4018 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4021 brcms_c_update_beacon(wlc);
4022 brcms_c_update_probe_resp(wlc, true);
4026 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4028 wlc->stf->ldpc = val;
4031 brcms_c_update_beacon(wlc);
4032 brcms_c_update_probe_resp(wlc, true);
4033 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4037 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4038 const struct ieee80211_tx_queue_params *params,
4042 struct shm_acparams acp_shm;
4045 /* Only apply params if the core is out of reset and has clocks */
4047 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4048 wlc->pub->unit, __func__);
4052 memset(&acp_shm, 0, sizeof(struct shm_acparams));
4053 /* fill in shm ac params struct */
4054 acp_shm.txop = params->txop;
4055 /* convert from units of 32us to us for ucode */
4056 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4057 EDCF_TXOP2USEC(acp_shm.txop);
4058 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4060 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4061 && acp_shm.aifs < EDCF_AIFSN_MAX)
4064 if (acp_shm.aifs < EDCF_AIFSN_MIN
4065 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4066 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4067 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4069 acp_shm.cwmin = params->cw_min;
4070 acp_shm.cwmax = params->cw_max;
4071 acp_shm.cwcur = acp_shm.cwmin;
4073 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4075 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4076 /* Indicate the new params to the ucode */
4077 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4080 M_EDCF_STATUS_OFF));
4081 acp_shm.status |= WME_STATUS_NEWAC;
4083 /* Fill in shm acparam table */
4084 shm_entry = (u16 *) &acp_shm;
4085 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4086 brcms_b_write_shm(wlc->hw,
4088 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4093 brcms_c_suspend_mac_and_wait(wlc);
4094 brcms_c_enable_mac(wlc);
4098 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4102 struct ieee80211_tx_queue_params txq_pars;
4103 static const struct edcf_acparam default_edcf_acparams[] = {
4104 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4105 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4106 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4107 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4108 }; /* ucode needs these parameters during its initialization */
4109 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4111 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4112 /* find out which ac this set of params applies to */
4113 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4115 /* fill in shm ac params struct */
4116 txq_pars.txop = edcf_acp->TXOP;
4117 txq_pars.aifs = edcf_acp->ACI;
4119 /* CWmin = 2^(ECWmin) - 1 */
4120 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4121 /* CWmax = 2^(ECWmax) - 1 */
4122 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4123 >> EDCF_ECWMAX_SHIFT);
4124 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4128 brcms_c_suspend_mac_and_wait(wlc);
4129 brcms_c_enable_mac(wlc);
4133 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4135 /* Don't start the timer if HWRADIO feature is disabled */
4136 if (wlc->radio_monitor)
4139 wlc->radio_monitor = true;
4140 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4141 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4144 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4146 if (!wlc->radio_monitor)
4149 wlc->radio_monitor = false;
4150 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4151 return brcms_del_timer(wlc->radio_timer);
4154 /* read hwdisable state and propagate to wlc flag */
4155 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4157 if (wlc->pub->hw_off)
4160 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4161 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4163 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4166 /* update hwradio status and return it */
4167 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4169 brcms_c_radio_hwdisable_upd(wlc);
4171 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4175 /* periodical query hw radio button while driver is "down" */
4176 static void brcms_c_radio_timer(void *arg)
4178 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4180 if (brcms_deviceremoved(wlc)) {
4181 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4182 wlc->pub->unit, __func__);
4183 brcms_down(wlc->wl);
4187 brcms_c_radio_hwdisable_upd(wlc);
4190 /* common low-level watchdog code */
4191 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4193 struct brcms_hardware *wlc_hw = wlc->hw;
4198 /* increment second count */
4201 /* Check for FIFO error interrupts */
4202 brcms_b_fifoerrors(wlc_hw);
4204 /* make sure RX dma has buffers */
4205 dma_rxfill(wlc->hw->di[RX_FIFO]);
4207 wlc_phy_watchdog(wlc_hw->band->pi);
4210 /* common watchdog code */
4211 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4213 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4218 if (brcms_deviceremoved(wlc)) {
4219 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4220 wlc->pub->unit, __func__);
4221 brcms_down(wlc->wl);
4225 /* increment second count */
4228 brcms_c_radio_hwdisable_upd(wlc);
4229 /* if radio is disable, driver may be down, quit here */
4230 if (wlc->pub->radio_disabled)
4233 brcms_b_watchdog(wlc);
4236 * occasionally sample mac stat counters to
4237 * detect 16-bit counter wrap
4239 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4240 brcms_c_statsupd(wlc);
4242 if (BRCMS_ISNPHY(wlc->band) &&
4243 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4244 BRCMS_TEMPSENSE_PERIOD)) {
4245 wlc->tempsense_lasttime = wlc->pub->now;
4246 brcms_c_tempsense_upd(wlc);
4250 static void brcms_c_watchdog_by_timer(void *arg)
4252 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4254 brcms_c_watchdog(wlc);
4257 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4259 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4261 if (!wlc->wdtimer) {
4262 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4267 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4269 if (!wlc->radio_timer) {
4270 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4282 * Initialize brcms_c_info default values ...
4283 * may get overrides later in this function
4285 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4289 /* Save our copy of the chanspec */
4290 wlc->chanspec = ch20mhz_chspec(1);
4292 /* various 802.11g modes */
4293 wlc->shortslot = false;
4294 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4296 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4297 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4299 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4300 BRCMS_PROTECTION_AUTO);
4301 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4302 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4303 BRCMS_PROTECTION_AUTO);
4304 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4305 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4307 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4308 BRCMS_PROTECTION_CTL_OVERLAP);
4310 /* 802.11g draft 4.0 NonERP elt advertisement */
4311 wlc->include_legacy_erp = true;
4313 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4314 wlc->stf->txant = ANT_TX_DEF;
4316 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4318 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4319 for (i = 0; i < NFIFO; i++)
4320 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4321 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4323 /* default rate fallback retry limits */
4324 wlc->SFBL = RETRY_SHORT_FB;
4325 wlc->LFBL = RETRY_LONG_FB;
4327 /* default mac retry limits */
4328 wlc->SRL = RETRY_SHORT_DEF;
4329 wlc->LRL = RETRY_LONG_DEF;
4331 /* WME QoS mode is Auto by default */
4332 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4333 wlc->pub->bcmerror = 0;
4336 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4340 unit = wlc->pub->unit;
4342 wlc->asi = brcms_c_antsel_attach(wlc);
4343 if (wlc->asi == NULL) {
4344 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4350 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4351 if (wlc->ampdu == NULL) {
4352 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4358 if ((brcms_c_stf_attach(wlc) != 0)) {
4359 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4368 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4374 * run backplane attach, init nvram
4376 * initialize software state for each core and band
4377 * put the whole chip in reset(driver down state), no clock
4379 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4380 uint unit, bool piomode)
4382 struct brcms_hardware *wlc_hw;
4386 struct shared_phy_params sha_params;
4387 struct wiphy *wiphy = wlc->wiphy;
4388 struct pci_dev *pcidev = core->bus->host_pci;
4389 struct ssb_sprom *sprom = &core->bus->sprom;
4391 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4392 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4396 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4397 core->bus->boardinfo.vendor,
4398 core->bus->boardinfo.type);
4404 wlc_hw->unit = unit;
4405 wlc_hw->band = wlc_hw->bandstate[0];
4406 wlc_hw->_piomode = piomode;
4408 /* populate struct brcms_hardware with default values */
4409 brcms_b_info_init(wlc_hw);
4412 * Do the hardware portion of the attach. Also initialize software
4413 * state that depends on the particular hardware we are running.
4415 wlc_hw->sih = ai_attach(core->bus);
4416 if (wlc_hw->sih == NULL) {
4417 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4423 /* verify again the device is supported */
4424 if (!brcms_c_chipmatch(core)) {
4425 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4431 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4432 wlc_hw->vendorid = pcidev->vendor;
4433 wlc_hw->deviceid = pcidev->device;
4435 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4436 wlc_hw->deviceid = core->bus->boardinfo.type;
4439 wlc_hw->d11core = core;
4440 wlc_hw->corerev = core->id.rev;
4442 /* validate chip, chiprev and corerev */
4443 if (!brcms_c_isgoodchip(wlc_hw)) {
4448 /* initialize power control registers */
4449 ai_clkctl_init(wlc_hw->sih);
4451 /* request fastclock and force fastclock for the rest of attach
4452 * bring the d11 core out of reset.
4453 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4454 * is still false; But it will be called again inside wlc_corereset,
4455 * after d11 is out of reset.
4457 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4458 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4460 if (!brcms_b_validate_chip_access(wlc_hw)) {
4461 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4467 /* get the board rev, used just below */
4468 j = sprom->board_rev;
4469 /* promote srom boardrev of 0xFF to 1 */
4470 if (j == BOARDREV_PROMOTABLE)
4471 j = BOARDREV_PROMOTED;
4472 wlc_hw->boardrev = (u16) j;
4473 if (!brcms_c_validboardtype(wlc_hw)) {
4474 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4475 "board type (0x%x)" " or revision level (0x%x)\n",
4476 unit, ai_get_boardtype(wlc_hw->sih),
4481 wlc_hw->sromrev = sprom->revision;
4482 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4483 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4485 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4486 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4488 /* check device id(srom, nvram etc.) to set bands */
4489 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4490 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4491 wlc_hw->deviceid == BCM43224_CHIP_ID)
4492 /* Dualband boards */
4493 wlc_hw->_nbands = 2;
4495 wlc_hw->_nbands = 1;
4497 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4498 wlc_hw->_nbands = 1;
4500 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4501 * unconditionally does the init of these values
4503 wlc->vendorid = wlc_hw->vendorid;
4504 wlc->deviceid = wlc_hw->deviceid;
4505 wlc->pub->sih = wlc_hw->sih;
4506 wlc->pub->corerev = wlc_hw->corerev;
4507 wlc->pub->sromrev = wlc_hw->sromrev;
4508 wlc->pub->boardrev = wlc_hw->boardrev;
4509 wlc->pub->boardflags = wlc_hw->boardflags;
4510 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4511 wlc->pub->_nbands = wlc_hw->_nbands;
4513 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4515 if (wlc_hw->physhim == NULL) {
4516 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4522 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4523 sha_params.sih = wlc_hw->sih;
4524 sha_params.physhim = wlc_hw->physhim;
4525 sha_params.unit = unit;
4526 sha_params.corerev = wlc_hw->corerev;
4527 sha_params.vid = wlc_hw->vendorid;
4528 sha_params.did = wlc_hw->deviceid;
4529 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4530 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4531 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4532 sha_params.sromrev = wlc_hw->sromrev;
4533 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4534 sha_params.boardrev = wlc_hw->boardrev;
4535 sha_params.boardflags = wlc_hw->boardflags;
4536 sha_params.boardflags2 = wlc_hw->boardflags2;
4538 /* alloc and save pointer to shared phy state area */
4539 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4540 if (!wlc_hw->phy_sh) {
4545 /* initialize software state for each core and band */
4546 for (j = 0; j < wlc_hw->_nbands; j++) {
4548 * band0 is always 2.4Ghz
4549 * band1, if present, is 5Ghz
4552 brcms_c_setxband(wlc_hw, j);
4554 wlc_hw->band->bandunit = j;
4555 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4556 wlc->band->bandunit = j;
4557 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4558 wlc->core->coreidx = core->core_index;
4560 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4561 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4563 /* init tx fifo size */
4564 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4565 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4566 ARRAY_SIZE(xmtfifo_sz));
4567 wlc_hw->xmtfifo_sz =
4568 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4569 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4571 /* Get a phy for this band */
4573 wlc_phy_attach(wlc_hw->phy_sh, core,
4574 wlc_hw->band->bandtype,
4576 if (wlc_hw->band->pi == NULL) {
4577 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4578 "attach failed\n", unit);
4583 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4585 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4586 &wlc_hw->band->phyrev,
4587 &wlc_hw->band->radioid,
4588 &wlc_hw->band->radiorev);
4589 wlc_hw->band->abgphy_encore =
4590 wlc_phy_get_encore(wlc_hw->band->pi);
4591 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4592 wlc_hw->band->core_flags =
4593 wlc_phy_get_coreflags(wlc_hw->band->pi);
4595 /* verify good phy_type & supported phy revision */
4596 if (BRCMS_ISNPHY(wlc_hw->band)) {
4597 if (NCONF_HAS(wlc_hw->band->phyrev))
4601 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4602 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4608 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4609 "phy type/rev (%d/%d)\n", unit,
4610 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4617 * BMAC_NOTE: wlc->band->pi should not be set below and should
4618 * be done in the high level attach. However we can not make
4619 * that change until all low level access is changed to
4620 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4621 * keeping wlc_hw->band->pi as well for incremental update of
4622 * low level fns, and cut over low only init when all fns
4625 wlc->band->pi = wlc_hw->band->pi;
4626 wlc->band->phytype = wlc_hw->band->phytype;
4627 wlc->band->phyrev = wlc_hw->band->phyrev;
4628 wlc->band->radioid = wlc_hw->band->radioid;
4629 wlc->band->radiorev = wlc_hw->band->radiorev;
4631 /* default contention windows size limits */
4632 wlc_hw->band->CWmin = APHY_CWMIN;
4633 wlc_hw->band->CWmax = PHY_CWMAX;
4635 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4641 /* disable core to match driver "down" state */
4642 brcms_c_coredisable(wlc_hw);
4644 /* Match driver "down" state */
4645 ai_pci_down(wlc_hw->sih);
4647 /* turn off pll and xtal to match driver "down" state */
4648 brcms_b_xtal(wlc_hw, OFF);
4650 /* *******************************************************************
4651 * The hardware is in the DOWN state at this point. D11 core
4652 * or cores are in reset with clocks off, and the board PLLs
4653 * are off if possible.
4655 * Beyond this point, wlc->sbclk == false and chip registers
4656 * should not be touched.
4657 *********************************************************************
4660 /* init etheraddr state variables */
4661 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4663 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4664 is_zero_ether_addr(wlc_hw->etheraddr)) {
4665 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4671 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4672 wlc_hw->deviceid, wlc_hw->_nbands,
4673 ai_get_boardtype(wlc_hw->sih));
4678 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4683 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4686 unit = wlc->pub->unit;
4688 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4689 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4690 wlc->band->antgain = 8;
4691 } else if (wlc->band->antgain == -1) {
4692 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4693 " srom, using 2dB\n", unit, __func__);
4694 wlc->band->antgain = 8;
4697 /* Older sroms specified gain in whole dbm only. In order
4698 * be able to specify qdbm granularity and remain backward
4699 * compatible the whole dbms are now encoded in only
4700 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4701 * 6 bit signed number ranges from -32 - 31.
4705 * 0xc1 = 1.75 db (1 + 3 quarters),
4706 * 0x3f = -1 (-1 + 0 quarters),
4707 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4708 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4710 gain = wlc->band->antgain & 0x3f;
4711 gain <<= 2; /* Sign extend */
4713 fract = (wlc->band->antgain & 0xc0) >> 6;
4714 wlc->band->antgain = 4 * gain + fract;
4718 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4723 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4725 unit = wlc->pub->unit;
4726 bandtype = wlc->band->bandtype;
4728 /* get antennas available */
4729 if (bandtype == BRCM_BAND_5G)
4730 aa = sprom->ant_available_a;
4732 aa = sprom->ant_available_bg;
4734 if ((aa < 1) || (aa > 15)) {
4735 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4736 " srom (0x%x), using 3\n", unit, __func__, aa);
4740 /* reset the defaults if we have a single antenna */
4742 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4743 wlc->stf->txant = ANT_TX_FORCE_0;
4744 } else if (aa == 2) {
4745 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4746 wlc->stf->txant = ANT_TX_FORCE_1;
4750 /* Compute Antenna Gain */
4751 if (bandtype == BRCM_BAND_5G)
4752 wlc->band->antgain = sprom->antenna_gain.a1;
4754 wlc->band->antgain = sprom->antenna_gain.a0;
4756 brcms_c_attach_antgain_init(wlc);
4761 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4764 struct brcms_band *band;
4765 struct brcms_bss_info *bi = wlc->default_bss;
4767 /* init default and target BSS with some sane initial values */
4768 memset(bi, 0, sizeof(*bi));
4769 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4771 /* fill the default channel as the first valid channel
4772 * starting from the 2G channels
4774 chanspec = ch20mhz_chspec(1);
4775 wlc->home_chanspec = bi->chanspec = chanspec;
4777 /* find the band of our default channel */
4779 if (wlc->pub->_nbands > 1 &&
4780 band->bandunit != chspec_bandunit(chanspec))
4781 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4783 /* init bss rates to the band specific default rate set */
4784 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4785 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4786 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4787 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4789 if (wlc->pub->_n_enab & SUPPORT_11N)
4790 bi->flags |= BRCMS_BSS_HT;
4793 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4796 struct brcms_band *band;
4798 for (i = 0; i < wlc->pub->_nbands; i++) {
4799 band = wlc->bandstate[i];
4800 if (band->bandtype == BRCM_BAND_5G) {
4801 if ((bwcap == BRCMS_N_BW_40ALL)
4802 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4803 band->mimo_cap_40 = true;
4805 band->mimo_cap_40 = false;
4807 if (bwcap == BRCMS_N_BW_40ALL)
4808 band->mimo_cap_40 = true;
4810 band->mimo_cap_40 = false;
4815 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4817 /* free timer state */
4819 brcms_free_timer(wlc->wdtimer);
4820 wlc->wdtimer = NULL;
4822 if (wlc->radio_timer) {
4823 brcms_free_timer(wlc->radio_timer);
4824 wlc->radio_timer = NULL;
4828 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4831 brcms_c_antsel_detach(wlc->asi);
4836 brcms_c_ampdu_detach(wlc->ampdu);
4840 brcms_c_stf_detach(wlc);
4846 static int brcms_b_detach(struct brcms_c_info *wlc)
4849 struct brcms_hw_band *band;
4850 struct brcms_hardware *wlc_hw = wlc->hw;
4855 brcms_b_detach_dmapio(wlc_hw);
4857 band = wlc_hw->band;
4858 for (i = 0; i < wlc_hw->_nbands; i++) {
4860 /* Detach this band's phy */
4861 wlc_phy_detach(band->pi);
4864 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4867 /* Free shared phy state */
4868 kfree(wlc_hw->phy_sh);
4870 wlc_phy_shim_detach(wlc_hw->physhim);
4873 ai_detach(wlc_hw->sih);
4882 * Return a count of the number of driver callbacks still pending.
4884 * General policy is that brcms_c_detach can only dealloc/free software states.
4885 * It can NOT touch hardware registers since the d11core may be in reset and
4886 * clock may not be available.
4887 * One exception is sb register access, which is possible if crystal is turned
4888 * on after "down" state, driver should avoid software timer with the exception
4891 uint brcms_c_detach(struct brcms_c_info *wlc)
4898 callbacks += brcms_b_detach(wlc);
4900 /* delete software timers */
4901 if (!brcms_c_radio_monitor_stop(wlc))
4904 brcms_c_channel_mgr_detach(wlc->cmi);
4906 brcms_c_timers_deinit(wlc);
4908 brcms_c_detach_module(wlc);
4910 brcms_c_detach_mfree(wlc);
4914 /* update state that depends on the current value of "ap" */
4915 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4917 /* STA-BSS; short capable */
4918 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4921 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4922 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4924 if (wlc_hw->wlc->pub->hw_up)
4927 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4930 * Enable pll and xtal, initialize the power control registers,
4931 * and force fastclock for the remainder of brcms_c_up().
4933 brcms_b_xtal(wlc_hw, ON);
4934 ai_clkctl_init(wlc_hw->sih);
4935 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4938 * TODO: test suspend/resume
4940 * AI chip doesn't restore bar0win2 on
4941 * hibernation/resume, need sw fixup
4945 * Inform phy that a POR reset has occurred so
4946 * it does a complete phy init
4948 wlc_phy_por_inform(wlc_hw->band->pi);
4950 wlc_hw->ucode_loaded = false;
4951 wlc_hw->wlc->pub->hw_up = true;
4953 if ((wlc_hw->boardflags & BFL_FEM)
4954 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4956 (wlc_hw->boardrev >= 0x1250
4957 && (wlc_hw->boardflags & BFL_FEM_BT)))
4958 ai_epa_4313war(wlc_hw->sih);
4962 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4964 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4967 * Enable pll and xtal, initialize the power control registers,
4968 * and force fastclock for the remainder of brcms_c_up().
4970 brcms_b_xtal(wlc_hw, ON);
4971 ai_clkctl_init(wlc_hw->sih);
4972 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4975 * Configure pci/pcmcia here instead of in brcms_c_attach()
4976 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
4978 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4982 * Need to read the hwradio status here to cover the case where the
4983 * system is loaded with the hw radio disabled. We do not want to
4984 * bring the driver up in this case.
4986 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4987 /* put SB PCI in down state again */
4988 ai_pci_down(wlc_hw->sih);
4989 brcms_b_xtal(wlc_hw, OFF);
4993 ai_pci_up(wlc_hw->sih);
4995 /* reset the d11 core */
4996 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5001 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5004 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5006 /* FULLY enable dynamic power control and d11 core interrupt */
5007 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5008 brcms_intrson(wlc_hw->wlc->wl);
5013 * Write WME tunable parameters for retransmit/max rate
5014 * from wlc struct to ucode
5016 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5020 /* Need clock to do this */
5024 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5025 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5026 wlc->wme_retries[ac]);
5029 /* make interface operational */
5030 int brcms_c_up(struct brcms_c_info *wlc)
5032 struct ieee80211_channel *ch;
5034 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5036 /* HW is turned off so don't try to access it */
5037 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5040 if (!wlc->pub->hw_up) {
5041 brcms_b_hw_up(wlc->hw);
5042 wlc->pub->hw_up = true;
5045 if ((wlc->pub->boardflags & BFL_FEM)
5046 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5047 if (wlc->pub->boardrev >= 0x1250
5048 && (wlc->pub->boardflags & BFL_FEM_BT))
5049 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5050 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5052 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5053 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5057 * Need to read the hwradio status here to cover the case where the
5058 * system is loaded with the hw radio disabled. We do not want to bring
5059 * the driver up in this case. If radio is disabled, abort up, lower
5060 * power, start radio timer and return 0(for NDIS) don't call
5061 * radio_update to avoid looping brcms_c_up.
5063 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5065 if (!wlc->pub->radio_disabled) {
5066 int status = brcms_b_up_prep(wlc->hw);
5067 if (status == -ENOMEDIUM) {
5069 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5070 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5071 mboolset(wlc->pub->radio_disabled,
5072 WL_RADIO_HW_DISABLE);
5073 if (bsscfg->enable &&
5074 (bsscfg->type == BRCMS_TYPE_STATION ||
5075 bsscfg->type == BRCMS_TYPE_ADHOC))
5076 brcms_err(wlc->hw->d11core,
5077 "wl%d: up: rfdisable -> "
5078 "bsscfg_disable()\n",
5084 if (wlc->pub->radio_disabled) {
5085 brcms_c_radio_monitor_start(wlc);
5089 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5092 brcms_c_radio_monitor_stop(wlc);
5094 /* Set EDCF hostflags */
5095 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5097 brcms_init(wlc->wl);
5098 wlc->pub->up = true;
5100 if (wlc->bandinit_pending) {
5101 ch = wlc->pub->ieee_hw->conf.channel;
5102 brcms_c_suspend_mac_and_wait(wlc);
5103 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5104 wlc->bandinit_pending = false;
5105 brcms_c_enable_mac(wlc);
5108 brcms_b_up_finish(wlc->hw);
5110 /* Program the TX wme params with the current settings */
5111 brcms_c_wme_retries_write(wlc);
5113 /* start one second watchdog timer */
5114 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5115 wlc->WDarmed = true;
5117 /* ensure antenna config is up to date */
5118 brcms_c_stf_phy_txant_upd(wlc);
5119 /* ensure LDPC config is in sync */
5120 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5125 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5132 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5140 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5142 /* disable interrupts */
5144 wlc_hw->wlc->macintmask = 0;
5146 /* now disable interrupts */
5147 brcms_intrsoff(wlc_hw->wlc->wl);
5149 /* ensure we're running on the pll clock again */
5150 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5152 /* down phy at the last of this stage */
5153 callbacks += wlc_phy_down(wlc_hw->band->pi);
5158 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5167 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5169 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5172 wlc_hw->sbclk = false;
5173 wlc_hw->clk = false;
5174 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5176 /* reclaim any posted packets */
5177 brcms_c_flushqueues(wlc_hw->wlc);
5180 /* Reset and disable the core */
5181 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5182 if (bcma_read32(wlc_hw->d11core,
5183 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5184 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5185 callbacks += brcms_reset(wlc_hw->wlc->wl);
5186 brcms_c_coredisable(wlc_hw);
5189 /* turn off primary xtal and pll */
5190 if (!wlc_hw->noreset) {
5191 ai_pci_down(wlc_hw->sih);
5192 brcms_b_xtal(wlc_hw, OFF);
5200 * Mark the interface nonoperational, stop the software mechanisms,
5201 * disable the hardware, free any transient buffer state.
5202 * Return a count of the number of driver callbacks still pending.
5204 uint brcms_c_down(struct brcms_c_info *wlc)
5209 bool dev_gone = false;
5211 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5213 /* check if we are already in the going down path */
5214 if (wlc->going_down) {
5215 brcms_err(wlc->hw->d11core,
5216 "wl%d: %s: Driver going down so return\n",
5217 wlc->pub->unit, __func__);
5223 wlc->going_down = true;
5225 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5227 dev_gone = brcms_deviceremoved(wlc);
5229 /* Call any registered down handlers */
5230 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5231 if (wlc->modulecb[i].down_fn)
5233 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5236 /* cancel the watchdog timer */
5238 if (!brcms_del_timer(wlc->wdtimer))
5240 wlc->WDarmed = false;
5242 /* cancel all other timers */
5243 callbacks += brcms_c_down_del_timer(wlc);
5245 wlc->pub->up = false;
5247 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5249 callbacks += brcms_b_down_finish(wlc->hw);
5251 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5254 wlc->going_down = false;
5258 /* Set the current gmode configuration */
5259 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5263 struct brcms_c_rateset rs;
5264 /* Default to 54g Auto */
5265 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5266 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5267 bool shortslot_restrict = false; /* Restrict association to stations
5268 * that support shortslot
5270 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5271 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5272 int preamble = BRCMS_PLCP_LONG;
5273 bool preamble_restrict = false; /* Restrict association to stations
5274 * that support short preambles
5276 struct brcms_band *band;
5278 /* if N-support is enabled, allow Gmode set as long as requested
5279 * Gmode is not GMODE_LEGACY_B
5281 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5284 /* verify that we are dealing with 2G band and grab the band pointer */
5285 if (wlc->band->bandtype == BRCM_BAND_2G)
5287 else if ((wlc->pub->_nbands > 1) &&
5288 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5289 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5293 /* update configuration value */
5295 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5297 /* Clear rateset override */
5298 memset(&rs, 0, sizeof(rs));
5301 case GMODE_LEGACY_B:
5302 shortslot = BRCMS_SHORTSLOT_OFF;
5303 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5311 /* Accept defaults */
5316 preamble = BRCMS_PLCP_SHORT;
5317 preamble_restrict = true;
5320 case GMODE_PERFORMANCE:
5321 shortslot = BRCMS_SHORTSLOT_ON;
5322 shortslot_restrict = true;
5324 preamble = BRCMS_PLCP_SHORT;
5325 preamble_restrict = true;
5330 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5331 wlc->pub->unit, __func__, gmode);
5335 band->gmode = gmode;
5337 wlc->shortslot_override = shortslot;
5339 /* Use the default 11g rateset */
5341 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5344 for (i = 0; i < rs.count; i++) {
5345 if (rs.rates[i] == BRCM_RATE_6M
5346 || rs.rates[i] == BRCM_RATE_12M
5347 || rs.rates[i] == BRCM_RATE_24M)
5348 rs.rates[i] |= BRCMS_RATE_FLAG;
5352 /* Set default bss rateset */
5353 wlc->default_bss->rateset.count = rs.count;
5354 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5355 sizeof(wlc->default_bss->rateset.rates));
5360 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5365 if (wlc->stf->txstreams == WL_11N_3x3)
5370 /* force GMODE_AUTO if NMODE is ON */
5371 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5372 if (nmode == WL_11N_3x3)
5373 wlc->pub->_n_enab = SUPPORT_HT;
5375 wlc->pub->_n_enab = SUPPORT_11N;
5376 wlc->default_bss->flags |= BRCMS_BSS_HT;
5377 /* add the mcs rates to the default and hw ratesets */
5378 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5379 wlc->stf->txstreams);
5380 for (i = 0; i < wlc->pub->_nbands; i++)
5381 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5382 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5388 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5389 struct brcms_c_rateset *rs_arg)
5391 struct brcms_c_rateset rs, new;
5394 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5396 /* check for bad count value */
5397 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5400 /* try the current band */
5401 bandunit = wlc->band->bandunit;
5402 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5403 if (brcms_c_rate_hwrs_filter_sort_validate
5404 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5405 wlc->stf->txstreams))
5408 /* try the other band */
5409 if (brcms_is_mband_unlocked(wlc)) {
5410 bandunit = OTHERBANDUNIT(wlc);
5411 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5412 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5414 bandstate[bandunit]->
5416 wlc->stf->txstreams))
5423 /* apply new rateset */
5424 memcpy(&wlc->default_bss->rateset, &new,
5425 sizeof(struct brcms_c_rateset));
5426 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5427 sizeof(struct brcms_c_rateset));
5431 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5436 if (wlc->bsscfg->associated)
5437 r = wlc->bsscfg->current_bss->rateset.rates[0];
5439 r = wlc->default_bss->rateset.rates[0];
5441 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5444 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5446 u16 chspec = ch20mhz_chspec(channel);
5448 if (channel < 0 || channel > MAXCHANNEL)
5451 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5455 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5456 if (wlc->band->bandunit != chspec_bandunit(chspec))
5457 wlc->bandinit_pending = true;
5459 wlc->bandinit_pending = false;
5462 wlc->default_bss->chanspec = chspec;
5463 /* brcms_c_BSSinit() will sanitize the rateset before
5465 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5466 brcms_c_set_home_chanspec(wlc, chspec);
5467 brcms_c_suspend_mac_and_wait(wlc);
5468 brcms_c_set_chanspec(wlc, chspec);
5469 brcms_c_enable_mac(wlc);
5474 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5478 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5479 lrl < 1 || lrl > RETRY_SHORT_MAX)
5485 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5487 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5488 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5489 EDCF_SHORT, wlc->SRL);
5490 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5491 EDCF_LONG, wlc->LRL);
5493 brcms_c_wme_retries_write(wlc);
5498 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5499 struct brcm_rateset *currs)
5501 struct brcms_c_rateset *rs;
5503 if (wlc->pub->associated)
5504 rs = &wlc->bsscfg->current_bss->rateset;
5506 rs = &wlc->default_bss->rateset;
5508 /* Copy only legacy rateset section */
5509 currs->count = rs->count;
5510 memcpy(&currs->rates, &rs->rates, rs->count);
5513 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5515 struct brcms_c_rateset internal_rs;
5518 if (rs->count > BRCMS_NUMRATES)
5521 memset(&internal_rs, 0, sizeof(internal_rs));
5523 /* Copy only legacy rateset section */
5524 internal_rs.count = rs->count;
5525 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5527 /* merge rateset coming in with the current mcsset */
5528 if (wlc->pub->_n_enab & SUPPORT_11N) {
5529 struct brcms_bss_info *mcsset_bss;
5530 if (wlc->bsscfg->associated)
5531 mcsset_bss = wlc->bsscfg->current_bss;
5533 mcsset_bss = wlc->default_bss;
5534 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5538 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5540 brcms_c_ofdm_rateset_war(wlc);
5545 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5547 bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5548 /* Commit the write */
5549 bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5552 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5554 bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5555 /* Commit the write */
5556 bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5559 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5564 wlc->default_bss->beacon_period = period;
5568 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5570 return wlc->band->phytype;
5573 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5575 wlc->shortslot_override = sslot_override;
5578 * shortslot is an 11g feature, so no more work if we are
5579 * currently on the 5G band
5581 if (wlc->band->bandtype == BRCM_BAND_5G)
5584 if (wlc->pub->up && wlc->pub->associated) {
5585 /* let watchdog or beacon processing update shortslot */
5586 } else if (wlc->pub->up) {
5587 /* unassociated shortslot is off */
5588 brcms_c_switch_shortslot(wlc, false);
5590 /* driver is down, so just update the brcms_c_info
5592 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5593 wlc->shortslot = false;
5596 (wlc->shortslot_override ==
5597 BRCMS_SHORTSLOT_ON);
5602 * register watchdog and down handlers.
5604 int brcms_c_module_register(struct brcms_pub *pub,
5605 const char *name, struct brcms_info *hdl,
5606 int (*d_fn)(void *handle))
5608 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5611 /* find an empty entry and just add, no duplication check! */
5612 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5613 if (wlc->modulecb[i].name[0] == '\0') {
5614 strncpy(wlc->modulecb[i].name, name,
5615 sizeof(wlc->modulecb[i].name) - 1);
5616 wlc->modulecb[i].hdl = hdl;
5617 wlc->modulecb[i].down_fn = d_fn;
5625 /* unregister module callbacks */
5626 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5627 struct brcms_info *hdl)
5629 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5635 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5636 if (!strcmp(wlc->modulecb[i].name, name) &&
5637 (wlc->modulecb[i].hdl == hdl)) {
5638 memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5643 /* table not found! */
5647 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5649 struct pci_dev *pcidev = core->bus->host_pci;
5650 u16 vendor = pcidev->vendor;
5651 u16 device = pcidev->device;
5653 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5654 pr_err("unknown vendor id %04x\n", vendor);
5658 if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5660 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5662 if (device == BCM4313_D11N2G_ID)
5664 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5667 pr_err("unknown device id %04x\n", device);
5671 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5673 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5675 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5678 pr_err("unknown chip id %04x\n", chipinfo->id);
5682 bool brcms_c_chipmatch(struct bcma_device *core)
5684 switch (core->bus->hosttype) {
5685 case BCMA_HOSTTYPE_PCI:
5686 return brcms_c_chipmatch_pci(core);
5687 case BCMA_HOSTTYPE_SOC:
5688 return brcms_c_chipmatch_soc(core);
5690 pr_err("unknown host type: %i\n", core->bus->hosttype);
5695 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5700 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5701 if (is_ofdm_rate(rate))
5702 table_ptr = M_RT_DIRMAP_A;
5704 table_ptr = M_RT_DIRMAP_B;
5706 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5707 * the index into the rate table.
5709 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5710 index = phy_rate & 0xf;
5712 /* Find the SHM pointer to the rate table entry by looking in the
5715 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5719 * bcmc_fid_generate:
5720 * Generate frame ID for a BCMC packet. The frag field is not used
5721 * for MC frames so is used as part of the sequence number.
5724 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5729 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5733 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5740 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5746 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5747 * is less than or equal to the rate of the immediately previous
5750 rspec = brcms_basic_rate(wlc, rspec);
5751 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5753 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5754 (DOT11_ACK_LEN + FCS_LEN));
5759 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5762 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5766 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5770 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5771 * is less than or equal to the rate of the immediately previous
5774 rspec = brcms_basic_rate(wlc, rspec);
5775 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5776 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5777 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5781 /* brcms_c_compute_frame_dur()
5783 * Calculate the 802.11 MAC header DUR field for MPDU
5784 * DUR for a single frame = 1 SIFS + 1 ACK
5785 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5787 * rate MPDU rate in unit of 500kbps
5788 * next_frag_len next MPDU length in bytes
5789 * preamble_type use short/GF or long/MM PLCP header
5792 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5793 u8 preamble_type, uint next_frag_len)
5797 sifs = get_sifs(wlc->band);
5800 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5802 if (next_frag_len) {
5803 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5805 /* add another SIFS and the frag time */
5808 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5814 /* The opposite of brcms_c_calc_frame_time */
5816 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5817 u8 preamble_type, uint dur)
5819 uint nsyms, mac_len, Ndps, kNdps;
5820 uint rate = rspec2rate(ratespec);
5822 if (is_mcs_rate(ratespec)) {
5823 uint mcs = ratespec & RSPEC_RATE_MASK;
5824 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5825 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5826 /* payload calculation matches that of regular ofdm */
5827 if (wlc->band->bandtype == BRCM_BAND_2G)
5828 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5829 /* kNdbps = kbps * 4 */
5830 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5831 rspec_issgi(ratespec)) * 4;
5832 nsyms = dur / APHY_SYMBOL_TIME;
5835 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5836 } else if (is_ofdm_rate(ratespec)) {
5837 dur -= APHY_PREAMBLE_TIME;
5838 dur -= APHY_SIGNAL_TIME;
5839 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5841 nsyms = dur / APHY_SYMBOL_TIME;
5844 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5846 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5847 dur -= BPHY_PLCP_SHORT_TIME;
5849 dur -= BPHY_PLCP_TIME;
5850 mac_len = dur * rate;
5851 /* divide out factor of 2 in rate (1/2 mbps) */
5852 mac_len = mac_len / 8 / 2;
5858 * Return true if the specified rate is supported by the specified band.
5859 * BRCM_BAND_AUTO indicates the current band.
5861 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5864 struct brcms_c_rateset *hw_rateset;
5867 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5868 hw_rateset = &wlc->band->hw_rateset;
5869 else if (wlc->pub->_nbands > 1)
5870 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5872 /* other band specified and we are a single band device */
5875 /* check if this is a mimo rate */
5876 if (is_mcs_rate(rspec)) {
5877 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5880 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5883 for (i = 0; i < hw_rateset->count; i++)
5884 if (hw_rateset->rates[i] == rspec2rate(rspec))
5888 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5889 "not in hw_rateset\n", wlc->pub->unit, rspec);
5895 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5898 struct bcma_device *core = wlc->hw->d11core;
5899 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5900 u8 rate = int_val & NRATE_RATE_MASK;
5902 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5903 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5904 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5905 == NRATE_OVERRIDE_MCS_ONLY);
5911 /* validate the combination of rate/mcs/stf is allowed */
5912 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5913 /* mcs only allowed when nmode */
5914 if (stf > PHY_TXC1_MODE_SDM) {
5915 brcms_err(core, "wl%d: %s: Invalid stf\n",
5916 wlc->pub->unit, __func__);
5921 /* mcs 32 is a special case, DUP mode 40 only */
5923 if (!CHSPEC_IS40(wlc->home_chanspec) ||
5924 ((stf != PHY_TXC1_MODE_SISO)
5925 && (stf != PHY_TXC1_MODE_CDD))) {
5926 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5927 wlc->pub->unit, __func__);
5931 /* mcs > 7 must use stf SDM */
5932 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5933 /* mcs > 7 must use stf SDM */
5934 if (stf != PHY_TXC1_MODE_SDM) {
5935 brcms_dbg_mac80211(core, "wl%d: enabling "
5936 "SDM mode for mcs %d\n",
5937 wlc->pub->unit, rate);
5938 stf = PHY_TXC1_MODE_SDM;
5942 * MCS 0-7 may use SISO, CDD, and for
5945 if ((stf > PHY_TXC1_MODE_STBC) ||
5946 (!BRCMS_STBC_CAP_PHY(wlc)
5947 && (stf == PHY_TXC1_MODE_STBC))) {
5948 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5949 wlc->pub->unit, __func__);
5954 } else if (is_ofdm_rate(rate)) {
5955 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5956 brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5957 wlc->pub->unit, __func__);
5961 } else if (is_cck_rate(rate)) {
5962 if ((cur_band->bandtype != BRCM_BAND_2G)
5963 || (stf != PHY_TXC1_MODE_SISO)) {
5964 brcms_err(core, "wl%d: %s: Invalid CCK\n",
5965 wlc->pub->unit, __func__);
5970 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5971 wlc->pub->unit, __func__);
5975 /* make sure multiple antennae are available for non-siso rates */
5976 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5977 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5978 "request\n", wlc->pub->unit, __func__);
5985 rspec |= RSPEC_MIMORATE;
5986 /* For STBC populate the STC field of the ratespec */
5987 if (stf == PHY_TXC1_MODE_STBC) {
5989 stc = 1; /* Nss for single stream is always 1 */
5990 rspec |= (stc << RSPEC_STC_SHIFT);
5994 rspec |= (stf << RSPEC_STF_SHIFT);
5996 if (override_mcs_only)
5997 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6000 rspec |= RSPEC_SHORT_GI;
6003 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6012 * Compute PLCP, but only requires actual rate and length of pkt.
6013 * Rate is given in the driver standard multiple of 500 kbps.
6014 * le is set for 11 Mbps rate if necessary.
6015 * Broken out for PRQ.
6018 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6019 uint length, u8 *plcp)
6032 usec = (length << 4) / 11;
6033 if ((length << 4) - (usec * 11) > 0)
6037 usec = (length << 3) / 11;
6038 if ((length << 3) - (usec * 11) > 0) {
6040 if ((usec * 11) - (length << 3) >= 8)
6041 le = D11B_PLCP_SIGNAL_LE;
6046 brcms_err(wlc->hw->d11core,
6047 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6049 rate_500 = BRCM_RATE_1M;
6053 /* PLCP signal byte */
6054 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6055 /* PLCP service byte */
6056 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6057 /* PLCP length u16, little endian */
6058 plcp[2] = usec & 0xff;
6059 plcp[3] = (usec >> 8) & 0xff;
6065 /* Rate: 802.11 rate code, length: PSDU length in octets */
6066 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6068 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6070 if (rspec_is40mhz(rspec) || (mcs == 32))
6071 plcp[0] |= MIMO_PLCP_40MHZ;
6072 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6073 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6074 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6075 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6079 /* Rate: 802.11 rate code, length: PSDU length in octets */
6081 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6085 int rate = rspec2rate(rspec);
6088 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6091 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6092 memset(plcp, 0, D11_PHY_HDR_LEN);
6093 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6095 tmp = (length & 0xfff) << 5;
6096 plcp[2] |= (tmp >> 16) & 0xff;
6097 plcp[1] |= (tmp >> 8) & 0xff;
6098 plcp[0] |= tmp & 0xff;
6101 /* Rate: 802.11 rate code, length: PSDU length in octets */
6102 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6103 uint length, u8 *plcp)
6105 int rate = rspec2rate(rspec);
6107 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6111 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6112 uint length, u8 *plcp)
6114 if (is_mcs_rate(rspec))
6115 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6116 else if (is_ofdm_rate(rspec))
6117 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6119 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6122 /* brcms_c_compute_rtscts_dur()
6124 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6125 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6126 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6128 * cts cts-to-self or rts/cts
6129 * rts_rate rts or cts rate in unit of 500kbps
6130 * rate next MPDU rate in unit of 500kbps
6131 * frame_len next MPDU frame length in bytes
6134 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6136 u32 frame_rate, u8 rts_preamble_type,
6137 u8 frame_preamble_type, uint frame_len, bool ba)
6141 sifs = get_sifs(wlc->band);
6147 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6155 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6159 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6160 BRCMS_SHORT_PREAMBLE);
6163 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6164 frame_preamble_type);
6168 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6173 if (BRCMS_ISLCNPHY(wlc->band)) {
6174 bw = PHY_TXC1_BW_20MHZ;
6176 bw = rspec_get_bw(rspec);
6177 /* 10Mhz is not supported yet */
6178 if (bw < PHY_TXC1_BW_20MHZ) {
6179 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6180 "not supported yet, set to 20L\n", bw);
6181 bw = PHY_TXC1_BW_20MHZ;
6185 if (is_mcs_rate(rspec)) {
6186 uint mcs = rspec & RSPEC_RATE_MASK;
6188 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6189 phyctl1 = rspec_phytxbyte2(rspec);
6190 /* set the upper byte of phyctl1 */
6191 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6192 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6193 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6195 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6196 * Data Rate. Eventually MIMOPHY would also be converted to
6199 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6200 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6201 } else { /* legacy OFDM/CCK */
6203 /* get the phyctl byte from rate phycfg table */
6204 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6206 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6207 "legacy OFDM/CCK rate\n");
6210 /* set the upper byte of phyctl1 */
6212 (bw | (phycfg << 8) |
6213 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6219 * Add struct d11txh, struct cck_phy_hdr.
6221 * 'p' data must start with 802.11 MAC header
6222 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6224 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6228 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6229 struct sk_buff *p, struct scb *scb, uint frag,
6230 uint nfrags, uint queue, uint next_frag_len)
6232 struct ieee80211_hdr *h;
6234 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6235 int len, phylen, rts_phylen;
6236 u16 mch, phyctl, xfts, mainrates;
6237 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6238 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6239 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6240 bool use_rts = false;
6241 bool use_cts = false;
6242 bool use_rifs = false;
6243 bool short_preamble[2] = { false, false };
6244 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6245 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6246 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6247 struct ieee80211_rts *rts = NULL;
6250 bool hwtkmic = false;
6251 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6252 #define ANTCFG_NONE 0xFF
6253 u8 antcfg = ANTCFG_NONE;
6254 u8 fbantcfg = ANTCFG_NONE;
6255 uint phyctl1_stf = 0;
6257 struct ieee80211_tx_rate *txrate[2];
6259 struct ieee80211_tx_info *tx_info;
6262 u8 mimo_preamble_type;
6264 /* locate 802.11 MAC header */
6265 h = (struct ieee80211_hdr *)(p->data);
6266 qos = ieee80211_is_data_qos(h->frame_control);
6268 /* compute length of frame in bytes for use in PLCP computations */
6270 phylen = len + FCS_LEN;
6273 tx_info = IEEE80211_SKB_CB(p);
6276 plcp = skb_push(p, D11_PHY_HDR_LEN);
6278 /* add Broadcom tx descriptor header */
6279 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6280 memset(txh, 0, D11_TXH_LEN);
6283 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6284 /* non-AP STA should never use BCMC queue */
6285 if (queue == TX_BCMC_FIFO) {
6286 brcms_err(wlc->hw->d11core,
6287 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6288 wlc->pub->unit, __func__);
6289 frameid = bcmc_fid_generate(wlc, NULL, txh);
6291 /* Increment the counter for first fragment */
6292 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6293 scb->seqnum[p->priority]++;
6295 /* extract fragment number from frame first */
6296 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6297 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6298 h->seq_ctrl = cpu_to_le16(seq);
6300 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6301 (queue & TXFID_QUEUE_MASK);
6304 frameid |= queue & TXFID_QUEUE_MASK;
6306 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6307 if (ieee80211_is_beacon(h->frame_control))
6308 mcl |= TXC_IGNOREPMQ;
6310 txrate[0] = tx_info->control.rates;
6311 txrate[1] = txrate[0] + 1;
6314 * if rate control algorithm didn't give us a fallback
6315 * rate, use the primary rate
6317 if (txrate[1]->idx < 0)
6318 txrate[1] = txrate[0];
6320 for (k = 0; k < hw->max_rates; k++) {
6321 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6323 if ((txrate[k]->idx >= 0)
6324 && (txrate[k]->idx <
6325 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6327 hw->wiphy->bands[tx_info->band]->
6328 bitrates[txrate[k]->idx].hw_value;
6331 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6334 rspec[k] = BRCM_RATE_1M;
6337 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6338 NRATE_MCS_INUSE | txrate[k]->idx);
6342 * Currently only support same setting for primay and
6343 * fallback rates. Unify flags for each rate into a
6344 * single value for the frame
6348 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6351 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6356 * determine and validate primary rate
6357 * and fallback rates
6359 if (!rspec_active(rspec[k])) {
6360 rspec[k] = BRCM_RATE_1M;
6362 if (!is_multicast_ether_addr(h->addr1)) {
6363 /* set tx antenna config */
6364 brcms_c_antsel_antcfg_get(wlc->asi, false,
6365 false, 0, 0, &antcfg, &fbantcfg);
6370 phyctl1_stf = wlc->stf->ss_opmode;
6372 if (wlc->pub->_n_enab & SUPPORT_11N) {
6373 for (k = 0; k < hw->max_rates; k++) {
6375 * apply siso/cdd to single stream mcs's or ofdm
6376 * if rspec is auto selected
6378 if (((is_mcs_rate(rspec[k]) &&
6379 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6380 is_ofdm_rate(rspec[k]))
6381 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6382 || !(rspec[k] & RSPEC_OVERRIDE))) {
6383 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6385 /* For SISO MCS use STBC if possible */
6386 if (is_mcs_rate(rspec[k])
6387 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6390 /* Nss for single stream is always 1 */
6392 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6394 (stc << RSPEC_STC_SHIFT);
6397 (phyctl1_stf << RSPEC_STF_SHIFT);
6401 * Is the phy configured to use 40MHZ frames? If
6402 * so then pick the desired txbw
6404 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6405 /* default txbw is 20in40 SB */
6406 mimo_ctlchbw = mimo_txbw =
6407 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6409 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6411 if (is_mcs_rate(rspec[k])) {
6412 /* mcs 32 must be 40b/w DUP */
6413 if ((rspec[k] & RSPEC_RATE_MASK)
6416 PHY_TXC1_BW_40MHZ_DUP;
6418 } else if (wlc->mimo_40txbw != AUTO)
6419 mimo_txbw = wlc->mimo_40txbw;
6420 /* else check if dst is using 40 Mhz */
6421 else if (scb->flags & SCB_IS40)
6422 mimo_txbw = PHY_TXC1_BW_40MHZ;
6423 } else if (is_ofdm_rate(rspec[k])) {
6424 if (wlc->ofdm_40txbw != AUTO)
6425 mimo_txbw = wlc->ofdm_40txbw;
6426 } else if (wlc->cck_40txbw != AUTO) {
6427 mimo_txbw = wlc->cck_40txbw;
6431 * mcs32 is 40 b/w only.
6432 * This is possible for probe packets on
6435 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6437 rspec[k] = RSPEC_MIMORATE;
6439 mimo_txbw = PHY_TXC1_BW_20MHZ;
6442 /* Set channel width */
6443 rspec[k] &= ~RSPEC_BW_MASK;
6444 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6445 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6447 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6449 /* Disable short GI, not supported yet */
6450 rspec[k] &= ~RSPEC_SHORT_GI;
6452 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6453 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6454 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6456 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6457 && (!is_mcs_rate(rspec[k]))) {
6458 brcms_warn(wlc->hw->d11core,
6459 "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6460 wlc->pub->unit, __func__);
6463 if (is_mcs_rate(rspec[k])) {
6464 preamble_type[k] = mimo_preamble_type;
6467 * if SGI is selected, then forced mm
6470 if ((rspec[k] & RSPEC_SHORT_GI)
6471 && is_single_stream(rspec[k] &
6473 preamble_type[k] = BRCMS_MM_PREAMBLE;
6476 /* should be better conditionalized */
6477 if (!is_mcs_rate(rspec[0])
6478 && (tx_info->control.rates[0].
6479 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6480 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6483 for (k = 0; k < hw->max_rates; k++) {
6484 /* Set ctrlchbw as 20Mhz */
6485 rspec[k] &= ~RSPEC_BW_MASK;
6486 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6488 /* for nphy, stf of ofdm frames must follow policies */
6489 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6490 rspec[k] &= ~RSPEC_STF_MASK;
6491 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6496 /* Reset these for use with AMPDU's */
6497 txrate[0]->count = 0;
6498 txrate[1]->count = 0;
6500 /* (2) PROTECTION, may change rspec */
6501 if ((ieee80211_is_data(h->frame_control) ||
6502 ieee80211_is_mgmt(h->frame_control)) &&
6503 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6506 /* (3) PLCP: determine PLCP header and MAC duration,
6507 * fill struct d11txh */
6508 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6509 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6510 memcpy(&txh->FragPLCPFallback,
6511 plcp_fallback, sizeof(txh->FragPLCPFallback));
6513 /* Length field now put in CCK FBR CRC field */
6514 if (is_cck_rate(rspec[1])) {
6515 txh->FragPLCPFallback[4] = phylen & 0xff;
6516 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6519 /* MIMO-RATE: need validation ?? */
6520 mainrates = is_ofdm_rate(rspec[0]) ?
6521 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6524 /* DUR field for main rate */
6525 if (!ieee80211_is_pspoll(h->frame_control) &&
6526 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6528 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6530 h->duration_id = cpu_to_le16(durid);
6531 } else if (use_rifs) {
6532 /* NAV protect to end of next max packet size */
6534 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6536 DOT11_MAX_FRAG_LEN);
6537 durid += RIFS_11N_TIME;
6538 h->duration_id = cpu_to_le16(durid);
6541 /* DUR field for fallback rate */
6542 if (ieee80211_is_pspoll(h->frame_control))
6543 txh->FragDurFallback = h->duration_id;
6544 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6545 txh->FragDurFallback = 0;
6547 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6548 preamble_type[1], next_frag_len);
6549 txh->FragDurFallback = cpu_to_le16(durid);
6552 /* (4) MAC-HDR: MacTxControlLow */
6554 mcl |= TXC_STARTMSDU;
6556 if (!is_multicast_ether_addr(h->addr1))
6557 mcl |= TXC_IMMEDACK;
6559 if (wlc->band->bandtype == BRCM_BAND_5G)
6560 mcl |= TXC_FREQBAND_5G;
6562 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6565 /* set AMIC bit if using hardware TKIP MIC */
6569 txh->MacTxControlLow = cpu_to_le16(mcl);
6571 /* MacTxControlHigh */
6574 /* Set fallback rate preamble type */
6575 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6576 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6577 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6578 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6581 /* MacFrameControl */
6582 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6583 txh->TxFesTimeNormal = cpu_to_le16(0);
6585 txh->TxFesTimeFallback = cpu_to_le16(0);
6588 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6591 txh->TxFrameID = cpu_to_le16(frameid);
6594 * TxStatus, Note the case of recreating the first frag of a suppressed
6595 * frame then we may need to reset the retry cnt's via the status reg
6597 txh->TxStatus = cpu_to_le16(status);
6600 * extra fields for ucode AMPDU aggregation, the new fields are added to
6601 * the END of previous structure so that it's compatible in driver.
6603 txh->MaxNMpdus = cpu_to_le16(0);
6604 txh->MaxABytes_MRT = cpu_to_le16(0);
6605 txh->MaxABytes_FBR = cpu_to_le16(0);
6606 txh->MinMBytes = cpu_to_le16(0);
6608 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6609 * furnish struct d11txh */
6610 /* RTS PLCP header and RTS frame */
6611 if (use_rts || use_cts) {
6612 if (use_rts && use_cts)
6615 for (k = 0; k < 2; k++) {
6616 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6621 if (!is_ofdm_rate(rts_rspec[0]) &&
6622 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6623 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6624 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6625 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6628 if (!is_ofdm_rate(rts_rspec[1]) &&
6629 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6630 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6631 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6632 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6635 /* RTS/CTS additions to MacTxControlLow */
6637 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6639 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6640 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6643 /* RTS PLCP header */
6644 rts_plcp = txh->RTSPhyHeader;
6646 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6648 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6650 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6652 /* fallback rate version of RTS PLCP header */
6653 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6655 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6656 sizeof(txh->RTSPLCPFallback));
6658 /* RTS frame fields... */
6659 rts = (struct ieee80211_rts *)&txh->rts_frame;
6661 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6662 rspec[0], rts_preamble_type[0],
6663 preamble_type[0], phylen, false);
6664 rts->duration = cpu_to_le16(durid);
6665 /* fallback rate version of RTS DUR field */
6666 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6667 rts_rspec[1], rspec[1],
6668 rts_preamble_type[1],
6669 preamble_type[1], phylen, false);
6670 txh->RTSDurFallback = cpu_to_le16(durid);
6673 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6674 IEEE80211_STYPE_CTS);
6676 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6678 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6679 IEEE80211_STYPE_RTS);
6681 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6685 * low 8 bits: main frag rate/mcs,
6686 * high 8 bits: rts/cts rate/mcs
6688 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6690 (struct ofdm_phy_hdr *) rts_plcp) :
6693 memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6694 memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6695 memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6696 txh->RTSDurFallback = 0;
6699 #ifdef SUPPORT_40MHZ
6700 /* add null delimiter count */
6701 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6702 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6703 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6708 * Now that RTS/RTS FB preamble types are updated, write
6711 txh->MacTxControlHigh = cpu_to_le16(mch);
6714 * MainRates (both the rts and frag plcp rates have
6715 * been calculated now)
6717 txh->MainRates = cpu_to_le16(mainrates);
6719 /* XtraFrameTypes */
6720 xfts = frametype(rspec[1], wlc->mimoft);
6721 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6722 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6723 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6725 txh->XtraFrameTypes = cpu_to_le16(xfts);
6727 /* PhyTxControlWord */
6728 phyctl = frametype(rspec[0], wlc->mimoft);
6729 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6730 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6731 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6732 phyctl |= PHY_TXC_SHORT_HDR;
6735 /* phytxant is properly bit shifted */
6736 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6737 txh->PhyTxControlWord = cpu_to_le16(phyctl);
6739 /* PhyTxControlWord_1 */
6740 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6743 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6744 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6745 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6746 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6748 if (use_rts || use_cts) {
6749 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6750 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6751 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6752 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6756 * For mcs frames, if mixedmode(overloaded with long preamble)
6757 * is going to be set, fill in non-zero MModeLen and/or
6758 * MModeFbrLen it will be unnecessary if they are separated
6760 if (is_mcs_rate(rspec[0]) &&
6761 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6763 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6764 txh->MModeLen = cpu_to_le16(mmodelen);
6767 if (is_mcs_rate(rspec[1]) &&
6768 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6770 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6771 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6775 ac = skb_get_queue_mapping(p);
6776 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6777 uint frag_dur, dur, dur_fallback;
6779 /* WME: Update TXOP threshold */
6780 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6782 brcms_c_calc_frame_time(wlc, rspec[0],
6783 preamble_type[0], phylen);
6786 /* 1 RTS or CTS-to-self frame */
6788 brcms_c_calc_cts_time(wlc, rts_rspec[0],
6789 rts_preamble_type[0]);
6791 brcms_c_calc_cts_time(wlc, rts_rspec[1],
6792 rts_preamble_type[1]);
6793 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6794 dur += le16_to_cpu(rts->duration);
6796 le16_to_cpu(txh->RTSDurFallback);
6797 } else if (use_rifs) {
6801 /* frame + SIFS + ACK */
6804 brcms_c_compute_frame_dur(wlc, rspec[0],
6805 preamble_type[0], 0);
6808 brcms_c_calc_frame_time(wlc, rspec[1],
6812 brcms_c_compute_frame_dur(wlc, rspec[1],
6813 preamble_type[1], 0);
6815 /* NEED to set TxFesTimeNormal (hard) */
6816 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6818 * NEED to set fallback rate version of
6819 * TxFesTimeNormal (hard)
6821 txh->TxFesTimeFallback =
6822 cpu_to_le16((u16) dur_fallback);
6825 * update txop byte threshold (txop minus intraframe
6828 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6832 brcms_c_calc_frame_len(wlc,
6833 rspec[0], preamble_type[0],
6834 (wlc->edcf_txop[ac] -
6836 /* range bound the fragthreshold */
6837 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6840 else if (newfragthresh >
6841 wlc->usr_fragthresh)
6843 wlc->usr_fragthresh;
6844 /* update the fragthresh and do txc update */
6845 if (wlc->fragthresh[queue] !=
6846 (u16) newfragthresh)
6847 wlc->fragthresh[queue] =
6848 (u16) newfragthresh;
6850 brcms_warn(wlc->hw->d11core,
6851 "wl%d: %s txop invalid for rate %d\n",
6852 wlc->pub->unit, fifo_names[queue],
6853 rspec2rate(rspec[0]));
6856 if (dur > wlc->edcf_txop[ac])
6857 brcms_warn(wlc->hw->d11core,
6858 "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6859 wlc->pub->unit, __func__,
6861 phylen, wlc->fragthresh[queue],
6862 dur, wlc->edcf_txop[ac]);
6869 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6871 struct dma_pub *dma;
6872 int fifo, ret = -ENOSPC;
6874 u16 frameid = INVALIDFID;
6876 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6877 dma = wlc->hw->di[fifo];
6878 txh = (struct d11txh *)(skb->data);
6880 if (dma->txavail == 0) {
6882 * We sometimes get a frame from mac80211 after stopping
6883 * the queues. This only ever seems to be a single frame
6884 * and is seems likely to be a race. TX_HEADROOM should
6885 * ensure that we have enough space to handle these stray
6886 * packets, so warn if there isn't. If we're out of space
6887 * in the tx ring and the tx queue isn't stopped then
6888 * we've really got a bug; warn loudly if that happens.
6890 brcms_warn(wlc->hw->d11core,
6891 "Received frame for tx with no space in DMA ring\n");
6892 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6893 skb_get_queue_mapping(skb)));
6897 /* When a BC/MC frame is being committed to the BCMC fifo
6898 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6900 if (fifo == TX_BCMC_FIFO)
6901 frameid = le16_to_cpu(txh->TxFrameID);
6903 /* Commit BCMC sequence number in the SHM frame ID location */
6904 if (frameid != INVALIDFID) {
6906 * To inform the ucode of the last mcast frame posted
6907 * so that it can clear moredata bit
6909 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6912 ret = brcms_c_txfifo(wlc, fifo, skb);
6914 * The only reason for brcms_c_txfifo to fail is because
6915 * there weren't any DMA descriptors, but we've already
6916 * checked for that. So if it does fail yell loudly.
6923 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6924 struct ieee80211_hw *hw)
6927 struct scb *scb = &wlc->pri_scb;
6929 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6930 brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6931 if (!brcms_c_tx(wlc, sdu))
6934 /* packet discarded */
6935 dev_kfree_skb_any(sdu);
6940 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6942 struct dma_pub *dma = wlc->hw->di[fifo];
6946 ret = dma_txfast(wlc, dma, p);
6948 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6951 * Stop queue if DMA ring is full. Reserve some free descriptors,
6952 * as we sometimes receive a frame from mac80211 after the queues
6955 queue = skb_get_queue_mapping(p);
6956 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6957 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6958 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6964 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6965 bool use_rspec, u16 mimo_ctlchbw)
6970 /* use frame rate as rts rate */
6972 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6973 /* Use 11Mbps as the g protection RTS target rate and fallback.
6974 * Use the brcms_basic_rate() lookup to find the best basic rate
6975 * under the target in case 11 Mbps is not Basic.
6976 * 6 and 9 Mbps are not usually selected by rate selection, but
6977 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6980 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6982 /* calculate RTS rate and fallback rate based on the frame rate
6983 * RTS must be sent at a basic rate since it is a
6984 * control frame, sec 9.6 of 802.11 spec
6986 rts_rspec = brcms_basic_rate(wlc, rspec);
6988 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6989 /* set rts txbw to correct side band */
6990 rts_rspec &= ~RSPEC_BW_MASK;
6993 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6994 * 20MHz channel (DUP), otherwise send RTS on control channel
6996 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
6997 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
6999 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7001 /* pick siso/cdd as default for ofdm */
7002 if (is_ofdm_rate(rts_rspec)) {
7003 rts_rspec &= ~RSPEC_STF_MASK;
7004 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7010 /* Update beacon listen interval in shared memory */
7011 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7013 /* wake up every DTIM is the default */
7014 if (wlc->bcn_li_dtim == 1)
7015 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7017 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7018 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7022 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7025 struct bcma_device *core = wlc_hw->d11core;
7027 /* read the tsf timer low, then high to get an atomic read */
7028 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7029 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7033 * recover 64bit TSF value from the 16bit TSF value in the rx header
7034 * given the assumption that the TSF passed in header is within 65ms
7035 * of the current tsf.
7038 * 3.......6.......8.......0.......2.......4.......6.......8......0
7039 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7041 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7042 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7043 * receive call sequence after rx interrupt. Only the higher 16 bits
7044 * are used. Finally, the tsf_h is read from the tsf register.
7046 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7047 struct d11rxhdr *rxh)
7050 u16 rx_tsf_0_15, rx_tsf_16_31;
7052 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7054 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7055 rx_tsf_0_15 = rxh->RxTSFTime;
7058 * a greater tsf time indicates the low 16 bits of
7059 * tsf_l wrapped, so decrement the high 16 bits.
7061 if ((u16)tsf_l < rx_tsf_0_15) {
7063 if (rx_tsf_16_31 == 0xffff)
7067 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7071 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7073 struct ieee80211_rx_status *rx_status)
7078 unsigned char *plcp;
7080 /* fill in TSF and flag its presence */
7081 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7082 rx_status->flag |= RX_FLAG_MACTIME_START;
7084 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7087 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7089 ieee80211_channel_to_frequency(channel, rx_status->band);
7091 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7095 rx_status->antenna =
7096 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7100 rspec = brcms_c_compute_rspec(rxh, plcp);
7101 if (is_mcs_rate(rspec)) {
7102 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7103 rx_status->flag |= RX_FLAG_HT;
7104 if (rspec_is40mhz(rspec))
7105 rx_status->flag |= RX_FLAG_40MHZ;
7107 switch (rspec2rate(rspec)) {
7109 rx_status->rate_idx = 0;
7112 rx_status->rate_idx = 1;
7115 rx_status->rate_idx = 2;
7118 rx_status->rate_idx = 3;
7121 rx_status->rate_idx = 4;
7124 rx_status->rate_idx = 5;
7127 rx_status->rate_idx = 6;
7130 rx_status->rate_idx = 7;
7133 rx_status->rate_idx = 8;
7136 rx_status->rate_idx = 9;
7139 rx_status->rate_idx = 10;
7142 rx_status->rate_idx = 11;
7145 brcms_err(wlc->hw->d11core,
7146 "%s: Unknown rate\n", __func__);
7150 * For 5GHz, we should decrease the index as it is
7151 * a subset of the 2.4G rates. See bitrates field
7152 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7154 if (rx_status->band == IEEE80211_BAND_5GHZ)
7155 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7157 /* Determine short preamble and rate_idx */
7159 if (is_cck_rate(rspec)) {
7160 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7161 rx_status->flag |= RX_FLAG_SHORTPRE;
7162 } else if (is_ofdm_rate(rspec)) {
7163 rx_status->flag |= RX_FLAG_SHORTPRE;
7165 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7170 if (plcp3_issgi(plcp[3]))
7171 rx_status->flag |= RX_FLAG_SHORT_GI;
7173 if (rxh->RxStatus1 & RXS_DECERR) {
7174 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7175 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7178 if (rxh->RxStatus1 & RXS_FCSERR) {
7179 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7180 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7186 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7190 struct ieee80211_rx_status rx_status;
7191 struct ieee80211_hdr *hdr;
7193 memset(&rx_status, 0, sizeof(rx_status));
7194 prep_mac80211_status(wlc, rxh, p, &rx_status);
7196 /* mac header+body length, exclude CRC and plcp header */
7197 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7198 skb_pull(p, D11_PHY_HDR_LEN);
7199 __skb_trim(p, len_mpdu);
7201 /* unmute transmit */
7202 if (wlc->hw->suspended_fifos) {
7203 hdr = (struct ieee80211_hdr *)p->data;
7204 if (ieee80211_is_beacon(hdr->frame_control))
7205 brcms_b_mute(wlc->hw, false);
7208 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7209 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7212 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7213 * number of bytes goes in the length field
7215 * Formula given by HT PHY Spec v 1.13
7216 * len = 3(nsyms + nstream + 3) - 3
7219 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7222 uint nsyms, len = 0, kNdps;
7224 if (is_mcs_rate(ratespec)) {
7225 uint mcs = ratespec & RSPEC_RATE_MASK;
7226 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7227 rspec_stc(ratespec);
7230 * the payload duration calculation matches that
7233 /* 1000Ndbps = kbps * 4 */
7234 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7235 rspec_issgi(ratespec)) * 4;
7237 if (rspec_stc(ratespec) == 0)
7239 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7240 APHY_TAIL_NBITS) * 1000, kNdps);
7242 /* STBC needs to have even number of symbols */
7245 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7246 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7248 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7249 nsyms += (tot_streams + 3);
7251 * 3 bytes/symbol @ legacy 6Mbps rate
7252 * (-3) excluding service bits and tail bits
7254 len = (3 * nsyms) - 3;
7261 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7263 const struct brcms_c_rateset *rs_dflt;
7264 struct brcms_c_rateset rs;
7267 u8 plcp[D11_PHY_HDR_LEN];
7271 sifs = get_sifs(wlc->band);
7273 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7275 brcms_c_rateset_copy(rs_dflt, &rs);
7276 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7279 * walk the phy rate table and update MAC core SHM
7280 * basic rate table entries
7282 for (i = 0; i < rs.count; i++) {
7283 rate = rs.rates[i] & BRCMS_RATE_MASK;
7285 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7287 /* Calculate the Probe Response PLCP for the given rate */
7288 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7291 * Calculate the duration of the Probe Response
7292 * frame plus SIFS for the MAC
7294 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7295 BRCMS_LONG_PREAMBLE, frame_len);
7298 /* Update the SHM Rate Table entry Probe Response values */
7299 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7300 (u16) (plcp[0] + (plcp[1] << 8)));
7301 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7302 (u16) (plcp[2] + (plcp[3] << 8)));
7303 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7307 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7309 * PLCP header is 6 bytes.
7310 * 802.11 A3 header is 24 bytes.
7311 * Max beacon frame body template length is 112 bytes.
7312 * Max probe resp frame body template length is 110 bytes.
7314 * *len on input contains the max length of the packet available.
7316 * The *len value is set to the number of bytes in buf used, and starts
7317 * with the PLCP and included up to, but not including, the 4 byte FCS.
7320 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7322 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7324 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7325 struct cck_phy_hdr *plcp;
7326 struct ieee80211_mgmt *h;
7327 int hdr_len, body_len;
7329 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7331 /* calc buffer size provided for frame body */
7332 body_len = *len - hdr_len;
7333 /* return actual size */
7334 *len = hdr_len + body_len;
7336 /* format PHY and MAC headers */
7337 memset(buf, 0, hdr_len);
7339 plcp = (struct cck_phy_hdr *) buf;
7342 * PLCP for Probe Response frames are filled in from
7345 if (type == IEEE80211_STYPE_BEACON)
7347 brcms_c_compute_plcp(wlc, bcn_rspec,
7348 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7351 /* "Regular" and 16 MBSS but not for 4 MBSS */
7352 /* Update the phytxctl for the beacon based on the rspec */
7353 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7355 h = (struct ieee80211_mgmt *)&plcp[1];
7357 /* fill in 802.11 header */
7358 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7360 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7361 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7362 if (type == IEEE80211_STYPE_BEACON)
7363 memcpy(&h->da, ðer_bcast, ETH_ALEN);
7364 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7365 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7367 /* SEQ filled in by MAC */
7370 int brcms_c_get_header_len(void)
7376 * Update all beacons for the system.
7378 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7380 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7382 if (bsscfg->up && (bsscfg->type == BRCMS_TYPE_AP ||
7383 bsscfg->type == BRCMS_TYPE_ADHOC))
7384 /* Clear the soft intmask */
7385 wlc->defmacintmask &= ~MI_BCNTPL;
7388 /* Write ssid into shared memory */
7390 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7392 u8 *ssidptr = cfg->SSID;
7394 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7396 /* padding the ssid with zero and copy it into shm */
7397 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7398 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7400 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7401 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7405 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7406 struct brcms_bss_cfg *cfg,
7410 int len = BCN_TMPL_LEN;
7412 prb_resp = kmalloc(BCN_TMPL_LEN, GFP_ATOMIC);
7417 * write the probe response to hardware, or save in
7418 * the config structure
7421 /* create the probe response template */
7422 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7423 cfg, prb_resp, &len);
7426 brcms_c_suspend_mac_and_wait(wlc);
7428 /* write the probe response into the template region */
7429 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7430 (len + 3) & ~3, prb_resp);
7432 /* write the length of the probe response frame (+PLCP/-FCS) */
7433 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7435 /* write the SSID and SSID length */
7436 brcms_c_shm_ssid_upd(wlc, cfg);
7439 * Write PLCP headers and durations for probe response frames
7440 * at all rates. Use the actual frame length covered by the
7441 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7442 * by subtracting the PLCP len and adding the FCS.
7444 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7445 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7448 brcms_c_enable_mac(wlc);
7453 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7455 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7457 /* update AP or IBSS probe responses */
7458 if (bsscfg->up && (bsscfg->type == BRCMS_TYPE_AP ||
7459 bsscfg->type == BRCMS_TYPE_ADHOC))
7460 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7463 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7469 *blocks = wlc_hw->xmtfifo_sz[fifo];
7475 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7478 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7479 if (match_reg_offset == RCM_BSSID_OFFSET)
7480 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7484 * Flag 'scan in progress' to withhold dynamic phy calibration
7486 void brcms_c_scan_start(struct brcms_c_info *wlc)
7488 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7491 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7493 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7496 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7498 wlc->pub->associated = state;
7499 wlc->bsscfg->associated = state;
7503 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7504 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7505 * when later on hardware releases them, they can be handled appropriately.
7507 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7508 struct ieee80211_sta *sta,
7509 void (*dma_callback_fn))
7511 struct dma_pub *dmah;
7513 for (i = 0; i < NFIFO; i++) {
7516 dma_walk_packets(dmah, dma_callback_fn, sta);
7520 int brcms_c_get_curband(struct brcms_c_info *wlc)
7522 return wlc->band->bandunit;
7525 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7529 /* Kick DMA to send any pending AMPDU */
7530 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7532 dma_kick_tx(wlc->hw->di[i]);
7534 return !brcms_txpktpendtot(wlc);
7537 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7539 wlc->bcn_li_bcn = interval;
7541 brcms_c_bcn_li_upd(wlc);
7544 u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
7549 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7558 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
7562 brcms_c_time_lock(wlc);
7565 tsf_h = (tsf >> 32);
7567 /* read the tsf timer low, then high to get an atomic read */
7568 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
7569 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
7571 brcms_c_time_unlock(wlc);
7574 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7578 /* Remove override bit and clip to max qdbm value */
7579 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7580 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7583 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7588 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7590 /* Return qdbm units */
7591 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7594 /* Process received frames */
7596 * Return true if more frames need to be processed. false otherwise.
7597 * Param 'bound' indicates max. # frames to process before break out.
7599 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7601 struct d11rxhdr *rxh;
7602 struct ieee80211_hdr *h;
7606 /* frame starts with rxhdr */
7607 rxh = (struct d11rxhdr *) (p->data);
7609 /* strip off rxhdr */
7610 skb_pull(p, BRCMS_HWRXOFF);
7612 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7613 if (rxh->RxStatus1 & RXS_PBPRES) {
7615 brcms_err(wlc->hw->d11core,
7616 "wl%d: recv: rcvd runt of len %d\n",
7617 wlc->pub->unit, p->len);
7623 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7626 if (rxh->RxStatus1 & RXS_FCSERR) {
7627 if (!(wlc->filter_flags & FIF_FCSFAIL))
7631 /* check received pkt has at least frame control field */
7632 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7635 /* not supporting A-MSDU */
7636 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7640 brcms_c_recvctl(wlc, rxh, p);
7644 brcmu_pkt_buf_free_skb(p);
7647 /* Process received frames */
7649 * Return true if more frames need to be processed. false otherwise.
7650 * Param 'bound' indicates max. # frames to process before break out.
7653 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7656 struct sk_buff *next = NULL;
7657 struct sk_buff_head recv_frames;
7660 uint bound_limit = bound ? RXBND : -1;
7661 bool morepending = false;
7663 skb_queue_head_init(&recv_frames);
7665 /* gather received frames */
7667 /* !give others some time to run! */
7668 if (n >= bound_limit)
7671 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7673 } while (morepending);
7675 /* post more rbufs */
7676 dma_rxfill(wlc_hw->di[fifo]);
7678 /* process each frame */
7679 skb_queue_walk_safe(&recv_frames, p, next) {
7680 struct d11rxhdr_le *rxh_le;
7681 struct d11rxhdr *rxh;
7683 skb_unlink(p, &recv_frames);
7684 rxh_le = (struct d11rxhdr_le *)p->data;
7685 rxh = (struct d11rxhdr *)p->data;
7687 /* fixup rx header endianness */
7688 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7689 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7690 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7691 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7692 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7693 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7694 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7695 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7696 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7697 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7698 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7700 brcms_c_recv(wlc_hw->wlc, p);
7706 /* second-level interrupt processing
7707 * Return true if another dpc needs to be re-scheduled. false otherwise.
7708 * Param 'bounded' indicates if applicable loops should be bounded.
7710 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7713 struct brcms_hardware *wlc_hw = wlc->hw;
7714 struct bcma_device *core = wlc_hw->d11core;
7716 if (brcms_deviceremoved(wlc)) {
7717 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7719 brcms_down(wlc->wl);
7723 /* grab and clear the saved software intstatus bits */
7724 macintstatus = wlc->macintstatus;
7725 wlc->macintstatus = 0;
7727 brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7728 wlc_hw->unit, macintstatus);
7730 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7733 if (macintstatus & MI_TFS) {
7735 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7736 wlc->macintstatus |= MI_TFS;
7738 brcms_err(core, "MI_TFS: fatal\n");
7743 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7746 /* ATIM window end */
7747 if (macintstatus & MI_ATIMWINEND) {
7748 brcms_dbg_info(core, "end of ATIM window\n");
7749 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7754 * received data or control frame, MI_DMAINT is
7755 * indication of RX_FIFO interrupt
7757 if (macintstatus & MI_DMAINT)
7758 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7759 wlc->macintstatus |= MI_DMAINT;
7761 /* noise sample collected */
7762 if (macintstatus & MI_BG_NOISE)
7763 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7765 if (macintstatus & MI_GP0) {
7766 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7767 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7769 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7770 __func__, ai_get_chip_id(wlc_hw->sih),
7771 ai_get_chiprev(wlc_hw->sih));
7772 brcms_fatal_error(wlc_hw->wlc->wl);
7775 /* gptimer timeout */
7776 if (macintstatus & MI_TO)
7777 bcma_write32(core, D11REGOFFS(gptimer), 0);
7779 if (macintstatus & MI_RFDISABLE) {
7780 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7781 " RF Disable Input\n", wlc_hw->unit);
7782 brcms_rfkill_set_hw_state(wlc->wl);
7785 /* it isn't done and needs to be resched if macintstatus is non-zero */
7786 return wlc->macintstatus != 0;
7789 brcms_fatal_error(wlc_hw->wlc->wl);
7790 return wlc->macintstatus != 0;
7793 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7795 struct bcma_device *core = wlc->hw->d11core;
7796 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7799 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7801 chanspec = ch20mhz_chspec(ch->hw_value);
7803 brcms_b_init(wlc->hw, chanspec);
7805 /* update beacon listen interval */
7806 brcms_c_bcn_li_upd(wlc);
7808 /* write ethernet address to core */
7809 brcms_c_set_mac(wlc->bsscfg);
7810 brcms_c_set_bssid(wlc->bsscfg);
7812 /* Update tsf_cfprep if associated and up */
7813 if (wlc->pub->associated && wlc->bsscfg->up) {
7816 /* get beacon period and convert to uS */
7817 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7819 * update since init path would reset
7822 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7823 bi << CFPREP_CBI_SHIFT);
7825 /* Update maccontrol PM related bits */
7826 brcms_c_set_ps_ctrl(wlc);
7829 brcms_c_bandinit_ordered(wlc, chanspec);
7831 /* init probe response timeout */
7832 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7834 /* init max burst txop (framebursting) */
7835 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7837 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7839 /* initialize maximum allowed duty cycle */
7840 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7841 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7844 * Update some shared memory locations related to
7845 * max AMPDU size allowed to received
7847 brcms_c_ampdu_shm_upd(wlc->ampdu);
7849 /* band-specific inits */
7850 brcms_c_bsinit(wlc);
7852 /* Enable EDCF mode (while the MAC is suspended) */
7853 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7854 brcms_c_edcf_setparams(wlc, false);
7856 /* read the ucode version if we have not yet done so */
7857 if (wlc->ucode_rev == 0) {
7861 rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
7862 patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7863 wlc->ucode_rev = (rev << NBITS(u16)) | patch;
7864 snprintf(wlc->wiphy->fw_version,
7865 sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
7868 /* ..now really unleash hell (allow the MAC out of suspend) */
7869 brcms_c_enable_mac(wlc);
7871 /* suspend the tx fifos and mute the phy for preism cac time */
7873 brcms_b_mute(wlc->hw, true);
7875 /* enable the RF Disable Delay timer */
7876 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7879 * Initialize WME parameters; if they haven't been set by some other
7880 * mechanism (IOVar, etc) then read them from the hardware.
7882 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7883 /* Uninitialized; read from HW */
7886 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7887 wlc->wme_retries[ac] =
7888 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7893 * The common driver entry routine. Error codes should be unique
7895 struct brcms_c_info *
7896 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7897 bool piomode, uint *perr)
7899 struct brcms_c_info *wlc;
7902 struct brcms_pub *pub;
7904 /* allocate struct brcms_c_info state and its substructures */
7905 wlc = brcms_c_attach_malloc(unit, &err, 0);
7908 wlc->wiphy = wl->wiphy;
7915 wlc->band = wlc->bandstate[0];
7916 wlc->core = wlc->corestate;
7919 pub->_piomode = piomode;
7920 wlc->bandinit_pending = false;
7922 /* populate struct brcms_c_info with default values */
7923 brcms_c_info_init(wlc, unit);
7925 /* update sta/ap related parameters */
7926 brcms_c_ap_upd(wlc);
7929 * low level attach steps(all hw accesses go
7930 * inside, no more in rest of the attach)
7932 err = brcms_b_attach(wlc, core, unit, piomode);
7936 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7938 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7940 /* disable allowed duty cycle */
7941 wlc->tx_duty_cycle_ofdm = 0;
7942 wlc->tx_duty_cycle_cck = 0;
7944 brcms_c_stf_phy_chain_calc(wlc);
7946 /* txchain 1: txant 0, txchain 2: txant 1 */
7947 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7948 wlc->stf->txant = wlc->stf->hw_txchain - 1;
7950 /* push to BMAC driver */
7951 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7952 wlc->stf->hw_rxchain);
7954 /* pull up some info resulting from the low attach */
7955 for (i = 0; i < NFIFO; i++)
7956 wlc->core->txavail[i] = wlc->hw->txavail[i];
7958 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7959 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7961 for (j = 0; j < wlc->pub->_nbands; j++) {
7962 wlc->band = wlc->bandstate[j];
7964 if (!brcms_c_attach_stf_ant_init(wlc)) {
7969 /* default contention windows size limits */
7970 wlc->band->CWmin = APHY_CWMIN;
7971 wlc->band->CWmax = PHY_CWMAX;
7973 /* init gmode value */
7974 if (wlc->band->bandtype == BRCM_BAND_2G) {
7975 wlc->band->gmode = GMODE_AUTO;
7976 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7980 /* init _n_enab supported mode */
7981 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7982 pub->_n_enab = SUPPORT_11N;
7983 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7985 SUPPORT_11N) ? WL_11N_2x2 :
7989 /* init per-band default rateset, depend on band->gmode */
7990 brcms_default_rateset(wlc, &wlc->band->defrateset);
7992 /* fill in hw_rateset */
7993 brcms_c_rateset_filter(&wlc->band->defrateset,
7994 &wlc->band->hw_rateset, false,
7995 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
7996 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8000 * update antenna config due to
8001 * wlc->stf->txant/txchain/ant_rx_ovr change
8003 brcms_c_stf_phy_txant_upd(wlc);
8005 /* attach each modules */
8006 err = brcms_c_attach_module(wlc);
8010 if (!brcms_c_timers_init(wlc, unit)) {
8011 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8017 /* depend on rateset, gmode */
8018 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8020 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8021 "\n", unit, __func__);
8026 /* init default when all parameters are ready, i.e. ->rateset */
8027 brcms_c_bss_default_init(wlc);
8030 * Complete the wlc default state initializations..
8033 wlc->bsscfg->wlc = wlc;
8035 wlc->mimoft = FT_HT;
8036 wlc->mimo_40txbw = AUTO;
8037 wlc->ofdm_40txbw = AUTO;
8038 wlc->cck_40txbw = AUTO;
8039 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8041 /* Set default values of SGI */
8042 if (BRCMS_SGI_CAP_PHY(wlc)) {
8043 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8045 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8046 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8049 brcms_c_ht_update_sgi_rx(wlc, 0);
8052 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8060 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8061 unit, __func__, err);
8063 brcms_c_detach(wlc);