2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
39 #include "brcms_trace_events.h"
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG 1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK 800
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT 100
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52 * control it independently
58 #define EDCF_ACI_MASK 0x60
59 #define EDCF_ACI_SHIFT 5
60 #define EDCF_ECWMIN_MASK 0x0f
61 #define EDCF_ECWMAX_SHIFT 4
62 #define EDCF_AIFSN_MASK 0x0f
63 #define EDCF_AIFSN_MAX 15
64 #define EDCF_ECWMAX_MASK 0xf0
66 #define EDCF_AC_BE_TXOP_STA 0x0000
67 #define EDCF_AC_BK_TXOP_STA 0x0000
68 #define EDCF_AC_VO_ACI_STA 0x62
69 #define EDCF_AC_VO_ECW_STA 0x32
70 #define EDCF_AC_VI_ACI_STA 0x42
71 #define EDCF_AC_VI_ECW_STA 0x43
72 #define EDCF_AC_BK_ECW_STA 0xA4
73 #define EDCF_AC_VI_TXOP_STA 0x005e
74 #define EDCF_AC_VO_TXOP_STA 0x002f
75 #define EDCF_AC_BE_ACI_STA 0x03
76 #define EDCF_AC_BE_ECW_STA 0xA4
77 #define EDCF_AC_BK_ACI_STA 0x27
78 #define EDCF_AC_VO_TXOP_AP 0x002f
80 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
81 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83 #define APHY_SYMBOL_TIME 4
84 #define APHY_PREAMBLE_TIME 16
85 #define APHY_SIGNAL_TIME 4
86 #define APHY_SIFS_TIME 16
87 #define APHY_SERVICE_NBITS 16
88 #define APHY_TAIL_NBITS 6
89 #define BPHY_SIFS_TIME 10
90 #define BPHY_PLCP_SHORT_TIME 96
92 #define PREN_PREAMBLE 24
93 #define PREN_MM_EXT 12
94 #define PREN_PREAMBLE_EXT 4
96 #define DOT11_MAC_HDR_LEN 24
97 #define DOT11_ACK_LEN 10
98 #define DOT11_BA_LEN 4
99 #define DOT11_OFDM_SIGNAL_EXTENSION 6
100 #define DOT11_MIN_FRAG_LEN 256
101 #define DOT11_RTS_LEN 16
102 #define DOT11_CTS_LEN 10
103 #define DOT11_BA_BITMAP_LEN 128
104 #define DOT11_MAXNUMFRAGS 16
105 #define DOT11_MAX_FRAG_LEN 2346
107 #define BPHY_PLCP_TIME 192
108 #define RIFS_11N_TIME 2
110 /* length of the BCN template area */
111 #define BCN_TMPL_LEN 512
113 /* brcms_bss_info flag bit values */
114 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
116 /* chip rx buffer offset */
117 #define BRCMS_HWRXOFF 38
119 /* rfdisable delay timer 500 ms, runs of ALP clock */
120 #define RFDISABLE_DEFAULT 10000000
122 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
124 /* synthpu_dly times in us */
125 #define SYNTHPU_DLY_APHY_US 3700
126 #define SYNTHPU_DLY_BPHY_US 1050
127 #define SYNTHPU_DLY_NPHY_US 2048
128 #define SYNTHPU_DLY_LPPHY_US 300
130 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
132 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
133 #define EDCF_SHORT_S 0
135 #define EDCF_LONG_S 8
136 #define EDCF_LFB_S 12
137 #define EDCF_SHORT_M BITFIELD_MASK(4)
138 #define EDCF_SFB_M BITFIELD_MASK(4)
139 #define EDCF_LONG_M BITFIELD_MASK(4)
140 #define EDCF_LFB_M BITFIELD_MASK(4)
142 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
143 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
144 #define RETRY_LONG_DEF 4 /* Default Long retry count */
145 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
146 #define RETRY_LONG_FB 2 /* Long count for fb rate */
148 #define APHY_CWMIN 15
149 #define PHY_CWMAX 1023
151 #define EDCF_AIFSN_MIN 1
153 #define FRAGNUM_MASK 0xF
155 #define APHY_SLOT_TIME 9
156 #define BPHY_SLOT_TIME 20
158 #define WL_SPURAVOID_OFF 0
159 #define WL_SPURAVOID_ON1 1
160 #define WL_SPURAVOID_ON2 2
162 /* invalid core flags, use the saved coreflags */
163 #define BRCMS_USE_COREFLAGS 0xffffffff
165 /* values for PLCPHdr_override */
166 #define BRCMS_PLCP_AUTO -1
167 #define BRCMS_PLCP_SHORT 0
168 #define BRCMS_PLCP_LONG 1
170 /* values for g_protection_override and n_protection_override */
171 #define BRCMS_PROTECTION_AUTO -1
172 #define BRCMS_PROTECTION_OFF 0
173 #define BRCMS_PROTECTION_ON 1
174 #define BRCMS_PROTECTION_MMHDR_ONLY 2
175 #define BRCMS_PROTECTION_CTS_ONLY 3
177 /* values for g_protection_control and n_protection_control */
178 #define BRCMS_PROTECTION_CTL_OFF 0
179 #define BRCMS_PROTECTION_CTL_LOCAL 1
180 #define BRCMS_PROTECTION_CTL_OVERLAP 2
182 /* values for n_protection */
183 #define BRCMS_N_PROTECTION_OFF 0
184 #define BRCMS_N_PROTECTION_OPTIONAL 1
185 #define BRCMS_N_PROTECTION_20IN40 2
186 #define BRCMS_N_PROTECTION_MIXEDMODE 3
188 /* values for band specific 40MHz capabilities */
189 #define BRCMS_N_BW_20ALL 0
190 #define BRCMS_N_BW_40ALL 1
191 #define BRCMS_N_BW_20IN2G_40IN5G 2
193 /* bitflags for SGI support (sgi_rx iovar) */
194 #define BRCMS_N_SGI_20 0x01
195 #define BRCMS_N_SGI_40 0x02
197 /* defines used by the nrate iovar */
198 /* MSC in use,indicates b0-6 holds an mcs */
199 #define NRATE_MCS_INUSE 0x00000080
201 #define NRATE_RATE_MASK 0x0000007f
202 /* stf mode mask: siso, cdd, stbc, sdm */
203 #define NRATE_STF_MASK 0x0000ff00
205 #define NRATE_STF_SHIFT 8
206 /* bit indicate to override mcs only */
207 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
208 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
209 #define NRATE_SGI_SHIFT 23 /* sgi mode */
210 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
211 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
213 #define NRATE_STF_SISO 0 /* stf mode SISO */
214 #define NRATE_STF_CDD 1 /* stf mode CDD */
215 #define NRATE_STF_STBC 2 /* stf mode STBC */
216 #define NRATE_STF_SDM 3 /* stf mode SDM */
218 #define MAX_DMA_SEGS 4
220 /* # of entries in Tx FIFO */
222 /* Max # of entries in Rx FIFO based on 4kb page size */
225 /* Amount of headroom to leave in Tx FIFO */
226 #define TX_HEADROOM 4
228 /* try to keep this # rbufs posted to the chip */
229 #define NRXBUFPOST 32
231 /* max # frames to process in brcms_c_recv() */
233 /* max # tx status to process in wlc_txstatus() */
236 /* brcmu_format_flags() bit description structure */
237 struct brcms_c_bit_desc {
243 * The following table lists the buffer memory allocated to xmt fifos in HW.
244 * the size is in units of 256bytes(one block), total size is HW dependent
245 * ucode has default fifo partition, sw can overwrite if necessary
247 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
248 * the twiki is updated before making changes.
251 /* Starting corerev for the fifo size table */
252 #define XMTFIFOTBL_STARTREV 17
260 struct edcf_acparam {
269 /* TX FIFO number to WME/802.1E Access Category */
270 static const u8 wme_fifo2ac[] = {
279 /* ieee80211 Access Category to TX FIFO number */
280 static const u8 wme_ac2fifo[] = {
287 static const u16 xmtfifo_sz[][NFIFO] = {
288 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
289 {20, 192, 192, 21, 17, 5},
294 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
295 {20, 192, 192, 21, 17, 5},
296 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
297 {9, 58, 22, 14, 14, 5},
298 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
299 {20, 192, 192, 21, 17, 5},
300 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
301 {20, 192, 192, 21, 17, 5},
302 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
303 {9, 58, 22, 14, 14, 5},
310 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
311 {9, 58, 22, 14, 14, 5},
315 static const char * const fifo_names[] = {
316 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
318 static const char fifo_names[6][0];
322 /* pointer to most recently allocated wl/wlc */
323 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
326 /* Mapping of ieee80211 AC numbers to tx fifos */
327 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
328 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
329 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
330 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
331 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
334 /* Mapping of tx fifos to ieee80211 AC numbers */
335 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
336 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
337 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
338 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
339 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
342 static u8 brcms_ac_to_fifo(u8 ac)
344 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
345 return TX_AC_BE_FIFO;
346 return ac_to_fifo_mapping[ac];
349 static u8 brcms_fifo_to_ac(u8 fifo)
351 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
352 return IEEE80211_AC_BE;
353 return fifo_to_ac_mapping[fifo];
356 /* Find basic rate for a given rate */
357 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
359 if (is_mcs_rate(rspec))
360 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
362 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
365 static u16 frametype(u32 rspec, u8 mimoframe)
367 if (is_mcs_rate(rspec))
369 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
372 /* currently the best mechanism for determining SIFS is the band in use */
373 static u16 get_sifs(struct brcms_band *band)
375 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
380 * Detect Card removed.
381 * Even checking an sbconfig register read will not false trigger when the core
382 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
383 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
384 * reg with fixed 0/1 pattern (some platforms return all 0).
385 * If clocks are present, call the sb routine which will figure out if the
388 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
393 return ai_deviceremoved(wlc->hw->sih);
394 macctrl = bcma_read32(wlc->hw->d11core,
395 D11REGOFFS(maccontrol));
396 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
399 /* sum the individual fifo tx pending packet counts */
400 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
405 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
407 pending += dma_txpending(wlc->hw->di[i]);
411 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
413 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
416 static int brcms_chspec_bw(u16 chanspec)
418 if (CHSPEC_IS40(chanspec))
420 if (CHSPEC_IS20(chanspec))
426 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
431 kfree(cfg->current_bss);
435 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
440 brcms_c_bsscfg_mfree(wlc->bsscfg);
442 kfree(wlc->modulecb);
443 kfree(wlc->default_bss);
444 kfree(wlc->protection);
446 kfree(wlc->bandstate[0]);
447 kfree(wlc->corestate->macstat_snapshot);
448 kfree(wlc->corestate);
449 kfree(wlc->hw->bandstate[0]);
457 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
459 struct brcms_bss_cfg *cfg;
461 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
465 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
466 if (cfg->current_bss == NULL)
472 brcms_c_bsscfg_mfree(cfg);
476 static struct brcms_c_info *
477 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
479 struct brcms_c_info *wlc;
481 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
487 /* allocate struct brcms_c_pub state structure */
488 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
489 if (wlc->pub == NULL) {
495 /* allocate struct brcms_hardware state structure */
497 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
498 if (wlc->hw == NULL) {
504 wlc->hw->bandstate[0] =
505 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
506 if (wlc->hw->bandstate[0] == NULL) {
512 for (i = 1; i < MAXBANDS; i++)
513 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
514 ((unsigned long)wlc->hw->bandstate[0] +
515 (sizeof(struct brcms_hw_band) * i));
519 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
520 if (wlc->modulecb == NULL) {
525 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
526 if (wlc->default_bss == NULL) {
531 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
532 if (wlc->bsscfg == NULL) {
537 wlc->protection = kzalloc(sizeof(struct brcms_protection),
539 if (wlc->protection == NULL) {
544 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
545 if (wlc->stf == NULL) {
551 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
552 if (wlc->bandstate[0] == NULL) {
558 for (i = 1; i < MAXBANDS; i++)
559 wlc->bandstate[i] = (struct brcms_band *)
560 ((unsigned long)wlc->bandstate[0]
561 + (sizeof(struct brcms_band)*i));
564 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
565 if (wlc->corestate == NULL) {
570 wlc->corestate->macstat_snapshot =
571 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
572 if (wlc->corestate->macstat_snapshot == NULL) {
580 brcms_c_detach_mfree(wlc);
585 * Update the slot timing for standard 11b/g (20us slots)
586 * or shortslot 11g (9us slots)
587 * The PSM needs to be suspended for this call.
589 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
592 struct bcma_device *core = wlc_hw->d11core;
595 /* 11g short slot: 11a timing */
596 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
597 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
599 /* 11g long slot: 11b timing */
600 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
601 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
606 * calculate frame duration of a given rate and length, return
609 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
610 u8 preamble_type, uint mac_len)
612 uint nsyms, dur = 0, Ndps, kNdps;
613 uint rate = rspec2rate(ratespec);
616 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
621 if (is_mcs_rate(ratespec)) {
622 uint mcs = ratespec & RSPEC_RATE_MASK;
623 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
625 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
626 if (preamble_type == BRCMS_MM_PREAMBLE)
628 /* 1000Ndbps = kbps * 4 */
629 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
630 rspec_issgi(ratespec)) * 4;
632 if (rspec_stc(ratespec) == 0)
634 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
635 APHY_TAIL_NBITS) * 1000, kNdps);
637 /* STBC needs to have even number of symbols */
640 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
641 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
643 dur += APHY_SYMBOL_TIME * nsyms;
644 if (wlc->band->bandtype == BRCM_BAND_2G)
645 dur += DOT11_OFDM_SIGNAL_EXTENSION;
646 } else if (is_ofdm_rate(rate)) {
647 dur = APHY_PREAMBLE_TIME;
648 dur += APHY_SIGNAL_TIME;
649 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
651 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
653 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
655 dur += APHY_SYMBOL_TIME * nsyms;
656 if (wlc->band->bandtype == BRCM_BAND_2G)
657 dur += DOT11_OFDM_SIGNAL_EXTENSION;
660 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
663 mac_len = mac_len * 8 * 2;
664 /* calc ceiling of bits/rate = microseconds of air time */
665 dur = (mac_len + rate - 1) / rate;
666 if (preamble_type & BRCMS_SHORT_PREAMBLE)
667 dur += BPHY_PLCP_SHORT_TIME;
669 dur += BPHY_PLCP_TIME;
674 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
675 const struct d11init *inits)
677 struct bcma_device *core = wlc_hw->d11core;
683 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
685 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
686 size = le16_to_cpu(inits[i].size);
687 offset = le16_to_cpu(inits[i].addr);
688 value = le32_to_cpu(inits[i].value);
690 bcma_write16(core, offset, value);
692 bcma_write32(core, offset, value);
698 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
702 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
706 for (idx = 0; idx < MHFMAX; idx++)
707 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
710 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
712 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
714 /* init microcode host flags */
715 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
717 /* do band-specific ucode IHR, SHM, and SCR inits */
718 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
719 if (BRCMS_ISNPHY(wlc_hw->band))
720 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
722 brcms_err(wlc_hw->d11core,
723 "%s: wl%d: unsupported phy in corerev %d\n",
724 __func__, wlc_hw->unit,
727 if (D11REV_IS(wlc_hw->corerev, 24)) {
728 if (BRCMS_ISLCNPHY(wlc_hw->band))
729 brcms_c_write_inits(wlc_hw,
730 ucode->d11lcn0bsinitvals24);
732 brcms_err(wlc_hw->d11core,
733 "%s: wl%d: unsupported phy in core rev %d\n",
734 __func__, wlc_hw->unit,
737 brcms_err(wlc_hw->d11core,
738 "%s: wl%d: unsupported corerev %d\n",
739 __func__, wlc_hw->unit, wlc_hw->corerev);
744 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
746 struct bcma_device *core = wlc_hw->d11core;
747 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
749 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
752 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
754 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
756 wlc_hw->phyclk = clk;
758 if (OFF == clk) { /* clear gmode bit, put phy into reset */
760 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
761 (SICF_PRST | SICF_FGC));
763 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
766 } else { /* take phy out of reset */
768 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
770 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
776 /* low-level band switch utility routine */
777 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
779 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
782 wlc_hw->band = wlc_hw->bandstate[bandunit];
786 * until we eliminate need for wlc->band refs in low level code
788 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
790 /* set gmode core flag */
791 if (wlc_hw->sbclk && !wlc_hw->noreset) {
797 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
801 /* switch to new band but leave it inactive */
802 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
804 struct brcms_hardware *wlc_hw = wlc->hw;
808 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
809 macctrl = bcma_read32(wlc_hw->d11core,
810 D11REGOFFS(maccontrol));
811 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
813 /* disable interrupts */
814 macintmask = brcms_intrsoff(wlc->wl);
817 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
819 brcms_b_core_phy_clk(wlc_hw, OFF);
821 brcms_c_setxband(wlc_hw, bandunit);
826 /* process an individual struct tx_status */
828 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
830 struct sk_buff *p = NULL;
832 struct dma_pub *dma = NULL;
833 struct d11txh *txh = NULL;
834 struct scb *scb = NULL;
836 int tx_rts, tx_frame_count, tx_rts_count;
837 uint totlen, supr_status;
839 struct ieee80211_hdr *h;
841 struct ieee80211_tx_info *tx_info;
842 struct ieee80211_tx_rate *txrate;
846 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
847 txs->frameid, txs->status, txs->lasttxtime,
848 txs->sequence, txs->phyerr, txs->ackphyrxsh);
850 /* discard intermediate indications for ucode with one legitimate case:
851 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
852 * but the subsequent tx of DATA failed. so it will start rts/cts
853 * from the beginning (resetting the rts transmission count)
855 if (!(txs->status & TX_STATUS_AMPDU)
856 && (txs->status & TX_STATUS_INTERMEDIATE)) {
857 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
862 queue = txs->frameid & TXFID_QUEUE_MASK;
863 if (queue >= NFIFO) {
864 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
868 dma = wlc->hw->di[queue];
870 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
872 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
876 txh = (struct d11txh *) (p->data);
877 mcl = le16_to_cpu(txh->MacTxControlLow);
880 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
881 txs->phyerr, txh->MainRates);
883 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
884 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
887 tx_info = IEEE80211_SKB_CB(p);
888 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
890 if (tx_info->rate_driver_data[0])
893 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
894 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
900 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
901 * frames; this traces them for the rest.
903 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
905 supr_status = txs->status & TX_STATUS_SUPR_MASK;
906 if (supr_status == TX_STATUS_SUPR_BADCH) {
907 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
908 brcms_dbg_tx(wlc->hw->d11core,
909 "Pkt tx suppressed, dest chan %u, current %d\n",
910 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
911 CHSPEC_CHANNEL(wlc->default_bss->chanspec));
914 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
916 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
918 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
920 lastframe = !ieee80211_has_morefrags(h->frame_control);
923 brcms_err(wlc->hw->d11core, "Not last frame!\n");
926 * Set information to be consumed by Minstrel ht.
928 * The "fallback limit" is the number of tx attempts a given
929 * MPDU is sent at the "primary" rate. Tx attempts beyond that
930 * limit are sent at the "secondary" rate.
931 * A 'short frame' does not exceed RTS treshold.
933 u16 sfbl, /* Short Frame Rate Fallback Limit */
934 lfbl, /* Long Frame Rate Fallback Limit */
937 if (queue < IEEE80211_NUM_ACS) {
938 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
940 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
947 txrate = tx_info->status.rates;
948 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
953 ieee80211_tx_info_clear_status(tx_info);
955 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
957 * rate selection requested a fallback rate
960 txrate[0].count = fbl;
961 txrate[1].count = tx_frame_count - fbl;
964 * rate selection did not request fallback rate, or
967 txrate[0].count = tx_frame_count;
969 * rc80211_minstrel.c:minstrel_tx_status() expects
970 * unused rates to be marked with idx = -1
976 /* clear the rest of the rates */
977 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
982 if (txs->status & TX_STATUS_ACK_RCV)
983 tx_info->flags |= IEEE80211_TX_STAT_ACK;
990 /* remove PLCP & Broadcom tx descriptor header */
991 skb_pull(p, D11_PHY_HDR_LEN);
992 skb_pull(p, D11_TXH_LEN);
993 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
995 brcms_err(wlc->hw->d11core,
996 "%s: Not last frame => not calling tx_status\n",
1005 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1008 brcmu_pkt_buf_free_skb(p);
1011 if (dma && queue < NFIFO) {
1012 u16 ac_queue = brcms_fifo_to_ac(queue);
1013 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1014 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1015 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1022 /* process tx completion events in BMAC
1023 * Return true if more tx status need to be processed. false otherwise.
1026 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1028 struct bcma_device *core;
1029 struct tx_status txstatus, *txs;
1033 * Param 'max_tx_num' indicates max. # tx status to process before
1036 uint max_tx_num = bound ? TXSBND : -1;
1039 core = wlc_hw->d11core;
1042 while (n < max_tx_num) {
1043 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1044 if (s1 == 0xffffffff) {
1045 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1050 /* only process when valid */
1054 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1055 txs->status = s1 & TXS_STATUS_MASK;
1056 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1057 txs->sequence = s2 & TXS_SEQ_MASK;
1058 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1059 txs->lasttxtime = 0;
1061 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1067 return n >= max_tx_num;
1070 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1072 if (!wlc->bsscfg->BSS)
1074 * DirFrmQ is now valid...defer setting until end
1077 wlc->qvalid |= MCMD_DIRFRMQVAL;
1080 /* set initial host flags value */
1082 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1084 struct brcms_hardware *wlc_hw = wlc->hw;
1086 memset(mhfs, 0, MHFMAX * sizeof(u16));
1088 mhfs[MHF2] |= mhf2_init;
1090 /* prohibit use of slowclock on multifunction boards */
1091 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1092 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1094 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1095 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1096 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1101 dmareg(uint direction, uint fifonum)
1103 if (direction == DMA_TX)
1104 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1105 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1108 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1113 * ucode host flag 2 needed for pio mode, independent of band and fifo
1116 struct brcms_hardware *wlc_hw = wlc->hw;
1117 uint unit = wlc_hw->unit;
1119 /* name and offsets for dma_attach */
1120 snprintf(name, sizeof(name), "wl%d", unit);
1122 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1123 int dma_attach_err = 0;
1127 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1128 * RX: RX_FIFO (RX data packets)
1130 wlc_hw->di[0] = dma_attach(name, wlc,
1131 (wme ? dmareg(DMA_TX, 0) : 0),
1133 (wme ? NTXD : 0), NRXD,
1134 RXBUFSZ, -1, NRXBUFPOST,
1136 dma_attach_err |= (NULL == wlc_hw->di[0]);
1140 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1141 * (legacy) TX_DATA_FIFO (TX data packets)
1144 wlc_hw->di[1] = dma_attach(name, wlc,
1145 dmareg(DMA_TX, 1), 0,
1146 NTXD, 0, 0, -1, 0, 0);
1147 dma_attach_err |= (NULL == wlc_hw->di[1]);
1151 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1154 wlc_hw->di[2] = dma_attach(name, wlc,
1155 dmareg(DMA_TX, 2), 0,
1156 NTXD, 0, 0, -1, 0, 0);
1157 dma_attach_err |= (NULL == wlc_hw->di[2]);
1160 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1161 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1163 wlc_hw->di[3] = dma_attach(name, wlc,
1167 dma_attach_err |= (NULL == wlc_hw->di[3]);
1168 /* Cleaner to leave this as if with AP defined */
1170 if (dma_attach_err) {
1171 brcms_err(wlc_hw->d11core,
1172 "wl%d: wlc_attach: dma_attach failed\n",
1177 /* get pointer to dma engine tx flow control variable */
1178 for (i = 0; i < NFIFO; i++)
1180 wlc_hw->txavail[i] =
1181 (uint *) dma_getvar(wlc_hw->di[i],
1185 /* initial ucode host flags */
1186 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1191 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1195 for (j = 0; j < NFIFO; j++) {
1196 if (wlc_hw->di[j]) {
1197 dma_detach(wlc_hw->di[j]);
1198 wlc_hw->di[j] = NULL;
1204 * Initialize brcms_c_info default values ...
1205 * may get overrides later in this function
1206 * BMAC_NOTES, move low out and resolve the dangling ones
1208 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1210 struct brcms_c_info *wlc = wlc_hw->wlc;
1212 /* set default sw macintmask value */
1213 wlc->defmacintmask = DEF_MACINTMASK;
1215 /* various 802.11g modes */
1216 wlc_hw->shortslot = false;
1218 wlc_hw->SFBL = RETRY_SHORT_FB;
1219 wlc_hw->LFBL = RETRY_LONG_FB;
1221 /* default mac retry limits */
1222 wlc_hw->SRL = RETRY_SHORT_DEF;
1223 wlc_hw->LRL = RETRY_LONG_DEF;
1224 wlc_hw->chanspec = ch20mhz_chspec(1);
1227 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1229 /* delay before first read of ucode state */
1232 /* wait until ucode is no longer asleep */
1233 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1234 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1237 /* control chip clock to save power, enable dynamic clock or force fast clock */
1238 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1240 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1241 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1242 * on backplane, but mac core will still run on ALP(not HT) when
1243 * it enters powersave mode, which means the FCA bit may not be
1244 * set. Should wakeup mac if driver wants it to run on HT.
1248 if (mode == BCMA_CLKMODE_FAST) {
1249 bcma_set32(wlc_hw->d11core,
1250 D11REGOFFS(clk_ctl_st),
1256 ((bcma_read32(wlc_hw->d11core,
1257 D11REGOFFS(clk_ctl_st)) &
1259 PMU_MAX_TRANSITION_DLY);
1260 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1261 D11REGOFFS(clk_ctl_st)) &
1264 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1265 (bcma_read32(wlc_hw->d11core,
1266 D11REGOFFS(clk_ctl_st)) &
1267 (CCS_FORCEHT | CCS_HTAREQ)))
1269 ((bcma_read32(wlc_hw->d11core,
1270 offsetof(struct d11regs,
1273 PMU_MAX_TRANSITION_DLY);
1274 bcma_mask32(wlc_hw->d11core,
1275 D11REGOFFS(clk_ctl_st),
1279 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1282 /* old chips w/o PMU, force HT through cc,
1283 * then use FCA to verify mac is running fast clock
1286 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1288 /* check fast clock is available (if core is not in reset) */
1289 if (wlc_hw->forcefastclk && wlc_hw->clk)
1290 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1294 * keep the ucode wake bit on if forcefastclk is on since we
1295 * do not want ucode to put us back to slow clock when it dozes
1296 * for PM mode. Code below matches the wake override bit with
1297 * current forcefastclk state. Only setting bit in wake_override
1298 * instead of waking ucode immediately since old code had this
1299 * behavior. Older code set wlc->forcefastclk but only had the
1300 * wake happen if the wakup_ucode work (protected by an up
1301 * check) was executed just below.
1303 if (wlc_hw->forcefastclk)
1304 mboolset(wlc_hw->wake_override,
1305 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1307 mboolclr(wlc_hw->wake_override,
1308 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1312 /* set or clear ucode host flag bits
1313 * it has an optimization for no-change write
1314 * it only writes through shared memory when the core has clock;
1315 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1318 * bands values are: BRCM_BAND_AUTO <--- Current band only
1319 * BRCM_BAND_5G <--- 5G band only
1320 * BRCM_BAND_2G <--- 2G band only
1321 * BRCM_BAND_ALL <--- All bands
1324 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1328 u16 addr[MHFMAX] = {
1329 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1332 struct brcms_hw_band *band;
1334 if ((val & ~mask) || idx >= MHFMAX)
1335 return; /* error condition */
1338 /* Current band only or all bands,
1339 * then set the band to current band
1341 case BRCM_BAND_AUTO:
1343 band = wlc_hw->band;
1346 band = wlc_hw->bandstate[BAND_5G_INDEX];
1349 band = wlc_hw->bandstate[BAND_2G_INDEX];
1352 band = NULL; /* error condition */
1356 save = band->mhfs[idx];
1357 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1359 /* optimization: only write through if changed, and
1360 * changed band is the current band
1362 if (wlc_hw->clk && (band->mhfs[idx] != save)
1363 && (band == wlc_hw->band))
1364 brcms_b_write_shm(wlc_hw, addr[idx],
1365 (u16) band->mhfs[idx]);
1368 if (bands == BRCM_BAND_ALL) {
1369 wlc_hw->bandstate[0]->mhfs[idx] =
1370 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1371 wlc_hw->bandstate[1]->mhfs[idx] =
1372 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1376 /* set the maccontrol register to desired reset state and
1377 * initialize the sw cache of the register
1379 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1381 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1382 wlc_hw->maccontrol = 0;
1383 wlc_hw->suspended_fifos = 0;
1384 wlc_hw->wake_override = 0;
1385 wlc_hw->mute_override = 0;
1386 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1390 * write the software state of maccontrol and
1391 * overrides to the maccontrol register
1393 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1395 u32 maccontrol = wlc_hw->maccontrol;
1397 /* OR in the wake bit if overridden */
1398 if (wlc_hw->wake_override)
1399 maccontrol |= MCTL_WAKE;
1401 /* set AP and INFRA bits for mute if needed */
1402 if (wlc_hw->mute_override) {
1403 maccontrol &= ~(MCTL_AP);
1404 maccontrol |= MCTL_INFRA;
1407 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1411 /* set or clear maccontrol bits */
1412 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1418 return; /* error condition */
1419 maccontrol = wlc_hw->maccontrol;
1420 new_maccontrol = (maccontrol & ~mask) | val;
1422 /* if the new maccontrol value is the same as the old, nothing to do */
1423 if (new_maccontrol == maccontrol)
1426 /* something changed, cache the new value */
1427 wlc_hw->maccontrol = new_maccontrol;
1429 /* write the new values with overrides applied */
1430 brcms_c_mctrl_write(wlc_hw);
1433 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1436 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1437 mboolset(wlc_hw->wake_override, override_bit);
1441 mboolset(wlc_hw->wake_override, override_bit);
1443 brcms_c_mctrl_write(wlc_hw);
1444 brcms_b_wait_for_wake(wlc_hw);
1447 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1450 mboolclr(wlc_hw->wake_override, override_bit);
1452 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1455 brcms_c_mctrl_write(wlc_hw);
1458 /* When driver needs ucode to stop beaconing, it has to make sure that
1459 * MCTL_AP is clear and MCTL_INFRA is set
1460 * Mode MCTL_AP MCTL_INFRA
1462 * STA 0 1 <--- This will ensure no beacons
1465 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1467 wlc_hw->mute_override = 1;
1469 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1470 * override, then there is no change to write
1472 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1475 brcms_c_mctrl_write(wlc_hw);
1478 /* Clear the override on AP and INFRA bits */
1479 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1481 if (wlc_hw->mute_override == 0)
1484 wlc_hw->mute_override = 0;
1486 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1487 * override, then there is no change to write
1489 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1492 brcms_c_mctrl_write(wlc_hw);
1496 * Write a MAC address to the given match reg offset in the RXE match engine.
1499 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1502 struct bcma_device *core = wlc_hw->d11core;
1507 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1509 mac_l = addr[0] | (addr[1] << 8);
1510 mac_m = addr[2] | (addr[3] << 8);
1511 mac_h = addr[4] | (addr[5] << 8);
1513 /* enter the MAC addr into the RXE match registers */
1514 bcma_write16(core, D11REGOFFS(rcm_ctl),
1515 RCM_INC_DATA | match_reg_offset);
1516 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1517 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1518 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1522 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1525 struct bcma_device *core = wlc_hw->d11core;
1530 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1532 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1534 /* if MCTL_BIGEND bit set in mac control register,
1535 * the chip swaps data in fifo, as well as data in
1538 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1541 memcpy(&word, buf, sizeof(u32));
1544 word_be = cpu_to_be32(word);
1545 word = *(u32 *)&word_be;
1547 word_le = cpu_to_le32(word);
1548 word = *(u32 *)&word_le;
1551 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1553 buf = (u8 *) buf + sizeof(u32);
1558 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1560 wlc_hw->band->CWmin = newmin;
1562 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1563 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1564 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1565 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1568 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1570 wlc_hw->band->CWmax = newmax;
1572 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1573 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1574 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1575 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1578 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1582 /* request FAST clock if not on */
1583 fastclk = wlc_hw->forcefastclk;
1585 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1587 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1589 brcms_b_phy_reset(wlc_hw);
1590 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1592 /* restore the clk */
1594 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1597 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1600 struct brcms_c_info *wlc = wlc_hw->wlc;
1601 /* update SYNTHPU_DLY */
1603 if (BRCMS_ISLCNPHY(wlc->band))
1604 v = SYNTHPU_DLY_LPPHY_US;
1605 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1606 v = SYNTHPU_DLY_NPHY_US;
1608 v = SYNTHPU_DLY_BPHY_US;
1610 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1613 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1616 u16 phytxant = wlc_hw->bmac_phytxant;
1617 u16 mask = PHY_TXC_ANT_MASK;
1619 /* set the Probe Response frame phy control word */
1620 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1621 phyctl = (phyctl & ~mask) | phytxant;
1622 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1624 /* set the Response (ACK/CTS) frame phy control word */
1625 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1626 phyctl = (phyctl & ~mask) | phytxant;
1627 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1630 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1635 struct plcp_signal_rate_lookup {
1639 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1640 const struct plcp_signal_rate_lookup rate_lookup[] = {
1641 {BRCM_RATE_6M, 0xB},
1642 {BRCM_RATE_9M, 0xF},
1643 {BRCM_RATE_12M, 0xA},
1644 {BRCM_RATE_18M, 0xE},
1645 {BRCM_RATE_24M, 0x9},
1646 {BRCM_RATE_36M, 0xD},
1647 {BRCM_RATE_48M, 0x8},
1648 {BRCM_RATE_54M, 0xC}
1651 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1652 if (rate == rate_lookup[i].rate) {
1653 plcp_rate = rate_lookup[i].signal_rate;
1658 /* Find the SHM pointer to the rate table entry by looking in the
1661 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1664 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1668 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1669 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1675 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1678 /* walk the phy rate table and update the entries */
1679 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1682 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1684 /* read the SHM Rate Table entry OFDM PCTL1 values */
1686 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1688 /* modify the value */
1689 pctl1 &= ~PHY_TXC1_MODE_MASK;
1690 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1692 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1693 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1698 /* band-specific init */
1699 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1701 struct brcms_hardware *wlc_hw = wlc->hw;
1703 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1704 wlc_hw->band->bandunit);
1706 brcms_c_ucode_bsinit(wlc_hw);
1708 wlc_phy_init(wlc_hw->band->pi, chanspec);
1710 brcms_c_ucode_txant_set(wlc_hw);
1713 * cwmin is band-specific, update hardware
1714 * with value for current band
1716 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1717 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1719 brcms_b_update_slot_timing(wlc_hw,
1720 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1721 true : wlc_hw->shortslot);
1723 /* write phytype and phyvers */
1724 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1725 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1728 * initialize the txphyctl1 rate table since
1729 * shmem is shared between bands
1731 brcms_upd_ofdm_pctl1_table(wlc_hw);
1733 brcms_b_upd_synthpu(wlc_hw);
1736 /* Perform a soft reset of the PHY PLL */
1737 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1739 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1742 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1748 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1753 /* light way to turn on phy clock without reset for NPHY only
1754 * refer to brcms_b_core_phy_clk for full version
1756 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1758 /* support(necessary for NPHY and HYPHY) only */
1759 if (!BRCMS_ISNPHY(wlc_hw->band))
1763 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1765 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1769 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1772 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1774 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1777 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1779 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1781 bool phy_in_reset = false;
1783 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1788 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1790 /* Specific reset sequence required for NPHY rev 3 and 4 */
1791 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1792 NREV_LE(wlc_hw->band->phyrev, 4)) {
1793 /* Set the PHY bandwidth */
1794 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1798 /* Perform a soft reset of the PHY PLL */
1799 brcms_b_core_phypll_reset(wlc_hw);
1802 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1803 (SICF_PRST | SICF_PCLKE));
1804 phy_in_reset = true;
1806 brcms_b_core_ioctl(wlc_hw,
1807 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1808 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1812 brcms_b_core_phy_clk(wlc_hw, ON);
1815 wlc_phy_anacore(pih, ON);
1818 /* switch to and initialize new band */
1819 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1821 struct brcms_c_info *wlc = wlc_hw->wlc;
1824 /* Enable the d11 core before accessing it */
1825 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1826 bcma_core_enable(wlc_hw->d11core, 0);
1827 brcms_c_mctrl_reset(wlc_hw);
1830 macintmask = brcms_c_setband_inact(wlc, bandunit);
1835 brcms_b_core_phy_clk(wlc_hw, ON);
1837 /* band-specific initializations */
1838 brcms_b_bsinit(wlc, chanspec);
1841 * If there are any pending software interrupt bits,
1842 * then replace these with a harmless nonzero value
1843 * so brcms_c_dpc() will re-enable interrupts when done.
1845 if (wlc->macintstatus)
1846 wlc->macintstatus = MI_DMAINT;
1848 /* restore macintmask */
1849 brcms_intrsrestore(wlc->wl, macintmask);
1851 /* ucode should still be suspended.. */
1852 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1856 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1859 /* reject unsupported corerev */
1860 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1861 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1869 /* Validate some board info parameters */
1870 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1872 uint boardrev = wlc_hw->boardrev;
1874 /* 4 bits each for board type, major, minor, and tiny version */
1875 uint brt = (boardrev & 0xf000) >> 12;
1876 uint b0 = (boardrev & 0xf00) >> 8;
1877 uint b1 = (boardrev & 0xf0) >> 4;
1878 uint b2 = boardrev & 0xf;
1880 /* voards from other vendors are always considered valid */
1881 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1884 /* do some boardrev sanity checks when boardvendor is Broadcom */
1888 if (boardrev <= 0xff)
1891 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1898 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1900 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1902 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1903 if (!is_zero_ether_addr(sprom->il0mac)) {
1904 memcpy(etheraddr, sprom->il0mac, 6);
1908 if (wlc_hw->_nbands > 1)
1909 memcpy(etheraddr, sprom->et1mac, 6);
1911 memcpy(etheraddr, sprom->il0mac, 6);
1914 /* power both the pll and external oscillator on/off */
1915 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1917 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1920 * dont power down if plldown is false or
1921 * we must poll hw radio disable
1923 if (!want && wlc_hw->pllreq)
1926 wlc_hw->sbclk = want;
1927 if (!wlc_hw->sbclk) {
1928 wlc_hw->clk = false;
1929 if (wlc_hw->band && wlc_hw->band->pi)
1930 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1935 * Return true if radio is disabled, otherwise false.
1936 * hw radio disable signal is an external pin, users activate it asynchronously
1937 * this function could be called when driver is down and w/o clock
1938 * it operates on different registers depending on corerev and boardflag.
1940 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1945 xtal = wlc_hw->sbclk;
1947 brcms_b_xtal(wlc_hw, ON);
1949 /* may need to take core out of reset first */
1953 * mac no longer enables phyclk automatically when driver
1954 * accesses phyreg throughput mac. This can be skipped since
1955 * only mac reg is accessed below
1957 if (D11REV_GE(wlc_hw->corerev, 18))
1958 flags |= SICF_PCLKE;
1961 * TODO: test suspend/resume
1963 * AI chip doesn't restore bar0win2 on
1964 * hibernation/resume, need sw fixup
1967 bcma_core_enable(wlc_hw->d11core, flags);
1968 brcms_c_mctrl_reset(wlc_hw);
1971 v = ((bcma_read32(wlc_hw->d11core,
1972 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1974 /* put core back into reset */
1976 bcma_core_disable(wlc_hw->d11core, 0);
1979 brcms_b_xtal(wlc_hw, OFF);
1984 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1986 struct dma_pub *di = wlc_hw->di[fifo];
1987 return dma_rxreset(di);
1991 * ensure fask clock during reset
1993 * reset d11(out of reset)
1994 * reset phy(out of reset)
1995 * clear software macintstatus for fresh new start
1996 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1998 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2003 if (flags == BRCMS_USE_COREFLAGS)
2004 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2006 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2008 /* request FAST clock if not on */
2009 fastclk = wlc_hw->forcefastclk;
2011 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2013 /* reset the dma engines except first time thru */
2014 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2015 for (i = 0; i < NFIFO; i++)
2016 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2017 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2018 "dma_txreset[%d]: cannot stop dma\n",
2019 wlc_hw->unit, __func__, i);
2021 if ((wlc_hw->di[RX_FIFO])
2022 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2023 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2024 "[%d]: cannot stop dma\n",
2025 wlc_hw->unit, __func__, RX_FIFO);
2027 /* if noreset, just stop the psm and return */
2028 if (wlc_hw->noreset) {
2029 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2030 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2035 * mac no longer enables phyclk automatically when driver accesses
2036 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2037 * band->pi is invalid. need to enable PHY CLK
2039 if (D11REV_GE(wlc_hw->corerev, 18))
2040 flags |= SICF_PCLKE;
2044 * In chips with PMU, the fastclk request goes through d11 core
2045 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2047 * This adds some delay and we can optimize it by also requesting
2048 * fastclk through chipcommon during this period if necessary. But
2049 * that has to work coordinate with other driver like mips/arm since
2050 * they may touch chipcommon as well.
2052 wlc_hw->clk = false;
2053 bcma_core_enable(wlc_hw->d11core, flags);
2055 if (wlc_hw->band && wlc_hw->band->pi)
2056 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2058 brcms_c_mctrl_reset(wlc_hw);
2060 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2061 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2063 brcms_b_phy_reset(wlc_hw);
2065 /* turn on PHY_PLL */
2066 brcms_b_core_phypll_ctl(wlc_hw, true);
2068 /* clear sw intstatus */
2069 wlc_hw->wlc->macintstatus = 0;
2071 /* restore the clk setting */
2073 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2076 /* txfifo sizes needs to be modified(increased) since the newer cores
2079 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2081 struct bcma_device *core = wlc_hw->d11core;
2083 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2084 u16 txfifo_def, txfifo_def1;
2087 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2088 txfifo_startblk = TXFIFO_START_BLK;
2090 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2091 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2093 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2094 txfifo_def = (txfifo_startblk & 0xff) |
2095 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2096 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2098 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2100 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2102 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2103 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2104 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2106 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2108 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2111 * need to propagate to shm location to be in sync since ucode/hw won't
2114 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2115 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2116 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2117 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2118 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2119 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2120 xmtfifo_sz[TX_AC_BK_FIFO]));
2121 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2122 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2123 xmtfifo_sz[TX_BCMC_FIFO]));
2126 /* This function is used for changing the tsf frac register
2127 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2128 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2129 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2130 * HTPHY Formula is 2^26/freq(MHz) e.g.
2131 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2132 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2133 * For spuron: 123MHz -> 2^26/123 = 545600.5
2134 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2135 * For spur off: 120MHz -> 2^26/120 = 559240.5
2136 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2139 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2141 struct bcma_device *core = wlc_hw->d11core;
2143 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2144 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2145 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2147 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2148 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2149 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2150 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2151 } else { /* 120Mhz */
2152 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2153 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2155 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2156 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2157 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2158 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2159 } else { /* 80Mhz */
2160 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2161 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2166 /* Initialize GPIOs that are controlled by D11 core */
2167 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2169 struct brcms_hardware *wlc_hw = wlc->hw;
2172 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2173 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2176 * Common GPIO setup:
2177 * G0 = LED 0 = WLAN Activity
2178 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2179 * G2 = LED 2 = WLAN 5 GHz Radio State
2180 * G4 = radio disable input (HI enabled, LO disabled)
2185 /* Allocate GPIOs for mimo antenna diversity feature */
2186 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2187 /* Enable antenna diversity, use 2x3 mode */
2188 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2189 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2190 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2191 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2193 /* init superswitch control */
2194 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2196 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2197 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2199 * The board itself is powered by these GPIOs
2200 * (when not sending pattern) so set them high
2202 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2203 (BOARD_GPIO_12 | BOARD_GPIO_13));
2204 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2205 (BOARD_GPIO_12 | BOARD_GPIO_13));
2207 /* Enable antenna diversity, use 2x4 mode */
2208 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2209 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2210 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2213 /* Configure the desired clock to be 4Mhz */
2214 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2215 ANTSEL_CLKDIV_4MHZ);
2219 * gpio 9 controls the PA. ucode is responsible
2220 * for wiggling out and oe
2222 if (wlc_hw->boardflags & BFL_PACTRL)
2223 gm |= gc |= BOARD_GPIO_PACTRL;
2225 /* apply to gpiocontrol register */
2226 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2229 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2230 const __le32 ucode[], const size_t nbytes)
2232 struct bcma_device *core = wlc_hw->d11core;
2236 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2238 count = (nbytes / sizeof(u32));
2240 bcma_write32(core, D11REGOFFS(objaddr),
2241 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2242 (void)bcma_read32(core, D11REGOFFS(objaddr));
2243 for (i = 0; i < count; i++)
2244 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2248 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2250 struct brcms_c_info *wlc;
2251 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2255 if (wlc_hw->ucode_loaded)
2258 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2259 if (BRCMS_ISNPHY(wlc_hw->band)) {
2260 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2261 ucode->bcm43xx_16_mimosz);
2262 wlc_hw->ucode_loaded = true;
2264 brcms_err(wlc_hw->d11core,
2265 "%s: wl%d: unsupported phy in corerev %d\n",
2266 __func__, wlc_hw->unit, wlc_hw->corerev);
2267 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2268 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2269 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2270 ucode->bcm43xx_24_lcnsz);
2271 wlc_hw->ucode_loaded = true;
2273 brcms_err(wlc_hw->d11core,
2274 "%s: wl%d: unsupported phy in corerev %d\n",
2275 __func__, wlc_hw->unit, wlc_hw->corerev);
2280 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2282 /* update sw state */
2283 wlc_hw->bmac_phytxant = phytxant;
2285 /* push to ucode if up */
2288 brcms_c_ucode_txant_set(wlc_hw);
2292 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2294 return (u16) wlc_hw->wlc->stf->txant;
2297 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2299 wlc_hw->antsel_type = antsel_type;
2301 /* Update the antsel type for phy module to use */
2302 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2305 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2309 uint intstatus, idx;
2310 struct bcma_device *core = wlc_hw->d11core;
2312 unit = wlc_hw->unit;
2314 for (idx = 0; idx < NFIFO; idx++) {
2315 /* read intstatus register and ignore any non-error bits */
2318 D11REGOFFS(intctrlregs[idx].intstatus)) &
2323 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2324 unit, idx, intstatus);
2326 if (intstatus & I_RO) {
2327 brcms_err(core, "wl%d: fifo %d: receive fifo "
2328 "overflow\n", unit, idx);
2332 if (intstatus & I_PC) {
2333 brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2338 if (intstatus & I_PD) {
2339 brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2344 if (intstatus & I_DE) {
2345 brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2346 "error\n", unit, idx);
2350 if (intstatus & I_RU)
2351 brcms_err(core, "wl%d: fifo %d: receive descriptor "
2352 "underflow\n", idx, unit);
2354 if (intstatus & I_XU) {
2355 brcms_err(core, "wl%d: fifo %d: transmit fifo "
2356 "underflow\n", idx, unit);
2361 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2365 D11REGOFFS(intctrlregs[idx].intstatus),
2370 void brcms_c_intrson(struct brcms_c_info *wlc)
2372 struct brcms_hardware *wlc_hw = wlc->hw;
2373 wlc->macintmask = wlc->defmacintmask;
2374 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2377 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2379 struct brcms_hardware *wlc_hw = wlc->hw;
2385 macintmask = wlc->macintmask; /* isr can still happen */
2387 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2388 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2389 udelay(1); /* ensure int line is no longer driven */
2390 wlc->macintmask = 0;
2392 /* return previous macintmask; resolve race between us and our isr */
2393 return wlc->macintstatus ? 0 : macintmask;
2396 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2398 struct brcms_hardware *wlc_hw = wlc->hw;
2402 wlc->macintmask = macintmask;
2403 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2406 /* assumes that the d11 MAC is enabled */
2407 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2410 u8 fifo = 1 << tx_fifo;
2412 /* Two clients of this code, 11h Quiet period and scanning. */
2414 /* only suspend if not already suspended */
2415 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2418 /* force the core awake only if not already */
2419 if (wlc_hw->suspended_fifos == 0)
2420 brcms_c_ucode_wake_override_set(wlc_hw,
2421 BRCMS_WAKE_OVERRIDE_TXFIFO);
2423 wlc_hw->suspended_fifos |= fifo;
2425 if (wlc_hw->di[tx_fifo]) {
2427 * Suspending AMPDU transmissions in the middle can cause
2428 * underflow which may result in mismatch between ucode and
2429 * driver so suspend the mac before suspending the FIFO
2431 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2432 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2434 dma_txsuspend(wlc_hw->di[tx_fifo]);
2436 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2437 brcms_c_enable_mac(wlc_hw->wlc);
2441 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2444 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2445 * but need to be done here for PIO otherwise the watchdog will catch
2446 * the inconsistency and fire
2448 /* Two clients of this code, 11h Quiet period and scanning. */
2449 if (wlc_hw->di[tx_fifo])
2450 dma_txresume(wlc_hw->di[tx_fifo]);
2452 /* allow core to sleep again */
2453 if (wlc_hw->suspended_fifos == 0)
2456 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2457 if (wlc_hw->suspended_fifos == 0)
2458 brcms_c_ucode_wake_override_clear(wlc_hw,
2459 BRCMS_WAKE_OVERRIDE_TXFIFO);
2463 /* precondition: requires the mac core to be enabled */
2464 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2466 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2467 u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2470 /* suspend tx fifos */
2471 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2472 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2473 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2474 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2476 /* zero the address match register so we do not send ACKs */
2477 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2479 /* resume tx fifos */
2480 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2481 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2482 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2483 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2485 /* Restore address */
2486 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2489 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2492 brcms_c_ucode_mute_override_set(wlc_hw);
2494 brcms_c_ucode_mute_override_clear(wlc_hw);
2498 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2500 brcms_b_mute(wlc->hw, mute_tx);
2504 * Read and clear macintmask and macintstatus and intstatus registers.
2505 * This routine should be called with interrupts off
2507 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2508 * 0 if the interrupt is not for us, or we are in some special cases;
2509 * device interrupt status bits otherwise.
2511 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2513 struct brcms_hardware *wlc_hw = wlc->hw;
2514 struct bcma_device *core = wlc_hw->d11core;
2515 u32 macintstatus, mask;
2517 /* macintstatus includes a DMA interrupt summary bit */
2518 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2519 mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2521 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2523 /* detect cardbus removed, in power down(suspend) and in reset */
2524 if (brcms_deviceremoved(wlc))
2527 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2528 * handle that case here.
2530 if (macintstatus == 0xffffffff)
2533 /* defer unsolicited interrupts */
2534 macintstatus &= mask;
2537 if (macintstatus == 0)
2540 /* turn off the interrupts */
2541 bcma_write32(core, D11REGOFFS(macintmask), 0);
2542 (void)bcma_read32(core, D11REGOFFS(macintmask));
2543 wlc->macintmask = 0;
2545 /* clear device interrupts */
2546 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2548 /* MI_DMAINT is indication of non-zero intstatus */
2549 if (macintstatus & MI_DMAINT)
2551 * only fifo interrupt enabled is I_RI in
2552 * RX_FIFO. If MI_DMAINT is set, assume it
2553 * is set and clear the interrupt.
2555 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2558 return macintstatus;
2561 /* Update wlc->macintstatus and wlc->intstatus[]. */
2562 /* Return true if they are updated successfully. false otherwise */
2563 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2567 /* read and clear macintstatus and intstatus registers */
2568 macintstatus = wlc_intstatus(wlc, false);
2570 /* device is removed */
2571 if (macintstatus == 0xffffffff)
2574 /* update interrupt status in software */
2575 wlc->macintstatus |= macintstatus;
2581 * First-level interrupt processing.
2582 * Return true if this was our interrupt
2583 * and if further brcms_c_dpc() processing is required,
2586 bool brcms_c_isr(struct brcms_c_info *wlc)
2588 struct brcms_hardware *wlc_hw = wlc->hw;
2591 if (!wlc_hw->up || !wlc->macintmask)
2594 /* read and clear macintstatus and intstatus registers */
2595 macintstatus = wlc_intstatus(wlc, true);
2597 if (macintstatus == 0xffffffff) {
2598 brcms_err(wlc_hw->d11core,
2599 "DEVICEREMOVED detected in the ISR code path\n");
2603 /* it is not for us */
2604 if (macintstatus == 0)
2607 /* save interrupt status bits */
2608 wlc->macintstatus = macintstatus;
2614 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2616 struct brcms_hardware *wlc_hw = wlc->hw;
2617 struct bcma_device *core = wlc_hw->d11core;
2620 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2621 wlc_hw->band->bandunit);
2624 * Track overlapping suspend requests
2626 wlc_hw->mac_suspend_depth++;
2627 if (wlc_hw->mac_suspend_depth > 1)
2630 /* force the core awake */
2631 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2633 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2635 if (mc == 0xffffffff) {
2636 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2638 brcms_down(wlc->wl);
2641 WARN_ON(mc & MCTL_PSM_JMP_0);
2642 WARN_ON(!(mc & MCTL_PSM_RUN));
2643 WARN_ON(!(mc & MCTL_EN_MAC));
2645 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2646 if (mi == 0xffffffff) {
2647 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2649 brcms_down(wlc->wl);
2652 WARN_ON(mi & MI_MACSSPNDD);
2654 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2656 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2657 BRCMS_MAX_MAC_SUSPEND);
2659 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2660 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2661 " and MI_MACSSPNDD is still not on.\n",
2662 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2663 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2664 "psm_brc 0x%04x\n", wlc_hw->unit,
2665 bcma_read32(core, D11REGOFFS(psmdebug)),
2666 bcma_read32(core, D11REGOFFS(phydebug)),
2667 bcma_read16(core, D11REGOFFS(psm_brc)));
2670 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2671 if (mc == 0xffffffff) {
2672 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2674 brcms_down(wlc->wl);
2677 WARN_ON(mc & MCTL_PSM_JMP_0);
2678 WARN_ON(!(mc & MCTL_PSM_RUN));
2679 WARN_ON(mc & MCTL_EN_MAC);
2682 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2684 struct brcms_hardware *wlc_hw = wlc->hw;
2685 struct bcma_device *core = wlc_hw->d11core;
2688 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2689 wlc->band->bandunit);
2692 * Track overlapping suspend requests
2694 wlc_hw->mac_suspend_depth--;
2695 if (wlc_hw->mac_suspend_depth > 0)
2698 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2699 WARN_ON(mc & MCTL_PSM_JMP_0);
2700 WARN_ON(mc & MCTL_EN_MAC);
2701 WARN_ON(!(mc & MCTL_PSM_RUN));
2703 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2704 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2706 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2707 WARN_ON(mc & MCTL_PSM_JMP_0);
2708 WARN_ON(!(mc & MCTL_EN_MAC));
2709 WARN_ON(!(mc & MCTL_PSM_RUN));
2711 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2712 WARN_ON(mi & MI_MACSSPNDD);
2714 brcms_c_ucode_wake_override_clear(wlc_hw,
2715 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2718 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2720 wlc_hw->hw_stf_ss_opmode = stf_mode;
2723 brcms_upd_ofdm_pctl1_table(wlc_hw);
2726 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2728 struct bcma_device *core = wlc_hw->d11core;
2730 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2732 /* Validate dchip register access */
2734 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2735 (void)bcma_read32(core, D11REGOFFS(objaddr));
2736 w = bcma_read32(core, D11REGOFFS(objdata));
2738 /* Can we write and read back a 32bit register? */
2739 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2740 (void)bcma_read32(core, D11REGOFFS(objaddr));
2741 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2743 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2744 (void)bcma_read32(core, D11REGOFFS(objaddr));
2745 val = bcma_read32(core, D11REGOFFS(objdata));
2746 if (val != (u32) 0xaa5555aa) {
2747 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2748 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2752 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753 (void)bcma_read32(core, D11REGOFFS(objaddr));
2754 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2756 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2757 (void)bcma_read32(core, D11REGOFFS(objaddr));
2758 val = bcma_read32(core, D11REGOFFS(objdata));
2759 if (val != (u32) 0x55aaaa55) {
2760 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2761 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2765 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766 (void)bcma_read32(core, D11REGOFFS(objaddr));
2767 bcma_write32(core, D11REGOFFS(objdata), w);
2769 /* clear CFPStart */
2770 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2772 w = bcma_read32(core, D11REGOFFS(maccontrol));
2773 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2774 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2775 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2776 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2777 (MCTL_IHR_EN | MCTL_WAKE),
2778 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2785 #define PHYPLL_WAIT_US 100000
2787 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2789 struct bcma_device *core = wlc_hw->d11core;
2792 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2797 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2798 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2800 CCS_ERSRC_REQ_D11PLL |
2801 CCS_ERSRC_REQ_PHYPLL);
2802 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2803 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2806 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2807 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2808 brcms_err(core, "%s: turn on PHY PLL failed\n",
2811 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2812 tmp | CCS_ERSRC_REQ_D11PLL |
2813 CCS_ERSRC_REQ_PHYPLL);
2814 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2815 (CCS_ERSRC_AVAIL_D11PLL |
2816 CCS_ERSRC_AVAIL_PHYPLL)) !=
2817 (CCS_ERSRC_AVAIL_D11PLL |
2818 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2820 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2822 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2824 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2825 brcms_err(core, "%s: turn on PHY PLL failed\n",
2830 * Since the PLL may be shared, other cores can still
2831 * be requesting it; so we'll deassert the request but
2832 * not wait for status to comply.
2834 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2835 ~CCS_ERSRC_REQ_PHYPLL);
2836 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2840 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2844 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2846 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2851 if (wlc_hw->noreset)
2855 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2857 /* turn off analog core */
2858 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2860 /* turn off PHYPLL to save power */
2861 brcms_b_core_phypll_ctl(wlc_hw, false);
2863 wlc_hw->clk = false;
2864 bcma_core_disable(wlc_hw->d11core, 0);
2865 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2868 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2870 struct brcms_hardware *wlc_hw = wlc->hw;
2873 /* free any posted tx packets */
2874 for (i = 0; i < NFIFO; i++) {
2875 if (wlc_hw->di[i]) {
2876 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2877 if (i < TX_BCMC_FIFO)
2878 ieee80211_wake_queue(wlc->pub->ieee_hw,
2879 brcms_fifo_to_ac(i));
2883 /* free any posted rx packets */
2884 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2888 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2890 struct bcma_device *core = wlc_hw->d11core;
2891 u16 objoff = D11REGOFFS(objdata);
2893 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2894 (void)bcma_read32(core, D11REGOFFS(objaddr));
2898 return bcma_read16(core, objoff);
2902 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2905 struct bcma_device *core = wlc_hw->d11core;
2906 u16 objoff = D11REGOFFS(objdata);
2908 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2909 (void)bcma_read32(core, D11REGOFFS(objaddr));
2913 bcma_wflush16(core, objoff, v);
2917 * Read a single u16 from shared memory.
2918 * SHM 'offset' needs to be an even address
2920 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2922 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2926 * Write a single u16 to shared memory.
2927 * SHM 'offset' needs to be an even address
2929 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2931 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2935 * Copy a buffer to shared memory of specified type .
2936 * SHM 'offset' needs to be an even address and
2937 * Buffer length 'len' must be an even number of bytes
2938 * 'sel' selects the type of memory
2941 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2942 const void *buf, int len, u32 sel)
2945 const u8 *p = (const u8 *)buf;
2948 if (len <= 0 || (offset & 1) || (len & 1))
2951 for (i = 0; i < len; i += 2) {
2952 v = p[i] | (p[i + 1] << 8);
2953 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2958 * Copy a piece of shared memory of specified type to a buffer .
2959 * SHM 'offset' needs to be an even address and
2960 * Buffer length 'len' must be an even number of bytes
2961 * 'sel' selects the type of memory
2964 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2971 if (len <= 0 || (offset & 1) || (len & 1))
2974 for (i = 0; i < len; i += 2) {
2975 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2977 p[i + 1] = (v >> 8) & 0xFF;
2981 /* Copy a buffer to shared memory.
2982 * SHM 'offset' needs to be an even address and
2983 * Buffer length 'len' must be an even number of bytes
2985 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2986 const void *buf, int len)
2988 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2991 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2997 /* write retry limit to SCR, shouldn't need to suspend */
2999 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3000 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3001 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3002 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3003 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3004 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3005 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3006 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3010 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3013 if (mboolisset(wlc_hw->pllreq, req_bit))
3016 mboolset(wlc_hw->pllreq, req_bit);
3018 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3020 brcms_b_xtal(wlc_hw, ON);
3023 if (!mboolisset(wlc_hw->pllreq, req_bit))
3026 mboolclr(wlc_hw->pllreq, req_bit);
3028 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3030 brcms_b_xtal(wlc_hw, OFF);
3035 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3037 wlc_hw->antsel_avail = antsel_avail;
3041 * conditions under which the PM bit should be set in outgoing frames
3042 * and STAY_AWAKE is meaningful
3044 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3046 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3048 /* disallow PS when one of the following global conditions meets */
3049 if (!wlc->pub->associated)
3052 /* disallow PS when one of these meets when not scanning */
3053 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3056 if (cfg->associated) {
3058 * disallow PS when one of the following
3059 * bsscfg specific conditions meets
3070 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3073 struct macstat macstats;
3080 /* if driver down, make no sense to update stats */
3085 /* save last rx fifo 0 overflow count */
3086 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3088 /* save last tx fifo underflow count */
3089 for (i = 0; i < NFIFO; i++)
3090 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3093 /* Read mac stats from contiguous shared memory */
3094 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3095 sizeof(struct macstat), OBJADDR_SHM_SEL);
3098 /* check for rx fifo 0 overflow */
3099 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3101 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3102 wlc->pub->unit, delta);
3104 /* check for tx fifo underflows */
3105 for (i = 0; i < NFIFO; i++) {
3107 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3110 brcms_err(wlc->hw->d11core,
3111 "wl%d: %u tx fifo %d underflows!\n",
3112 wlc->pub->unit, delta, i);
3116 /* merge counters from dma module */
3117 for (i = 0; i < NFIFO; i++) {
3119 dma_counterreset(wlc->hw->di[i]);
3123 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3125 /* reset the core */
3126 if (!brcms_deviceremoved(wlc_hw->wlc))
3127 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3129 /* purge the dma rings */
3130 brcms_c_flushqueues(wlc_hw->wlc);
3133 void brcms_c_reset(struct brcms_c_info *wlc)
3135 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3137 /* slurp up hw mac counters before core reset */
3138 brcms_c_statsupd(wlc);
3140 /* reset our snapshot of macstat counters */
3141 memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3143 brcms_b_reset(wlc->hw);
3146 void brcms_c_init_scb(struct scb *scb)
3150 memset(scb, 0, sizeof(struct scb));
3151 scb->flags = SCB_WMECAP | SCB_HTCAP;
3152 for (i = 0; i < NUMPRIO; i++) {
3154 scb->seqctl[i] = 0xFFFF;
3157 scb->seqctl_nonqos = 0xFFFF;
3158 scb->magic = SCB_MAGIC;
3163 * download ucode/PCM
3164 * let ucode run to suspended
3165 * download ucode inits
3166 * config other core registers
3169 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3171 struct brcms_hardware *wlc_hw = wlc->hw;
3172 struct bcma_device *core = wlc_hw->d11core;
3176 bool fifosz_fixup = false;
3179 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3181 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3184 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3186 brcms_ucode_download(wlc_hw);
3188 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3190 fifosz_fixup = true;
3192 /* let the PSM run to the suspended state, set mode to BSS STA */
3193 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3194 brcms_b_mctrl(wlc_hw, ~0,
3195 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3197 /* wait for ucode to self-suspend after auto-init */
3198 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3199 MI_MACSSPNDD) == 0), 1000 * 1000);
3200 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3201 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3202 "suspend!\n", wlc_hw->unit);
3204 brcms_c_gpio_init(wlc);
3206 sflags = bcma_aread32(core, BCMA_IOST);
3208 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3209 if (BRCMS_ISNPHY(wlc_hw->band))
3210 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3212 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3213 " %d\n", __func__, wlc_hw->unit,
3215 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3216 if (BRCMS_ISLCNPHY(wlc_hw->band))
3217 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3219 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3220 " %d\n", __func__, wlc_hw->unit,
3223 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3224 __func__, wlc_hw->unit, wlc_hw->corerev);
3227 /* For old ucode, txfifo sizes needs to be modified(increased) */
3229 brcms_b_corerev_fifofixup(wlc_hw);
3231 /* check txfifo allocations match between ucode and driver */
3232 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3233 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3237 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3238 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3242 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3243 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3244 buf[TX_AC_BK_FIFO] &= 0xff;
3245 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3249 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3253 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3254 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3255 buf[TX_BCMC_FIFO] &= 0xff;
3256 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3260 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3265 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3266 " driver size %d index %d\n", buf[i],
3267 wlc_hw->xmtfifo_sz[i], i);
3269 /* make sure we can still talk to the mac */
3270 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3272 /* band-specific inits done by wlc_bsinit() */
3274 /* Set up frame burst size and antenna swap threshold init values */
3275 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3276 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3278 /* enable one rx interrupt per received frame */
3279 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3281 /* set the station mode (BSS STA) */
3282 brcms_b_mctrl(wlc_hw,
3283 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3284 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3286 /* set up Beacon interval */
3287 bcnint_us = 0x8000 << 10;
3288 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3289 (bcnint_us << CFPREP_CBI_SHIFT));
3290 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3291 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3293 /* write interrupt mask */
3294 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3297 /* allow the MAC to control the PHY clock (dynamic on/off) */
3298 brcms_b_macphyclk_set(wlc_hw, ON);
3300 /* program dynamic clock control fast powerup delay register */
3301 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3302 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3304 /* tell the ucode the corerev */
3305 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3307 /* tell the ucode MAC capabilities */
3308 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3309 (u16) (wlc_hw->machwcap & 0xffff));
3310 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3312 machwcap >> 16) & 0xffff));
3314 /* write retry limits to SCR, this done after PSM init */
3315 bcma_write32(core, D11REGOFFS(objaddr),
3316 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3317 (void)bcma_read32(core, D11REGOFFS(objaddr));
3318 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3319 bcma_write32(core, D11REGOFFS(objaddr),
3320 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3321 (void)bcma_read32(core, D11REGOFFS(objaddr));
3322 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3324 /* write rate fallback retry limits */
3325 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3326 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3328 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3329 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3331 /* init the tx dma engines */
3332 for (i = 0; i < NFIFO; i++) {
3334 dma_txinit(wlc_hw->di[i]);
3337 /* init the rx dma engine(s) and post receive buffers */
3338 dma_rxinit(wlc_hw->di[RX_FIFO]);
3339 dma_rxfill(wlc_hw->di[RX_FIFO]);
3343 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3346 struct brcms_c_info *wlc = wlc_hw->wlc;
3348 /* request FAST clock if not on */
3349 fastclk = wlc_hw->forcefastclk;
3351 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3353 /* disable interrupts */
3354 macintmask = brcms_intrsoff(wlc->wl);
3356 /* set up the specified band and chanspec */
3357 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3358 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3360 /* do one-time phy inits and calibration */
3361 wlc_phy_cal_init(wlc_hw->band->pi);
3363 /* core-specific initialization */
3364 brcms_b_coreinit(wlc);
3366 /* band-specific inits */
3367 brcms_b_bsinit(wlc, chanspec);
3369 /* restore macintmask */
3370 brcms_intrsrestore(wlc->wl, macintmask);
3372 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3373 * is suspended and brcms_c_enable_mac() will clear this override bit.
3375 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3378 * initialize mac_suspend_depth to 1 to match ucode
3379 * initial suspended state
3381 wlc_hw->mac_suspend_depth = 1;
3383 /* restore the clk */
3385 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3388 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3391 /* Save our copy of the chanspec */
3392 wlc->chanspec = chanspec;
3394 /* Set the chanspec and power limits for this locale */
3395 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3397 if (wlc->stf->ss_algosel_auto)
3398 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3401 brcms_c_stf_ss_update(wlc, wlc->band);
3405 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3407 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3408 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3409 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3410 brcms_chspec_bw(wlc->default_bss->chanspec),
3411 wlc->stf->txstreams);
3414 /* derive wlc->band->basic_rate[] table from 'rateset' */
3415 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3416 struct brcms_c_rateset *rateset)
3422 u8 *br = wlc->band->basic_rate;
3425 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3426 memset(br, 0, BRCM_MAXRATE + 1);
3428 /* For each basic rate in the rates list, make an entry in the
3429 * best basic lookup.
3431 for (i = 0; i < rateset->count; i++) {
3432 /* only make an entry for a basic rate */
3433 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3436 /* mask off basic bit */
3437 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3439 if (rate > BRCM_MAXRATE) {
3440 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3441 "invalid rate 0x%X in rate set\n",
3449 /* The rate lookup table now has non-zero entries for each
3450 * basic rate, equal to the basic rate: br[basicN] = basicN
3452 * To look up the best basic rate corresponding to any
3453 * particular rate, code can use the basic_rate table
3456 * basic_rate = wlc->band->basic_rate[tx_rate]
3458 * Make sure there is a best basic rate entry for
3459 * every rate by walking up the table from low rates
3460 * to high, filling in holes in the lookup table
3463 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3464 rate = wlc->band->hw_rateset.rates[i];
3466 if (br[rate] != 0) {
3467 /* This rate is a basic rate.
3468 * Keep track of the best basic rate so far by
3471 if (is_ofdm_rate(rate))
3479 /* This rate is not a basic rate so figure out the
3480 * best basic rate less than this rate and fill in
3481 * the hole in the table
3484 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3489 if (is_ofdm_rate(rate)) {
3491 * In 11g and 11a, the OFDM mandatory rates
3492 * are 6, 12, and 24 Mbps
3494 if (rate >= BRCM_RATE_24M)
3495 mandatory = BRCM_RATE_24M;
3496 else if (rate >= BRCM_RATE_12M)
3497 mandatory = BRCM_RATE_12M;
3499 mandatory = BRCM_RATE_6M;
3501 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3505 br[rate] = mandatory;
3509 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3512 struct brcms_c_rateset default_rateset;
3514 uint i, band_order[2];
3517 * We might have been bandlocked during down and the chip
3518 * power-cycled (hibernate). Figure out the right band to park on
3520 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3521 /* updated in brcms_c_bandlock() */
3522 parkband = wlc->band->bandunit;
3523 band_order[0] = band_order[1] = parkband;
3525 /* park on the band of the specified chanspec */
3526 parkband = chspec_bandunit(chanspec);
3528 /* order so that parkband initialize last */
3529 band_order[0] = parkband ^ 1;
3530 band_order[1] = parkband;
3533 /* make each band operational, software state init */
3534 for (i = 0; i < wlc->pub->_nbands; i++) {
3535 uint j = band_order[i];
3537 wlc->band = wlc->bandstate[j];
3539 brcms_default_rateset(wlc, &default_rateset);
3541 /* fill in hw_rate */
3542 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3543 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3544 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3546 /* init basic rate lookup */
3547 brcms_c_rate_lookup_init(wlc, &default_rateset);
3550 /* sync up phy/radio chanspec */
3551 brcms_c_set_phy_chanspec(wlc, chanspec);
3555 * Set or clear filtering related maccontrol bits based on
3556 * specified filter flags
3558 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3560 u32 promisc_bits = 0;
3562 wlc->filter_flags = filter_flags;
3564 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3565 promisc_bits |= MCTL_PROMISC;
3567 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3568 promisc_bits |= MCTL_BCNS_PROMISC;
3570 if (filter_flags & FIF_FCSFAIL)
3571 promisc_bits |= MCTL_KEEPBADFCS;
3573 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3574 promisc_bits |= MCTL_KEEPCONTROL;
3576 brcms_b_mctrl(wlc->hw,
3577 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3578 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3583 * ucode, hwmac update
3584 * Channel dependent updates for ucode and hw
3586 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3588 /* enable or disable any active IBSSs depending on whether or not
3589 * we are on the home channel
3591 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3592 if (wlc->pub->associated) {
3594 * BMAC_NOTE: This is something that should be fixed
3595 * in ucode inits. I think that the ucode inits set
3596 * up the bcn templates and shm values with a bogus
3597 * beacon. This should not be done in the inits. If
3598 * ucode needs to set up a beacon for testing, the
3599 * test routines should write it down, not expect the
3600 * inits to populate a bogus beacon.
3602 if (BRCMS_PHY_11N_CAP(wlc->band))
3603 brcms_b_write_shm(wlc->hw,
3604 M_BCN_TXTSF_OFFSET, 0);
3607 /* disable an active IBSS if we are not on the home channel */
3611 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3615 u8 basic_phy_rate, basic_index;
3616 u16 dir_table, basic_table;
3619 /* Shared memory address for the table we are reading */
3620 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3622 /* Shared memory address for the table we are writing */
3623 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3626 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3627 * the index into the rate table.
3629 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3630 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3631 index = phy_rate & 0xf;
3632 basic_index = basic_phy_rate & 0xf;
3634 /* Find the SHM pointer to the ACK rate entry by looking in the
3637 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3639 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3640 * to the correct basic rate for the given incoming rate
3642 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3645 static const struct brcms_c_rateset *
3646 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3648 const struct brcms_c_rateset *rs_dflt;
3650 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3651 if (wlc->band->bandtype == BRCM_BAND_5G)
3652 rs_dflt = &ofdm_mimo_rates;
3654 rs_dflt = &cck_ofdm_mimo_rates;
3655 } else if (wlc->band->gmode)
3656 rs_dflt = &cck_ofdm_rates;
3658 rs_dflt = &cck_rates;
3663 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3665 const struct brcms_c_rateset *rs_dflt;
3666 struct brcms_c_rateset rs;
3667 u8 rate, basic_rate;
3670 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3672 brcms_c_rateset_copy(rs_dflt, &rs);
3673 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3675 /* walk the phy rate table and update SHM basic rate lookup table */
3676 for (i = 0; i < rs.count; i++) {
3677 rate = rs.rates[i] & BRCMS_RATE_MASK;
3679 /* for a given rate brcms_basic_rate returns the rate at
3680 * which a response ACK/CTS should be sent.
3682 basic_rate = brcms_basic_rate(wlc, rate);
3683 if (basic_rate == 0)
3684 /* This should only happen if we are using a
3685 * restricted rateset.
3687 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3689 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3693 /* band-specific init */
3694 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3696 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3697 wlc->pub->unit, wlc->band->bandunit);
3699 /* write ucode ACK/CTS rate table */
3700 brcms_c_set_ratetable(wlc);
3702 /* update some band specific mac configuration */
3703 brcms_c_ucode_mac_upd(wlc);
3705 /* init antenna selection */
3706 brcms_c_antsel_init(wlc->asi);
3710 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3712 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3715 int idle_busy_ratio_x_16 = 0;
3717 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3718 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3719 if (duty_cycle > 100 || duty_cycle < 0) {
3720 brcms_err(wlc->hw->d11core,
3721 "wl%d: duty cycle value off limit\n",
3726 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3727 /* Only write to shared memory when wl is up */
3729 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3732 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3734 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3739 /* push sw hps and wake state through hardware */
3740 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3746 hps = brcms_c_ps_allowed(wlc);
3748 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3751 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3756 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3758 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3761 brcms_b_wait_for_wake(wlc->hw);
3765 * Write this BSS config's MAC address to core.
3766 * Updates RXE match engine.
3768 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3771 struct brcms_c_info *wlc = bsscfg->wlc;
3773 /* enter the MAC addr into the RXE match registers */
3774 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3776 brcms_c_ampdu_macaddr_upd(wlc);
3781 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3782 * Updates RXE match engine.
3784 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3786 /* we need to update BSSID in RXE match registers */
3787 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3790 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3792 wlc_hw->shortslot = shortslot;
3794 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3795 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3796 brcms_b_update_slot_timing(wlc_hw, shortslot);
3797 brcms_c_enable_mac(wlc_hw->wlc);
3802 * Suspend the the MAC and update the slot timing
3803 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3805 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3807 /* use the override if it is set */
3808 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3809 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3811 if (wlc->shortslot == shortslot)
3814 wlc->shortslot = shortslot;
3816 brcms_b_set_shortslot(wlc->hw, shortslot);
3819 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3821 if (wlc->home_chanspec != chanspec) {
3822 wlc->home_chanspec = chanspec;
3824 if (wlc->bsscfg->associated)
3825 wlc->bsscfg->current_bss->chanspec = chanspec;
3830 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3831 bool mute_tx, struct txpwr_limits *txpwr)
3835 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3838 wlc_hw->chanspec = chanspec;
3840 /* Switch bands if necessary */
3841 if (wlc_hw->_nbands > 1) {
3842 bandunit = chspec_bandunit(chanspec);
3843 if (wlc_hw->band->bandunit != bandunit) {
3844 /* brcms_b_setband disables other bandunit,
3845 * use light band switch if not up yet
3848 wlc_phy_chanspec_radio_set(wlc_hw->
3849 bandstate[bandunit]->
3851 brcms_b_setband(wlc_hw, bandunit, chanspec);
3853 brcms_c_setxband(wlc_hw, bandunit);
3858 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3862 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3864 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3866 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3867 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3869 /* Update muting of the channel */
3870 brcms_b_mute(wlc_hw, mute_tx);
3874 /* switch to and initialize new band */
3875 static void brcms_c_setband(struct brcms_c_info *wlc,
3878 wlc->band = wlc->bandstate[bandunit];
3883 /* wait for at least one beacon before entering sleeping state */
3884 brcms_c_set_ps_ctrl(wlc);
3886 /* band-specific initializations */
3887 brcms_c_bsinit(wlc);
3890 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3893 bool switchband = false;
3894 u16 old_chanspec = wlc->chanspec;
3896 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3897 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3898 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3902 /* Switch bands if necessary */
3903 if (wlc->pub->_nbands > 1) {
3904 bandunit = chspec_bandunit(chanspec);
3905 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3907 if (wlc->bandlocked) {
3908 brcms_err(wlc->hw->d11core,
3909 "wl%d: %s: chspec %d band is locked!\n",
3910 wlc->pub->unit, __func__,
3911 CHSPEC_CHANNEL(chanspec));
3915 * should the setband call come after the
3916 * brcms_b_chanspec() ? if the setband updates
3917 * (brcms_c_bsinit) use low level calls to inspect and
3918 * set state, the state inspected may be from the wrong
3919 * band, or the following brcms_b_set_chanspec() may
3922 brcms_c_setband(wlc, bandunit);
3926 /* sync up phy/radio chanspec */
3927 brcms_c_set_phy_chanspec(wlc, chanspec);
3929 /* init antenna selection */
3930 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3931 brcms_c_antsel_init(wlc->asi);
3933 /* Fix the hardware rateset based on bw.
3934 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3936 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3937 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3940 /* update some mac configuration since chanspec changed */
3941 brcms_c_ucode_mac_upd(wlc);
3945 * This function changes the phytxctl for beacon based on current
3946 * beacon ratespec AND txant setting as per this table:
3947 * ratespec CCK ant = wlc->stf->txant
3950 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3954 u16 phytxant = wlc->stf->phytxant;
3955 u16 mask = PHY_TXC_ANT_MASK;
3957 /* for non-siso rates or default setting, use the available chains */
3958 if (BRCMS_PHY_11N_CAP(wlc->band))
3959 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3961 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3962 phyctl = (phyctl & ~mask) | phytxant;
3963 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3967 * centralized protection config change function to simplify debugging, no
3968 * consistency checking this should be called only on changes to avoid overhead
3969 * in periodic function
3971 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3974 * Cannot use brcms_dbg_* here because this function is called
3975 * before wlc is sufficiently initialized.
3977 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3980 case BRCMS_PROT_G_SPEC:
3981 wlc->protection->_g = (bool) val;
3983 case BRCMS_PROT_G_OVR:
3984 wlc->protection->g_override = (s8) val;
3986 case BRCMS_PROT_G_USER:
3987 wlc->protection->gmode_user = (u8) val;
3989 case BRCMS_PROT_OVERLAP:
3990 wlc->protection->overlap = (s8) val;
3992 case BRCMS_PROT_N_USER:
3993 wlc->protection->nmode_user = (s8) val;
3995 case BRCMS_PROT_N_CFG:
3996 wlc->protection->n_cfg = (s8) val;
3998 case BRCMS_PROT_N_CFG_OVR:
3999 wlc->protection->n_cfg_override = (s8) val;
4001 case BRCMS_PROT_N_NONGF:
4002 wlc->protection->nongf = (bool) val;
4004 case BRCMS_PROT_N_NONGF_OVR:
4005 wlc->protection->nongf_override = (s8) val;
4007 case BRCMS_PROT_N_PAM_OVR:
4008 wlc->protection->n_pam_override = (s8) val;
4010 case BRCMS_PROT_N_OBSS:
4011 wlc->protection->n_obss = (bool) val;
4020 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4023 brcms_c_update_beacon(wlc);
4024 brcms_c_update_probe_resp(wlc, true);
4028 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4030 wlc->stf->ldpc = val;
4033 brcms_c_update_beacon(wlc);
4034 brcms_c_update_probe_resp(wlc, true);
4035 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4039 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4040 const struct ieee80211_tx_queue_params *params,
4044 struct shm_acparams acp_shm;
4047 /* Only apply params if the core is out of reset and has clocks */
4049 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4050 wlc->pub->unit, __func__);
4054 memset(&acp_shm, 0, sizeof(struct shm_acparams));
4055 /* fill in shm ac params struct */
4056 acp_shm.txop = params->txop;
4057 /* convert from units of 32us to us for ucode */
4058 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4059 EDCF_TXOP2USEC(acp_shm.txop);
4060 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4062 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4063 && acp_shm.aifs < EDCF_AIFSN_MAX)
4066 if (acp_shm.aifs < EDCF_AIFSN_MIN
4067 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4068 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4069 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4071 acp_shm.cwmin = params->cw_min;
4072 acp_shm.cwmax = params->cw_max;
4073 acp_shm.cwcur = acp_shm.cwmin;
4075 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4077 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4078 /* Indicate the new params to the ucode */
4079 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4082 M_EDCF_STATUS_OFF));
4083 acp_shm.status |= WME_STATUS_NEWAC;
4085 /* Fill in shm acparam table */
4086 shm_entry = (u16 *) &acp_shm;
4087 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4088 brcms_b_write_shm(wlc->hw,
4090 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4095 brcms_c_suspend_mac_and_wait(wlc);
4096 brcms_c_enable_mac(wlc);
4100 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4104 struct ieee80211_tx_queue_params txq_pars;
4105 static const struct edcf_acparam default_edcf_acparams[] = {
4106 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4107 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4108 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4109 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4110 }; /* ucode needs these parameters during its initialization */
4111 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4113 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4114 /* find out which ac this set of params applies to */
4115 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4117 /* fill in shm ac params struct */
4118 txq_pars.txop = edcf_acp->TXOP;
4119 txq_pars.aifs = edcf_acp->ACI;
4121 /* CWmin = 2^(ECWmin) - 1 */
4122 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4123 /* CWmax = 2^(ECWmax) - 1 */
4124 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4125 >> EDCF_ECWMAX_SHIFT);
4126 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4130 brcms_c_suspend_mac_and_wait(wlc);
4131 brcms_c_enable_mac(wlc);
4135 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4137 /* Don't start the timer if HWRADIO feature is disabled */
4138 if (wlc->radio_monitor)
4141 wlc->radio_monitor = true;
4142 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4143 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4146 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4148 if (!wlc->radio_monitor)
4151 wlc->radio_monitor = false;
4152 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4153 return brcms_del_timer(wlc->radio_timer);
4156 /* read hwdisable state and propagate to wlc flag */
4157 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4159 if (wlc->pub->hw_off)
4162 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4163 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4165 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4168 /* update hwradio status and return it */
4169 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4171 brcms_c_radio_hwdisable_upd(wlc);
4173 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4177 /* periodical query hw radio button while driver is "down" */
4178 static void brcms_c_radio_timer(void *arg)
4180 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4182 if (brcms_deviceremoved(wlc)) {
4183 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4184 wlc->pub->unit, __func__);
4185 brcms_down(wlc->wl);
4189 brcms_c_radio_hwdisable_upd(wlc);
4192 /* common low-level watchdog code */
4193 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4195 struct brcms_hardware *wlc_hw = wlc->hw;
4200 /* increment second count */
4203 /* Check for FIFO error interrupts */
4204 brcms_b_fifoerrors(wlc_hw);
4206 /* make sure RX dma has buffers */
4207 dma_rxfill(wlc->hw->di[RX_FIFO]);
4209 wlc_phy_watchdog(wlc_hw->band->pi);
4212 /* common watchdog code */
4213 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4215 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4220 if (brcms_deviceremoved(wlc)) {
4221 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4222 wlc->pub->unit, __func__);
4223 brcms_down(wlc->wl);
4227 /* increment second count */
4230 brcms_c_radio_hwdisable_upd(wlc);
4231 /* if radio is disable, driver may be down, quit here */
4232 if (wlc->pub->radio_disabled)
4235 brcms_b_watchdog(wlc);
4238 * occasionally sample mac stat counters to
4239 * detect 16-bit counter wrap
4241 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4242 brcms_c_statsupd(wlc);
4244 if (BRCMS_ISNPHY(wlc->band) &&
4245 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4246 BRCMS_TEMPSENSE_PERIOD)) {
4247 wlc->tempsense_lasttime = wlc->pub->now;
4248 brcms_c_tempsense_upd(wlc);
4252 static void brcms_c_watchdog_by_timer(void *arg)
4254 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4256 brcms_c_watchdog(wlc);
4259 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4261 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4263 if (!wlc->wdtimer) {
4264 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4269 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4271 if (!wlc->radio_timer) {
4272 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4284 * Initialize brcms_c_info default values ...
4285 * may get overrides later in this function
4287 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4291 /* Save our copy of the chanspec */
4292 wlc->chanspec = ch20mhz_chspec(1);
4294 /* various 802.11g modes */
4295 wlc->shortslot = false;
4296 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4298 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4299 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4301 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4302 BRCMS_PROTECTION_AUTO);
4303 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4304 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4305 BRCMS_PROTECTION_AUTO);
4306 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4307 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4309 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4310 BRCMS_PROTECTION_CTL_OVERLAP);
4312 /* 802.11g draft 4.0 NonERP elt advertisement */
4313 wlc->include_legacy_erp = true;
4315 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4316 wlc->stf->txant = ANT_TX_DEF;
4318 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4320 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4321 for (i = 0; i < NFIFO; i++)
4322 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4323 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4325 /* default rate fallback retry limits */
4326 wlc->SFBL = RETRY_SHORT_FB;
4327 wlc->LFBL = RETRY_LONG_FB;
4329 /* default mac retry limits */
4330 wlc->SRL = RETRY_SHORT_DEF;
4331 wlc->LRL = RETRY_LONG_DEF;
4333 /* WME QoS mode is Auto by default */
4334 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4335 wlc->pub->bcmerror = 0;
4338 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4342 unit = wlc->pub->unit;
4344 wlc->asi = brcms_c_antsel_attach(wlc);
4345 if (wlc->asi == NULL) {
4346 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4352 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4353 if (wlc->ampdu == NULL) {
4354 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4360 if ((brcms_c_stf_attach(wlc) != 0)) {
4361 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4370 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4376 * run backplane attach, init nvram
4378 * initialize software state for each core and band
4379 * put the whole chip in reset(driver down state), no clock
4381 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4382 uint unit, bool piomode)
4384 struct brcms_hardware *wlc_hw;
4388 struct shared_phy_params sha_params;
4389 struct wiphy *wiphy = wlc->wiphy;
4390 struct pci_dev *pcidev = core->bus->host_pci;
4391 struct ssb_sprom *sprom = &core->bus->sprom;
4393 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4394 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4398 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4399 core->bus->boardinfo.vendor,
4400 core->bus->boardinfo.type);
4406 wlc_hw->unit = unit;
4407 wlc_hw->band = wlc_hw->bandstate[0];
4408 wlc_hw->_piomode = piomode;
4410 /* populate struct brcms_hardware with default values */
4411 brcms_b_info_init(wlc_hw);
4414 * Do the hardware portion of the attach. Also initialize software
4415 * state that depends on the particular hardware we are running.
4417 wlc_hw->sih = ai_attach(core->bus);
4418 if (wlc_hw->sih == NULL) {
4419 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4425 /* verify again the device is supported */
4426 if (!brcms_c_chipmatch(core)) {
4427 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4433 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4434 wlc_hw->vendorid = pcidev->vendor;
4435 wlc_hw->deviceid = pcidev->device;
4437 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4438 wlc_hw->deviceid = core->bus->boardinfo.type;
4441 wlc_hw->d11core = core;
4442 wlc_hw->corerev = core->id.rev;
4444 /* validate chip, chiprev and corerev */
4445 if (!brcms_c_isgoodchip(wlc_hw)) {
4450 /* initialize power control registers */
4451 ai_clkctl_init(wlc_hw->sih);
4453 /* request fastclock and force fastclock for the rest of attach
4454 * bring the d11 core out of reset.
4455 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4456 * is still false; But it will be called again inside wlc_corereset,
4457 * after d11 is out of reset.
4459 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4460 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4462 if (!brcms_b_validate_chip_access(wlc_hw)) {
4463 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4469 /* get the board rev, used just below */
4470 j = sprom->board_rev;
4471 /* promote srom boardrev of 0xFF to 1 */
4472 if (j == BOARDREV_PROMOTABLE)
4473 j = BOARDREV_PROMOTED;
4474 wlc_hw->boardrev = (u16) j;
4475 if (!brcms_c_validboardtype(wlc_hw)) {
4476 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4477 "board type (0x%x)" " or revision level (0x%x)\n",
4478 unit, ai_get_boardtype(wlc_hw->sih),
4483 wlc_hw->sromrev = sprom->revision;
4484 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4485 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4487 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4488 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4490 /* check device id(srom, nvram etc.) to set bands */
4491 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4492 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4493 wlc_hw->deviceid == BCM43224_CHIP_ID)
4494 /* Dualband boards */
4495 wlc_hw->_nbands = 2;
4497 wlc_hw->_nbands = 1;
4499 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4500 wlc_hw->_nbands = 1;
4502 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4503 * unconditionally does the init of these values
4505 wlc->vendorid = wlc_hw->vendorid;
4506 wlc->deviceid = wlc_hw->deviceid;
4507 wlc->pub->sih = wlc_hw->sih;
4508 wlc->pub->corerev = wlc_hw->corerev;
4509 wlc->pub->sromrev = wlc_hw->sromrev;
4510 wlc->pub->boardrev = wlc_hw->boardrev;
4511 wlc->pub->boardflags = wlc_hw->boardflags;
4512 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4513 wlc->pub->_nbands = wlc_hw->_nbands;
4515 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4517 if (wlc_hw->physhim == NULL) {
4518 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4524 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4525 sha_params.sih = wlc_hw->sih;
4526 sha_params.physhim = wlc_hw->physhim;
4527 sha_params.unit = unit;
4528 sha_params.corerev = wlc_hw->corerev;
4529 sha_params.vid = wlc_hw->vendorid;
4530 sha_params.did = wlc_hw->deviceid;
4531 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4532 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4533 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4534 sha_params.sromrev = wlc_hw->sromrev;
4535 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4536 sha_params.boardrev = wlc_hw->boardrev;
4537 sha_params.boardflags = wlc_hw->boardflags;
4538 sha_params.boardflags2 = wlc_hw->boardflags2;
4540 /* alloc and save pointer to shared phy state area */
4541 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4542 if (!wlc_hw->phy_sh) {
4547 /* initialize software state for each core and band */
4548 for (j = 0; j < wlc_hw->_nbands; j++) {
4550 * band0 is always 2.4Ghz
4551 * band1, if present, is 5Ghz
4554 brcms_c_setxband(wlc_hw, j);
4556 wlc_hw->band->bandunit = j;
4557 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4558 wlc->band->bandunit = j;
4559 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4560 wlc->core->coreidx = core->core_index;
4562 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4563 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4565 /* init tx fifo size */
4566 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4567 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4568 ARRAY_SIZE(xmtfifo_sz));
4569 wlc_hw->xmtfifo_sz =
4570 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4571 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4573 /* Get a phy for this band */
4575 wlc_phy_attach(wlc_hw->phy_sh, core,
4576 wlc_hw->band->bandtype,
4578 if (wlc_hw->band->pi == NULL) {
4579 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4580 "attach failed\n", unit);
4585 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4587 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4588 &wlc_hw->band->phyrev,
4589 &wlc_hw->band->radioid,
4590 &wlc_hw->band->radiorev);
4591 wlc_hw->band->abgphy_encore =
4592 wlc_phy_get_encore(wlc_hw->band->pi);
4593 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4594 wlc_hw->band->core_flags =
4595 wlc_phy_get_coreflags(wlc_hw->band->pi);
4597 /* verify good phy_type & supported phy revision */
4598 if (BRCMS_ISNPHY(wlc_hw->band)) {
4599 if (NCONF_HAS(wlc_hw->band->phyrev))
4603 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4604 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4610 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4611 "phy type/rev (%d/%d)\n", unit,
4612 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4619 * BMAC_NOTE: wlc->band->pi should not be set below and should
4620 * be done in the high level attach. However we can not make
4621 * that change until all low level access is changed to
4622 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4623 * keeping wlc_hw->band->pi as well for incremental update of
4624 * low level fns, and cut over low only init when all fns
4627 wlc->band->pi = wlc_hw->band->pi;
4628 wlc->band->phytype = wlc_hw->band->phytype;
4629 wlc->band->phyrev = wlc_hw->band->phyrev;
4630 wlc->band->radioid = wlc_hw->band->radioid;
4631 wlc->band->radiorev = wlc_hw->band->radiorev;
4633 /* default contention windows size limits */
4634 wlc_hw->band->CWmin = APHY_CWMIN;
4635 wlc_hw->band->CWmax = PHY_CWMAX;
4637 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4643 /* disable core to match driver "down" state */
4644 brcms_c_coredisable(wlc_hw);
4646 /* Match driver "down" state */
4647 ai_pci_down(wlc_hw->sih);
4649 /* turn off pll and xtal to match driver "down" state */
4650 brcms_b_xtal(wlc_hw, OFF);
4652 /* *******************************************************************
4653 * The hardware is in the DOWN state at this point. D11 core
4654 * or cores are in reset with clocks off, and the board PLLs
4655 * are off if possible.
4657 * Beyond this point, wlc->sbclk == false and chip registers
4658 * should not be touched.
4659 *********************************************************************
4662 /* init etheraddr state variables */
4663 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4665 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4666 is_zero_ether_addr(wlc_hw->etheraddr)) {
4667 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4673 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4674 wlc_hw->deviceid, wlc_hw->_nbands,
4675 ai_get_boardtype(wlc_hw->sih));
4680 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4685 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4688 unit = wlc->pub->unit;
4690 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4691 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4692 wlc->band->antgain = 8;
4693 } else if (wlc->band->antgain == -1) {
4694 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4695 " srom, using 2dB\n", unit, __func__);
4696 wlc->band->antgain = 8;
4699 /* Older sroms specified gain in whole dbm only. In order
4700 * be able to specify qdbm granularity and remain backward
4701 * compatible the whole dbms are now encoded in only
4702 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4703 * 6 bit signed number ranges from -32 - 31.
4707 * 0xc1 = 1.75 db (1 + 3 quarters),
4708 * 0x3f = -1 (-1 + 0 quarters),
4709 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4710 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4712 gain = wlc->band->antgain & 0x3f;
4713 gain <<= 2; /* Sign extend */
4715 fract = (wlc->band->antgain & 0xc0) >> 6;
4716 wlc->band->antgain = 4 * gain + fract;
4720 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4725 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4727 unit = wlc->pub->unit;
4728 bandtype = wlc->band->bandtype;
4730 /* get antennas available */
4731 if (bandtype == BRCM_BAND_5G)
4732 aa = sprom->ant_available_a;
4734 aa = sprom->ant_available_bg;
4736 if ((aa < 1) || (aa > 15)) {
4737 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4738 " srom (0x%x), using 3\n", unit, __func__, aa);
4742 /* reset the defaults if we have a single antenna */
4744 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4745 wlc->stf->txant = ANT_TX_FORCE_0;
4746 } else if (aa == 2) {
4747 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4748 wlc->stf->txant = ANT_TX_FORCE_1;
4752 /* Compute Antenna Gain */
4753 if (bandtype == BRCM_BAND_5G)
4754 wlc->band->antgain = sprom->antenna_gain.a1;
4756 wlc->band->antgain = sprom->antenna_gain.a0;
4758 brcms_c_attach_antgain_init(wlc);
4763 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4766 struct brcms_band *band;
4767 struct brcms_bss_info *bi = wlc->default_bss;
4769 /* init default and target BSS with some sane initial values */
4770 memset(bi, 0, sizeof(*bi));
4771 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4773 /* fill the default channel as the first valid channel
4774 * starting from the 2G channels
4776 chanspec = ch20mhz_chspec(1);
4777 wlc->home_chanspec = bi->chanspec = chanspec;
4779 /* find the band of our default channel */
4781 if (wlc->pub->_nbands > 1 &&
4782 band->bandunit != chspec_bandunit(chanspec))
4783 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4785 /* init bss rates to the band specific default rate set */
4786 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4787 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4788 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4789 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4791 if (wlc->pub->_n_enab & SUPPORT_11N)
4792 bi->flags |= BRCMS_BSS_HT;
4795 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4798 struct brcms_band *band;
4800 for (i = 0; i < wlc->pub->_nbands; i++) {
4801 band = wlc->bandstate[i];
4802 if (band->bandtype == BRCM_BAND_5G) {
4803 if ((bwcap == BRCMS_N_BW_40ALL)
4804 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4805 band->mimo_cap_40 = true;
4807 band->mimo_cap_40 = false;
4809 if (bwcap == BRCMS_N_BW_40ALL)
4810 band->mimo_cap_40 = true;
4812 band->mimo_cap_40 = false;
4817 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4819 /* free timer state */
4821 brcms_free_timer(wlc->wdtimer);
4822 wlc->wdtimer = NULL;
4824 if (wlc->radio_timer) {
4825 brcms_free_timer(wlc->radio_timer);
4826 wlc->radio_timer = NULL;
4830 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4833 brcms_c_antsel_detach(wlc->asi);
4838 brcms_c_ampdu_detach(wlc->ampdu);
4842 brcms_c_stf_detach(wlc);
4848 static int brcms_b_detach(struct brcms_c_info *wlc)
4851 struct brcms_hw_band *band;
4852 struct brcms_hardware *wlc_hw = wlc->hw;
4857 brcms_b_detach_dmapio(wlc_hw);
4859 band = wlc_hw->band;
4860 for (i = 0; i < wlc_hw->_nbands; i++) {
4862 /* Detach this band's phy */
4863 wlc_phy_detach(band->pi);
4866 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4869 /* Free shared phy state */
4870 kfree(wlc_hw->phy_sh);
4872 wlc_phy_shim_detach(wlc_hw->physhim);
4875 ai_detach(wlc_hw->sih);
4884 * Return a count of the number of driver callbacks still pending.
4886 * General policy is that brcms_c_detach can only dealloc/free software states.
4887 * It can NOT touch hardware registers since the d11core may be in reset and
4888 * clock may not be available.
4889 * One exception is sb register access, which is possible if crystal is turned
4890 * on after "down" state, driver should avoid software timer with the exception
4893 uint brcms_c_detach(struct brcms_c_info *wlc)
4900 callbacks += brcms_b_detach(wlc);
4902 /* delete software timers */
4903 if (!brcms_c_radio_monitor_stop(wlc))
4906 brcms_c_channel_mgr_detach(wlc->cmi);
4908 brcms_c_timers_deinit(wlc);
4910 brcms_c_detach_module(wlc);
4912 brcms_c_detach_mfree(wlc);
4916 /* update state that depends on the current value of "ap" */
4917 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4919 /* STA-BSS; short capable */
4920 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4923 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4924 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4926 if (wlc_hw->wlc->pub->hw_up)
4929 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4932 * Enable pll and xtal, initialize the power control registers,
4933 * and force fastclock for the remainder of brcms_c_up().
4935 brcms_b_xtal(wlc_hw, ON);
4936 ai_clkctl_init(wlc_hw->sih);
4937 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4940 * TODO: test suspend/resume
4942 * AI chip doesn't restore bar0win2 on
4943 * hibernation/resume, need sw fixup
4947 * Inform phy that a POR reset has occurred so
4948 * it does a complete phy init
4950 wlc_phy_por_inform(wlc_hw->band->pi);
4952 wlc_hw->ucode_loaded = false;
4953 wlc_hw->wlc->pub->hw_up = true;
4955 if ((wlc_hw->boardflags & BFL_FEM)
4956 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4958 (wlc_hw->boardrev >= 0x1250
4959 && (wlc_hw->boardflags & BFL_FEM_BT)))
4960 ai_epa_4313war(wlc_hw->sih);
4964 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4966 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4969 * Enable pll and xtal, initialize the power control registers,
4970 * and force fastclock for the remainder of brcms_c_up().
4972 brcms_b_xtal(wlc_hw, ON);
4973 ai_clkctl_init(wlc_hw->sih);
4974 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4977 * Configure pci/pcmcia here instead of in brcms_c_attach()
4978 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
4980 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4984 * Need to read the hwradio status here to cover the case where the
4985 * system is loaded with the hw radio disabled. We do not want to
4986 * bring the driver up in this case.
4988 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4989 /* put SB PCI in down state again */
4990 ai_pci_down(wlc_hw->sih);
4991 brcms_b_xtal(wlc_hw, OFF);
4995 ai_pci_up(wlc_hw->sih);
4997 /* reset the d11 core */
4998 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5003 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5006 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5008 /* FULLY enable dynamic power control and d11 core interrupt */
5009 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5010 brcms_intrson(wlc_hw->wlc->wl);
5015 * Write WME tunable parameters for retransmit/max rate
5016 * from wlc struct to ucode
5018 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5022 /* Need clock to do this */
5026 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5027 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5028 wlc->wme_retries[ac]);
5031 /* make interface operational */
5032 int brcms_c_up(struct brcms_c_info *wlc)
5034 struct ieee80211_channel *ch;
5036 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5038 /* HW is turned off so don't try to access it */
5039 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5042 if (!wlc->pub->hw_up) {
5043 brcms_b_hw_up(wlc->hw);
5044 wlc->pub->hw_up = true;
5047 if ((wlc->pub->boardflags & BFL_FEM)
5048 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5049 if (wlc->pub->boardrev >= 0x1250
5050 && (wlc->pub->boardflags & BFL_FEM_BT))
5051 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5052 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5054 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5055 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5059 * Need to read the hwradio status here to cover the case where the
5060 * system is loaded with the hw radio disabled. We do not want to bring
5061 * the driver up in this case. If radio is disabled, abort up, lower
5062 * power, start radio timer and return 0(for NDIS) don't call
5063 * radio_update to avoid looping brcms_c_up.
5065 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5067 if (!wlc->pub->radio_disabled) {
5068 int status = brcms_b_up_prep(wlc->hw);
5069 if (status == -ENOMEDIUM) {
5071 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5072 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5073 mboolset(wlc->pub->radio_disabled,
5074 WL_RADIO_HW_DISABLE);
5076 if (bsscfg->enable && bsscfg->BSS)
5077 brcms_err(wlc->hw->d11core,
5078 "wl%d: up: rfdisable -> "
5079 "bsscfg_disable()\n",
5085 if (wlc->pub->radio_disabled) {
5086 brcms_c_radio_monitor_start(wlc);
5090 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5093 brcms_c_radio_monitor_stop(wlc);
5095 /* Set EDCF hostflags */
5096 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5098 brcms_init(wlc->wl);
5099 wlc->pub->up = true;
5101 if (wlc->bandinit_pending) {
5102 ch = wlc->pub->ieee_hw->conf.channel;
5103 brcms_c_suspend_mac_and_wait(wlc);
5104 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5105 wlc->bandinit_pending = false;
5106 brcms_c_enable_mac(wlc);
5109 brcms_b_up_finish(wlc->hw);
5111 /* Program the TX wme params with the current settings */
5112 brcms_c_wme_retries_write(wlc);
5114 /* start one second watchdog timer */
5115 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5116 wlc->WDarmed = true;
5118 /* ensure antenna config is up to date */
5119 brcms_c_stf_phy_txant_upd(wlc);
5120 /* ensure LDPC config is in sync */
5121 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5126 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5133 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5141 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5143 /* disable interrupts */
5145 wlc_hw->wlc->macintmask = 0;
5147 /* now disable interrupts */
5148 brcms_intrsoff(wlc_hw->wlc->wl);
5150 /* ensure we're running on the pll clock again */
5151 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5153 /* down phy at the last of this stage */
5154 callbacks += wlc_phy_down(wlc_hw->band->pi);
5159 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5168 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5170 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5173 wlc_hw->sbclk = false;
5174 wlc_hw->clk = false;
5175 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5177 /* reclaim any posted packets */
5178 brcms_c_flushqueues(wlc_hw->wlc);
5181 /* Reset and disable the core */
5182 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5183 if (bcma_read32(wlc_hw->d11core,
5184 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5185 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5186 callbacks += brcms_reset(wlc_hw->wlc->wl);
5187 brcms_c_coredisable(wlc_hw);
5190 /* turn off primary xtal and pll */
5191 if (!wlc_hw->noreset) {
5192 ai_pci_down(wlc_hw->sih);
5193 brcms_b_xtal(wlc_hw, OFF);
5201 * Mark the interface nonoperational, stop the software mechanisms,
5202 * disable the hardware, free any transient buffer state.
5203 * Return a count of the number of driver callbacks still pending.
5205 uint brcms_c_down(struct brcms_c_info *wlc)
5210 bool dev_gone = false;
5212 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5214 /* check if we are already in the going down path */
5215 if (wlc->going_down) {
5216 brcms_err(wlc->hw->d11core,
5217 "wl%d: %s: Driver going down so return\n",
5218 wlc->pub->unit, __func__);
5224 wlc->going_down = true;
5226 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5228 dev_gone = brcms_deviceremoved(wlc);
5230 /* Call any registered down handlers */
5231 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5232 if (wlc->modulecb[i].down_fn)
5234 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5237 /* cancel the watchdog timer */
5239 if (!brcms_del_timer(wlc->wdtimer))
5241 wlc->WDarmed = false;
5243 /* cancel all other timers */
5244 callbacks += brcms_c_down_del_timer(wlc);
5246 wlc->pub->up = false;
5248 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5250 callbacks += brcms_b_down_finish(wlc->hw);
5252 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5255 wlc->going_down = false;
5259 /* Set the current gmode configuration */
5260 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5264 struct brcms_c_rateset rs;
5265 /* Default to 54g Auto */
5266 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5267 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5268 bool shortslot_restrict = false; /* Restrict association to stations
5269 * that support shortslot
5271 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5272 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5273 int preamble = BRCMS_PLCP_LONG;
5274 bool preamble_restrict = false; /* Restrict association to stations
5275 * that support short preambles
5277 struct brcms_band *band;
5279 /* if N-support is enabled, allow Gmode set as long as requested
5280 * Gmode is not GMODE_LEGACY_B
5282 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5285 /* verify that we are dealing with 2G band and grab the band pointer */
5286 if (wlc->band->bandtype == BRCM_BAND_2G)
5288 else if ((wlc->pub->_nbands > 1) &&
5289 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5290 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5294 /* update configuration value */
5296 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5298 /* Clear rateset override */
5299 memset(&rs, 0, sizeof(rs));
5302 case GMODE_LEGACY_B:
5303 shortslot = BRCMS_SHORTSLOT_OFF;
5304 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5312 /* Accept defaults */
5317 preamble = BRCMS_PLCP_SHORT;
5318 preamble_restrict = true;
5321 case GMODE_PERFORMANCE:
5322 shortslot = BRCMS_SHORTSLOT_ON;
5323 shortslot_restrict = true;
5325 preamble = BRCMS_PLCP_SHORT;
5326 preamble_restrict = true;
5331 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5332 wlc->pub->unit, __func__, gmode);
5336 band->gmode = gmode;
5338 wlc->shortslot_override = shortslot;
5340 /* Use the default 11g rateset */
5342 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5345 for (i = 0; i < rs.count; i++) {
5346 if (rs.rates[i] == BRCM_RATE_6M
5347 || rs.rates[i] == BRCM_RATE_12M
5348 || rs.rates[i] == BRCM_RATE_24M)
5349 rs.rates[i] |= BRCMS_RATE_FLAG;
5353 /* Set default bss rateset */
5354 wlc->default_bss->rateset.count = rs.count;
5355 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5356 sizeof(wlc->default_bss->rateset.rates));
5361 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5366 if (wlc->stf->txstreams == WL_11N_3x3)
5371 /* force GMODE_AUTO if NMODE is ON */
5372 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5373 if (nmode == WL_11N_3x3)
5374 wlc->pub->_n_enab = SUPPORT_HT;
5376 wlc->pub->_n_enab = SUPPORT_11N;
5377 wlc->default_bss->flags |= BRCMS_BSS_HT;
5378 /* add the mcs rates to the default and hw ratesets */
5379 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5380 wlc->stf->txstreams);
5381 for (i = 0; i < wlc->pub->_nbands; i++)
5382 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5383 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5389 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5390 struct brcms_c_rateset *rs_arg)
5392 struct brcms_c_rateset rs, new;
5395 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5397 /* check for bad count value */
5398 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5401 /* try the current band */
5402 bandunit = wlc->band->bandunit;
5403 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5404 if (brcms_c_rate_hwrs_filter_sort_validate
5405 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5406 wlc->stf->txstreams))
5409 /* try the other band */
5410 if (brcms_is_mband_unlocked(wlc)) {
5411 bandunit = OTHERBANDUNIT(wlc);
5412 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5413 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5415 bandstate[bandunit]->
5417 wlc->stf->txstreams))
5424 /* apply new rateset */
5425 memcpy(&wlc->default_bss->rateset, &new,
5426 sizeof(struct brcms_c_rateset));
5427 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5428 sizeof(struct brcms_c_rateset));
5432 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5437 if (wlc->bsscfg->associated)
5438 r = wlc->bsscfg->current_bss->rateset.rates[0];
5440 r = wlc->default_bss->rateset.rates[0];
5442 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5445 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5447 u16 chspec = ch20mhz_chspec(channel);
5449 if (channel < 0 || channel > MAXCHANNEL)
5452 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5456 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5457 if (wlc->band->bandunit != chspec_bandunit(chspec))
5458 wlc->bandinit_pending = true;
5460 wlc->bandinit_pending = false;
5463 wlc->default_bss->chanspec = chspec;
5464 /* brcms_c_BSSinit() will sanitize the rateset before
5466 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5467 brcms_c_set_home_chanspec(wlc, chspec);
5468 brcms_c_suspend_mac_and_wait(wlc);
5469 brcms_c_set_chanspec(wlc, chspec);
5470 brcms_c_enable_mac(wlc);
5475 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5479 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5480 lrl < 1 || lrl > RETRY_SHORT_MAX)
5486 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5488 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5489 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5490 EDCF_SHORT, wlc->SRL);
5491 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5492 EDCF_LONG, wlc->LRL);
5494 brcms_c_wme_retries_write(wlc);
5499 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5500 struct brcm_rateset *currs)
5502 struct brcms_c_rateset *rs;
5504 if (wlc->pub->associated)
5505 rs = &wlc->bsscfg->current_bss->rateset;
5507 rs = &wlc->default_bss->rateset;
5509 /* Copy only legacy rateset section */
5510 currs->count = rs->count;
5511 memcpy(&currs->rates, &rs->rates, rs->count);
5514 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5516 struct brcms_c_rateset internal_rs;
5519 if (rs->count > BRCMS_NUMRATES)
5522 memset(&internal_rs, 0, sizeof(internal_rs));
5524 /* Copy only legacy rateset section */
5525 internal_rs.count = rs->count;
5526 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5528 /* merge rateset coming in with the current mcsset */
5529 if (wlc->pub->_n_enab & SUPPORT_11N) {
5530 struct brcms_bss_info *mcsset_bss;
5531 if (wlc->bsscfg->associated)
5532 mcsset_bss = wlc->bsscfg->current_bss;
5534 mcsset_bss = wlc->default_bss;
5535 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5539 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5541 brcms_c_ofdm_rateset_war(wlc);
5546 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5551 wlc->default_bss->beacon_period = period;
5555 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5557 return wlc->band->phytype;
5560 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5562 wlc->shortslot_override = sslot_override;
5565 * shortslot is an 11g feature, so no more work if we are
5566 * currently on the 5G band
5568 if (wlc->band->bandtype == BRCM_BAND_5G)
5571 if (wlc->pub->up && wlc->pub->associated) {
5572 /* let watchdog or beacon processing update shortslot */
5573 } else if (wlc->pub->up) {
5574 /* unassociated shortslot is off */
5575 brcms_c_switch_shortslot(wlc, false);
5577 /* driver is down, so just update the brcms_c_info
5579 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5580 wlc->shortslot = false;
5583 (wlc->shortslot_override ==
5584 BRCMS_SHORTSLOT_ON);
5589 * register watchdog and down handlers.
5591 int brcms_c_module_register(struct brcms_pub *pub,
5592 const char *name, struct brcms_info *hdl,
5593 int (*d_fn)(void *handle))
5595 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5598 /* find an empty entry and just add, no duplication check! */
5599 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5600 if (wlc->modulecb[i].name[0] == '\0') {
5601 strncpy(wlc->modulecb[i].name, name,
5602 sizeof(wlc->modulecb[i].name) - 1);
5603 wlc->modulecb[i].hdl = hdl;
5604 wlc->modulecb[i].down_fn = d_fn;
5612 /* unregister module callbacks */
5613 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5614 struct brcms_info *hdl)
5616 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5622 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5623 if (!strcmp(wlc->modulecb[i].name, name) &&
5624 (wlc->modulecb[i].hdl == hdl)) {
5625 memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5630 /* table not found! */
5634 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5636 struct pci_dev *pcidev = core->bus->host_pci;
5637 u16 vendor = pcidev->vendor;
5638 u16 device = pcidev->device;
5640 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5641 pr_err("unknown vendor id %04x\n", vendor);
5645 if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5647 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5649 if (device == BCM4313_D11N2G_ID)
5651 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5654 pr_err("unknown device id %04x\n", device);
5658 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5660 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5662 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5665 pr_err("unknown chip id %04x\n", chipinfo->id);
5669 bool brcms_c_chipmatch(struct bcma_device *core)
5671 switch (core->bus->hosttype) {
5672 case BCMA_HOSTTYPE_PCI:
5673 return brcms_c_chipmatch_pci(core);
5674 case BCMA_HOSTTYPE_SOC:
5675 return brcms_c_chipmatch_soc(core);
5677 pr_err("unknown host type: %i\n", core->bus->hosttype);
5682 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5687 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5688 if (is_ofdm_rate(rate))
5689 table_ptr = M_RT_DIRMAP_A;
5691 table_ptr = M_RT_DIRMAP_B;
5693 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5694 * the index into the rate table.
5696 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5697 index = phy_rate & 0xf;
5699 /* Find the SHM pointer to the rate table entry by looking in the
5702 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5706 * bcmc_fid_generate:
5707 * Generate frame ID for a BCMC packet. The frag field is not used
5708 * for MC frames so is used as part of the sequence number.
5711 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5716 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5720 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5727 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5733 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5734 * is less than or equal to the rate of the immediately previous
5737 rspec = brcms_basic_rate(wlc, rspec);
5738 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5740 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5741 (DOT11_ACK_LEN + FCS_LEN));
5746 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5749 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5753 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5757 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5758 * is less than or equal to the rate of the immediately previous
5761 rspec = brcms_basic_rate(wlc, rspec);
5762 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5763 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5764 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5768 /* brcms_c_compute_frame_dur()
5770 * Calculate the 802.11 MAC header DUR field for MPDU
5771 * DUR for a single frame = 1 SIFS + 1 ACK
5772 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5774 * rate MPDU rate in unit of 500kbps
5775 * next_frag_len next MPDU length in bytes
5776 * preamble_type use short/GF or long/MM PLCP header
5779 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5780 u8 preamble_type, uint next_frag_len)
5784 sifs = get_sifs(wlc->band);
5787 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5789 if (next_frag_len) {
5790 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5792 /* add another SIFS and the frag time */
5795 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5801 /* The opposite of brcms_c_calc_frame_time */
5803 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5804 u8 preamble_type, uint dur)
5806 uint nsyms, mac_len, Ndps, kNdps;
5807 uint rate = rspec2rate(ratespec);
5809 if (is_mcs_rate(ratespec)) {
5810 uint mcs = ratespec & RSPEC_RATE_MASK;
5811 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5812 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5813 /* payload calculation matches that of regular ofdm */
5814 if (wlc->band->bandtype == BRCM_BAND_2G)
5815 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5816 /* kNdbps = kbps * 4 */
5817 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5818 rspec_issgi(ratespec)) * 4;
5819 nsyms = dur / APHY_SYMBOL_TIME;
5822 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5823 } else if (is_ofdm_rate(ratespec)) {
5824 dur -= APHY_PREAMBLE_TIME;
5825 dur -= APHY_SIGNAL_TIME;
5826 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5828 nsyms = dur / APHY_SYMBOL_TIME;
5831 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5833 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5834 dur -= BPHY_PLCP_SHORT_TIME;
5836 dur -= BPHY_PLCP_TIME;
5837 mac_len = dur * rate;
5838 /* divide out factor of 2 in rate (1/2 mbps) */
5839 mac_len = mac_len / 8 / 2;
5845 * Return true if the specified rate is supported by the specified band.
5846 * BRCM_BAND_AUTO indicates the current band.
5848 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5851 struct brcms_c_rateset *hw_rateset;
5854 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5855 hw_rateset = &wlc->band->hw_rateset;
5856 else if (wlc->pub->_nbands > 1)
5857 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5859 /* other band specified and we are a single band device */
5862 /* check if this is a mimo rate */
5863 if (is_mcs_rate(rspec)) {
5864 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5867 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5870 for (i = 0; i < hw_rateset->count; i++)
5871 if (hw_rateset->rates[i] == rspec2rate(rspec))
5875 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5876 "not in hw_rateset\n", wlc->pub->unit, rspec);
5882 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5885 struct bcma_device *core = wlc->hw->d11core;
5886 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5887 u8 rate = int_val & NRATE_RATE_MASK;
5889 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5890 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5891 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5892 == NRATE_OVERRIDE_MCS_ONLY);
5898 /* validate the combination of rate/mcs/stf is allowed */
5899 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5900 /* mcs only allowed when nmode */
5901 if (stf > PHY_TXC1_MODE_SDM) {
5902 brcms_err(core, "wl%d: %s: Invalid stf\n",
5903 wlc->pub->unit, __func__);
5908 /* mcs 32 is a special case, DUP mode 40 only */
5910 if (!CHSPEC_IS40(wlc->home_chanspec) ||
5911 ((stf != PHY_TXC1_MODE_SISO)
5912 && (stf != PHY_TXC1_MODE_CDD))) {
5913 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5914 wlc->pub->unit, __func__);
5918 /* mcs > 7 must use stf SDM */
5919 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5920 /* mcs > 7 must use stf SDM */
5921 if (stf != PHY_TXC1_MODE_SDM) {
5922 brcms_dbg_mac80211(core, "wl%d: enabling "
5923 "SDM mode for mcs %d\n",
5924 wlc->pub->unit, rate);
5925 stf = PHY_TXC1_MODE_SDM;
5929 * MCS 0-7 may use SISO, CDD, and for
5932 if ((stf > PHY_TXC1_MODE_STBC) ||
5933 (!BRCMS_STBC_CAP_PHY(wlc)
5934 && (stf == PHY_TXC1_MODE_STBC))) {
5935 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5936 wlc->pub->unit, __func__);
5941 } else if (is_ofdm_rate(rate)) {
5942 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5943 brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5944 wlc->pub->unit, __func__);
5948 } else if (is_cck_rate(rate)) {
5949 if ((cur_band->bandtype != BRCM_BAND_2G)
5950 || (stf != PHY_TXC1_MODE_SISO)) {
5951 brcms_err(core, "wl%d: %s: Invalid CCK\n",
5952 wlc->pub->unit, __func__);
5957 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5958 wlc->pub->unit, __func__);
5962 /* make sure multiple antennae are available for non-siso rates */
5963 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5964 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5965 "request\n", wlc->pub->unit, __func__);
5972 rspec |= RSPEC_MIMORATE;
5973 /* For STBC populate the STC field of the ratespec */
5974 if (stf == PHY_TXC1_MODE_STBC) {
5976 stc = 1; /* Nss for single stream is always 1 */
5977 rspec |= (stc << RSPEC_STC_SHIFT);
5981 rspec |= (stf << RSPEC_STF_SHIFT);
5983 if (override_mcs_only)
5984 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5987 rspec |= RSPEC_SHORT_GI;
5990 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
5999 * Compute PLCP, but only requires actual rate and length of pkt.
6000 * Rate is given in the driver standard multiple of 500 kbps.
6001 * le is set for 11 Mbps rate if necessary.
6002 * Broken out for PRQ.
6005 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6006 uint length, u8 *plcp)
6019 usec = (length << 4) / 11;
6020 if ((length << 4) - (usec * 11) > 0)
6024 usec = (length << 3) / 11;
6025 if ((length << 3) - (usec * 11) > 0) {
6027 if ((usec * 11) - (length << 3) >= 8)
6028 le = D11B_PLCP_SIGNAL_LE;
6033 brcms_err(wlc->hw->d11core,
6034 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6036 rate_500 = BRCM_RATE_1M;
6040 /* PLCP signal byte */
6041 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6042 /* PLCP service byte */
6043 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6044 /* PLCP length u16, little endian */
6045 plcp[2] = usec & 0xff;
6046 plcp[3] = (usec >> 8) & 0xff;
6052 /* Rate: 802.11 rate code, length: PSDU length in octets */
6053 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6055 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6057 if (rspec_is40mhz(rspec) || (mcs == 32))
6058 plcp[0] |= MIMO_PLCP_40MHZ;
6059 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6060 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6061 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6062 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6066 /* Rate: 802.11 rate code, length: PSDU length in octets */
6068 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6072 int rate = rspec2rate(rspec);
6075 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6078 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6079 memset(plcp, 0, D11_PHY_HDR_LEN);
6080 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6082 tmp = (length & 0xfff) << 5;
6083 plcp[2] |= (tmp >> 16) & 0xff;
6084 plcp[1] |= (tmp >> 8) & 0xff;
6085 plcp[0] |= tmp & 0xff;
6088 /* Rate: 802.11 rate code, length: PSDU length in octets */
6089 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6090 uint length, u8 *plcp)
6092 int rate = rspec2rate(rspec);
6094 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6098 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6099 uint length, u8 *plcp)
6101 if (is_mcs_rate(rspec))
6102 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6103 else if (is_ofdm_rate(rspec))
6104 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6106 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6109 /* brcms_c_compute_rtscts_dur()
6111 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6112 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6113 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6115 * cts cts-to-self or rts/cts
6116 * rts_rate rts or cts rate in unit of 500kbps
6117 * rate next MPDU rate in unit of 500kbps
6118 * frame_len next MPDU frame length in bytes
6121 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6123 u32 frame_rate, u8 rts_preamble_type,
6124 u8 frame_preamble_type, uint frame_len, bool ba)
6128 sifs = get_sifs(wlc->band);
6134 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6142 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6146 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6147 BRCMS_SHORT_PREAMBLE);
6150 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6151 frame_preamble_type);
6155 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6160 if (BRCMS_ISLCNPHY(wlc->band)) {
6161 bw = PHY_TXC1_BW_20MHZ;
6163 bw = rspec_get_bw(rspec);
6164 /* 10Mhz is not supported yet */
6165 if (bw < PHY_TXC1_BW_20MHZ) {
6166 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6167 "not supported yet, set to 20L\n", bw);
6168 bw = PHY_TXC1_BW_20MHZ;
6172 if (is_mcs_rate(rspec)) {
6173 uint mcs = rspec & RSPEC_RATE_MASK;
6175 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6176 phyctl1 = rspec_phytxbyte2(rspec);
6177 /* set the upper byte of phyctl1 */
6178 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6179 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6180 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6182 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6183 * Data Rate. Eventually MIMOPHY would also be converted to
6186 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6187 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6188 } else { /* legacy OFDM/CCK */
6190 /* get the phyctl byte from rate phycfg table */
6191 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6193 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6194 "legacy OFDM/CCK rate\n");
6197 /* set the upper byte of phyctl1 */
6199 (bw | (phycfg << 8) |
6200 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6206 * Add struct d11txh, struct cck_phy_hdr.
6208 * 'p' data must start with 802.11 MAC header
6209 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6211 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6215 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6216 struct sk_buff *p, struct scb *scb, uint frag,
6217 uint nfrags, uint queue, uint next_frag_len)
6219 struct ieee80211_hdr *h;
6221 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6222 int len, phylen, rts_phylen;
6223 u16 mch, phyctl, xfts, mainrates;
6224 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6225 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6226 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6227 bool use_rts = false;
6228 bool use_cts = false;
6229 bool use_rifs = false;
6230 bool short_preamble[2] = { false, false };
6231 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6232 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6233 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6234 struct ieee80211_rts *rts = NULL;
6237 bool hwtkmic = false;
6238 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6239 #define ANTCFG_NONE 0xFF
6240 u8 antcfg = ANTCFG_NONE;
6241 u8 fbantcfg = ANTCFG_NONE;
6242 uint phyctl1_stf = 0;
6244 struct ieee80211_tx_rate *txrate[2];
6246 struct ieee80211_tx_info *tx_info;
6249 u8 mimo_preamble_type;
6251 /* locate 802.11 MAC header */
6252 h = (struct ieee80211_hdr *)(p->data);
6253 qos = ieee80211_is_data_qos(h->frame_control);
6255 /* compute length of frame in bytes for use in PLCP computations */
6257 phylen = len + FCS_LEN;
6260 tx_info = IEEE80211_SKB_CB(p);
6263 plcp = skb_push(p, D11_PHY_HDR_LEN);
6265 /* add Broadcom tx descriptor header */
6266 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6267 memset(txh, 0, D11_TXH_LEN);
6270 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6271 /* non-AP STA should never use BCMC queue */
6272 if (queue == TX_BCMC_FIFO) {
6273 brcms_err(wlc->hw->d11core,
6274 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6275 wlc->pub->unit, __func__);
6276 frameid = bcmc_fid_generate(wlc, NULL, txh);
6278 /* Increment the counter for first fragment */
6279 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6280 scb->seqnum[p->priority]++;
6282 /* extract fragment number from frame first */
6283 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6284 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6285 h->seq_ctrl = cpu_to_le16(seq);
6287 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6288 (queue & TXFID_QUEUE_MASK);
6291 frameid |= queue & TXFID_QUEUE_MASK;
6293 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6294 if (ieee80211_is_beacon(h->frame_control))
6295 mcl |= TXC_IGNOREPMQ;
6297 txrate[0] = tx_info->control.rates;
6298 txrate[1] = txrate[0] + 1;
6301 * if rate control algorithm didn't give us a fallback
6302 * rate, use the primary rate
6304 if (txrate[1]->idx < 0)
6305 txrate[1] = txrate[0];
6307 for (k = 0; k < hw->max_rates; k++) {
6308 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6310 if ((txrate[k]->idx >= 0)
6311 && (txrate[k]->idx <
6312 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6314 hw->wiphy->bands[tx_info->band]->
6315 bitrates[txrate[k]->idx].hw_value;
6318 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6321 rspec[k] = BRCM_RATE_1M;
6324 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6325 NRATE_MCS_INUSE | txrate[k]->idx);
6329 * Currently only support same setting for primay and
6330 * fallback rates. Unify flags for each rate into a
6331 * single value for the frame
6335 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6338 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6343 * determine and validate primary rate
6344 * and fallback rates
6346 if (!rspec_active(rspec[k])) {
6347 rspec[k] = BRCM_RATE_1M;
6349 if (!is_multicast_ether_addr(h->addr1)) {
6350 /* set tx antenna config */
6351 brcms_c_antsel_antcfg_get(wlc->asi, false,
6352 false, 0, 0, &antcfg, &fbantcfg);
6357 phyctl1_stf = wlc->stf->ss_opmode;
6359 if (wlc->pub->_n_enab & SUPPORT_11N) {
6360 for (k = 0; k < hw->max_rates; k++) {
6362 * apply siso/cdd to single stream mcs's or ofdm
6363 * if rspec is auto selected
6365 if (((is_mcs_rate(rspec[k]) &&
6366 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6367 is_ofdm_rate(rspec[k]))
6368 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6369 || !(rspec[k] & RSPEC_OVERRIDE))) {
6370 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6372 /* For SISO MCS use STBC if possible */
6373 if (is_mcs_rate(rspec[k])
6374 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6377 /* Nss for single stream is always 1 */
6379 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6381 (stc << RSPEC_STC_SHIFT);
6384 (phyctl1_stf << RSPEC_STF_SHIFT);
6388 * Is the phy configured to use 40MHZ frames? If
6389 * so then pick the desired txbw
6391 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6392 /* default txbw is 20in40 SB */
6393 mimo_ctlchbw = mimo_txbw =
6394 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6396 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6398 if (is_mcs_rate(rspec[k])) {
6399 /* mcs 32 must be 40b/w DUP */
6400 if ((rspec[k] & RSPEC_RATE_MASK)
6403 PHY_TXC1_BW_40MHZ_DUP;
6405 } else if (wlc->mimo_40txbw != AUTO)
6406 mimo_txbw = wlc->mimo_40txbw;
6407 /* else check if dst is using 40 Mhz */
6408 else if (scb->flags & SCB_IS40)
6409 mimo_txbw = PHY_TXC1_BW_40MHZ;
6410 } else if (is_ofdm_rate(rspec[k])) {
6411 if (wlc->ofdm_40txbw != AUTO)
6412 mimo_txbw = wlc->ofdm_40txbw;
6413 } else if (wlc->cck_40txbw != AUTO) {
6414 mimo_txbw = wlc->cck_40txbw;
6418 * mcs32 is 40 b/w only.
6419 * This is possible for probe packets on
6422 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6424 rspec[k] = RSPEC_MIMORATE;
6426 mimo_txbw = PHY_TXC1_BW_20MHZ;
6429 /* Set channel width */
6430 rspec[k] &= ~RSPEC_BW_MASK;
6431 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6432 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6434 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6436 /* Disable short GI, not supported yet */
6437 rspec[k] &= ~RSPEC_SHORT_GI;
6439 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6440 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6441 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6443 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6444 && (!is_mcs_rate(rspec[k]))) {
6445 brcms_warn(wlc->hw->d11core,
6446 "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6447 wlc->pub->unit, __func__);
6450 if (is_mcs_rate(rspec[k])) {
6451 preamble_type[k] = mimo_preamble_type;
6454 * if SGI is selected, then forced mm
6457 if ((rspec[k] & RSPEC_SHORT_GI)
6458 && is_single_stream(rspec[k] &
6460 preamble_type[k] = BRCMS_MM_PREAMBLE;
6463 /* should be better conditionalized */
6464 if (!is_mcs_rate(rspec[0])
6465 && (tx_info->control.rates[0].
6466 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6467 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6470 for (k = 0; k < hw->max_rates; k++) {
6471 /* Set ctrlchbw as 20Mhz */
6472 rspec[k] &= ~RSPEC_BW_MASK;
6473 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6475 /* for nphy, stf of ofdm frames must follow policies */
6476 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6477 rspec[k] &= ~RSPEC_STF_MASK;
6478 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6483 /* Reset these for use with AMPDU's */
6484 txrate[0]->count = 0;
6485 txrate[1]->count = 0;
6487 /* (2) PROTECTION, may change rspec */
6488 if ((ieee80211_is_data(h->frame_control) ||
6489 ieee80211_is_mgmt(h->frame_control)) &&
6490 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6493 /* (3) PLCP: determine PLCP header and MAC duration,
6494 * fill struct d11txh */
6495 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6496 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6497 memcpy(&txh->FragPLCPFallback,
6498 plcp_fallback, sizeof(txh->FragPLCPFallback));
6500 /* Length field now put in CCK FBR CRC field */
6501 if (is_cck_rate(rspec[1])) {
6502 txh->FragPLCPFallback[4] = phylen & 0xff;
6503 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6506 /* MIMO-RATE: need validation ?? */
6507 mainrates = is_ofdm_rate(rspec[0]) ?
6508 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6511 /* DUR field for main rate */
6512 if (!ieee80211_is_pspoll(h->frame_control) &&
6513 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6515 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6517 h->duration_id = cpu_to_le16(durid);
6518 } else if (use_rifs) {
6519 /* NAV protect to end of next max packet size */
6521 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6523 DOT11_MAX_FRAG_LEN);
6524 durid += RIFS_11N_TIME;
6525 h->duration_id = cpu_to_le16(durid);
6528 /* DUR field for fallback rate */
6529 if (ieee80211_is_pspoll(h->frame_control))
6530 txh->FragDurFallback = h->duration_id;
6531 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6532 txh->FragDurFallback = 0;
6534 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6535 preamble_type[1], next_frag_len);
6536 txh->FragDurFallback = cpu_to_le16(durid);
6539 /* (4) MAC-HDR: MacTxControlLow */
6541 mcl |= TXC_STARTMSDU;
6543 if (!is_multicast_ether_addr(h->addr1))
6544 mcl |= TXC_IMMEDACK;
6546 if (wlc->band->bandtype == BRCM_BAND_5G)
6547 mcl |= TXC_FREQBAND_5G;
6549 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6552 /* set AMIC bit if using hardware TKIP MIC */
6556 txh->MacTxControlLow = cpu_to_le16(mcl);
6558 /* MacTxControlHigh */
6561 /* Set fallback rate preamble type */
6562 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6563 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6564 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6565 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6568 /* MacFrameControl */
6569 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6570 txh->TxFesTimeNormal = cpu_to_le16(0);
6572 txh->TxFesTimeFallback = cpu_to_le16(0);
6575 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6578 txh->TxFrameID = cpu_to_le16(frameid);
6581 * TxStatus, Note the case of recreating the first frag of a suppressed
6582 * frame then we may need to reset the retry cnt's via the status reg
6584 txh->TxStatus = cpu_to_le16(status);
6587 * extra fields for ucode AMPDU aggregation, the new fields are added to
6588 * the END of previous structure so that it's compatible in driver.
6590 txh->MaxNMpdus = cpu_to_le16(0);
6591 txh->MaxABytes_MRT = cpu_to_le16(0);
6592 txh->MaxABytes_FBR = cpu_to_le16(0);
6593 txh->MinMBytes = cpu_to_le16(0);
6595 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6596 * furnish struct d11txh */
6597 /* RTS PLCP header and RTS frame */
6598 if (use_rts || use_cts) {
6599 if (use_rts && use_cts)
6602 for (k = 0; k < 2; k++) {
6603 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6608 if (!is_ofdm_rate(rts_rspec[0]) &&
6609 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6610 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6611 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6612 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6615 if (!is_ofdm_rate(rts_rspec[1]) &&
6616 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6617 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6618 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6619 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6622 /* RTS/CTS additions to MacTxControlLow */
6624 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6626 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6627 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6630 /* RTS PLCP header */
6631 rts_plcp = txh->RTSPhyHeader;
6633 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6635 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6637 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6639 /* fallback rate version of RTS PLCP header */
6640 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6642 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6643 sizeof(txh->RTSPLCPFallback));
6645 /* RTS frame fields... */
6646 rts = (struct ieee80211_rts *)&txh->rts_frame;
6648 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6649 rspec[0], rts_preamble_type[0],
6650 preamble_type[0], phylen, false);
6651 rts->duration = cpu_to_le16(durid);
6652 /* fallback rate version of RTS DUR field */
6653 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6654 rts_rspec[1], rspec[1],
6655 rts_preamble_type[1],
6656 preamble_type[1], phylen, false);
6657 txh->RTSDurFallback = cpu_to_le16(durid);
6660 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6661 IEEE80211_STYPE_CTS);
6663 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6665 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6666 IEEE80211_STYPE_RTS);
6668 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6672 * low 8 bits: main frag rate/mcs,
6673 * high 8 bits: rts/cts rate/mcs
6675 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6677 (struct ofdm_phy_hdr *) rts_plcp) :
6680 memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6681 memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6682 memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6683 txh->RTSDurFallback = 0;
6686 #ifdef SUPPORT_40MHZ
6687 /* add null delimiter count */
6688 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6689 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6690 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6695 * Now that RTS/RTS FB preamble types are updated, write
6698 txh->MacTxControlHigh = cpu_to_le16(mch);
6701 * MainRates (both the rts and frag plcp rates have
6702 * been calculated now)
6704 txh->MainRates = cpu_to_le16(mainrates);
6706 /* XtraFrameTypes */
6707 xfts = frametype(rspec[1], wlc->mimoft);
6708 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6709 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6710 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6712 txh->XtraFrameTypes = cpu_to_le16(xfts);
6714 /* PhyTxControlWord */
6715 phyctl = frametype(rspec[0], wlc->mimoft);
6716 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6717 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6718 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6719 phyctl |= PHY_TXC_SHORT_HDR;
6722 /* phytxant is properly bit shifted */
6723 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6724 txh->PhyTxControlWord = cpu_to_le16(phyctl);
6726 /* PhyTxControlWord_1 */
6727 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6730 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6731 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6732 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6733 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6735 if (use_rts || use_cts) {
6736 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6737 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6738 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6739 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6743 * For mcs frames, if mixedmode(overloaded with long preamble)
6744 * is going to be set, fill in non-zero MModeLen and/or
6745 * MModeFbrLen it will be unnecessary if they are separated
6747 if (is_mcs_rate(rspec[0]) &&
6748 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6750 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6751 txh->MModeLen = cpu_to_le16(mmodelen);
6754 if (is_mcs_rate(rspec[1]) &&
6755 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6757 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6758 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6762 ac = skb_get_queue_mapping(p);
6763 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6764 uint frag_dur, dur, dur_fallback;
6766 /* WME: Update TXOP threshold */
6767 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6769 brcms_c_calc_frame_time(wlc, rspec[0],
6770 preamble_type[0], phylen);
6773 /* 1 RTS or CTS-to-self frame */
6775 brcms_c_calc_cts_time(wlc, rts_rspec[0],
6776 rts_preamble_type[0]);
6778 brcms_c_calc_cts_time(wlc, rts_rspec[1],
6779 rts_preamble_type[1]);
6780 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6781 dur += le16_to_cpu(rts->duration);
6783 le16_to_cpu(txh->RTSDurFallback);
6784 } else if (use_rifs) {
6788 /* frame + SIFS + ACK */
6791 brcms_c_compute_frame_dur(wlc, rspec[0],
6792 preamble_type[0], 0);
6795 brcms_c_calc_frame_time(wlc, rspec[1],
6799 brcms_c_compute_frame_dur(wlc, rspec[1],
6800 preamble_type[1], 0);
6802 /* NEED to set TxFesTimeNormal (hard) */
6803 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6805 * NEED to set fallback rate version of
6806 * TxFesTimeNormal (hard)
6808 txh->TxFesTimeFallback =
6809 cpu_to_le16((u16) dur_fallback);
6812 * update txop byte threshold (txop minus intraframe
6815 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6819 brcms_c_calc_frame_len(wlc,
6820 rspec[0], preamble_type[0],
6821 (wlc->edcf_txop[ac] -
6823 /* range bound the fragthreshold */
6824 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6827 else if (newfragthresh >
6828 wlc->usr_fragthresh)
6830 wlc->usr_fragthresh;
6831 /* update the fragthresh and do txc update */
6832 if (wlc->fragthresh[queue] !=
6833 (u16) newfragthresh)
6834 wlc->fragthresh[queue] =
6835 (u16) newfragthresh;
6837 brcms_warn(wlc->hw->d11core,
6838 "wl%d: %s txop invalid for rate %d\n",
6839 wlc->pub->unit, fifo_names[queue],
6840 rspec2rate(rspec[0]));
6843 if (dur > wlc->edcf_txop[ac])
6844 brcms_warn(wlc->hw->d11core,
6845 "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6846 wlc->pub->unit, __func__,
6848 phylen, wlc->fragthresh[queue],
6849 dur, wlc->edcf_txop[ac]);
6856 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6858 struct dma_pub *dma;
6859 int fifo, ret = -ENOSPC;
6861 u16 frameid = INVALIDFID;
6863 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6864 dma = wlc->hw->di[fifo];
6865 txh = (struct d11txh *)(skb->data);
6867 if (dma->txavail == 0) {
6869 * We sometimes get a frame from mac80211 after stopping
6870 * the queues. This only ever seems to be a single frame
6871 * and is seems likely to be a race. TX_HEADROOM should
6872 * ensure that we have enough space to handle these stray
6873 * packets, so warn if there isn't. If we're out of space
6874 * in the tx ring and the tx queue isn't stopped then
6875 * we've really got a bug; warn loudly if that happens.
6877 brcms_warn(wlc->hw->d11core,
6878 "Received frame for tx with no space in DMA ring\n");
6879 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6880 skb_get_queue_mapping(skb)));
6884 /* When a BC/MC frame is being committed to the BCMC fifo
6885 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6887 if (fifo == TX_BCMC_FIFO)
6888 frameid = le16_to_cpu(txh->TxFrameID);
6890 /* Commit BCMC sequence number in the SHM frame ID location */
6891 if (frameid != INVALIDFID) {
6893 * To inform the ucode of the last mcast frame posted
6894 * so that it can clear moredata bit
6896 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6899 ret = brcms_c_txfifo(wlc, fifo, skb);
6901 * The only reason for brcms_c_txfifo to fail is because
6902 * there weren't any DMA descriptors, but we've already
6903 * checked for that. So if it does fail yell loudly.
6910 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6911 struct ieee80211_hw *hw)
6914 struct scb *scb = &wlc->pri_scb;
6916 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6917 brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6918 if (!brcms_c_tx(wlc, sdu))
6921 /* packet discarded */
6922 dev_kfree_skb_any(sdu);
6927 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6929 struct dma_pub *dma = wlc->hw->di[fifo];
6933 ret = dma_txfast(wlc, dma, p);
6935 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6938 * Stop queue if DMA ring is full. Reserve some free descriptors,
6939 * as we sometimes receive a frame from mac80211 after the queues
6942 queue = skb_get_queue_mapping(p);
6943 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6944 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6945 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6951 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6952 bool use_rspec, u16 mimo_ctlchbw)
6957 /* use frame rate as rts rate */
6959 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6960 /* Use 11Mbps as the g protection RTS target rate and fallback.
6961 * Use the brcms_basic_rate() lookup to find the best basic rate
6962 * under the target in case 11 Mbps is not Basic.
6963 * 6 and 9 Mbps are not usually selected by rate selection, but
6964 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6967 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6969 /* calculate RTS rate and fallback rate based on the frame rate
6970 * RTS must be sent at a basic rate since it is a
6971 * control frame, sec 9.6 of 802.11 spec
6973 rts_rspec = brcms_basic_rate(wlc, rspec);
6975 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6976 /* set rts txbw to correct side band */
6977 rts_rspec &= ~RSPEC_BW_MASK;
6980 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6981 * 20MHz channel (DUP), otherwise send RTS on control channel
6983 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
6984 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
6986 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6988 /* pick siso/cdd as default for ofdm */
6989 if (is_ofdm_rate(rts_rspec)) {
6990 rts_rspec &= ~RSPEC_STF_MASK;
6991 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
6997 /* Update beacon listen interval in shared memory */
6998 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7000 /* wake up every DTIM is the default */
7001 if (wlc->bcn_li_dtim == 1)
7002 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7004 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7005 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7009 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7012 struct bcma_device *core = wlc_hw->d11core;
7014 /* read the tsf timer low, then high to get an atomic read */
7015 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7016 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7020 * recover 64bit TSF value from the 16bit TSF value in the rx header
7021 * given the assumption that the TSF passed in header is within 65ms
7022 * of the current tsf.
7025 * 3.......6.......8.......0.......2.......4.......6.......8......0
7026 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7028 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7029 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7030 * receive call sequence after rx interrupt. Only the higher 16 bits
7031 * are used. Finally, the tsf_h is read from the tsf register.
7033 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7034 struct d11rxhdr *rxh)
7037 u16 rx_tsf_0_15, rx_tsf_16_31;
7039 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7041 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7042 rx_tsf_0_15 = rxh->RxTSFTime;
7045 * a greater tsf time indicates the low 16 bits of
7046 * tsf_l wrapped, so decrement the high 16 bits.
7048 if ((u16)tsf_l < rx_tsf_0_15) {
7050 if (rx_tsf_16_31 == 0xffff)
7054 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7058 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7060 struct ieee80211_rx_status *rx_status)
7065 unsigned char *plcp;
7067 /* fill in TSF and flag its presence */
7068 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7069 rx_status->flag |= RX_FLAG_MACTIME_START;
7071 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7074 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7076 ieee80211_channel_to_frequency(channel, rx_status->band);
7078 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7082 rx_status->antenna =
7083 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7087 rspec = brcms_c_compute_rspec(rxh, plcp);
7088 if (is_mcs_rate(rspec)) {
7089 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7090 rx_status->flag |= RX_FLAG_HT;
7091 if (rspec_is40mhz(rspec))
7092 rx_status->flag |= RX_FLAG_40MHZ;
7094 switch (rspec2rate(rspec)) {
7096 rx_status->rate_idx = 0;
7099 rx_status->rate_idx = 1;
7102 rx_status->rate_idx = 2;
7105 rx_status->rate_idx = 3;
7108 rx_status->rate_idx = 4;
7111 rx_status->rate_idx = 5;
7114 rx_status->rate_idx = 6;
7117 rx_status->rate_idx = 7;
7120 rx_status->rate_idx = 8;
7123 rx_status->rate_idx = 9;
7126 rx_status->rate_idx = 10;
7129 rx_status->rate_idx = 11;
7132 brcms_err(wlc->hw->d11core,
7133 "%s: Unknown rate\n", __func__);
7137 * For 5GHz, we should decrease the index as it is
7138 * a subset of the 2.4G rates. See bitrates field
7139 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7141 if (rx_status->band == IEEE80211_BAND_5GHZ)
7142 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7144 /* Determine short preamble and rate_idx */
7146 if (is_cck_rate(rspec)) {
7147 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7148 rx_status->flag |= RX_FLAG_SHORTPRE;
7149 } else if (is_ofdm_rate(rspec)) {
7150 rx_status->flag |= RX_FLAG_SHORTPRE;
7152 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7157 if (plcp3_issgi(plcp[3]))
7158 rx_status->flag |= RX_FLAG_SHORT_GI;
7160 if (rxh->RxStatus1 & RXS_DECERR) {
7161 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7162 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7165 if (rxh->RxStatus1 & RXS_FCSERR) {
7166 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7167 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7173 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7177 struct ieee80211_rx_status rx_status;
7178 struct ieee80211_hdr *hdr;
7180 memset(&rx_status, 0, sizeof(rx_status));
7181 prep_mac80211_status(wlc, rxh, p, &rx_status);
7183 /* mac header+body length, exclude CRC and plcp header */
7184 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7185 skb_pull(p, D11_PHY_HDR_LEN);
7186 __skb_trim(p, len_mpdu);
7188 /* unmute transmit */
7189 if (wlc->hw->suspended_fifos) {
7190 hdr = (struct ieee80211_hdr *)p->data;
7191 if (ieee80211_is_beacon(hdr->frame_control))
7192 brcms_b_mute(wlc->hw, false);
7195 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7196 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7199 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7200 * number of bytes goes in the length field
7202 * Formula given by HT PHY Spec v 1.13
7203 * len = 3(nsyms + nstream + 3) - 3
7206 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7209 uint nsyms, len = 0, kNdps;
7211 if (is_mcs_rate(ratespec)) {
7212 uint mcs = ratespec & RSPEC_RATE_MASK;
7213 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7214 rspec_stc(ratespec);
7217 * the payload duration calculation matches that
7220 /* 1000Ndbps = kbps * 4 */
7221 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7222 rspec_issgi(ratespec)) * 4;
7224 if (rspec_stc(ratespec) == 0)
7226 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7227 APHY_TAIL_NBITS) * 1000, kNdps);
7229 /* STBC needs to have even number of symbols */
7232 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7233 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7235 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7236 nsyms += (tot_streams + 3);
7238 * 3 bytes/symbol @ legacy 6Mbps rate
7239 * (-3) excluding service bits and tail bits
7241 len = (3 * nsyms) - 3;
7248 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7250 const struct brcms_c_rateset *rs_dflt;
7251 struct brcms_c_rateset rs;
7254 u8 plcp[D11_PHY_HDR_LEN];
7258 sifs = get_sifs(wlc->band);
7260 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7262 brcms_c_rateset_copy(rs_dflt, &rs);
7263 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7266 * walk the phy rate table and update MAC core SHM
7267 * basic rate table entries
7269 for (i = 0; i < rs.count; i++) {
7270 rate = rs.rates[i] & BRCMS_RATE_MASK;
7272 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7274 /* Calculate the Probe Response PLCP for the given rate */
7275 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7278 * Calculate the duration of the Probe Response
7279 * frame plus SIFS for the MAC
7281 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7282 BRCMS_LONG_PREAMBLE, frame_len);
7285 /* Update the SHM Rate Table entry Probe Response values */
7286 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7287 (u16) (plcp[0] + (plcp[1] << 8)));
7288 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7289 (u16) (plcp[2] + (plcp[3] << 8)));
7290 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7294 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7296 * PLCP header is 6 bytes.
7297 * 802.11 A3 header is 24 bytes.
7298 * Max beacon frame body template length is 112 bytes.
7299 * Max probe resp frame body template length is 110 bytes.
7301 * *len on input contains the max length of the packet available.
7303 * The *len value is set to the number of bytes in buf used, and starts
7304 * with the PLCP and included up to, but not including, the 4 byte FCS.
7307 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7309 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7311 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7312 struct cck_phy_hdr *plcp;
7313 struct ieee80211_mgmt *h;
7314 int hdr_len, body_len;
7316 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7318 /* calc buffer size provided for frame body */
7319 body_len = *len - hdr_len;
7320 /* return actual size */
7321 *len = hdr_len + body_len;
7323 /* format PHY and MAC headers */
7324 memset(buf, 0, hdr_len);
7326 plcp = (struct cck_phy_hdr *) buf;
7329 * PLCP for Probe Response frames are filled in from
7332 if (type == IEEE80211_STYPE_BEACON)
7334 brcms_c_compute_plcp(wlc, bcn_rspec,
7335 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7338 /* "Regular" and 16 MBSS but not for 4 MBSS */
7339 /* Update the phytxctl for the beacon based on the rspec */
7340 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7342 h = (struct ieee80211_mgmt *)&plcp[1];
7344 /* fill in 802.11 header */
7345 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7347 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7348 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7349 if (type == IEEE80211_STYPE_BEACON)
7350 memcpy(&h->da, ðer_bcast, ETH_ALEN);
7351 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7352 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7354 /* SEQ filled in by MAC */
7357 int brcms_c_get_header_len(void)
7363 * Update all beacons for the system.
7365 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7367 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7369 if (bsscfg->up && !bsscfg->BSS)
7370 /* Clear the soft intmask */
7371 wlc->defmacintmask &= ~MI_BCNTPL;
7374 /* Write ssid into shared memory */
7376 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7378 u8 *ssidptr = cfg->SSID;
7380 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7382 /* padding the ssid with zero and copy it into shm */
7383 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7384 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7386 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7387 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7391 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7392 struct brcms_bss_cfg *cfg,
7396 int len = BCN_TMPL_LEN;
7398 prb_resp = kmalloc(BCN_TMPL_LEN, GFP_ATOMIC);
7403 * write the probe response to hardware, or save in
7404 * the config structure
7407 /* create the probe response template */
7408 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7409 cfg, prb_resp, &len);
7412 brcms_c_suspend_mac_and_wait(wlc);
7414 /* write the probe response into the template region */
7415 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7416 (len + 3) & ~3, prb_resp);
7418 /* write the length of the probe response frame (+PLCP/-FCS) */
7419 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7421 /* write the SSID and SSID length */
7422 brcms_c_shm_ssid_upd(wlc, cfg);
7425 * Write PLCP headers and durations for probe response frames
7426 * at all rates. Use the actual frame length covered by the
7427 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7428 * by subtracting the PLCP len and adding the FCS.
7430 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7431 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7434 brcms_c_enable_mac(wlc);
7439 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7441 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7443 /* update AP or IBSS probe responses */
7444 if (bsscfg->up && !bsscfg->BSS)
7445 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7448 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7454 *blocks = wlc_hw->xmtfifo_sz[fifo];
7460 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7463 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7464 if (match_reg_offset == RCM_BSSID_OFFSET)
7465 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7469 * Flag 'scan in progress' to withhold dynamic phy calibration
7471 void brcms_c_scan_start(struct brcms_c_info *wlc)
7473 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7476 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7478 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7481 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7483 wlc->pub->associated = state;
7484 wlc->bsscfg->associated = state;
7488 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7489 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7490 * when later on hardware releases them, they can be handled appropriately.
7492 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7493 struct ieee80211_sta *sta,
7494 void (*dma_callback_fn))
7496 struct dma_pub *dmah;
7498 for (i = 0; i < NFIFO; i++) {
7501 dma_walk_packets(dmah, dma_callback_fn, sta);
7505 int brcms_c_get_curband(struct brcms_c_info *wlc)
7507 return wlc->band->bandunit;
7510 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7514 /* Kick DMA to send any pending AMPDU */
7515 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7517 dma_kick_tx(wlc->hw->di[i]);
7519 return !brcms_txpktpendtot(wlc);
7522 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7524 wlc->bcn_li_bcn = interval;
7526 brcms_c_bcn_li_upd(wlc);
7529 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7533 /* Remove override bit and clip to max qdbm value */
7534 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7535 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7538 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7543 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7545 /* Return qdbm units */
7546 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7549 /* Process received frames */
7551 * Return true if more frames need to be processed. false otherwise.
7552 * Param 'bound' indicates max. # frames to process before break out.
7554 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7556 struct d11rxhdr *rxh;
7557 struct ieee80211_hdr *h;
7561 /* frame starts with rxhdr */
7562 rxh = (struct d11rxhdr *) (p->data);
7564 /* strip off rxhdr */
7565 skb_pull(p, BRCMS_HWRXOFF);
7567 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7568 if (rxh->RxStatus1 & RXS_PBPRES) {
7570 brcms_err(wlc->hw->d11core,
7571 "wl%d: recv: rcvd runt of len %d\n",
7572 wlc->pub->unit, p->len);
7578 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7581 if (rxh->RxStatus1 & RXS_FCSERR) {
7582 if (!(wlc->filter_flags & FIF_FCSFAIL))
7586 /* check received pkt has at least frame control field */
7587 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7590 /* not supporting A-MSDU */
7591 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7595 brcms_c_recvctl(wlc, rxh, p);
7599 brcmu_pkt_buf_free_skb(p);
7602 /* Process received frames */
7604 * Return true if more frames need to be processed. false otherwise.
7605 * Param 'bound' indicates max. # frames to process before break out.
7608 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7611 struct sk_buff *next = NULL;
7612 struct sk_buff_head recv_frames;
7615 uint bound_limit = bound ? RXBND : -1;
7616 bool morepending = false;
7618 skb_queue_head_init(&recv_frames);
7620 /* gather received frames */
7622 /* !give others some time to run! */
7623 if (n >= bound_limit)
7626 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7628 } while (morepending);
7630 /* post more rbufs */
7631 dma_rxfill(wlc_hw->di[fifo]);
7633 /* process each frame */
7634 skb_queue_walk_safe(&recv_frames, p, next) {
7635 struct d11rxhdr_le *rxh_le;
7636 struct d11rxhdr *rxh;
7638 skb_unlink(p, &recv_frames);
7639 rxh_le = (struct d11rxhdr_le *)p->data;
7640 rxh = (struct d11rxhdr *)p->data;
7642 /* fixup rx header endianness */
7643 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7644 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7645 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7646 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7647 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7648 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7649 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7650 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7651 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7652 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7653 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7655 brcms_c_recv(wlc_hw->wlc, p);
7661 /* second-level interrupt processing
7662 * Return true if another dpc needs to be re-scheduled. false otherwise.
7663 * Param 'bounded' indicates if applicable loops should be bounded.
7665 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7668 struct brcms_hardware *wlc_hw = wlc->hw;
7669 struct bcma_device *core = wlc_hw->d11core;
7671 if (brcms_deviceremoved(wlc)) {
7672 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7674 brcms_down(wlc->wl);
7678 /* grab and clear the saved software intstatus bits */
7679 macintstatus = wlc->macintstatus;
7680 wlc->macintstatus = 0;
7682 brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7683 wlc_hw->unit, macintstatus);
7685 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7688 if (macintstatus & MI_TFS) {
7690 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7691 wlc->macintstatus |= MI_TFS;
7693 brcms_err(core, "MI_TFS: fatal\n");
7698 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7701 /* ATIM window end */
7702 if (macintstatus & MI_ATIMWINEND) {
7703 brcms_dbg_info(core, "end of ATIM window\n");
7704 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7709 * received data or control frame, MI_DMAINT is
7710 * indication of RX_FIFO interrupt
7712 if (macintstatus & MI_DMAINT)
7713 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7714 wlc->macintstatus |= MI_DMAINT;
7716 /* noise sample collected */
7717 if (macintstatus & MI_BG_NOISE)
7718 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7720 if (macintstatus & MI_GP0) {
7721 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7722 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7724 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7725 __func__, ai_get_chip_id(wlc_hw->sih),
7726 ai_get_chiprev(wlc_hw->sih));
7727 brcms_fatal_error(wlc_hw->wlc->wl);
7730 /* gptimer timeout */
7731 if (macintstatus & MI_TO)
7732 bcma_write32(core, D11REGOFFS(gptimer), 0);
7734 if (macintstatus & MI_RFDISABLE) {
7735 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7736 " RF Disable Input\n", wlc_hw->unit);
7737 brcms_rfkill_set_hw_state(wlc->wl);
7740 /* it isn't done and needs to be resched if macintstatus is non-zero */
7741 return wlc->macintstatus != 0;
7744 brcms_fatal_error(wlc_hw->wlc->wl);
7745 return wlc->macintstatus != 0;
7748 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7750 struct bcma_device *core = wlc->hw->d11core;
7751 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7754 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7756 chanspec = ch20mhz_chspec(ch->hw_value);
7758 brcms_b_init(wlc->hw, chanspec);
7760 /* update beacon listen interval */
7761 brcms_c_bcn_li_upd(wlc);
7763 /* write ethernet address to core */
7764 brcms_c_set_mac(wlc->bsscfg);
7765 brcms_c_set_bssid(wlc->bsscfg);
7767 /* Update tsf_cfprep if associated and up */
7768 if (wlc->pub->associated && wlc->bsscfg->up) {
7771 /* get beacon period and convert to uS */
7772 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7774 * update since init path would reset
7777 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7778 bi << CFPREP_CBI_SHIFT);
7780 /* Update maccontrol PM related bits */
7781 brcms_c_set_ps_ctrl(wlc);
7784 brcms_c_bandinit_ordered(wlc, chanspec);
7786 /* init probe response timeout */
7787 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7789 /* init max burst txop (framebursting) */
7790 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7792 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7794 /* initialize maximum allowed duty cycle */
7795 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7796 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7799 * Update some shared memory locations related to
7800 * max AMPDU size allowed to received
7802 brcms_c_ampdu_shm_upd(wlc->ampdu);
7804 /* band-specific inits */
7805 brcms_c_bsinit(wlc);
7807 /* Enable EDCF mode (while the MAC is suspended) */
7808 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7809 brcms_c_edcf_setparams(wlc, false);
7811 /* read the ucode version if we have not yet done so */
7812 if (wlc->ucode_rev == 0) {
7814 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
7815 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7818 /* ..now really unleash hell (allow the MAC out of suspend) */
7819 brcms_c_enable_mac(wlc);
7821 /* suspend the tx fifos and mute the phy for preism cac time */
7823 brcms_b_mute(wlc->hw, true);
7825 /* enable the RF Disable Delay timer */
7826 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7829 * Initialize WME parameters; if they haven't been set by some other
7830 * mechanism (IOVar, etc) then read them from the hardware.
7832 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7833 /* Uninitialized; read from HW */
7836 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7837 wlc->wme_retries[ac] =
7838 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7843 * The common driver entry routine. Error codes should be unique
7845 struct brcms_c_info *
7846 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7847 bool piomode, uint *perr)
7849 struct brcms_c_info *wlc;
7852 struct brcms_pub *pub;
7854 /* allocate struct brcms_c_info state and its substructures */
7855 wlc = brcms_c_attach_malloc(unit, &err, 0);
7858 wlc->wiphy = wl->wiphy;
7865 wlc->band = wlc->bandstate[0];
7866 wlc->core = wlc->corestate;
7869 pub->_piomode = piomode;
7870 wlc->bandinit_pending = false;
7872 /* populate struct brcms_c_info with default values */
7873 brcms_c_info_init(wlc, unit);
7875 /* update sta/ap related parameters */
7876 brcms_c_ap_upd(wlc);
7879 * low level attach steps(all hw accesses go
7880 * inside, no more in rest of the attach)
7882 err = brcms_b_attach(wlc, core, unit, piomode);
7886 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7888 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7890 /* disable allowed duty cycle */
7891 wlc->tx_duty_cycle_ofdm = 0;
7892 wlc->tx_duty_cycle_cck = 0;
7894 brcms_c_stf_phy_chain_calc(wlc);
7896 /* txchain 1: txant 0, txchain 2: txant 1 */
7897 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7898 wlc->stf->txant = wlc->stf->hw_txchain - 1;
7900 /* push to BMAC driver */
7901 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7902 wlc->stf->hw_rxchain);
7904 /* pull up some info resulting from the low attach */
7905 for (i = 0; i < NFIFO; i++)
7906 wlc->core->txavail[i] = wlc->hw->txavail[i];
7908 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7909 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7911 for (j = 0; j < wlc->pub->_nbands; j++) {
7912 wlc->band = wlc->bandstate[j];
7914 if (!brcms_c_attach_stf_ant_init(wlc)) {
7919 /* default contention windows size limits */
7920 wlc->band->CWmin = APHY_CWMIN;
7921 wlc->band->CWmax = PHY_CWMAX;
7923 /* init gmode value */
7924 if (wlc->band->bandtype == BRCM_BAND_2G) {
7925 wlc->band->gmode = GMODE_AUTO;
7926 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7930 /* init _n_enab supported mode */
7931 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7932 pub->_n_enab = SUPPORT_11N;
7933 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7935 SUPPORT_11N) ? WL_11N_2x2 :
7939 /* init per-band default rateset, depend on band->gmode */
7940 brcms_default_rateset(wlc, &wlc->band->defrateset);
7942 /* fill in hw_rateset */
7943 brcms_c_rateset_filter(&wlc->band->defrateset,
7944 &wlc->band->hw_rateset, false,
7945 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
7946 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
7950 * update antenna config due to
7951 * wlc->stf->txant/txchain/ant_rx_ovr change
7953 brcms_c_stf_phy_txant_upd(wlc);
7955 /* attach each modules */
7956 err = brcms_c_attach_module(wlc);
7960 if (!brcms_c_timers_init(wlc, unit)) {
7961 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
7967 /* depend on rateset, gmode */
7968 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
7970 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
7971 "\n", unit, __func__);
7976 /* init default when all parameters are ready, i.e. ->rateset */
7977 brcms_c_bss_default_init(wlc);
7980 * Complete the wlc default state initializations..
7983 wlc->bsscfg->wlc = wlc;
7985 wlc->mimoft = FT_HT;
7986 wlc->mimo_40txbw = AUTO;
7987 wlc->ofdm_40txbw = AUTO;
7988 wlc->cck_40txbw = AUTO;
7989 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
7991 /* Set default values of SGI */
7992 if (BRCMS_SGI_CAP_PHY(wlc)) {
7993 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
7995 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
7996 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
7999 brcms_c_ht_update_sgi_rx(wlc, 0);
8002 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8010 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8011 unit, __func__, err);
8013 brcms_c_detach(wlc);