drivers/net/wireless/brcm80211/brcmsmac/main.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  12  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  14  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  15  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/pci_ids.h>
  21 #include <linux/if_ether.h>
  22 #include <net/cfg80211.h>
  23 #include <net/mac80211.h>
  24 #include <brcm_hw_ids.h>
  25 #include <aiutils.h>
  26 #include <chipcommon.h>
  27 #include "rate.h"
  28 #include "scb.h"
  29 #include "phy/phy_hal.h"
  30 #include "channel.h"
  31 #include "antsel.h"
  32 #include "stf.h"
  33 #include "ampdu.h"
  34 #include "mac80211_if.h"
  35 #include "ucode_loader.h"
  36 #include "main.h"
  37 #include "soc.h"
  38 #include "dma.h"
  39 #include "debug.h"
  40 #include "brcms_trace_events.h"
  41
  42 /* watchdog timer, in unit of ms */
  43 #define TIMER_INTERVAL_WATCHDOG         1000
  44 /* radio monitor timer, in unit of ms */
  45 #define TIMER_INTERVAL_RADIOCHK         800
  46
  47 /* beacon interval, in unit of 1024TU */
  48 #define BEACON_INTERVAL_DEFAULT         100
  49
  50 /* n-mode support capability */
  51 /* 2x2 includes both 1x1 & 2x2 devices
  52  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  53  * control it independently
  54  */
  55 #define WL_11N_2x2                      1
  56 #define WL_11N_3x3                      3
  57 #define WL_11N_4x4                      4
  58
  59 #define EDCF_ACI_MASK                   0x60
  60 #define EDCF_ACI_SHIFT                  5
  61 #define EDCF_ECWMIN_MASK                0x0f
  62 #define EDCF_ECWMAX_SHIFT               4
  63 #define EDCF_AIFSN_MASK                 0x0f
  64 #define EDCF_AIFSN_MAX                  15
  65 #define EDCF_ECWMAX_MASK                0xf0
  66
  67 #define EDCF_AC_BE_TXOP_STA             0x0000
  68 #define EDCF_AC_BK_TXOP_STA             0x0000
  69 #define EDCF_AC_VO_ACI_STA              0x62
  70 #define EDCF_AC_VO_ECW_STA              0x32
  71 #define EDCF_AC_VI_ACI_STA              0x42
  72 #define EDCF_AC_VI_ECW_STA              0x43
  73 #define EDCF_AC_BK_ECW_STA              0xA4
  74 #define EDCF_AC_VI_TXOP_STA             0x005e
  75 #define EDCF_AC_VO_TXOP_STA             0x002f
  76 #define EDCF_AC_BE_ACI_STA              0x03
  77 #define EDCF_AC_BE_ECW_STA              0xA4
  78 #define EDCF_AC_BK_ACI_STA              0x27
  79 #define EDCF_AC_VO_TXOP_AP              0x002f
  80
  81 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
  82 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
  83
  84 #define APHY_SYMBOL_TIME                4
  85 #define APHY_PREAMBLE_TIME              16
  86 #define APHY_SIGNAL_TIME                4
  87 #define APHY_SIFS_TIME                  16
  88 #define APHY_SERVICE_NBITS              16
  89 #define APHY_TAIL_NBITS                 6
  90 #define BPHY_SIFS_TIME                  10
  91 #define BPHY_PLCP_SHORT_TIME            96
  92
  93 #define PREN_PREAMBLE                   24
  94 #define PREN_MM_EXT                     12
  95 #define PREN_PREAMBLE_EXT               4
  96
  97 #define DOT11_MAC_HDR_LEN               24
  98 #define DOT11_ACK_LEN                   10
  99 #define DOT11_BA_LEN                    4
 100 #define DOT11_OFDM_SIGNAL_EXTENSION     6
 101 #define DOT11_MIN_FRAG_LEN              256
 102 #define DOT11_RTS_LEN                   16
 103 #define DOT11_CTS_LEN                   10
 104 #define DOT11_BA_BITMAP_LEN             128
 105 #define DOT11_MAXNUMFRAGS               16
 106 #define DOT11_MAX_FRAG_LEN              2346
 107
 108 #define BPHY_PLCP_TIME                  192
 109 #define RIFS_11N_TIME                   2
 110
 111 /* length of the BCN template area */
 112 #define BCN_TMPL_LEN                    512
 113
 114 /* brcms_bss_info flag bit values */
 115 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
 116
 117 /* chip rx buffer offset */
 118 #define BRCMS_HWRXOFF                   38
 119
 120 /* rfdisable delay timer 500 ms, runs of ALP clock */
 121 #define RFDISABLE_DEFAULT               10000000
 122
 123 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
 124
 125 /* synthpu_dly times in us */
 126 #define SYNTHPU_DLY_APHY_US             3700
 127 #define SYNTHPU_DLY_BPHY_US             1050
 128 #define SYNTHPU_DLY_NPHY_US             2048
 129 #define SYNTHPU_DLY_LPPHY_US            300
 130
 131 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
 132
 133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
 134 #define EDCF_SHORT_S                    0
 135 #define EDCF_SFB_S                      4
 136 #define EDCF_LONG_S                     8
 137 #define EDCF_LFB_S                      12
 138 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
 139 #define EDCF_SFB_M                      BITFIELD_MASK(4)
 140 #define EDCF_LONG_M                     BITFIELD_MASK(4)
 141 #define EDCF_LFB_M                      BITFIELD_MASK(4)
 142
 143 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
 144 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
 145 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
 146 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
 147 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
 148
 149 #define APHY_CWMIN                      15
 150 #define PHY_CWMAX                       1023
 151
 152 #define EDCF_AIFSN_MIN                  1
 153
 154 #define FRAGNUM_MASK                    0xF
 155
 156 #define APHY_SLOT_TIME                  9
 157 #define BPHY_SLOT_TIME                  20
 158
 159 #define WL_SPURAVOID_OFF                0
 160 #define WL_SPURAVOID_ON1                1
 161 #define WL_SPURAVOID_ON2                2
 162
 163 /* invalid core flags, use the saved coreflags */
 164 #define BRCMS_USE_COREFLAGS             0xffffffff
 165
 166 /* values for PLCPHdr_override */
 167 #define BRCMS_PLCP_AUTO                 -1
 168 #define BRCMS_PLCP_SHORT                0
 169 #define BRCMS_PLCP_LONG                 1
 170
 171 /* values for g_protection_override and n_protection_override */
 172 #define BRCMS_PROTECTION_AUTO           -1
 173 #define BRCMS_PROTECTION_OFF            0
 174 #define BRCMS_PROTECTION_ON             1
 175 #define BRCMS_PROTECTION_MMHDR_ONLY     2
 176 #define BRCMS_PROTECTION_CTS_ONLY       3
 177
 178 /* values for g_protection_control and n_protection_control */
 179 #define BRCMS_PROTECTION_CTL_OFF        0
 180 #define BRCMS_PROTECTION_CTL_LOCAL      1
 181 #define BRCMS_PROTECTION_CTL_OVERLAP    2
 182
 183 /* values for n_protection */
 184 #define BRCMS_N_PROTECTION_OFF          0
 185 #define BRCMS_N_PROTECTION_OPTIONAL     1
 186 #define BRCMS_N_PROTECTION_20IN40       2
 187 #define BRCMS_N_PROTECTION_MIXEDMODE    3
 188
 189 /* values for band specific 40MHz capabilities */
 190 #define BRCMS_N_BW_20ALL                0
 191 #define BRCMS_N_BW_40ALL                1
 192 #define BRCMS_N_BW_20IN2G_40IN5G        2
 193
 194 /* bitflags for SGI support (sgi_rx iovar) */
 195 #define BRCMS_N_SGI_20                  0x01
 196 #define BRCMS_N_SGI_40                  0x02
 197
 198 /* defines used by the nrate iovar */
 199 /* MSC in use,indicates b0-6 holds an mcs */
 200 #define NRATE_MCS_INUSE                 0x00000080
 201 /* rate/mcs value */
 202 #define NRATE_RATE_MASK                 0x0000007f
 203 /* stf mode mask: siso, cdd, stbc, sdm */
 204 #define NRATE_STF_MASK                  0x0000ff00
 205 /* stf mode shift */
 206 #define NRATE_STF_SHIFT                 8
 207 /* bit indicate to override mcs only */
 208 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
 209 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
 210 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
 211 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
 212 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
 213
 214 #define NRATE_STF_SISO                  0               /* stf mode SISO */
 215 #define NRATE_STF_CDD                   1               /* stf mode CDD */
 216 #define NRATE_STF_STBC                  2               /* stf mode STBC */
 217 #define NRATE_STF_SDM                   3               /* stf mode SDM */
 218
 219 #define MAX_DMA_SEGS                    4
 220
 221 /* # of entries in Tx FIFO */
 222 #define NTXD                            64
 223 /* Max # of entries in Rx FIFO based on 4kb page size */
 224 #define NRXD                            256
 225
 226 /* Amount of headroom to leave in Tx FIFO */
 227 #define TX_HEADROOM                     4
 228
 229 /* try to keep this # rbufs posted to the chip */
 230 #define NRXBUFPOST                      32
 231
 232 /* max # frames to process in brcms_c_recv() */
 233 #define RXBND                           8
 234 /* max # tx status to process in wlc_txstatus() */
 235 #define TXSBND                          8
 236
 237 /* brcmu_format_flags() bit description structure */
 238 struct brcms_c_bit_desc {
 239         u32 bit;
 240         const char *name;
 241 };
 242
 243 /*
 244  * The following table lists the buffer memory allocated to xmt fifos in HW.
 245  * the size is in units of 256bytes(one block), total size is HW dependent
 246  * ucode has default fifo partition, sw can overwrite if necessary
 247  *
 248  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 249  * the twiki is updated before making changes.
 250  */
 251
 252 /* Starting corerev for the fifo size table */
 253 #define XMTFIFOTBL_STARTREV     17
 254
 255 struct d11init {
 256         __le16 addr;
 257         __le16 size;
 258         __le32 value;
 259 };
 260
 261 struct edcf_acparam {
 262         u8 ACI;
 263         u8 ECW;
 264         u16 TXOP;
 265 } __packed;
 266
 267 /* debug/trace */
 268 uint brcm_msg_level;
 269
 270 /* TX FIFO number to WME/802.1E Access Category */
 271 static const u8 wme_fifo2ac[] = {
 272         IEEE80211_AC_BK,
 273         IEEE80211_AC_BE,
 274         IEEE80211_AC_VI,
 275         IEEE80211_AC_VO,
 276         IEEE80211_AC_BE,
 277         IEEE80211_AC_BE
 278 };
 279
 280 /* ieee80211 Access Category to TX FIFO number */
 281 static const u8 wme_ac2fifo[] = {
 282         TX_AC_VO_FIFO,
 283         TX_AC_VI_FIFO,
 284         TX_AC_BE_FIFO,
 285         TX_AC_BK_FIFO
 286 };
 287
 288 static const u16 xmtfifo_sz[][NFIFO] = {
 289         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
 290         {20, 192, 192, 21, 17, 5},
 291         /* corerev 18: */
 292         {0, 0, 0, 0, 0, 0},
 293         /* corerev 19: */
 294         {0, 0, 0, 0, 0, 0},
 295         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 296         {20, 192, 192, 21, 17, 5},
 297         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 298         {9, 58, 22, 14, 14, 5},
 299         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 300         {20, 192, 192, 21, 17, 5},
 301         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 302         {20, 192, 192, 21, 17, 5},
 303         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 304         {9, 58, 22, 14, 14, 5},
 305         /* corerev 25: */
 306         {0, 0, 0, 0, 0, 0},
 307         /* corerev 26: */
 308         {0, 0, 0, 0, 0, 0},
 309         /* corerev 27: */
 310         {0, 0, 0, 0, 0, 0},
 311         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
 312         {9, 58, 22, 14, 14, 5},
 313 };
 314
 315 #ifdef DEBUG
 316 static const char * const fifo_names[] = {
 317         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
 318 #else
 319 static const char fifo_names[6][0];
 320 #endif
 321
 322 #ifdef DEBUG
 323 /* pointer to most recently allocated wl/wlc */
 324 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
 325 #endif
 326
 327 /* Mapping of ieee80211 AC numbers to tx fifos */
 328 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
 329         [IEEE80211_AC_VO]       = TX_AC_VO_FIFO,
 330         [IEEE80211_AC_VI]       = TX_AC_VI_FIFO,
 331         [IEEE80211_AC_BE]       = TX_AC_BE_FIFO,
 332         [IEEE80211_AC_BK]       = TX_AC_BK_FIFO,
 333 };
 334
 335 /* Mapping of tx fifos to ieee80211 AC numbers */
 336 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
 337         [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
 338         [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
 339         [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
 340         [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
 341 };
 342
 343 static u8 brcms_ac_to_fifo(u8 ac)
 344 {
 345         if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
 346                 return TX_AC_BE_FIFO;
 347         return ac_to_fifo_mapping[ac];
 348 }
 349
 350 static u8 brcms_fifo_to_ac(u8 fifo)
 351 {
 352         if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
 353                 return IEEE80211_AC_BE;
 354         return fifo_to_ac_mapping[fifo];
 355 }
 356
 357 /* Find basic rate for a given rate */
 358 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
 359 {
 360         if (is_mcs_rate(rspec))
 361                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
 362                        .leg_ofdm];
 363         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
 364 }
 365
 366 static u16 frametype(u32 rspec, u8 mimoframe)
 367 {
 368         if (is_mcs_rate(rspec))
 369                 return mimoframe;
 370         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
 371 }
 372
 373 /* currently the best mechanism for determining SIFS is the band in use */
 374 static u16 get_sifs(struct brcms_band *band)
 375 {
 376         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
 377                                  BPHY_SIFS_TIME;
 378 }
 379
 380 /*
 381  * Detect Card removed.
 382  * Even checking an sbconfig register read will not false trigger when the core
 383  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
 384  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
 385  * reg with fixed 0/1 pattern (some platforms return all 0).
 386  * If clocks are present, call the sb routine which will figure out if the
 387  * device is removed.
 388  */
 389 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
 390 {
 391         u32 macctrl;
 392
 393         if (!wlc->hw->clk)
 394                 return ai_deviceremoved(wlc->hw->sih);
 395         macctrl = bcma_read32(wlc->hw->d11core,
 396                               D11REGOFFS(maccontrol));
 397         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
 398 }
 399
 400 /* sum the individual fifo tx pending packet counts */
 401 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
 402 {
 403         int i;
 404         int pending = 0;
 405
 406         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
 407                 if (wlc->hw->di[i])
 408                         pending += dma_txpending(wlc->hw->di[i]);
 409         return pending;
 410 }
 411
 412 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
 413 {
 414         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
 415 }
 416
 417 static int brcms_chspec_bw(u16 chanspec)
 418 {
 419         if (CHSPEC_IS40(chanspec))
 420                 return BRCMS_40_MHZ;
 421         if (CHSPEC_IS20(chanspec))
 422                 return BRCMS_20_MHZ;
 423
 424         return BRCMS_10_MHZ;
 425 }
 426
 427 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
 428 {
 429         if (cfg == NULL)
 430                 return;
 431
 432         kfree(cfg->current_bss);
 433         kfree(cfg);
 434 }
 435
 436 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
 437 {
 438         if (wlc == NULL)
 439                 return;
 440
 441         brcms_c_bsscfg_mfree(wlc->bsscfg);
 442         kfree(wlc->pub);
 443         kfree(wlc->modulecb);
 444         kfree(wlc->default_bss);
 445         kfree(wlc->protection);
 446         kfree(wlc->stf);
 447         kfree(wlc->bandstate[0]);
 448         kfree(wlc->corestate->macstat_snapshot);
 449         kfree(wlc->corestate);
 450         kfree(wlc->hw->bandstate[0]);
 451         kfree(wlc->hw);
 452         if (wlc->beacon)
 453                 dev_kfree_skb_any(wlc->beacon);
 454
 455         /* free the wlc */
 456         kfree(wlc);
 457         wlc = NULL;
 458 }
 459
 460 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
 461 {
 462         struct brcms_bss_cfg *cfg;
 463
 464         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
 465         if (cfg == NULL)
 466                 goto fail;
 467
 468         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
 469         if (cfg->current_bss == NULL)
 470                 goto fail;
 471
 472         return cfg;
 473
 474  fail:
 475         brcms_c_bsscfg_mfree(cfg);
 476         return NULL;
 477 }
 478
 479 static struct brcms_c_info *
 480 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
 481 {
 482         struct brcms_c_info *wlc;
 483
 484         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
 485         if (wlc == NULL) {
 486                 *err = 1002;
 487                 goto fail;
 488         }
 489
 490         /* allocate struct brcms_c_pub state structure */
 491         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
 492         if (wlc->pub == NULL) {
 493                 *err = 1003;
 494                 goto fail;
 495         }
 496         wlc->pub->wlc = wlc;
 497
 498         /* allocate struct brcms_hardware state structure */
 499
 500         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
 501         if (wlc->hw == NULL) {
 502                 *err = 1005;
 503                 goto fail;
 504         }
 505         wlc->hw->wlc = wlc;
 506
 507         wlc->hw->bandstate[0] =
 508                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
 509         if (wlc->hw->bandstate[0] == NULL) {
 510                 *err = 1006;
 511                 goto fail;
 512         } else {
 513                 int i;
 514
 515                 for (i = 1; i < MAXBANDS; i++)
 516                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
 517                             ((unsigned long)wlc->hw->bandstate[0] +
 518                              (sizeof(struct brcms_hw_band) * i));
 519         }
 520
 521         wlc->modulecb =
 522                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
 523         if (wlc->modulecb == NULL) {
 524                 *err = 1009;
 525                 goto fail;
 526         }
 527
 528         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
 529         if (wlc->default_bss == NULL) {
 530                 *err = 1010;
 531                 goto fail;
 532         }
 533
 534         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
 535         if (wlc->bsscfg == NULL) {
 536                 *err = 1011;
 537                 goto fail;
 538         }
 539
 540         wlc->protection = kzalloc(sizeof(struct brcms_protection),
 541                                   GFP_ATOMIC);
 542         if (wlc->protection == NULL) {
 543                 *err = 1016;
 544                 goto fail;
 545         }
 546
 547         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
 548         if (wlc->stf == NULL) {
 549                 *err = 1017;
 550                 goto fail;
 551         }
 552
 553         wlc->bandstate[0] =
 554                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
 555         if (wlc->bandstate[0] == NULL) {
 556                 *err = 1025;
 557                 goto fail;
 558         } else {
 559                 int i;
 560
 561                 for (i = 1; i < MAXBANDS; i++)
 562                         wlc->bandstate[i] = (struct brcms_band *)
 563                                 ((unsigned long)wlc->bandstate[0]
 564                                 + (sizeof(struct brcms_band)*i));
 565         }
 566
 567         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
 568         if (wlc->corestate == NULL) {
 569                 *err = 1026;
 570                 goto fail;
 571         }
 572
 573         wlc->corestate->macstat_snapshot =
 574                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
 575         if (wlc->corestate->macstat_snapshot == NULL) {
 576                 *err = 1027;
 577                 goto fail;
 578         }
 579
 580         return wlc;
 581
 582  fail:
 583         brcms_c_detach_mfree(wlc);
 584         return NULL;
 585 }
 586
 587 /*
 588  * Update the slot timing for standard 11b/g (20us slots)
 589  * or shortslot 11g (9us slots)
 590  * The PSM needs to be suspended for this call.
 591  */
 592 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
 593                                         bool shortslot)
 594 {
 595         struct bcma_device *core = wlc_hw->d11core;
 596
 597         if (shortslot) {
 598                 /* 11g short slot: 11a timing */
 599                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
 600                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 601         } else {
 602                 /* 11g long slot: 11b timing */
 603                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
 604                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 605         }
 606 }
 607
 608 /*
 609  * calculate frame duration of a given rate and length, return
 610  * time in usec unit
 611  */
 612 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
 613                                     u8 preamble_type, uint mac_len)
 614 {
 615         uint nsyms, dur = 0, Ndps, kNdps;
 616         uint rate = rspec2rate(ratespec);
 617
 618         if (rate == 0) {
 619                 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
 620                           wlc->pub->unit);
 621                 rate = BRCM_RATE_1M;
 622         }
 623
 624         if (is_mcs_rate(ratespec)) {
 625                 uint mcs = ratespec & RSPEC_RATE_MASK;
 626                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
 627
 628                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
 629                 if (preamble_type == BRCMS_MM_PREAMBLE)
 630                         dur += PREN_MM_EXT;
 631                 /* 1000Ndbps = kbps * 4 */
 632                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
 633                                    rspec_issgi(ratespec)) * 4;
 634
 635                 if (rspec_stc(ratespec) == 0)
 636                         nsyms =
 637                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
 638                                   APHY_TAIL_NBITS) * 1000, kNdps);
 639                 else
 640                         /* STBC needs to have even number of symbols */
 641                         nsyms =
 642                             2 *
 643                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
 644                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
 645
 646                 dur += APHY_SYMBOL_TIME * nsyms;
 647                 if (wlc->band->bandtype == BRCM_BAND_2G)
 648                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
 649         } else if (is_ofdm_rate(rate)) {
 650                 dur = APHY_PREAMBLE_TIME;
 651                 dur += APHY_SIGNAL_TIME;
 652                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
 653                 Ndps = rate * 2;
 654                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
 655                 nsyms =
 656                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
 657                          Ndps);
 658                 dur += APHY_SYMBOL_TIME * nsyms;
 659                 if (wlc->band->bandtype == BRCM_BAND_2G)
 660                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
 661         } else {
 662                 /*
 663                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
 664                  * will divide out
 665                  */
 666                 mac_len = mac_len * 8 * 2;
 667                 /* calc ceiling of bits/rate = microseconds of air time */
 668                 dur = (mac_len + rate - 1) / rate;
 669                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
 670                         dur += BPHY_PLCP_SHORT_TIME;
 671                 else
 672                         dur += BPHY_PLCP_TIME;
 673         }
 674         return dur;
 675 }
 676
 677 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
 678                                 const struct d11init *inits)
 679 {
 680         struct bcma_device *core = wlc_hw->d11core;
 681         int i;
 682         uint offset;
 683         u16 size;
 684         u32 value;
 685
 686         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
 687
 688         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
 689                 size = le16_to_cpu(inits[i].size);
 690                 offset = le16_to_cpu(inits[i].addr);
 691                 value = le32_to_cpu(inits[i].value);
 692                 if (size == 2)
 693                         bcma_write16(core, offset, value);
 694                 else if (size == 4)
 695                         bcma_write32(core, offset, value);
 696                 else
 697                         break;
 698         }
 699 }
 700
 701 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
 702 {
 703         u8 idx;
 704         u16 addr[] = {
 705                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
 706                 M_HOST_FLAGS5
 707         };
 708
 709         for (idx = 0; idx < MHFMAX; idx++)
 710                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
 711 }
 712
 713 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
 714 {
 715         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
 716
 717         /* init microcode host flags */
 718         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 719
 720         /* do band-specific ucode IHR, SHM, and SCR inits */
 721         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
 722                 if (BRCMS_ISNPHY(wlc_hw->band))
 723                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
 724                 else
 725                         brcms_err(wlc_hw->d11core,
 726                                   "%s: wl%d: unsupported phy in corerev %d\n",
 727                                   __func__, wlc_hw->unit,
 728                                   wlc_hw->corerev);
 729         } else {
 730                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 731                         if (BRCMS_ISLCNPHY(wlc_hw->band))
 732                                 brcms_c_write_inits(wlc_hw,
 733                                                     ucode->d11lcn0bsinitvals24);
 734                         else
 735                                 brcms_err(wlc_hw->d11core,
 736                                           "%s: wl%d: unsupported phy in core rev %d\n",
 737                                           __func__, wlc_hw->unit,
 738                                           wlc_hw->corerev);
 739                 } else {
 740                         brcms_err(wlc_hw->d11core,
 741                                   "%s: wl%d: unsupported corerev %d\n",
 742                                   __func__, wlc_hw->unit, wlc_hw->corerev);
 743                 }
 744         }
 745 }
 746
 747 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
 748 {
 749         struct bcma_device *core = wlc_hw->d11core;
 750         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
 751
 752         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
 753 }
 754
 755 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
 756 {
 757         brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
 758
 759         wlc_hw->phyclk = clk;
 760
 761         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
 762
 763                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
 764                                    (SICF_PRST | SICF_FGC));
 765                 udelay(1);
 766                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
 767                 udelay(1);
 768
 769         } else {                /* take phy out of reset */
 770
 771                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
 772                 udelay(1);
 773                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
 774                 udelay(1);
 775
 776         }
 777 }
 778
 779 /* low-level band switch utility routine */
 780 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
 781 {
 782         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
 783                            bandunit);
 784
 785         wlc_hw->band = wlc_hw->bandstate[bandunit];
 786
 787         /*
 788          * BMAC_NOTE:
 789          *   until we eliminate need for wlc->band refs in low level code
 790          */
 791         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
 792
 793         /* set gmode core flag */
 794         if (wlc_hw->sbclk && !wlc_hw->noreset) {
 795                 u32 gmode = 0;
 796
 797                 if (bandunit == 0)
 798                         gmode = SICF_GMODE;
 799
 800                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
 801         }
 802 }
 803
 804 /* switch to new band but leave it inactive */
 805 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
 806 {
 807         struct brcms_hardware *wlc_hw = wlc->hw;
 808         u32 macintmask;
 809         u32 macctrl;
 810
 811         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
 812         macctrl = bcma_read32(wlc_hw->d11core,
 813                               D11REGOFFS(maccontrol));
 814         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
 815
 816         /* disable interrupts */
 817         macintmask = brcms_intrsoff(wlc->wl);
 818
 819         /* radio off */
 820         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 821
 822         brcms_b_core_phy_clk(wlc_hw, OFF);
 823
 824         brcms_c_setxband(wlc_hw, bandunit);
 825
 826         return macintmask;
 827 }
 828
 829 /* process an individual struct tx_status */
 830 static bool
 831 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
 832 {
 833         struct sk_buff *p = NULL;
 834         uint queue = NFIFO;
 835         struct dma_pub *dma = NULL;
 836         struct d11txh *txh = NULL;
 837         struct scb *scb = NULL;
 838         bool free_pdu;
 839         int tx_rts, tx_frame_count, tx_rts_count;
 840         uint totlen, supr_status;
 841         bool lastframe;
 842         struct ieee80211_hdr *h;
 843         u16 mcl;
 844         struct ieee80211_tx_info *tx_info;
 845         struct ieee80211_tx_rate *txrate;
 846         int i;
 847         bool fatal = true;
 848
 849         trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
 850                              txs->frameid, txs->status, txs->lasttxtime,
 851                              txs->sequence, txs->phyerr, txs->ackphyrxsh);
 852
 853         /* discard intermediate indications for ucode with one legitimate case:
 854          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
 855          *   but the subsequent tx of DATA failed. so it will start rts/cts
 856          *   from the beginning (resetting the rts transmission count)
 857          */
 858         if (!(txs->status & TX_STATUS_AMPDU)
 859             && (txs->status & TX_STATUS_INTERMEDIATE)) {
 860                 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
 861                 fatal = false;
 862                 goto out;
 863         }
 864
 865         queue = txs->frameid & TXFID_QUEUE_MASK;
 866         if (queue >= NFIFO) {
 867                 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
 868                 goto out;
 869         }
 870
 871         dma = wlc->hw->di[queue];
 872
 873         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
 874         if (p == NULL) {
 875                 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
 876                 goto out;
 877         }
 878
 879         txh = (struct d11txh *) (p->data);
 880         mcl = le16_to_cpu(txh->MacTxControlLow);
 881
 882         if (txs->phyerr)
 883                 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
 884                           txs->phyerr, txh->MainRates);
 885
 886         if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
 887                 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
 888                 goto out;
 889         }
 890         tx_info = IEEE80211_SKB_CB(p);
 891         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
 892
 893         if (tx_info->rate_driver_data[0])
 894                 scb = &wlc->pri_scb;
 895
 896         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
 897                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
 898                 fatal = false;
 899                 goto out;
 900         }
 901
 902         /*
 903          * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
 904          * frames; this traces them for the rest.
 905          */
 906         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
 907
 908         supr_status = txs->status & TX_STATUS_SUPR_MASK;
 909         if (supr_status == TX_STATUS_SUPR_BADCH) {
 910                 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
 911                 brcms_dbg_tx(wlc->hw->d11core,
 912                              "Pkt tx suppressed, dest chan %u, current %d\n",
 913                              (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
 914                              CHSPEC_CHANNEL(wlc->default_bss->chanspec));
 915         }
 916
 917         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
 918         tx_frame_count =
 919             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
 920         tx_rts_count =
 921             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
 922
 923         lastframe = !ieee80211_has_morefrags(h->frame_control);
 924
 925         if (!lastframe) {
 926                 brcms_err(wlc->hw->d11core, "Not last frame!\n");
 927         } else {
 928                 /*
 929                  * Set information to be consumed by Minstrel ht.
 930                  *
 931                  * The "fallback limit" is the number of tx attempts a given
 932                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
 933                  * limit are sent at the "secondary" rate.
 934                  * A 'short frame' does not exceed RTS treshold.
 935                  */
 936                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
 937                     lfbl,       /* Long Frame Rate Fallback Limit */
 938                     fbl;
 939
 940                 if (queue < IEEE80211_NUM_ACS) {
 941                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
 942                                       EDCF_SFB);
 943                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
 944                                       EDCF_LFB);
 945                 } else {
 946                         sfbl = wlc->SFBL;
 947                         lfbl = wlc->LFBL;
 948                 }
 949
 950                 txrate = tx_info->status.rates;
 951                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
 952                         fbl = lfbl;
 953                 else
 954                         fbl = sfbl;
 955
 956                 ieee80211_tx_info_clear_status(tx_info);
 957
 958                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
 959                         /*
 960                          * rate selection requested a fallback rate
 961                          * and we used it
 962                          */
 963                         txrate[0].count = fbl;
 964                         txrate[1].count = tx_frame_count - fbl;
 965                 } else {
 966                         /*
 967                          * rate selection did not request fallback rate, or
 968                          * we didn't need it
 969                          */
 970                         txrate[0].count = tx_frame_count;
 971                         /*
 972                          * rc80211_minstrel.c:minstrel_tx_status() expects
 973                          * unused rates to be marked with idx = -1
 974                          */
 975                         txrate[1].idx = -1;
 976                         txrate[1].count = 0;
 977                 }
 978
 979                 /* clear the rest of the rates */
 980                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
 981                         txrate[i].idx = -1;
 982                         txrate[i].count = 0;
 983                 }
 984
 985                 if (txs->status & TX_STATUS_ACK_RCV)
 986                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
 987         }
 988
 989         totlen = p->len;
 990         free_pdu = true;
 991
 992         if (lastframe) {
 993                 /* remove PLCP & Broadcom tx descriptor header */
 994                 skb_pull(p, D11_PHY_HDR_LEN);
 995                 skb_pull(p, D11_TXH_LEN);
 996                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
 997         } else {
 998                 brcms_err(wlc->hw->d11core,
 999                           "%s: Not last frame => not calling tx_status\n",
1000                           __func__);
1001         }
1002
1003         fatal = false;
1004
1005  out:
1006         if (fatal) {
1007                 if (txh)
1008                         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1009                                            sizeof(*txh));
1010                 if (p)
1011                         brcmu_pkt_buf_free_skb(p);
1012         }
1013
1014         if (dma && queue < NFIFO) {
1015                 u16 ac_queue = brcms_fifo_to_ac(queue);
1016                 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1017                     ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1018                         ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1019                 dma_kick_tx(dma);
1020         }
1021
1022         return fatal;
1023 }
1024
1025 /* process tx completion events in BMAC
1026  * Return true if more tx status need to be processed. false otherwise.
1027  */
1028 static bool
1029 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1030 {
1031         struct bcma_device *core;
1032         struct tx_status txstatus, *txs;
1033         u32 s1, s2;
1034         uint n = 0;
1035         /*
1036          * Param 'max_tx_num' indicates max. # tx status to process before
1037          * break out.
1038          */
1039         uint max_tx_num = bound ? TXSBND : -1;
1040
1041         txs = &txstatus;
1042         core = wlc_hw->d11core;
1043         *fatal = false;
1044
1045         while (n < max_tx_num) {
1046                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1047                 if (s1 == 0xffffffff) {
1048                         brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1049                                   __func__);
1050                         *fatal = true;
1051                         return false;
1052                 }
1053                 /* only process when valid */
1054                 if (!(s1 & TXS_V))
1055                         break;
1056
1057                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1058                 txs->status = s1 & TXS_STATUS_MASK;
1059                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1060                 txs->sequence = s2 & TXS_SEQ_MASK;
1061                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1062                 txs->lasttxtime = 0;
1063
1064                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1065                 if (*fatal == true)
1066                         return false;
1067                 n++;
1068         }
1069
1070         return n >= max_tx_num;
1071 }
1072
1073 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1074 {
1075         if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1076                 /*
1077                  * DirFrmQ is now valid...defer setting until end
1078                  * of ATIM window
1079                  */
1080                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1081 }
1082
1083 /* set initial host flags value */
1084 static void
1085 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1086 {
1087         struct brcms_hardware *wlc_hw = wlc->hw;
1088
1089         memset(mhfs, 0, MHFMAX * sizeof(u16));
1090
1091         mhfs[MHF2] |= mhf2_init;
1092
1093         /* prohibit use of slowclock on multifunction boards */
1094         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1095                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1096
1097         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1098                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1099                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1100         }
1101 }
1102
1103 static uint
1104 dmareg(uint direction, uint fifonum)
1105 {
1106         if (direction == DMA_TX)
1107                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1108         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1109 }
1110
1111 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1112 {
1113         uint i;
1114         char name[8];
1115         /*
1116          * ucode host flag 2 needed for pio mode, independent of band and fifo
1117          */
1118         u16 pio_mhf2 = 0;
1119         struct brcms_hardware *wlc_hw = wlc->hw;
1120         uint unit = wlc_hw->unit;
1121
1122         /* name and offsets for dma_attach */
1123         snprintf(name, sizeof(name), "wl%d", unit);
1124
1125         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1126                 int dma_attach_err = 0;
1127
1128                 /*
1129                  * FIFO 0
1130                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1131                  * RX: RX_FIFO (RX data packets)
1132                  */
1133                 wlc_hw->di[0] = dma_attach(name, wlc,
1134                                            (wme ? dmareg(DMA_TX, 0) : 0),
1135                                            dmareg(DMA_RX, 0),
1136                                            (wme ? NTXD : 0), NRXD,
1137                                            RXBUFSZ, -1, NRXBUFPOST,
1138                                            BRCMS_HWRXOFF);
1139                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1140
1141                 /*
1142                  * FIFO 1
1143                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1144                  *   (legacy) TX_DATA_FIFO (TX data packets)
1145                  * RX: UNUSED
1146                  */
1147                 wlc_hw->di[1] = dma_attach(name, wlc,
1148                                            dmareg(DMA_TX, 1), 0,
1149                                            NTXD, 0, 0, -1, 0, 0);
1150                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1151
1152                 /*
1153                  * FIFO 2
1154                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1155                  * RX: UNUSED
1156                  */
1157                 wlc_hw->di[2] = dma_attach(name, wlc,
1158                                            dmareg(DMA_TX, 2), 0,
1159                                            NTXD, 0, 0, -1, 0, 0);
1160                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1161                 /*
1162                  * FIFO 3
1163                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1164                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1165                  */
1166                 wlc_hw->di[3] = dma_attach(name, wlc,
1167                                            dmareg(DMA_TX, 3),
1168                                            0, NTXD, 0, 0, -1,
1169                                            0, 0);
1170                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1171 /* Cleaner to leave this as if with AP defined */
1172
1173                 if (dma_attach_err) {
1174                         brcms_err(wlc_hw->d11core,
1175                                   "wl%d: wlc_attach: dma_attach failed\n",
1176                                   unit);
1177                         return false;
1178                 }
1179
1180                 /* get pointer to dma engine tx flow control variable */
1181                 for (i = 0; i < NFIFO; i++)
1182                         if (wlc_hw->di[i])
1183                                 wlc_hw->txavail[i] =
1184                                     (uint *) dma_getvar(wlc_hw->di[i],
1185                                                         "&txavail");
1186         }
1187
1188         /* initial ucode host flags */
1189         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1190
1191         return true;
1192 }
1193
1194 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1195 {
1196         uint j;
1197
1198         for (j = 0; j < NFIFO; j++) {
1199                 if (wlc_hw->di[j]) {
1200                         dma_detach(wlc_hw->di[j]);
1201                         wlc_hw->di[j] = NULL;
1202                 }
1203         }
1204 }
1205
1206 /*
1207  * Initialize brcms_c_info default values ...
1208  * may get overrides later in this function
1209  *  BMAC_NOTES, move low out and resolve the dangling ones
1210  */
1211 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1212 {
1213         struct brcms_c_info *wlc = wlc_hw->wlc;
1214
1215         /* set default sw macintmask value */
1216         wlc->defmacintmask = DEF_MACINTMASK;
1217
1218         /* various 802.11g modes */
1219         wlc_hw->shortslot = false;
1220
1221         wlc_hw->SFBL = RETRY_SHORT_FB;
1222         wlc_hw->LFBL = RETRY_LONG_FB;
1223
1224         /* default mac retry limits */
1225         wlc_hw->SRL = RETRY_SHORT_DEF;
1226         wlc_hw->LRL = RETRY_LONG_DEF;
1227         wlc_hw->chanspec = ch20mhz_chspec(1);
1228 }
1229
1230 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1231 {
1232         /* delay before first read of ucode state */
1233         udelay(40);
1234
1235         /* wait until ucode is no longer asleep */
1236         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1237                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1238 }
1239
1240 /* control chip clock to save power, enable dynamic clock or force fast clock */
1241 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1242 {
1243         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1244                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1245                  * on backplane, but mac core will still run on ALP(not HT) when
1246                  * it enters powersave mode, which means the FCA bit may not be
1247                  * set. Should wakeup mac if driver wants it to run on HT.
1248                  */
1249
1250                 if (wlc_hw->clk) {
1251                         if (mode == BCMA_CLKMODE_FAST) {
1252                                 bcma_set32(wlc_hw->d11core,
1253                                            D11REGOFFS(clk_ctl_st),
1254                                            CCS_FORCEHT);
1255
1256                                 udelay(64);
1257
1258                                 SPINWAIT(
1259                                     ((bcma_read32(wlc_hw->d11core,
1260                                       D11REGOFFS(clk_ctl_st)) &
1261                                       CCS_HTAVAIL) == 0),
1262                                       PMU_MAX_TRANSITION_DLY);
1263                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1264                                         D11REGOFFS(clk_ctl_st)) &
1265                                         CCS_HTAVAIL));
1266                         } else {
1267                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1268                                     (bcma_read32(wlc_hw->d11core,
1269                                         D11REGOFFS(clk_ctl_st)) &
1270                                         (CCS_FORCEHT | CCS_HTAREQ)))
1271                                         SPINWAIT(
1272                                             ((bcma_read32(wlc_hw->d11core,
1273                                               offsetof(struct d11regs,
1274                                                        clk_ctl_st)) &
1275                                               CCS_HTAVAIL) == 0),
1276                                               PMU_MAX_TRANSITION_DLY);
1277                                 bcma_mask32(wlc_hw->d11core,
1278                                         D11REGOFFS(clk_ctl_st),
1279                                         ~CCS_FORCEHT);
1280                         }
1281                 }
1282                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1283         } else {
1284
1285                 /* old chips w/o PMU, force HT through cc,
1286                  * then use FCA to verify mac is running fast clock
1287                  */
1288
1289                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1290
1291                 /* check fast clock is available (if core is not in reset) */
1292                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1293                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1294                                   SISF_FCLKA));
1295
1296                 /*
1297                  * keep the ucode wake bit on if forcefastclk is on since we
1298                  * do not want ucode to put us back to slow clock when it dozes
1299                  * for PM mode. Code below matches the wake override bit with
1300                  * current forcefastclk state. Only setting bit in wake_override
1301                  * instead of waking ucode immediately since old code had this
1302                  * behavior. Older code set wlc->forcefastclk but only had the
1303                  * wake happen if the wakup_ucode work (protected by an up
1304                  * check) was executed just below.
1305                  */
1306                 if (wlc_hw->forcefastclk)
1307                         mboolset(wlc_hw->wake_override,
1308                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1309                 else
1310                         mboolclr(wlc_hw->wake_override,
1311                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1312         }
1313 }
1314
1315 /* set or clear ucode host flag bits
1316  * it has an optimization for no-change write
1317  * it only writes through shared memory when the core has clock;
1318  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1319  *
1320  *
1321  * bands values are: BRCM_BAND_AUTO <--- Current band only
1322  *                   BRCM_BAND_5G   <--- 5G band only
1323  *                   BRCM_BAND_2G   <--- 2G band only
1324  *                   BRCM_BAND_ALL  <--- All bands
1325  */
1326 void
1327 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1328              int bands)
1329 {
1330         u16 save;
1331         u16 addr[MHFMAX] = {
1332                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1333                 M_HOST_FLAGS5
1334         };
1335         struct brcms_hw_band *band;
1336
1337         if ((val & ~mask) || idx >= MHFMAX)
1338                 return; /* error condition */
1339
1340         switch (bands) {
1341                 /* Current band only or all bands,
1342                  * then set the band to current band
1343                  */
1344         case BRCM_BAND_AUTO:
1345         case BRCM_BAND_ALL:
1346                 band = wlc_hw->band;
1347                 break;
1348         case BRCM_BAND_5G:
1349                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1350                 break;
1351         case BRCM_BAND_2G:
1352                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1353                 break;
1354         default:
1355                 band = NULL;    /* error condition */
1356         }
1357
1358         if (band) {
1359                 save = band->mhfs[idx];
1360                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1361
1362                 /* optimization: only write through if changed, and
1363                  * changed band is the current band
1364                  */
1365                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1366                     && (band == wlc_hw->band))
1367                         brcms_b_write_shm(wlc_hw, addr[idx],
1368                                            (u16) band->mhfs[idx]);
1369         }
1370
1371         if (bands == BRCM_BAND_ALL) {
1372                 wlc_hw->bandstate[0]->mhfs[idx] =
1373                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1374                 wlc_hw->bandstate[1]->mhfs[idx] =
1375                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1376         }
1377 }
1378
1379 /* set the maccontrol register to desired reset state and
1380  * initialize the sw cache of the register
1381  */
1382 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1383 {
1384         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1385         wlc_hw->maccontrol = 0;
1386         wlc_hw->suspended_fifos = 0;
1387         wlc_hw->wake_override = 0;
1388         wlc_hw->mute_override = 0;
1389         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1390 }
1391
1392 /*
1393  * write the software state of maccontrol and
1394  * overrides to the maccontrol register
1395  */
1396 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1397 {
1398         u32 maccontrol = wlc_hw->maccontrol;
1399
1400         /* OR in the wake bit if overridden */
1401         if (wlc_hw->wake_override)
1402                 maccontrol |= MCTL_WAKE;
1403
1404         /* set AP and INFRA bits for mute if needed */
1405         if (wlc_hw->mute_override) {
1406                 maccontrol &= ~(MCTL_AP);
1407                 maccontrol |= MCTL_INFRA;
1408         }
1409
1410         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1411                      maccontrol);
1412 }
1413
1414 /* set or clear maccontrol bits */
1415 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1416 {
1417         u32 maccontrol;
1418         u32 new_maccontrol;
1419
1420         if (val & ~mask)
1421                 return; /* error condition */
1422         maccontrol = wlc_hw->maccontrol;
1423         new_maccontrol = (maccontrol & ~mask) | val;
1424
1425         /* if the new maccontrol value is the same as the old, nothing to do */
1426         if (new_maccontrol == maccontrol)
1427                 return;
1428
1429         /* something changed, cache the new value */
1430         wlc_hw->maccontrol = new_maccontrol;
1431
1432         /* write the new values with overrides applied */
1433         brcms_c_mctrl_write(wlc_hw);
1434 }
1435
1436 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1437                                  u32 override_bit)
1438 {
1439         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1440                 mboolset(wlc_hw->wake_override, override_bit);
1441                 return;
1442         }
1443
1444         mboolset(wlc_hw->wake_override, override_bit);
1445
1446         brcms_c_mctrl_write(wlc_hw);
1447         brcms_b_wait_for_wake(wlc_hw);
1448 }
1449
1450 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1451                                    u32 override_bit)
1452 {
1453         mboolclr(wlc_hw->wake_override, override_bit);
1454
1455         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1456                 return;
1457
1458         brcms_c_mctrl_write(wlc_hw);
1459 }
1460
1461 /* When driver needs ucode to stop beaconing, it has to make sure that
1462  * MCTL_AP is clear and MCTL_INFRA is set
1463  * Mode           MCTL_AP        MCTL_INFRA
1464  * AP                1              1
1465  * STA               0              1 <--- This will ensure no beacons
1466  * IBSS              0              0
1467  */
1468 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1469 {
1470         wlc_hw->mute_override = 1;
1471
1472         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1473          * override, then there is no change to write
1474          */
1475         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1476                 return;
1477
1478         brcms_c_mctrl_write(wlc_hw);
1479 }
1480
1481 /* Clear the override on AP and INFRA bits */
1482 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1483 {
1484         if (wlc_hw->mute_override == 0)
1485                 return;
1486
1487         wlc_hw->mute_override = 0;
1488
1489         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1490          * override, then there is no change to write
1491          */
1492         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1493                 return;
1494
1495         brcms_c_mctrl_write(wlc_hw);
1496 }
1497
1498 /*
1499  * Write a MAC address to the given match reg offset in the RXE match engine.
1500  */
1501 static void
1502 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1503                        const u8 *addr)
1504 {
1505         struct bcma_device *core = wlc_hw->d11core;
1506         u16 mac_l;
1507         u16 mac_m;
1508         u16 mac_h;
1509
1510         brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1511
1512         mac_l = addr[0] | (addr[1] << 8);
1513         mac_m = addr[2] | (addr[3] << 8);
1514         mac_h = addr[4] | (addr[5] << 8);
1515
1516         /* enter the MAC addr into the RXE match registers */
1517         bcma_write16(core, D11REGOFFS(rcm_ctl),
1518                      RCM_INC_DATA | match_reg_offset);
1519         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1520         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1521         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1522 }
1523
1524 void
1525 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1526                             void *buf)
1527 {
1528         struct bcma_device *core = wlc_hw->d11core;
1529         u32 word;
1530         __le32 word_le;
1531         __be32 word_be;
1532         bool be_bit;
1533         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1534
1535         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1536
1537         /* if MCTL_BIGEND bit set in mac control register,
1538          * the chip swaps data in fifo, as well as data in
1539          * template ram
1540          */
1541         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1542
1543         while (len > 0) {
1544                 memcpy(&word, buf, sizeof(u32));
1545
1546                 if (be_bit) {
1547                         word_be = cpu_to_be32(word);
1548                         word = *(u32 *)&word_be;
1549                 } else {
1550                         word_le = cpu_to_le32(word);
1551                         word = *(u32 *)&word_le;
1552                 }
1553
1554                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1555
1556                 buf = (u8 *) buf + sizeof(u32);
1557                 len -= sizeof(u32);
1558         }
1559 }
1560
1561 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1562 {
1563         wlc_hw->band->CWmin = newmin;
1564
1565         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1566                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1567         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1568         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1569 }
1570
1571 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1572 {
1573         wlc_hw->band->CWmax = newmax;
1574
1575         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1576                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1577         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1578         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1579 }
1580
1581 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1582 {
1583         bool fastclk;
1584
1585         /* request FAST clock if not on */
1586         fastclk = wlc_hw->forcefastclk;
1587         if (!fastclk)
1588                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1589
1590         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1591
1592         brcms_b_phy_reset(wlc_hw);
1593         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1594
1595         /* restore the clk */
1596         if (!fastclk)
1597                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1598 }
1599
1600 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1601 {
1602         u16 v;
1603         struct brcms_c_info *wlc = wlc_hw->wlc;
1604         /* update SYNTHPU_DLY */
1605
1606         if (BRCMS_ISLCNPHY(wlc->band))
1607                 v = SYNTHPU_DLY_LPPHY_US;
1608         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1609                 v = SYNTHPU_DLY_NPHY_US;
1610         else
1611                 v = SYNTHPU_DLY_BPHY_US;
1612
1613         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1614 }
1615
1616 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1617 {
1618         u16 phyctl;
1619         u16 phytxant = wlc_hw->bmac_phytxant;
1620         u16 mask = PHY_TXC_ANT_MASK;
1621
1622         /* set the Probe Response frame phy control word */
1623         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1624         phyctl = (phyctl & ~mask) | phytxant;
1625         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1626
1627         /* set the Response (ACK/CTS) frame phy control word */
1628         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1629         phyctl = (phyctl & ~mask) | phytxant;
1630         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1631 }
1632
1633 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1634                                          u8 rate)
1635 {
1636         uint i;
1637         u8 plcp_rate = 0;
1638         struct plcp_signal_rate_lookup {
1639                 u8 rate;
1640                 u8 signal_rate;
1641         };
1642         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1643         const struct plcp_signal_rate_lookup rate_lookup[] = {
1644                 {BRCM_RATE_6M, 0xB},
1645                 {BRCM_RATE_9M, 0xF},
1646                 {BRCM_RATE_12M, 0xA},
1647                 {BRCM_RATE_18M, 0xE},
1648                 {BRCM_RATE_24M, 0x9},
1649                 {BRCM_RATE_36M, 0xD},
1650                 {BRCM_RATE_48M, 0x8},
1651                 {BRCM_RATE_54M, 0xC}
1652         };
1653
1654         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1655                 if (rate == rate_lookup[i].rate) {
1656                         plcp_rate = rate_lookup[i].signal_rate;
1657                         break;
1658                 }
1659         }
1660
1661         /* Find the SHM pointer to the rate table entry by looking in the
1662          * Direct-map Table
1663          */
1664         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1665 }
1666
1667 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1668 {
1669         u8 rate;
1670         u8 rates[8] = {
1671                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1672                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1673         };
1674         u16 entry_ptr;
1675         u16 pctl1;
1676         uint i;
1677
1678         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1679                 return;
1680
1681         /* walk the phy rate table and update the entries */
1682         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1683                 rate = rates[i];
1684
1685                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1686
1687                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1688                 pctl1 =
1689                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1690
1691                 /* modify the value */
1692                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1693                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1694
1695                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1696                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1697                                    pctl1);
1698         }
1699 }
1700
1701 /* band-specific init */
1702 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1703 {
1704         struct brcms_hardware *wlc_hw = wlc->hw;
1705
1706         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1707                            wlc_hw->band->bandunit);
1708
1709         brcms_c_ucode_bsinit(wlc_hw);
1710
1711         wlc_phy_init(wlc_hw->band->pi, chanspec);
1712
1713         brcms_c_ucode_txant_set(wlc_hw);
1714
1715         /*
1716          * cwmin is band-specific, update hardware
1717          * with value for current band
1718          */
1719         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1720         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1721
1722         brcms_b_update_slot_timing(wlc_hw,
1723                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1724                                    true : wlc_hw->shortslot);
1725
1726         /* write phytype and phyvers */
1727         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1728         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1729
1730         /*
1731          * initialize the txphyctl1 rate table since
1732          * shmem is shared between bands
1733          */
1734         brcms_upd_ofdm_pctl1_table(wlc_hw);
1735
1736         brcms_b_upd_synthpu(wlc_hw);
1737 }
1738
1739 /* Perform a soft reset of the PHY PLL */
1740 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1741 {
1742         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1743                   ~0, 0);
1744         udelay(1);
1745         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1746                   0x4, 0);
1747         udelay(1);
1748         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1749                   0x4, 4);
1750         udelay(1);
1751         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1752                   0x4, 0);
1753         udelay(1);
1754 }
1755
1756 /* light way to turn on phy clock without reset for NPHY only
1757  *  refer to brcms_b_core_phy_clk for full version
1758  */
1759 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1760 {
1761         /* support(necessary for NPHY and HYPHY) only */
1762         if (!BRCMS_ISNPHY(wlc_hw->band))
1763                 return;
1764
1765         if (ON == clk)
1766                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1767         else
1768                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1769
1770 }
1771
1772 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1773 {
1774         if (ON == clk)
1775                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1776         else
1777                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1778 }
1779
1780 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1781 {
1782         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1783         u32 phy_bw_clkbits;
1784         bool phy_in_reset = false;
1785
1786         brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1787
1788         if (pih == NULL)
1789                 return;
1790
1791         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1792
1793         /* Specific reset sequence required for NPHY rev 3 and 4 */
1794         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1795             NREV_LE(wlc_hw->band->phyrev, 4)) {
1796                 /* Set the PHY bandwidth */
1797                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1798
1799                 udelay(1);
1800
1801                 /* Perform a soft reset of the PHY PLL */
1802                 brcms_b_core_phypll_reset(wlc_hw);
1803
1804                 /* reset the PHY */
1805                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1806                                    (SICF_PRST | SICF_PCLKE));
1807                 phy_in_reset = true;
1808         } else {
1809                 brcms_b_core_ioctl(wlc_hw,
1810                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1811                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1812         }
1813
1814         udelay(2);
1815         brcms_b_core_phy_clk(wlc_hw, ON);
1816
1817         if (pih)
1818                 wlc_phy_anacore(pih, ON);
1819 }
1820
1821 /* switch to and initialize new band */
1822 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1823                             u16 chanspec) {
1824         struct brcms_c_info *wlc = wlc_hw->wlc;
1825         u32 macintmask;
1826
1827         /* Enable the d11 core before accessing it */
1828         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1829                 bcma_core_enable(wlc_hw->d11core, 0);
1830                 brcms_c_mctrl_reset(wlc_hw);
1831         }
1832
1833         macintmask = brcms_c_setband_inact(wlc, bandunit);
1834
1835         if (!wlc_hw->up)
1836                 return;
1837
1838         brcms_b_core_phy_clk(wlc_hw, ON);
1839
1840         /* band-specific initializations */
1841         brcms_b_bsinit(wlc, chanspec);
1842
1843         /*
1844          * If there are any pending software interrupt bits,
1845          * then replace these with a harmless nonzero value
1846          * so brcms_c_dpc() will re-enable interrupts when done.
1847          */
1848         if (wlc->macintstatus)
1849                 wlc->macintstatus = MI_DMAINT;
1850
1851         /* restore macintmask */
1852         brcms_intrsrestore(wlc->wl, macintmask);
1853
1854         /* ucode should still be suspended.. */
1855         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1856                  MCTL_EN_MAC) != 0);
1857 }
1858
1859 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1860 {
1861
1862         /* reject unsupported corerev */
1863         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1864                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1865                           wlc_hw->corerev);
1866                 return false;
1867         }
1868
1869         return true;
1870 }
1871
1872 /* Validate some board info parameters */
1873 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1874 {
1875         uint boardrev = wlc_hw->boardrev;
1876
1877         /* 4 bits each for board type, major, minor, and tiny version */
1878         uint brt = (boardrev & 0xf000) >> 12;
1879         uint b0 = (boardrev & 0xf00) >> 8;
1880         uint b1 = (boardrev & 0xf0) >> 4;
1881         uint b2 = boardrev & 0xf;
1882
1883         /* voards from other vendors are always considered valid */
1884         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1885                 return true;
1886
1887         /* do some boardrev sanity checks when boardvendor is Broadcom */
1888         if (boardrev == 0)
1889                 return false;
1890
1891         if (boardrev <= 0xff)
1892                 return true;
1893
1894         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1895                 || (b2 > 9))
1896                 return false;
1897
1898         return true;
1899 }
1900
1901 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1902 {
1903         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1904
1905         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1906         if (!is_zero_ether_addr(sprom->il0mac)) {
1907                 memcpy(etheraddr, sprom->il0mac, 6);
1908                 return;
1909         }
1910
1911         if (wlc_hw->_nbands > 1)
1912                 memcpy(etheraddr, sprom->et1mac, 6);
1913         else
1914                 memcpy(etheraddr, sprom->il0mac, 6);
1915 }
1916
1917 /* power both the pll and external oscillator on/off */
1918 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1919 {
1920         brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1921
1922         /*
1923          * dont power down if plldown is false or
1924          * we must poll hw radio disable
1925          */
1926         if (!want && wlc_hw->pllreq)
1927                 return;
1928
1929         wlc_hw->sbclk = want;
1930         if (!wlc_hw->sbclk) {
1931                 wlc_hw->clk = false;
1932                 if (wlc_hw->band && wlc_hw->band->pi)
1933                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1934         }
1935 }
1936
1937 /*
1938  * Return true if radio is disabled, otherwise false.
1939  * hw radio disable signal is an external pin, users activate it asynchronously
1940  * this function could be called when driver is down and w/o clock
1941  * it operates on different registers depending on corerev and boardflag.
1942  */
1943 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1944 {
1945         bool v, clk, xtal;
1946         u32 flags = 0;
1947
1948         xtal = wlc_hw->sbclk;
1949         if (!xtal)
1950                 brcms_b_xtal(wlc_hw, ON);
1951
1952         /* may need to take core out of reset first */
1953         clk = wlc_hw->clk;
1954         if (!clk) {
1955                 /*
1956                  * mac no longer enables phyclk automatically when driver
1957                  * accesses phyreg throughput mac. This can be skipped since
1958                  * only mac reg is accessed below
1959                  */
1960                 if (D11REV_GE(wlc_hw->corerev, 18))
1961                         flags |= SICF_PCLKE;
1962
1963                 /*
1964                  * TODO: test suspend/resume
1965                  *
1966                  * AI chip doesn't restore bar0win2 on
1967                  * hibernation/resume, need sw fixup
1968                  */
1969
1970                 bcma_core_enable(wlc_hw->d11core, flags);
1971                 brcms_c_mctrl_reset(wlc_hw);
1972         }
1973
1974         v = ((bcma_read32(wlc_hw->d11core,
1975                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1976
1977         /* put core back into reset */
1978         if (!clk)
1979                 bcma_core_disable(wlc_hw->d11core, 0);
1980
1981         if (!xtal)
1982                 brcms_b_xtal(wlc_hw, OFF);
1983
1984         return v;
1985 }
1986
1987 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1988 {
1989         struct dma_pub *di = wlc_hw->di[fifo];
1990         return dma_rxreset(di);
1991 }
1992
1993 /* d11 core reset
1994  *   ensure fask clock during reset
1995  *   reset dma
1996  *   reset d11(out of reset)
1997  *   reset phy(out of reset)
1998  *   clear software macintstatus for fresh new start
1999  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2000  */
2001 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2002 {
2003         uint i;
2004         bool fastclk;
2005
2006         if (flags == BRCMS_USE_COREFLAGS)
2007                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2008
2009         brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2010
2011         /* request FAST clock if not on  */
2012         fastclk = wlc_hw->forcefastclk;
2013         if (!fastclk)
2014                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2015
2016         /* reset the dma engines except first time thru */
2017         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2018                 for (i = 0; i < NFIFO; i++)
2019                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2020                                 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2021                                           "dma_txreset[%d]: cannot stop dma\n",
2022                                            wlc_hw->unit, __func__, i);
2023
2024                 if ((wlc_hw->di[RX_FIFO])
2025                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2026                         brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2027                                   "[%d]: cannot stop dma\n",
2028                                   wlc_hw->unit, __func__, RX_FIFO);
2029         }
2030         /* if noreset, just stop the psm and return */
2031         if (wlc_hw->noreset) {
2032                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2033                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2034                 return;
2035         }
2036
2037         /*
2038          * mac no longer enables phyclk automatically when driver accesses
2039          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2040          * band->pi is invalid. need to enable PHY CLK
2041          */
2042         if (D11REV_GE(wlc_hw->corerev, 18))
2043                 flags |= SICF_PCLKE;
2044
2045         /*
2046          * reset the core
2047          * In chips with PMU, the fastclk request goes through d11 core
2048          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2049          *
2050          * This adds some delay and we can optimize it by also requesting
2051          * fastclk through chipcommon during this period if necessary. But
2052          * that has to work coordinate with other driver like mips/arm since
2053          * they may touch chipcommon as well.
2054          */
2055         wlc_hw->clk = false;
2056         bcma_core_enable(wlc_hw->d11core, flags);
2057         wlc_hw->clk = true;
2058         if (wlc_hw->band && wlc_hw->band->pi)
2059                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2060
2061         brcms_c_mctrl_reset(wlc_hw);
2062
2063         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2064                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2065
2066         brcms_b_phy_reset(wlc_hw);
2067
2068         /* turn on PHY_PLL */
2069         brcms_b_core_phypll_ctl(wlc_hw, true);
2070
2071         /* clear sw intstatus */
2072         wlc_hw->wlc->macintstatus = 0;
2073
2074         /* restore the clk setting */
2075         if (!fastclk)
2076                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2077 }
2078
2079 /* txfifo sizes needs to be modified(increased) since the newer cores
2080  * have more memory.
2081  */
2082 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2083 {
2084         struct bcma_device *core = wlc_hw->d11core;
2085         u16 fifo_nu;
2086         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2087         u16 txfifo_def, txfifo_def1;
2088         u16 txfifo_cmd;
2089
2090         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2091         txfifo_startblk = TXFIFO_START_BLK;
2092
2093         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2094         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2095
2096                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2097                 txfifo_def = (txfifo_startblk & 0xff) |
2098                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2099                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2100                     ((((txfifo_endblk -
2101                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2102                 txfifo_cmd =
2103                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2104
2105                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2106                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2107                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2108
2109                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2110
2111                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2112         }
2113         /*
2114          * need to propagate to shm location to be in sync since ucode/hw won't
2115          * do this
2116          */
2117         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2118                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2119         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2120                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2121         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2122                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2123                             xmtfifo_sz[TX_AC_BK_FIFO]));
2124         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2125                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2126                             xmtfifo_sz[TX_BCMC_FIFO]));
2127 }
2128
2129 /* This function is used for changing the tsf frac register
2130  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2131  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2132  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2133  * HTPHY Formula is 2^26/freq(MHz) e.g.
2134  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2135  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2136  * For spuron: 123MHz -> 2^26/123    = 545600.5
2137  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2138  * For spur off: 120MHz -> 2^26/120    = 559240.5
2139  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2140  */
2141
2142 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2143 {
2144         struct bcma_device *core = wlc_hw->d11core;
2145
2146         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2147             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2148                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2149                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2150                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2151                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2152                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2153                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2154                 } else {        /* 120Mhz */
2155                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2156                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2157                 }
2158         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2159                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2160                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2161                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2162                 } else {        /* 80Mhz */
2163                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2164                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2165                 }
2166         }
2167 }
2168
2169 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2170 {
2171         memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2172         wlc->bsscfg->type = BRCMS_TYPE_STATION;
2173 }
2174
2175 /* Initialize GPIOs that are controlled by D11 core */
2176 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2177 {
2178         struct brcms_hardware *wlc_hw = wlc->hw;
2179         u32 gc, gm;
2180
2181         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2182         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2183
2184         /*
2185          * Common GPIO setup:
2186          *      G0 = LED 0 = WLAN Activity
2187          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2188          *      G2 = LED 2 = WLAN 5 GHz Radio State
2189          *      G4 = radio disable input (HI enabled, LO disabled)
2190          */
2191
2192         gc = gm = 0;
2193
2194         /* Allocate GPIOs for mimo antenna diversity feature */
2195         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2196                 /* Enable antenna diversity, use 2x3 mode */
2197                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2198                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2199                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2200                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2201
2202                 /* init superswitch control */
2203                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2204
2205         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2206                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2207                 /*
2208                  * The board itself is powered by these GPIOs
2209                  * (when not sending pattern) so set them high
2210                  */
2211                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2212                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2213                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2214                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2215
2216                 /* Enable antenna diversity, use 2x4 mode */
2217                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2218                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2219                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2220                              BRCM_BAND_ALL);
2221
2222                 /* Configure the desired clock to be 4Mhz */
2223                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2224                                    ANTSEL_CLKDIV_4MHZ);
2225         }
2226
2227         /*
2228          * gpio 9 controls the PA. ucode is responsible
2229          * for wiggling out and oe
2230          */
2231         if (wlc_hw->boardflags & BFL_PACTRL)
2232                 gm |= gc |= BOARD_GPIO_PACTRL;
2233
2234         /* apply to gpiocontrol register */
2235         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2236 }
2237
2238 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2239                               const __le32 ucode[], const size_t nbytes)
2240 {
2241         struct bcma_device *core = wlc_hw->d11core;
2242         uint i;
2243         uint count;
2244
2245         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2246
2247         count = (nbytes / sizeof(u32));
2248
2249         bcma_write32(core, D11REGOFFS(objaddr),
2250                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2251         (void)bcma_read32(core, D11REGOFFS(objaddr));
2252         for (i = 0; i < count; i++)
2253                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2254
2255 }
2256
2257 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2258 {
2259         struct brcms_c_info *wlc;
2260         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2261
2262         wlc = wlc_hw->wlc;
2263
2264         if (wlc_hw->ucode_loaded)
2265                 return;
2266
2267         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2268                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2269                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2270                                           ucode->bcm43xx_16_mimosz);
2271                         wlc_hw->ucode_loaded = true;
2272                 } else
2273                         brcms_err(wlc_hw->d11core,
2274                                   "%s: wl%d: unsupported phy in corerev %d\n",
2275                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2276         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2277                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2278                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2279                                           ucode->bcm43xx_24_lcnsz);
2280                         wlc_hw->ucode_loaded = true;
2281                 } else {
2282                         brcms_err(wlc_hw->d11core,
2283                                   "%s: wl%d: unsupported phy in corerev %d\n",
2284                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2285                 }
2286         }
2287 }
2288
2289 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2290 {
2291         /* update sw state */
2292         wlc_hw->bmac_phytxant = phytxant;
2293
2294         /* push to ucode if up */
2295         if (!wlc_hw->up)
2296                 return;
2297         brcms_c_ucode_txant_set(wlc_hw);
2298
2299 }
2300
2301 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2302 {
2303         return (u16) wlc_hw->wlc->stf->txant;
2304 }
2305
2306 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2307 {
2308         wlc_hw->antsel_type = antsel_type;
2309
2310         /* Update the antsel type for phy module to use */
2311         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2312 }
2313
2314 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2315 {
2316         bool fatal = false;
2317         uint unit;
2318         uint intstatus, idx;
2319         struct bcma_device *core = wlc_hw->d11core;
2320
2321         unit = wlc_hw->unit;
2322
2323         for (idx = 0; idx < NFIFO; idx++) {
2324                 /* read intstatus register and ignore any non-error bits */
2325                 intstatus =
2326                         bcma_read32(core,
2327                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2328                         I_ERRORS;
2329                 if (!intstatus)
2330                         continue;
2331
2332                 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2333                               unit, idx, intstatus);
2334
2335                 if (intstatus & I_RO) {
2336                         brcms_err(core, "wl%d: fifo %d: receive fifo "
2337                                   "overflow\n", unit, idx);
2338                         fatal = true;
2339                 }
2340
2341                 if (intstatus & I_PC) {
2342                         brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2343                                   unit, idx);
2344                         fatal = true;
2345                 }
2346
2347                 if (intstatus & I_PD) {
2348                         brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2349                                   idx);
2350                         fatal = true;
2351                 }
2352
2353                 if (intstatus & I_DE) {
2354                         brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2355                                   "error\n", unit, idx);
2356                         fatal = true;
2357                 }
2358
2359                 if (intstatus & I_RU)
2360                         brcms_err(core, "wl%d: fifo %d: receive descriptor "
2361                                   "underflow\n", idx, unit);
2362
2363                 if (intstatus & I_XU) {
2364                         brcms_err(core, "wl%d: fifo %d: transmit fifo "
2365                                   "underflow\n", idx, unit);
2366                         fatal = true;
2367                 }
2368
2369                 if (fatal) {
2370                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2371                         break;
2372                 } else
2373                         bcma_write32(core,
2374                                      D11REGOFFS(intctrlregs[idx].intstatus),
2375                                      intstatus);
2376         }
2377 }
2378
2379 void brcms_c_intrson(struct brcms_c_info *wlc)
2380 {
2381         struct brcms_hardware *wlc_hw = wlc->hw;
2382         wlc->macintmask = wlc->defmacintmask;
2383         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2384 }
2385
2386 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2387 {
2388         struct brcms_hardware *wlc_hw = wlc->hw;
2389         u32 macintmask;
2390
2391         if (!wlc_hw->clk)
2392                 return 0;
2393
2394         macintmask = wlc->macintmask;   /* isr can still happen */
2395
2396         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2397         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2398         udelay(1);              /* ensure int line is no longer driven */
2399         wlc->macintmask = 0;
2400
2401         /* return previous macintmask; resolve race between us and our isr */
2402         return wlc->macintstatus ? 0 : macintmask;
2403 }
2404
2405 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2406 {
2407         struct brcms_hardware *wlc_hw = wlc->hw;
2408         if (!wlc_hw->clk)
2409                 return;
2410
2411         wlc->macintmask = macintmask;
2412         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2413 }
2414
2415 /* assumes that the d11 MAC is enabled */
2416 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2417                                     uint tx_fifo)
2418 {
2419         u8 fifo = 1 << tx_fifo;
2420
2421         /* Two clients of this code, 11h Quiet period and scanning. */
2422
2423         /* only suspend if not already suspended */
2424         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2425                 return;
2426
2427         /* force the core awake only if not already */
2428         if (wlc_hw->suspended_fifos == 0)
2429                 brcms_c_ucode_wake_override_set(wlc_hw,
2430                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2431
2432         wlc_hw->suspended_fifos |= fifo;
2433
2434         if (wlc_hw->di[tx_fifo]) {
2435                 /*
2436                  * Suspending AMPDU transmissions in the middle can cause
2437                  * underflow which may result in mismatch between ucode and
2438                  * driver so suspend the mac before suspending the FIFO
2439                  */
2440                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2441                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2442
2443                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2444
2445                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2446                         brcms_c_enable_mac(wlc_hw->wlc);
2447         }
2448 }
2449
2450 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2451                                    uint tx_fifo)
2452 {
2453         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2454          * but need to be done here for PIO otherwise the watchdog will catch
2455          * the inconsistency and fire
2456          */
2457         /* Two clients of this code, 11h Quiet period and scanning. */
2458         if (wlc_hw->di[tx_fifo])
2459                 dma_txresume(wlc_hw->di[tx_fifo]);
2460
2461         /* allow core to sleep again */
2462         if (wlc_hw->suspended_fifos == 0)
2463                 return;
2464         else {
2465                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2466                 if (wlc_hw->suspended_fifos == 0)
2467                         brcms_c_ucode_wake_override_clear(wlc_hw,
2468                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2469         }
2470 }
2471
2472 /* precondition: requires the mac core to be enabled */
2473 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2474 {
2475         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2476         u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2477
2478         if (mute_tx) {
2479                 /* suspend tx fifos */
2480                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2481                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2482                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2483                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2484
2485                 /* zero the address match register so we do not send ACKs */
2486                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2487         } else {
2488                 /* resume tx fifos */
2489                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2490                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2491                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2492                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2493
2494                 /* Restore address */
2495                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2496         }
2497
2498         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2499
2500         if (mute_tx)
2501                 brcms_c_ucode_mute_override_set(wlc_hw);
2502         else
2503                 brcms_c_ucode_mute_override_clear(wlc_hw);
2504 }
2505
2506 void
2507 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2508 {
2509         brcms_b_mute(wlc->hw, mute_tx);
2510 }
2511
2512 /*
2513  * Read and clear macintmask and macintstatus and intstatus registers.
2514  * This routine should be called with interrupts off
2515  * Return:
2516  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2517  *   0 if the interrupt is not for us, or we are in some special cases;
2518  *   device interrupt status bits otherwise.
2519  */
2520 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2521 {
2522         struct brcms_hardware *wlc_hw = wlc->hw;
2523         struct bcma_device *core = wlc_hw->d11core;
2524         u32 macintstatus, mask;
2525
2526         /* macintstatus includes a DMA interrupt summary bit */
2527         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2528         mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2529
2530         trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2531
2532         /* detect cardbus removed, in power down(suspend) and in reset */
2533         if (brcms_deviceremoved(wlc))
2534                 return -1;
2535
2536         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2537          * handle that case here.
2538          */
2539         if (macintstatus == 0xffffffff)
2540                 return 0;
2541
2542         /* defer unsolicited interrupts */
2543         macintstatus &= mask;
2544
2545         /* if not for us */
2546         if (macintstatus == 0)
2547                 return 0;
2548
2549         /* turn off the interrupts */
2550         bcma_write32(core, D11REGOFFS(macintmask), 0);
2551         (void)bcma_read32(core, D11REGOFFS(macintmask));
2552         wlc->macintmask = 0;
2553
2554         /* clear device interrupts */
2555         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2556
2557         /* MI_DMAINT is indication of non-zero intstatus */
2558         if (macintstatus & MI_DMAINT)
2559                 /*
2560                  * only fifo interrupt enabled is I_RI in
2561                  * RX_FIFO. If MI_DMAINT is set, assume it
2562                  * is set and clear the interrupt.
2563                  */
2564                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2565                              DEF_RXINTMASK);
2566
2567         return macintstatus;
2568 }
2569
2570 /* Update wlc->macintstatus and wlc->intstatus[]. */
2571 /* Return true if they are updated successfully. false otherwise */
2572 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2573 {
2574         u32 macintstatus;
2575
2576         /* read and clear macintstatus and intstatus registers */
2577         macintstatus = wlc_intstatus(wlc, false);
2578
2579         /* device is removed */
2580         if (macintstatus == 0xffffffff)
2581                 return false;
2582
2583         /* update interrupt status in software */
2584         wlc->macintstatus |= macintstatus;
2585
2586         return true;
2587 }
2588
2589 /*
2590  * First-level interrupt processing.
2591  * Return true if this was our interrupt
2592  * and if further brcms_c_dpc() processing is required,
2593  * false otherwise.
2594  */
2595 bool brcms_c_isr(struct brcms_c_info *wlc)
2596 {
2597         struct brcms_hardware *wlc_hw = wlc->hw;
2598         u32 macintstatus;
2599
2600         if (!wlc_hw->up || !wlc->macintmask)
2601                 return false;
2602
2603         /* read and clear macintstatus and intstatus registers */
2604         macintstatus = wlc_intstatus(wlc, true);
2605
2606         if (macintstatus == 0xffffffff) {
2607                 brcms_err(wlc_hw->d11core,
2608                           "DEVICEREMOVED detected in the ISR code path\n");
2609                 return false;
2610         }
2611
2612         /* it is not for us */
2613         if (macintstatus == 0)
2614                 return false;
2615
2616         /* save interrupt status bits */
2617         wlc->macintstatus = macintstatus;
2618
2619         return true;
2620
2621 }
2622
2623 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2624 {
2625         struct brcms_hardware *wlc_hw = wlc->hw;
2626         struct bcma_device *core = wlc_hw->d11core;
2627         u32 mc, mi;
2628
2629         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2630                            wlc_hw->band->bandunit);
2631
2632         /*
2633          * Track overlapping suspend requests
2634          */
2635         wlc_hw->mac_suspend_depth++;
2636         if (wlc_hw->mac_suspend_depth > 1)
2637                 return;
2638
2639         /* force the core awake */
2640         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2641
2642         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2643
2644         if (mc == 0xffffffff) {
2645                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2646                           __func__);
2647                 brcms_down(wlc->wl);
2648                 return;
2649         }
2650         WARN_ON(mc & MCTL_PSM_JMP_0);
2651         WARN_ON(!(mc & MCTL_PSM_RUN));
2652         WARN_ON(!(mc & MCTL_EN_MAC));
2653
2654         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2655         if (mi == 0xffffffff) {
2656                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2657                           __func__);
2658                 brcms_down(wlc->wl);
2659                 return;
2660         }
2661         WARN_ON(mi & MI_MACSSPNDD);
2662
2663         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2664
2665         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2666                  BRCMS_MAX_MAC_SUSPEND);
2667
2668         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2669                 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2670                           " and MI_MACSSPNDD is still not on.\n",
2671                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2672                 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2673                           "psm_brc 0x%04x\n", wlc_hw->unit,
2674                           bcma_read32(core, D11REGOFFS(psmdebug)),
2675                           bcma_read32(core, D11REGOFFS(phydebug)),
2676                           bcma_read16(core, D11REGOFFS(psm_brc)));
2677         }
2678
2679         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2680         if (mc == 0xffffffff) {
2681                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2682                           __func__);
2683                 brcms_down(wlc->wl);
2684                 return;
2685         }
2686         WARN_ON(mc & MCTL_PSM_JMP_0);
2687         WARN_ON(!(mc & MCTL_PSM_RUN));
2688         WARN_ON(mc & MCTL_EN_MAC);
2689 }
2690
2691 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2692 {
2693         struct brcms_hardware *wlc_hw = wlc->hw;
2694         struct bcma_device *core = wlc_hw->d11core;
2695         u32 mc, mi;
2696
2697         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2698                            wlc->band->bandunit);
2699
2700         /*
2701          * Track overlapping suspend requests
2702          */
2703         wlc_hw->mac_suspend_depth--;
2704         if (wlc_hw->mac_suspend_depth > 0)
2705                 return;
2706
2707         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2708         WARN_ON(mc & MCTL_PSM_JMP_0);
2709         WARN_ON(mc & MCTL_EN_MAC);
2710         WARN_ON(!(mc & MCTL_PSM_RUN));
2711
2712         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2713         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2714
2715         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2716         WARN_ON(mc & MCTL_PSM_JMP_0);
2717         WARN_ON(!(mc & MCTL_EN_MAC));
2718         WARN_ON(!(mc & MCTL_PSM_RUN));
2719
2720         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2721         WARN_ON(mi & MI_MACSSPNDD);
2722
2723         brcms_c_ucode_wake_override_clear(wlc_hw,
2724                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2725 }
2726
2727 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2728 {
2729         wlc_hw->hw_stf_ss_opmode = stf_mode;
2730
2731         if (wlc_hw->clk)
2732                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2733 }
2734
2735 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2736 {
2737         struct bcma_device *core = wlc_hw->d11core;
2738         u32 w, val;
2739         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2740
2741         /* Validate dchip register access */
2742
2743         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2744         (void)bcma_read32(core, D11REGOFFS(objaddr));
2745         w = bcma_read32(core, D11REGOFFS(objdata));
2746
2747         /* Can we write and read back a 32bit register? */
2748         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2749         (void)bcma_read32(core, D11REGOFFS(objaddr));
2750         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2751
2752         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753         (void)bcma_read32(core, D11REGOFFS(objaddr));
2754         val = bcma_read32(core, D11REGOFFS(objdata));
2755         if (val != (u32) 0xaa5555aa) {
2756                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2757                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2758                 return false;
2759         }
2760
2761         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2762         (void)bcma_read32(core, D11REGOFFS(objaddr));
2763         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2764
2765         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766         (void)bcma_read32(core, D11REGOFFS(objaddr));
2767         val = bcma_read32(core, D11REGOFFS(objdata));
2768         if (val != (u32) 0x55aaaa55) {
2769                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2770                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2771                 return false;
2772         }
2773
2774         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2775         (void)bcma_read32(core, D11REGOFFS(objaddr));
2776         bcma_write32(core, D11REGOFFS(objdata), w);
2777
2778         /* clear CFPStart */
2779         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2780
2781         w = bcma_read32(core, D11REGOFFS(maccontrol));
2782         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2783             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2784                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2785                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2786                           (MCTL_IHR_EN | MCTL_WAKE),
2787                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2788                 return false;
2789         }
2790
2791         return true;
2792 }
2793
2794 #define PHYPLL_WAIT_US  100000
2795
2796 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2797 {
2798         struct bcma_device *core = wlc_hw->d11core;
2799         u32 tmp;
2800
2801         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2802
2803         tmp = 0;
2804
2805         if (on) {
2806                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2807                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2808                                    CCS_ERSRC_REQ_HT |
2809                                    CCS_ERSRC_REQ_D11PLL |
2810                                    CCS_ERSRC_REQ_PHYPLL);
2811                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2812                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2813                                  PHYPLL_WAIT_US);
2814
2815                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2816                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2817                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2818                                           __func__);
2819                 } else {
2820                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2821                                    tmp | CCS_ERSRC_REQ_D11PLL |
2822                                    CCS_ERSRC_REQ_PHYPLL);
2823                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2824                                   (CCS_ERSRC_AVAIL_D11PLL |
2825                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2826                                  (CCS_ERSRC_AVAIL_D11PLL |
2827                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2828
2829                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2830                         if ((tmp &
2831                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2832                             !=
2833                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2834                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2835                                           __func__);
2836                 }
2837         } else {
2838                 /*
2839                  * Since the PLL may be shared, other cores can still
2840                  * be requesting it; so we'll deassert the request but
2841                  * not wait for status to comply.
2842                  */
2843                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2844                             ~CCS_ERSRC_REQ_PHYPLL);
2845                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2846         }
2847 }
2848
2849 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2850 {
2851         bool dev_gone;
2852
2853         brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2854
2855         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2856
2857         if (dev_gone)
2858                 return;
2859
2860         if (wlc_hw->noreset)
2861                 return;
2862
2863         /* radio off */
2864         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2865
2866         /* turn off analog core */
2867         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2868
2869         /* turn off PHYPLL to save power */
2870         brcms_b_core_phypll_ctl(wlc_hw, false);
2871
2872         wlc_hw->clk = false;
2873         bcma_core_disable(wlc_hw->d11core, 0);
2874         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2875 }
2876
2877 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2878 {
2879         struct brcms_hardware *wlc_hw = wlc->hw;
2880         uint i;
2881
2882         /* free any posted tx packets */
2883         for (i = 0; i < NFIFO; i++) {
2884                 if (wlc_hw->di[i]) {
2885                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2886                         if (i < TX_BCMC_FIFO)
2887                                 ieee80211_wake_queue(wlc->pub->ieee_hw,
2888                                                      brcms_fifo_to_ac(i));
2889                 }
2890         }
2891
2892         /* free any posted rx packets */
2893         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2894 }
2895
2896 static u16
2897 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2898 {
2899         struct bcma_device *core = wlc_hw->d11core;
2900         u16 objoff = D11REGOFFS(objdata);
2901
2902         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2903         (void)bcma_read32(core, D11REGOFFS(objaddr));
2904         if (offset & 2)
2905                 objoff += 2;
2906
2907         return bcma_read16(core, objoff);
2908 }
2909
2910 static void
2911 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2912                      u32 sel)
2913 {
2914         struct bcma_device *core = wlc_hw->d11core;
2915         u16 objoff = D11REGOFFS(objdata);
2916
2917         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2918         (void)bcma_read32(core, D11REGOFFS(objaddr));
2919         if (offset & 2)
2920                 objoff += 2;
2921
2922         bcma_wflush16(core, objoff, v);
2923 }
2924
2925 /*
2926  * Read a single u16 from shared memory.
2927  * SHM 'offset' needs to be an even address
2928  */
2929 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2930 {
2931         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2932 }
2933
2934 /*
2935  * Write a single u16 to shared memory.
2936  * SHM 'offset' needs to be an even address
2937  */
2938 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2939 {
2940         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2941 }
2942
2943 /*
2944  * Copy a buffer to shared memory of specified type .
2945  * SHM 'offset' needs to be an even address and
2946  * Buffer length 'len' must be an even number of bytes
2947  * 'sel' selects the type of memory
2948  */
2949 void
2950 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2951                       const void *buf, int len, u32 sel)
2952 {
2953         u16 v;
2954         const u8 *p = (const u8 *)buf;
2955         int i;
2956
2957         if (len <= 0 || (offset & 1) || (len & 1))
2958                 return;
2959
2960         for (i = 0; i < len; i += 2) {
2961                 v = p[i] | (p[i + 1] << 8);
2962                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2963         }
2964 }
2965
2966 /*
2967  * Copy a piece of shared memory of specified type to a buffer .
2968  * SHM 'offset' needs to be an even address and
2969  * Buffer length 'len' must be an even number of bytes
2970  * 'sel' selects the type of memory
2971  */
2972 void
2973 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2974                          int len, u32 sel)
2975 {
2976         u16 v;
2977         u8 *p = (u8 *) buf;
2978         int i;
2979
2980         if (len <= 0 || (offset & 1) || (len & 1))
2981                 return;
2982
2983         for (i = 0; i < len; i += 2) {
2984                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2985                 p[i] = v & 0xFF;
2986                 p[i + 1] = (v >> 8) & 0xFF;
2987         }
2988 }
2989
2990 /* Copy a buffer to shared memory.
2991  * SHM 'offset' needs to be an even address and
2992  * Buffer length 'len' must be an even number of bytes
2993  */
2994 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2995                         const void *buf, int len)
2996 {
2997         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2998 }
2999
3000 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3001                                    u16 SRL, u16 LRL)
3002 {
3003         wlc_hw->SRL = SRL;
3004         wlc_hw->LRL = LRL;
3005
3006         /* write retry limit to SCR, shouldn't need to suspend */
3007         if (wlc_hw->up) {
3008                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3009                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3010                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3011                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3012                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3013                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3014                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3015                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3016         }
3017 }
3018
3019 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3020 {
3021         if (set) {
3022                 if (mboolisset(wlc_hw->pllreq, req_bit))
3023                         return;
3024
3025                 mboolset(wlc_hw->pllreq, req_bit);
3026
3027                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3028                         if (!wlc_hw->sbclk)
3029                                 brcms_b_xtal(wlc_hw, ON);
3030                 }
3031         } else {
3032                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3033                         return;
3034
3035                 mboolclr(wlc_hw->pllreq, req_bit);
3036
3037                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3038                         if (wlc_hw->sbclk)
3039                                 brcms_b_xtal(wlc_hw, OFF);
3040                 }
3041         }
3042 }
3043
3044 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3045 {
3046         wlc_hw->antsel_avail = antsel_avail;
3047 }
3048
3049 /*
3050  * conditions under which the PM bit should be set in outgoing frames
3051  * and STAY_AWAKE is meaningful
3052  */
3053 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3054 {
3055         /* disallow PS when one of the following global conditions meets */
3056         if (!wlc->pub->associated)
3057                 return false;
3058
3059         /* disallow PS when one of these meets when not scanning */
3060         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3061                 return false;
3062
3063         return true;
3064 }
3065
3066 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3067 {
3068         int i;
3069         struct macstat macstats;
3070 #ifdef DEBUG
3071         u16 delta;
3072         u16 rxf0ovfl;
3073         u16 txfunfl[NFIFO];
3074 #endif                          /* DEBUG */
3075
3076         /* if driver down, make no sense to update stats */
3077         if (!wlc->pub->up)
3078                 return;
3079
3080 #ifdef DEBUG
3081         /* save last rx fifo 0 overflow count */
3082         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3083
3084         /* save last tx fifo  underflow count */
3085         for (i = 0; i < NFIFO; i++)
3086                 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3087 #endif                          /* DEBUG */
3088
3089         /* Read mac stats from contiguous shared memory */
3090         brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3091                                 sizeof(struct macstat), OBJADDR_SHM_SEL);
3092
3093 #ifdef DEBUG
3094         /* check for rx fifo 0 overflow */
3095         delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3096         if (delta)
3097                 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3098                           wlc->pub->unit, delta);
3099
3100         /* check for tx fifo underflows */
3101         for (i = 0; i < NFIFO; i++) {
3102                 delta =
3103                     (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3104                               txfunfl[i]);
3105                 if (delta)
3106                         brcms_err(wlc->hw->d11core,
3107                                   "wl%d: %u tx fifo %d underflows!\n",
3108                                   wlc->pub->unit, delta, i);
3109         }
3110 #endif                          /* DEBUG */
3111
3112         /* merge counters from dma module */
3113         for (i = 0; i < NFIFO; i++) {
3114                 if (wlc->hw->di[i])
3115                         dma_counterreset(wlc->hw->di[i]);
3116         }
3117 }
3118
3119 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3120 {
3121         /* reset the core */
3122         if (!brcms_deviceremoved(wlc_hw->wlc))
3123                 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3124
3125         /* purge the dma rings */
3126         brcms_c_flushqueues(wlc_hw->wlc);
3127 }
3128
3129 void brcms_c_reset(struct brcms_c_info *wlc)
3130 {
3131         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3132
3133         /* slurp up hw mac counters before core reset */
3134         brcms_c_statsupd(wlc);
3135
3136         /* reset our snapshot of macstat counters */
3137         memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3138
3139         brcms_b_reset(wlc->hw);
3140 }
3141
3142 void brcms_c_init_scb(struct scb *scb)
3143 {
3144         int i;
3145
3146         memset(scb, 0, sizeof(struct scb));
3147         scb->flags = SCB_WMECAP | SCB_HTCAP;
3148         for (i = 0; i < NUMPRIO; i++) {
3149                 scb->seqnum[i] = 0;
3150                 scb->seqctl[i] = 0xFFFF;
3151         }
3152
3153         scb->seqctl_nonqos = 0xFFFF;
3154         scb->magic = SCB_MAGIC;
3155 }
3156
3157 /* d11 core init
3158  *   reset PSM
3159  *   download ucode/PCM
3160  *   let ucode run to suspended
3161  *   download ucode inits
3162  *   config other core registers
3163  *   init dma
3164  */
3165 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3166 {
3167         struct brcms_hardware *wlc_hw = wlc->hw;
3168         struct bcma_device *core = wlc_hw->d11core;
3169         u32 sflags;
3170         u32 bcnint_us;
3171         uint i = 0;
3172         bool fifosz_fixup = false;
3173         int err = 0;
3174         u16 buf[NFIFO];
3175         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3176
3177         brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3178
3179         /* reset PSM */
3180         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3181
3182         brcms_ucode_download(wlc_hw);
3183         /*
3184          * FIFOSZ fixup. driver wants to controls the fifo allocation.
3185          */
3186         fifosz_fixup = true;
3187
3188         /* let the PSM run to the suspended state, set mode to BSS STA */
3189         bcma_write32(core, D11REGOFFS(macintstatus), -1);
3190         brcms_b_mctrl(wlc_hw, ~0,
3191                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3192
3193         /* wait for ucode to self-suspend after auto-init */
3194         SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3195                    MI_MACSSPNDD) == 0), 1000 * 1000);
3196         if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3197                 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3198                           "suspend!\n", wlc_hw->unit);
3199
3200         brcms_c_gpio_init(wlc);
3201
3202         sflags = bcma_aread32(core, BCMA_IOST);
3203
3204         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3205                 if (BRCMS_ISNPHY(wlc_hw->band))
3206                         brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3207                 else
3208                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3209                                   " %d\n", __func__, wlc_hw->unit,
3210                                   wlc_hw->corerev);
3211         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3212                 if (BRCMS_ISLCNPHY(wlc_hw->band))
3213                         brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3214                 else
3215                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3216                                   " %d\n", __func__, wlc_hw->unit,
3217                                   wlc_hw->corerev);
3218         } else {
3219                 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3220                           __func__, wlc_hw->unit, wlc_hw->corerev);
3221         }
3222
3223         /* For old ucode, txfifo sizes needs to be modified(increased) */
3224         if (fifosz_fixup)
3225                 brcms_b_corerev_fifofixup(wlc_hw);
3226
3227         /* check txfifo allocations match between ucode and driver */
3228         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3229         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3230                 i = TX_AC_BE_FIFO;
3231                 err = -1;
3232         }
3233         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3234         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3235                 i = TX_AC_VI_FIFO;
3236                 err = -1;
3237         }
3238         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3239         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3240         buf[TX_AC_BK_FIFO] &= 0xff;
3241         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3242                 i = TX_AC_BK_FIFO;
3243                 err = -1;
3244         }
3245         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3246                 i = TX_AC_VO_FIFO;
3247                 err = -1;
3248         }
3249         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3250         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3251         buf[TX_BCMC_FIFO] &= 0xff;
3252         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3253                 i = TX_BCMC_FIFO;
3254                 err = -1;
3255         }
3256         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3257                 i = TX_ATIM_FIFO;
3258                 err = -1;
3259         }
3260         if (err != 0)
3261                 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3262                           " driver size %d index %d\n", buf[i],
3263                           wlc_hw->xmtfifo_sz[i], i);
3264
3265         /* make sure we can still talk to the mac */
3266         WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3267
3268         /* band-specific inits done by wlc_bsinit() */
3269
3270         /* Set up frame burst size and antenna swap threshold init values */
3271         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3272         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3273
3274         /* enable one rx interrupt per received frame */
3275         bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3276
3277         /* set the station mode (BSS STA) */
3278         brcms_b_mctrl(wlc_hw,
3279                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3280                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
3281
3282         /* set up Beacon interval */
3283         bcnint_us = 0x8000 << 10;
3284         bcma_write32(core, D11REGOFFS(tsf_cfprep),
3285                      (bcnint_us << CFPREP_CBI_SHIFT));
3286         bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3287         bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3288
3289         /* write interrupt mask */
3290         bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3291                      DEF_RXINTMASK);
3292
3293         /* allow the MAC to control the PHY clock (dynamic on/off) */
3294         brcms_b_macphyclk_set(wlc_hw, ON);
3295
3296         /* program dynamic clock control fast powerup delay register */
3297         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3298         bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3299
3300         /* tell the ucode the corerev */
3301         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3302
3303         /* tell the ucode MAC capabilities */
3304         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3305                            (u16) (wlc_hw->machwcap & 0xffff));
3306         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3307                            (u16) ((wlc_hw->
3308                                       machwcap >> 16) & 0xffff));
3309
3310         /* write retry limits to SCR, this done after PSM init */
3311         bcma_write32(core, D11REGOFFS(objaddr),
3312                      OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3313         (void)bcma_read32(core, D11REGOFFS(objaddr));
3314         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3315         bcma_write32(core, D11REGOFFS(objaddr),
3316                      OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3317         (void)bcma_read32(core, D11REGOFFS(objaddr));
3318         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3319
3320         /* write rate fallback retry limits */
3321         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3322         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3323
3324         bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3325         bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3326
3327         /* init the tx dma engines */
3328         for (i = 0; i < NFIFO; i++) {
3329                 if (wlc_hw->di[i])
3330                         dma_txinit(wlc_hw->di[i]);
3331         }
3332
3333         /* init the rx dma engine(s) and post receive buffers */
3334         dma_rxinit(wlc_hw->di[RX_FIFO]);
3335         dma_rxfill(wlc_hw->di[RX_FIFO]);
3336 }
3337
3338 void
3339 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3340         u32 macintmask;
3341         bool fastclk;
3342         struct brcms_c_info *wlc = wlc_hw->wlc;
3343
3344         /* request FAST clock if not on */
3345         fastclk = wlc_hw->forcefastclk;
3346         if (!fastclk)
3347                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3348
3349         /* disable interrupts */
3350         macintmask = brcms_intrsoff(wlc->wl);
3351
3352         /* set up the specified band and chanspec */
3353         brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3354         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3355
3356         /* do one-time phy inits and calibration */
3357         wlc_phy_cal_init(wlc_hw->band->pi);
3358
3359         /* core-specific initialization */
3360         brcms_b_coreinit(wlc);
3361
3362         /* band-specific inits */
3363         brcms_b_bsinit(wlc, chanspec);
3364
3365         /* restore macintmask */
3366         brcms_intrsrestore(wlc->wl, macintmask);
3367
3368         /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3369          * is suspended and brcms_c_enable_mac() will clear this override bit.
3370          */
3371         mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3372
3373         /*
3374          * initialize mac_suspend_depth to 1 to match ucode
3375          * initial suspended state
3376          */
3377         wlc_hw->mac_suspend_depth = 1;
3378
3379         /* restore the clk */
3380         if (!fastclk)
3381                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3382 }
3383
3384 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3385                                      u16 chanspec)
3386 {
3387         /* Save our copy of the chanspec */
3388         wlc->chanspec = chanspec;
3389
3390         /* Set the chanspec and power limits for this locale */
3391         brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3392
3393         if (wlc->stf->ss_algosel_auto)
3394                 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3395                                             chanspec);
3396
3397         brcms_c_stf_ss_update(wlc, wlc->band);
3398 }
3399
3400 static void
3401 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3402 {
3403         brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3404                 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3405                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3406                 brcms_chspec_bw(wlc->default_bss->chanspec),
3407                 wlc->stf->txstreams);
3408 }
3409
3410 /* derive wlc->band->basic_rate[] table from 'rateset' */
3411 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3412                               struct brcms_c_rateset *rateset)
3413 {
3414         u8 rate;
3415         u8 mandatory;
3416         u8 cck_basic = 0;
3417         u8 ofdm_basic = 0;
3418         u8 *br = wlc->band->basic_rate;
3419         uint i;
3420
3421         /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3422         memset(br, 0, BRCM_MAXRATE + 1);
3423
3424         /* For each basic rate in the rates list, make an entry in the
3425          * best basic lookup.
3426          */
3427         for (i = 0; i < rateset->count; i++) {
3428                 /* only make an entry for a basic rate */
3429                 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3430                         continue;
3431
3432                 /* mask off basic bit */
3433                 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3434
3435                 if (rate > BRCM_MAXRATE) {
3436                         brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3437                                   "invalid rate 0x%X in rate set\n",
3438                                   rateset->rates[i]);
3439                         continue;
3440                 }
3441
3442                 br[rate] = rate;
3443         }
3444
3445         /* The rate lookup table now has non-zero entries for each
3446          * basic rate, equal to the basic rate: br[basicN] = basicN
3447          *
3448          * To look up the best basic rate corresponding to any
3449          * particular rate, code can use the basic_rate table
3450          * like this
3451          *
3452          * basic_rate = wlc->band->basic_rate[tx_rate]
3453          *
3454          * Make sure there is a best basic rate entry for
3455          * every rate by walking up the table from low rates
3456          * to high, filling in holes in the lookup table
3457          */
3458
3459         for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3460                 rate = wlc->band->hw_rateset.rates[i];
3461
3462                 if (br[rate] != 0) {
3463                         /* This rate is a basic rate.
3464                          * Keep track of the best basic rate so far by
3465                          * modulation type.
3466                          */
3467                         if (is_ofdm_rate(rate))
3468                                 ofdm_basic = rate;
3469                         else
3470                                 cck_basic = rate;
3471
3472                         continue;
3473                 }
3474
3475                 /* This rate is not a basic rate so figure out the
3476                  * best basic rate less than this rate and fill in
3477                  * the hole in the table
3478                  */
3479
3480                 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3481
3482                 if (br[rate] != 0)
3483                         continue;
3484
3485                 if (is_ofdm_rate(rate)) {
3486                         /*
3487                          * In 11g and 11a, the OFDM mandatory rates
3488                          * are 6, 12, and 24 Mbps
3489                          */
3490                         if (rate >= BRCM_RATE_24M)
3491                                 mandatory = BRCM_RATE_24M;
3492                         else if (rate >= BRCM_RATE_12M)
3493                                 mandatory = BRCM_RATE_12M;
3494                         else
3495                                 mandatory = BRCM_RATE_6M;
3496                 } else {
3497                         /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3498                         mandatory = rate;
3499                 }
3500
3501                 br[rate] = mandatory;
3502         }
3503 }
3504
3505 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3506                                      u16 chanspec)
3507 {
3508         struct brcms_c_rateset default_rateset;
3509         uint parkband;
3510         uint i, band_order[2];
3511
3512         /*
3513          * We might have been bandlocked during down and the chip
3514          * power-cycled (hibernate). Figure out the right band to park on
3515          */
3516         if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3517                 /* updated in brcms_c_bandlock() */
3518                 parkband = wlc->band->bandunit;
3519                 band_order[0] = band_order[1] = parkband;
3520         } else {
3521                 /* park on the band of the specified chanspec */
3522                 parkband = chspec_bandunit(chanspec);
3523
3524                 /* order so that parkband initialize last */
3525                 band_order[0] = parkband ^ 1;
3526                 band_order[1] = parkband;
3527         }
3528
3529         /* make each band operational, software state init */
3530         for (i = 0; i < wlc->pub->_nbands; i++) {
3531                 uint j = band_order[i];
3532
3533                 wlc->band = wlc->bandstate[j];
3534
3535                 brcms_default_rateset(wlc, &default_rateset);
3536
3537                 /* fill in hw_rate */
3538                 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3539                                    false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3540                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3541
3542                 /* init basic rate lookup */
3543                 brcms_c_rate_lookup_init(wlc, &default_rateset);
3544         }
3545
3546         /* sync up phy/radio chanspec */
3547         brcms_c_set_phy_chanspec(wlc, chanspec);
3548 }
3549
3550 /*
3551  * Set or clear filtering related maccontrol bits based on
3552  * specified filter flags
3553  */
3554 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3555 {
3556         u32 promisc_bits = 0;
3557
3558         wlc->filter_flags = filter_flags;
3559
3560         if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3561                 promisc_bits |= MCTL_PROMISC;
3562
3563         if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3564                 promisc_bits |= MCTL_BCNS_PROMISC;
3565
3566         if (filter_flags & FIF_FCSFAIL)
3567                 promisc_bits |= MCTL_KEEPBADFCS;
3568
3569         if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3570                 promisc_bits |= MCTL_KEEPCONTROL;
3571
3572         brcms_b_mctrl(wlc->hw,
3573                 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3574                 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3575                 promisc_bits);
3576 }
3577
3578 /*
3579  * ucode, hwmac update
3580  *    Channel dependent updates for ucode and hw
3581  */
3582 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3583 {
3584         /* enable or disable any active IBSSs depending on whether or not
3585          * we are on the home channel
3586          */
3587         if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3588                 if (wlc->pub->associated) {
3589                         /*
3590                          * BMAC_NOTE: This is something that should be fixed
3591                          * in ucode inits. I think that the ucode inits set
3592                          * up the bcn templates and shm values with a bogus
3593                          * beacon. This should not be done in the inits. If
3594                          * ucode needs to set up a beacon for testing, the
3595                          * test routines should write it down, not expect the
3596                          * inits to populate a bogus beacon.
3597                          */
3598                         if (BRCMS_PHY_11N_CAP(wlc->band))
3599                                 brcms_b_write_shm(wlc->hw,
3600                                                 M_BCN_TXTSF_OFFSET, 0);
3601                 }
3602         } else {
3603                 /* disable an active IBSS if we are not on the home channel */
3604         }
3605 }
3606
3607 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3608                                    u8 basic_rate)
3609 {
3610         u8 phy_rate, index;
3611         u8 basic_phy_rate, basic_index;
3612         u16 dir_table, basic_table;
3613         u16 basic_ptr;
3614
3615         /* Shared memory address for the table we are reading */
3616         dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3617
3618         /* Shared memory address for the table we are writing */
3619         basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3620
3621         /*
3622          * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3623          * the index into the rate table.
3624          */
3625         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3626         basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3627         index = phy_rate & 0xf;
3628         basic_index = basic_phy_rate & 0xf;
3629
3630         /* Find the SHM pointer to the ACK rate entry by looking in the
3631          * Direct-map Table
3632          */
3633         basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3634
3635         /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3636          * to the correct basic rate for the given incoming rate
3637          */
3638         brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3639 }
3640
3641 static const struct brcms_c_rateset *
3642 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3643 {
3644         const struct brcms_c_rateset *rs_dflt;
3645
3646         if (BRCMS_PHY_11N_CAP(wlc->band)) {
3647                 if (wlc->band->bandtype == BRCM_BAND_5G)
3648                         rs_dflt = &ofdm_mimo_rates;
3649                 else
3650                         rs_dflt = &cck_ofdm_mimo_rates;
3651         } else if (wlc->band->gmode)
3652                 rs_dflt = &cck_ofdm_rates;
3653         else
3654                 rs_dflt = &cck_rates;
3655
3656         return rs_dflt;
3657 }
3658
3659 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3660 {
3661         const struct brcms_c_rateset *rs_dflt;
3662         struct brcms_c_rateset rs;
3663         u8 rate, basic_rate;
3664         uint i;
3665
3666         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3667
3668         brcms_c_rateset_copy(rs_dflt, &rs);
3669         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3670
3671         /* walk the phy rate table and update SHM basic rate lookup table */
3672         for (i = 0; i < rs.count; i++) {
3673                 rate = rs.rates[i] & BRCMS_RATE_MASK;
3674
3675                 /* for a given rate brcms_basic_rate returns the rate at
3676                  * which a response ACK/CTS should be sent.
3677                  */
3678                 basic_rate = brcms_basic_rate(wlc, rate);
3679                 if (basic_rate == 0)
3680                         /* This should only happen if we are using a
3681                          * restricted rateset.
3682                          */
3683                         basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3684
3685                 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3686         }
3687 }
3688
3689 /* band-specific init */
3690 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3691 {
3692         brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3693                        wlc->pub->unit, wlc->band->bandunit);
3694
3695         /* write ucode ACK/CTS rate table */
3696         brcms_c_set_ratetable(wlc);
3697
3698         /* update some band specific mac configuration */
3699         brcms_c_ucode_mac_upd(wlc);
3700
3701         /* init antenna selection */
3702         brcms_c_antsel_init(wlc->asi);
3703
3704 }
3705
3706 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3707 static int
3708 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3709                    bool writeToShm)
3710 {
3711         int idle_busy_ratio_x_16 = 0;
3712         uint offset =
3713             isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3714             M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3715         if (duty_cycle > 100 || duty_cycle < 0) {
3716                 brcms_err(wlc->hw->d11core,
3717                           "wl%d:  duty cycle value off limit\n",
3718                           wlc->pub->unit);
3719                 return -EINVAL;
3720         }
3721         if (duty_cycle)
3722                 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3723         /* Only write to shared memory  when wl is up */
3724         if (writeToShm)
3725                 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3726
3727         if (isOFDM)
3728                 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3729         else
3730                 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3731
3732         return 0;
3733 }
3734
3735 /* push sw hps and wake state through hardware */
3736 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3737 {
3738         u32 v1, v2;
3739         bool hps;
3740         bool awake_before;
3741
3742         hps = brcms_c_ps_allowed(wlc);
3743
3744         brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3745                            hps);
3746
3747         v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3748         v2 = MCTL_WAKE;
3749         if (hps)
3750                 v2 |= MCTL_HPS;
3751
3752         brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3753
3754         awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3755
3756         if (!awake_before)
3757                 brcms_b_wait_for_wake(wlc->hw);
3758 }
3759
3760 /*
3761  * Write this BSS config's MAC address to core.
3762  * Updates RXE match engine.
3763  */
3764 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3765 {
3766         int err = 0;
3767         struct brcms_c_info *wlc = bsscfg->wlc;
3768
3769         /* enter the MAC addr into the RXE match registers */
3770         brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr);
3771
3772         brcms_c_ampdu_macaddr_upd(wlc);
3773
3774         return err;
3775 }
3776
3777 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3778  * Updates RXE match engine.
3779  */
3780 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3781 {
3782         /* we need to update BSSID in RXE match registers */
3783         brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3784 }
3785
3786 void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len)
3787 {
3788         u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len);
3789         memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID));
3790
3791         memcpy(wlc->bsscfg->SSID, ssid, len);
3792         wlc->bsscfg->SSID_len = len;
3793 }
3794
3795 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3796 {
3797         wlc_hw->shortslot = shortslot;
3798
3799         if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3800                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3801                 brcms_b_update_slot_timing(wlc_hw, shortslot);
3802                 brcms_c_enable_mac(wlc_hw->wlc);
3803         }
3804 }
3805
3806 /*
3807  * Suspend the the MAC and update the slot timing
3808  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3809  */
3810 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3811 {
3812         /* use the override if it is set */
3813         if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3814                 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3815
3816         if (wlc->shortslot == shortslot)
3817                 return;
3818
3819         wlc->shortslot = shortslot;
3820
3821         brcms_b_set_shortslot(wlc->hw, shortslot);
3822 }
3823
3824 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3825 {
3826         if (wlc->home_chanspec != chanspec) {
3827                 wlc->home_chanspec = chanspec;
3828
3829                 if (wlc->pub->associated)
3830                         wlc->bsscfg->current_bss->chanspec = chanspec;
3831         }
3832 }
3833
3834 void
3835 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3836                       bool mute_tx, struct txpwr_limits *txpwr)
3837 {
3838         uint bandunit;
3839
3840         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3841                            chanspec);
3842
3843         wlc_hw->chanspec = chanspec;
3844
3845         /* Switch bands if necessary */
3846         if (wlc_hw->_nbands > 1) {
3847                 bandunit = chspec_bandunit(chanspec);
3848                 if (wlc_hw->band->bandunit != bandunit) {
3849                         /* brcms_b_setband disables other bandunit,
3850                          *  use light band switch if not up yet
3851                          */
3852                         if (wlc_hw->up) {
3853                                 wlc_phy_chanspec_radio_set(wlc_hw->
3854                                                            bandstate[bandunit]->
3855                                                            pi, chanspec);
3856                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
3857                         } else {
3858                                 brcms_c_setxband(wlc_hw, bandunit);
3859                         }
3860                 }
3861         }
3862
3863         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3864
3865         if (!wlc_hw->up) {
3866                 if (wlc_hw->clk)
3867                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3868                                                   chanspec);
3869                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3870         } else {
3871                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3872                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3873
3874                 /* Update muting of the channel */
3875                 brcms_b_mute(wlc_hw, mute_tx);
3876         }
3877 }
3878
3879 /* switch to and initialize new band */
3880 static void brcms_c_setband(struct brcms_c_info *wlc,
3881                                            uint bandunit)
3882 {
3883         wlc->band = wlc->bandstate[bandunit];
3884
3885         if (!wlc->pub->up)
3886                 return;
3887
3888         /* wait for at least one beacon before entering sleeping state */
3889         brcms_c_set_ps_ctrl(wlc);
3890
3891         /* band-specific initializations */
3892         brcms_c_bsinit(wlc);
3893 }
3894
3895 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3896 {
3897         uint bandunit;
3898         bool switchband = false;
3899         u16 old_chanspec = wlc->chanspec;
3900
3901         if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3902                 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3903                           wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3904                 return;
3905         }
3906
3907         /* Switch bands if necessary */
3908         if (wlc->pub->_nbands > 1) {
3909                 bandunit = chspec_bandunit(chanspec);
3910                 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3911                         switchband = true;
3912                         if (wlc->bandlocked) {
3913                                 brcms_err(wlc->hw->d11core,
3914                                           "wl%d: %s: chspec %d band is locked!\n",
3915                                           wlc->pub->unit, __func__,
3916                                           CHSPEC_CHANNEL(chanspec));
3917                                 return;
3918                         }
3919                         /*
3920                          * should the setband call come after the
3921                          * brcms_b_chanspec() ? if the setband updates
3922                          * (brcms_c_bsinit) use low level calls to inspect and
3923                          * set state, the state inspected may be from the wrong
3924                          * band, or the following brcms_b_set_chanspec() may
3925                          * undo the work.
3926                          */
3927                         brcms_c_setband(wlc, bandunit);
3928                 }
3929         }
3930
3931         /* sync up phy/radio chanspec */
3932         brcms_c_set_phy_chanspec(wlc, chanspec);
3933
3934         /* init antenna selection */
3935         if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3936                 brcms_c_antsel_init(wlc->asi);
3937
3938                 /* Fix the hardware rateset based on bw.
3939                  * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3940                  */
3941                 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3942                         wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3943         }
3944
3945         /* update some mac configuration since chanspec changed */
3946         brcms_c_ucode_mac_upd(wlc);
3947 }
3948
3949 /*
3950  * This function changes the phytxctl for beacon based on current
3951  * beacon ratespec AND txant setting as per this table:
3952  *  ratespec     CCK            ant = wlc->stf->txant
3953  *              OFDM            ant = 3
3954  */
3955 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3956                                        u32 bcn_rspec)
3957 {
3958         u16 phyctl;
3959         u16 phytxant = wlc->stf->phytxant;
3960         u16 mask = PHY_TXC_ANT_MASK;
3961
3962         /* for non-siso rates or default setting, use the available chains */
3963         if (BRCMS_PHY_11N_CAP(wlc->band))
3964                 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3965
3966         phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3967         phyctl = (phyctl & ~mask) | phytxant;
3968         brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3969 }
3970
3971 /*
3972  * centralized protection config change function to simplify debugging, no
3973  * consistency checking this should be called only on changes to avoid overhead
3974  * in periodic function
3975  */
3976 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3977 {
3978         /*
3979          * Cannot use brcms_dbg_* here because this function is called
3980          * before wlc is sufficiently initialized.
3981          */
3982         BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3983
3984         switch (idx) {
3985         case BRCMS_PROT_G_SPEC:
3986                 wlc->protection->_g = (bool) val;
3987                 break;
3988         case BRCMS_PROT_G_OVR:
3989                 wlc->protection->g_override = (s8) val;
3990                 break;
3991         case BRCMS_PROT_G_USER:
3992                 wlc->protection->gmode_user = (u8) val;
3993                 break;
3994         case BRCMS_PROT_OVERLAP:
3995                 wlc->protection->overlap = (s8) val;
3996                 break;
3997         case BRCMS_PROT_N_USER:
3998                 wlc->protection->nmode_user = (s8) val;
3999                 break;
4000         case BRCMS_PROT_N_CFG:
4001                 wlc->protection->n_cfg = (s8) val;
4002                 break;
4003         case BRCMS_PROT_N_CFG_OVR:
4004                 wlc->protection->n_cfg_override = (s8) val;
4005                 break;
4006         case BRCMS_PROT_N_NONGF:
4007                 wlc->protection->nongf = (bool) val;
4008                 break;
4009         case BRCMS_PROT_N_NONGF_OVR:
4010                 wlc->protection->nongf_override = (s8) val;
4011                 break;
4012         case BRCMS_PROT_N_PAM_OVR:
4013                 wlc->protection->n_pam_override = (s8) val;
4014                 break;
4015         case BRCMS_PROT_N_OBSS:
4016                 wlc->protection->n_obss = (bool) val;
4017                 break;
4018
4019         default:
4020                 break;
4021         }
4022
4023 }
4024
4025 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4026 {
4027         if (wlc->pub->up) {
4028                 brcms_c_update_beacon(wlc);
4029                 brcms_c_update_probe_resp(wlc, true);
4030         }
4031 }
4032
4033 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4034 {
4035         wlc->stf->ldpc = val;
4036
4037         if (wlc->pub->up) {
4038                 brcms_c_update_beacon(wlc);
4039                 brcms_c_update_probe_resp(wlc, true);
4040                 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4041         }
4042 }
4043
4044 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4045                        const struct ieee80211_tx_queue_params *params,
4046                        bool suspend)
4047 {
4048         int i;
4049         struct shm_acparams acp_shm;
4050         u16 *shm_entry;
4051
4052         /* Only apply params if the core is out of reset and has clocks */
4053         if (!wlc->clk) {
4054                 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4055                           wlc->pub->unit, __func__);
4056                 return;
4057         }
4058
4059         memset(&acp_shm, 0, sizeof(struct shm_acparams));
4060         /* fill in shm ac params struct */
4061         acp_shm.txop = params->txop;
4062         /* convert from units of 32us to us for ucode */
4063         wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4064             EDCF_TXOP2USEC(acp_shm.txop);
4065         acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4066
4067         if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4068             && acp_shm.aifs < EDCF_AIFSN_MAX)
4069                 acp_shm.aifs++;
4070
4071         if (acp_shm.aifs < EDCF_AIFSN_MIN
4072             || acp_shm.aifs > EDCF_AIFSN_MAX) {
4073                 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4074                           "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4075         } else {
4076                 acp_shm.cwmin = params->cw_min;
4077                 acp_shm.cwmax = params->cw_max;
4078                 acp_shm.cwcur = acp_shm.cwmin;
4079                 acp_shm.bslots =
4080                         bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4081                         acp_shm.cwcur;
4082                 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4083                 /* Indicate the new params to the ucode */
4084                 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4085                                                   wme_ac2fifo[aci] *
4086                                                   M_EDCF_QLEN +
4087                                                   M_EDCF_STATUS_OFF));
4088                 acp_shm.status |= WME_STATUS_NEWAC;
4089
4090                 /* Fill in shm acparam table */
4091                 shm_entry = (u16 *) &acp_shm;
4092                 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4093                         brcms_b_write_shm(wlc->hw,
4094                                           M_EDCF_QINFO +
4095                                           wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4096                                           *shm_entry++);
4097         }
4098
4099         if (suspend)
4100                 brcms_c_suspend_mac_and_wait(wlc);
4101
4102         brcms_c_update_beacon(wlc);
4103         brcms_c_update_probe_resp(wlc, false);
4104
4105         if (suspend)
4106                 brcms_c_enable_mac(wlc);
4107 }
4108
4109 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4110 {
4111         u16 aci;
4112         int i_ac;
4113         struct ieee80211_tx_queue_params txq_pars;
4114         static const struct edcf_acparam default_edcf_acparams[] = {
4115                  {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4116                  {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4117                  {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4118                  {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4119         }; /* ucode needs these parameters during its initialization */
4120         const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4121
4122         for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4123                 /* find out which ac this set of params applies to */
4124                 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4125
4126                 /* fill in shm ac params struct */
4127                 txq_pars.txop = edcf_acp->TXOP;
4128                 txq_pars.aifs = edcf_acp->ACI;
4129
4130                 /* CWmin = 2^(ECWmin) - 1 */
4131                 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4132                 /* CWmax = 2^(ECWmax) - 1 */
4133                 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4134                                             >> EDCF_ECWMAX_SHIFT);
4135                 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4136         }
4137
4138         if (suspend) {
4139                 brcms_c_suspend_mac_and_wait(wlc);
4140                 brcms_c_enable_mac(wlc);
4141         }
4142 }
4143
4144 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4145 {
4146         /* Don't start the timer if HWRADIO feature is disabled */
4147         if (wlc->radio_monitor)
4148                 return;
4149
4150         wlc->radio_monitor = true;
4151         brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4152         brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4153 }
4154
4155 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4156 {
4157         if (!wlc->radio_monitor)
4158                 return true;
4159
4160         wlc->radio_monitor = false;
4161         brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4162         return brcms_del_timer(wlc->radio_timer);
4163 }
4164
4165 /* read hwdisable state and propagate to wlc flag */
4166 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4167 {
4168         if (wlc->pub->hw_off)
4169                 return;
4170
4171         if (brcms_b_radio_read_hwdisabled(wlc->hw))
4172                 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4173         else
4174                 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4175 }
4176
4177 /* update hwradio status and return it */
4178 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4179 {
4180         brcms_c_radio_hwdisable_upd(wlc);
4181
4182         return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4183                         true : false;
4184 }
4185
4186 /* periodical query hw radio button while driver is "down" */
4187 static void brcms_c_radio_timer(void *arg)
4188 {
4189         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4190
4191         if (brcms_deviceremoved(wlc)) {
4192                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4193                           wlc->pub->unit, __func__);
4194                 brcms_down(wlc->wl);
4195                 return;
4196         }
4197
4198         brcms_c_radio_hwdisable_upd(wlc);
4199 }
4200
4201 /* common low-level watchdog code */
4202 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4203 {
4204         struct brcms_hardware *wlc_hw = wlc->hw;
4205
4206         if (!wlc_hw->up)
4207                 return;
4208
4209         /* increment second count */
4210         wlc_hw->now++;
4211
4212         /* Check for FIFO error interrupts */
4213         brcms_b_fifoerrors(wlc_hw);
4214
4215         /* make sure RX dma has buffers */
4216         dma_rxfill(wlc->hw->di[RX_FIFO]);
4217
4218         wlc_phy_watchdog(wlc_hw->band->pi);
4219 }
4220
4221 /* common watchdog code */
4222 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4223 {
4224         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4225
4226         if (!wlc->pub->up)
4227                 return;
4228
4229         if (brcms_deviceremoved(wlc)) {
4230                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4231                           wlc->pub->unit, __func__);
4232                 brcms_down(wlc->wl);
4233                 return;
4234         }
4235
4236         /* increment second count */
4237         wlc->pub->now++;
4238
4239         brcms_c_radio_hwdisable_upd(wlc);
4240         /* if radio is disable, driver may be down, quit here */
4241         if (wlc->pub->radio_disabled)
4242                 return;
4243
4244         brcms_b_watchdog(wlc);
4245
4246         /*
4247          * occasionally sample mac stat counters to
4248          * detect 16-bit counter wrap
4249          */
4250         if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4251                 brcms_c_statsupd(wlc);
4252
4253         if (BRCMS_ISNPHY(wlc->band) &&
4254             ((wlc->pub->now - wlc->tempsense_lasttime) >=
4255              BRCMS_TEMPSENSE_PERIOD)) {
4256                 wlc->tempsense_lasttime = wlc->pub->now;
4257                 brcms_c_tempsense_upd(wlc);
4258         }
4259 }
4260
4261 static void brcms_c_watchdog_by_timer(void *arg)
4262 {
4263         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4264
4265         brcms_c_watchdog(wlc);
4266 }
4267
4268 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4269 {
4270         wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4271                 wlc, "watchdog");
4272         if (!wlc->wdtimer) {
4273                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4274                           "failed\n", unit);
4275                 goto fail;
4276         }
4277
4278         wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4279                 wlc, "radio");
4280         if (!wlc->radio_timer) {
4281                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4282                           "failed\n", unit);
4283                 goto fail;
4284         }
4285
4286         return true;
4287
4288  fail:
4289         return false;
4290 }
4291
4292 /*
4293  * Initialize brcms_c_info default values ...
4294  * may get overrides later in this function
4295  */
4296 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4297 {
4298         int i;
4299
4300         /* Save our copy of the chanspec */
4301         wlc->chanspec = ch20mhz_chspec(1);
4302
4303         /* various 802.11g modes */
4304         wlc->shortslot = false;
4305         wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4306
4307         brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4308         brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4309
4310         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4311                                BRCMS_PROTECTION_AUTO);
4312         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4313         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4314                                BRCMS_PROTECTION_AUTO);
4315         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4316         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4317
4318         brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4319                                BRCMS_PROTECTION_CTL_OVERLAP);
4320
4321         /* 802.11g draft 4.0 NonERP elt advertisement */
4322         wlc->include_legacy_erp = true;
4323
4324         wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4325         wlc->stf->txant = ANT_TX_DEF;
4326
4327         wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4328
4329         wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4330         for (i = 0; i < NFIFO; i++)
4331                 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4332         wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4333
4334         /* default rate fallback retry limits */
4335         wlc->SFBL = RETRY_SHORT_FB;
4336         wlc->LFBL = RETRY_LONG_FB;
4337
4338         /* default mac retry limits */
4339         wlc->SRL = RETRY_SHORT_DEF;
4340         wlc->LRL = RETRY_LONG_DEF;
4341
4342         /* WME QoS mode is Auto by default */
4343         wlc->pub->_ampdu = AMPDU_AGG_HOST;
4344 }
4345
4346 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4347 {
4348         uint err = 0;
4349         uint unit;
4350         unit = wlc->pub->unit;
4351
4352         wlc->asi = brcms_c_antsel_attach(wlc);
4353         if (wlc->asi == NULL) {
4354                 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4355                           "failed\n", unit);
4356                 err = 44;
4357                 goto fail;
4358         }
4359
4360         wlc->ampdu = brcms_c_ampdu_attach(wlc);
4361         if (wlc->ampdu == NULL) {
4362                 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4363                           "failed\n", unit);
4364                 err = 50;
4365                 goto fail;
4366         }
4367
4368         if ((brcms_c_stf_attach(wlc) != 0)) {
4369                 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4370                           "failed\n", unit);
4371                 err = 68;
4372                 goto fail;
4373         }
4374  fail:
4375         return err;
4376 }
4377
4378 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4379 {
4380         return wlc->pub;
4381 }
4382
4383 /* low level attach
4384  *    run backplane attach, init nvram
4385  *    run phy attach
4386  *    initialize software state for each core and band
4387  *    put the whole chip in reset(driver down state), no clock
4388  */
4389 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4390                           uint unit, bool piomode)
4391 {
4392         struct brcms_hardware *wlc_hw;
4393         uint err = 0;
4394         uint j;
4395         bool wme = false;
4396         struct shared_phy_params sha_params;
4397         struct wiphy *wiphy = wlc->wiphy;
4398         struct pci_dev *pcidev = core->bus->host_pci;
4399         struct ssb_sprom *sprom = &core->bus->sprom;
4400
4401         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4402                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4403                                pcidev->vendor,
4404                                pcidev->device);
4405         else
4406                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4407                                core->bus->boardinfo.vendor,
4408                                core->bus->boardinfo.type);
4409
4410         wme = true;
4411
4412         wlc_hw = wlc->hw;
4413         wlc_hw->wlc = wlc;
4414         wlc_hw->unit = unit;
4415         wlc_hw->band = wlc_hw->bandstate[0];
4416         wlc_hw->_piomode = piomode;
4417
4418         /* populate struct brcms_hardware with default values  */
4419         brcms_b_info_init(wlc_hw);
4420
4421         /*
4422          * Do the hardware portion of the attach. Also initialize software
4423          * state that depends on the particular hardware we are running.
4424          */
4425         wlc_hw->sih = ai_attach(core->bus);
4426         if (wlc_hw->sih == NULL) {
4427                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4428                           unit);
4429                 err = 11;
4430                 goto fail;
4431         }
4432
4433         /* verify again the device is supported */
4434         if (!brcms_c_chipmatch(core)) {
4435                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4436                          unit);
4437                 err = 12;
4438                 goto fail;
4439         }
4440
4441         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4442                 wlc_hw->vendorid = pcidev->vendor;
4443                 wlc_hw->deviceid = pcidev->device;
4444         } else {
4445                 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4446                 wlc_hw->deviceid = core->bus->boardinfo.type;
4447         }
4448
4449         wlc_hw->d11core = core;
4450         wlc_hw->corerev = core->id.rev;
4451
4452         /* validate chip, chiprev and corerev */
4453         if (!brcms_c_isgoodchip(wlc_hw)) {
4454                 err = 13;
4455                 goto fail;
4456         }
4457
4458         /* initialize power control registers */
4459         ai_clkctl_init(wlc_hw->sih);
4460
4461         /* request fastclock and force fastclock for the rest of attach
4462          * bring the d11 core out of reset.
4463          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4464          *   is still false; But it will be called again inside wlc_corereset,
4465          *   after d11 is out of reset.
4466          */
4467         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4468         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4469
4470         if (!brcms_b_validate_chip_access(wlc_hw)) {
4471                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4472                         "failed\n", unit);
4473                 err = 14;
4474                 goto fail;
4475         }
4476
4477         /* get the board rev, used just below */
4478         j = sprom->board_rev;
4479         /* promote srom boardrev of 0xFF to 1 */
4480         if (j == BOARDREV_PROMOTABLE)
4481                 j = BOARDREV_PROMOTED;
4482         wlc_hw->boardrev = (u16) j;
4483         if (!brcms_c_validboardtype(wlc_hw)) {
4484                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4485                           "board type (0x%x)" " or revision level (0x%x)\n",
4486                           unit, ai_get_boardtype(wlc_hw->sih),
4487                           wlc_hw->boardrev);
4488                 err = 15;
4489                 goto fail;
4490         }
4491         wlc_hw->sromrev = sprom->revision;
4492         wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4493         wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4494
4495         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4496                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4497
4498         /* check device id(srom, nvram etc.) to set bands */
4499         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4500             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4501             wlc_hw->deviceid == BCM43224_CHIP_ID)
4502                 /* Dualband boards */
4503                 wlc_hw->_nbands = 2;
4504         else
4505                 wlc_hw->_nbands = 1;
4506
4507         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4508                 wlc_hw->_nbands = 1;
4509
4510         /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4511          * unconditionally does the init of these values
4512          */
4513         wlc->vendorid = wlc_hw->vendorid;
4514         wlc->deviceid = wlc_hw->deviceid;
4515         wlc->pub->sih = wlc_hw->sih;
4516         wlc->pub->corerev = wlc_hw->corerev;
4517         wlc->pub->sromrev = wlc_hw->sromrev;
4518         wlc->pub->boardrev = wlc_hw->boardrev;
4519         wlc->pub->boardflags = wlc_hw->boardflags;
4520         wlc->pub->boardflags2 = wlc_hw->boardflags2;
4521         wlc->pub->_nbands = wlc_hw->_nbands;
4522
4523         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4524
4525         if (wlc_hw->physhim == NULL) {
4526                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4527                         "failed\n", unit);
4528                 err = 25;
4529                 goto fail;
4530         }
4531
4532         /* pass all the parameters to wlc_phy_shared_attach in one struct */
4533         sha_params.sih = wlc_hw->sih;
4534         sha_params.physhim = wlc_hw->physhim;
4535         sha_params.unit = unit;
4536         sha_params.corerev = wlc_hw->corerev;
4537         sha_params.vid = wlc_hw->vendorid;
4538         sha_params.did = wlc_hw->deviceid;
4539         sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4540         sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4541         sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4542         sha_params.sromrev = wlc_hw->sromrev;
4543         sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4544         sha_params.boardrev = wlc_hw->boardrev;
4545         sha_params.boardflags = wlc_hw->boardflags;
4546         sha_params.boardflags2 = wlc_hw->boardflags2;
4547
4548         /* alloc and save pointer to shared phy state area */
4549         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4550         if (!wlc_hw->phy_sh) {
4551                 err = 16;
4552                 goto fail;
4553         }
4554
4555         /* initialize software state for each core and band */
4556         for (j = 0; j < wlc_hw->_nbands; j++) {
4557                 /*
4558                  * band0 is always 2.4Ghz
4559                  * band1, if present, is 5Ghz
4560                  */
4561
4562                 brcms_c_setxband(wlc_hw, j);
4563
4564                 wlc_hw->band->bandunit = j;
4565                 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4566                 wlc->band->bandunit = j;
4567                 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4568                 wlc->core->coreidx = core->core_index;
4569
4570                 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4571                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4572
4573                 /* init tx fifo size */
4574                 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4575                         (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4576                                 ARRAY_SIZE(xmtfifo_sz));
4577                 wlc_hw->xmtfifo_sz =
4578                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4579                 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4580
4581                 /* Get a phy for this band */
4582                 wlc_hw->band->pi =
4583                         wlc_phy_attach(wlc_hw->phy_sh, core,
4584                                        wlc_hw->band->bandtype,
4585                                        wlc->wiphy);
4586                 if (wlc_hw->band->pi == NULL) {
4587                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4588                                   "attach failed\n", unit);
4589                         err = 17;
4590                         goto fail;
4591                 }
4592
4593                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4594
4595                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4596                                        &wlc_hw->band->phyrev,
4597                                        &wlc_hw->band->radioid,
4598                                        &wlc_hw->band->radiorev);
4599                 wlc_hw->band->abgphy_encore =
4600                     wlc_phy_get_encore(wlc_hw->band->pi);
4601                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4602                 wlc_hw->band->core_flags =
4603                     wlc_phy_get_coreflags(wlc_hw->band->pi);
4604
4605                 /* verify good phy_type & supported phy revision */
4606                 if (BRCMS_ISNPHY(wlc_hw->band)) {
4607                         if (NCONF_HAS(wlc_hw->band->phyrev))
4608                                 goto good_phy;
4609                         else
4610                                 goto bad_phy;
4611                 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4612                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
4613                                 goto good_phy;
4614                         else
4615                                 goto bad_phy;
4616                 } else {
4617  bad_phy:
4618                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4619                                   "phy type/rev (%d/%d)\n", unit,
4620                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
4621                         err = 18;
4622                         goto fail;
4623                 }
4624
4625  good_phy:
4626                 /*
4627                  * BMAC_NOTE: wlc->band->pi should not be set below and should
4628                  * be done in the high level attach. However we can not make
4629                  * that change until all low level access is changed to
4630                  * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4631                  * keeping wlc_hw->band->pi as well for incremental update of
4632                  * low level fns, and cut over low only init when all fns
4633                  * updated.
4634                  */
4635                 wlc->band->pi = wlc_hw->band->pi;
4636                 wlc->band->phytype = wlc_hw->band->phytype;
4637                 wlc->band->phyrev = wlc_hw->band->phyrev;
4638                 wlc->band->radioid = wlc_hw->band->radioid;
4639                 wlc->band->radiorev = wlc_hw->band->radiorev;
4640
4641                 /* default contention windows size limits */
4642                 wlc_hw->band->CWmin = APHY_CWMIN;
4643                 wlc_hw->band->CWmax = PHY_CWMAX;
4644
4645                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4646                         err = 19;
4647                         goto fail;
4648                 }
4649         }
4650
4651         /* disable core to match driver "down" state */
4652         brcms_c_coredisable(wlc_hw);
4653
4654         /* Match driver "down" state */
4655         ai_pci_down(wlc_hw->sih);
4656
4657         /* turn off pll and xtal to match driver "down" state */
4658         brcms_b_xtal(wlc_hw, OFF);
4659
4660         /* *******************************************************************
4661          * The hardware is in the DOWN state at this point. D11 core
4662          * or cores are in reset with clocks off, and the board PLLs
4663          * are off if possible.
4664          *
4665          * Beyond this point, wlc->sbclk == false and chip registers
4666          * should not be touched.
4667          *********************************************************************
4668          */
4669
4670         /* init etheraddr state variables */
4671         brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4672
4673         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4674             is_zero_ether_addr(wlc_hw->etheraddr)) {
4675                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4676                           unit);
4677                 err = 22;
4678                 goto fail;
4679         }
4680
4681         brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4682                        wlc_hw->deviceid, wlc_hw->_nbands,
4683                        ai_get_boardtype(wlc_hw->sih));
4684
4685         return err;
4686
4687  fail:
4688         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4689                   err);
4690         return err;
4691 }
4692
4693 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4694 {
4695         uint unit;
4696         unit = wlc->pub->unit;
4697
4698         if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4699                 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4700                 wlc->band->antgain = 8;
4701         } else if (wlc->band->antgain == -1) {
4702                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4703                           " srom, using 2dB\n", unit, __func__);
4704                 wlc->band->antgain = 8;
4705         } else {
4706                 s8 gain, fract;
4707                 /* Older sroms specified gain in whole dbm only.  In order
4708                  * be able to specify qdbm granularity and remain backward
4709                  * compatible the whole dbms are now encoded in only
4710                  * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4711                  * 6 bit signed number ranges from -32 - 31.
4712                  *
4713                  * Examples:
4714                  * 0x1 = 1 db,
4715                  * 0xc1 = 1.75 db (1 + 3 quarters),
4716                  * 0x3f = -1 (-1 + 0 quarters),
4717                  * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4718                  * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4719                  */
4720                 gain = wlc->band->antgain & 0x3f;
4721                 gain <<= 2;     /* Sign extend */
4722                 gain >>= 2;
4723                 fract = (wlc->band->antgain & 0xc0) >> 6;
4724                 wlc->band->antgain = 4 * gain + fract;
4725         }
4726 }
4727
4728 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4729 {
4730         int aa;
4731         uint unit;
4732         int bandtype;
4733         struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4734
4735         unit = wlc->pub->unit;
4736         bandtype = wlc->band->bandtype;
4737
4738         /* get antennas available */
4739         if (bandtype == BRCM_BAND_5G)
4740                 aa = sprom->ant_available_a;
4741         else
4742                 aa = sprom->ant_available_bg;
4743
4744         if ((aa < 1) || (aa > 15)) {
4745                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4746                           " srom (0x%x), using 3\n", unit, __func__, aa);
4747                 aa = 3;
4748         }
4749
4750         /* reset the defaults if we have a single antenna */
4751         if (aa == 1) {
4752                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4753                 wlc->stf->txant = ANT_TX_FORCE_0;
4754         } else if (aa == 2) {
4755                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4756                 wlc->stf->txant = ANT_TX_FORCE_1;
4757         } else {
4758         }
4759
4760         /* Compute Antenna Gain */
4761         if (bandtype == BRCM_BAND_5G)
4762                 wlc->band->antgain = sprom->antenna_gain.a1;
4763         else
4764                 wlc->band->antgain = sprom->antenna_gain.a0;
4765
4766         brcms_c_attach_antgain_init(wlc);
4767
4768         return true;
4769 }
4770
4771 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4772 {
4773         u16 chanspec;
4774         struct brcms_band *band;
4775         struct brcms_bss_info *bi = wlc->default_bss;
4776
4777         /* init default and target BSS with some sane initial values */
4778         memset(bi, 0, sizeof(*bi));
4779         bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4780
4781         /* fill the default channel as the first valid channel
4782          * starting from the 2G channels
4783          */
4784         chanspec = ch20mhz_chspec(1);
4785         wlc->home_chanspec = bi->chanspec = chanspec;
4786
4787         /* find the band of our default channel */
4788         band = wlc->band;
4789         if (wlc->pub->_nbands > 1 &&
4790             band->bandunit != chspec_bandunit(chanspec))
4791                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4792
4793         /* init bss rates to the band specific default rate set */
4794         brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4795                 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4796                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4797                 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4798
4799         if (wlc->pub->_n_enab & SUPPORT_11N)
4800                 bi->flags |= BRCMS_BSS_HT;
4801 }
4802
4803 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4804 {
4805         uint i;
4806         struct brcms_band *band;
4807
4808         for (i = 0; i < wlc->pub->_nbands; i++) {
4809                 band = wlc->bandstate[i];
4810                 if (band->bandtype == BRCM_BAND_5G) {
4811                         if ((bwcap == BRCMS_N_BW_40ALL)
4812                             || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4813                                 band->mimo_cap_40 = true;
4814                         else
4815                                 band->mimo_cap_40 = false;
4816                 } else {
4817                         if (bwcap == BRCMS_N_BW_40ALL)
4818                                 band->mimo_cap_40 = true;
4819                         else
4820                                 band->mimo_cap_40 = false;
4821                 }
4822         }
4823 }
4824
4825 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4826 {
4827         /* free timer state */
4828         if (wlc->wdtimer) {
4829                 brcms_free_timer(wlc->wdtimer);
4830                 wlc->wdtimer = NULL;
4831         }
4832         if (wlc->radio_timer) {
4833                 brcms_free_timer(wlc->radio_timer);
4834                 wlc->radio_timer = NULL;
4835         }
4836 }
4837
4838 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4839 {
4840         if (wlc->asi) {
4841                 brcms_c_antsel_detach(wlc->asi);
4842                 wlc->asi = NULL;
4843         }
4844
4845         if (wlc->ampdu) {
4846                 brcms_c_ampdu_detach(wlc->ampdu);
4847                 wlc->ampdu = NULL;
4848         }
4849
4850         brcms_c_stf_detach(wlc);
4851 }
4852
4853 /*
4854  * low level detach
4855  */
4856 static int brcms_b_detach(struct brcms_c_info *wlc)
4857 {
4858         uint i;
4859         struct brcms_hw_band *band;
4860         struct brcms_hardware *wlc_hw = wlc->hw;
4861         int callbacks;
4862
4863         callbacks = 0;
4864
4865         brcms_b_detach_dmapio(wlc_hw);
4866
4867         band = wlc_hw->band;
4868         for (i = 0; i < wlc_hw->_nbands; i++) {
4869                 if (band->pi) {
4870                         /* Detach this band's phy */
4871                         wlc_phy_detach(band->pi);
4872                         band->pi = NULL;
4873                 }
4874                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4875         }
4876
4877         /* Free shared phy state */
4878         kfree(wlc_hw->phy_sh);
4879
4880         wlc_phy_shim_detach(wlc_hw->physhim);
4881
4882         if (wlc_hw->sih) {
4883                 ai_detach(wlc_hw->sih);
4884                 wlc_hw->sih = NULL;
4885         }
4886
4887         return callbacks;
4888
4889 }
4890
4891 /*
4892  * Return a count of the number of driver callbacks still pending.
4893  *
4894  * General policy is that brcms_c_detach can only dealloc/free software states.
4895  * It can NOT touch hardware registers since the d11core may be in reset and
4896  * clock may not be available.
4897  * One exception is sb register access, which is possible if crystal is turned
4898  * on after "down" state, driver should avoid software timer with the exception
4899  * of radio_monitor.
4900  */
4901 uint brcms_c_detach(struct brcms_c_info *wlc)
4902 {
4903         uint callbacks = 0;
4904
4905         if (wlc == NULL)
4906                 return 0;
4907
4908         callbacks += brcms_b_detach(wlc);
4909
4910         /* delete software timers */
4911         if (!brcms_c_radio_monitor_stop(wlc))
4912                 callbacks++;
4913
4914         brcms_c_channel_mgr_detach(wlc->cmi);
4915
4916         brcms_c_timers_deinit(wlc);
4917
4918         brcms_c_detach_module(wlc);
4919
4920         brcms_c_detach_mfree(wlc);
4921         return callbacks;
4922 }
4923
4924 /* update state that depends on the current value of "ap" */
4925 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4926 {
4927         /* STA-BSS; short capable */
4928         wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4929 }
4930
4931 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4932 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4933 {
4934         if (wlc_hw->wlc->pub->hw_up)
4935                 return;
4936
4937         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4938
4939         /*
4940          * Enable pll and xtal, initialize the power control registers,
4941          * and force fastclock for the remainder of brcms_c_up().
4942          */
4943         brcms_b_xtal(wlc_hw, ON);
4944         ai_clkctl_init(wlc_hw->sih);
4945         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4946
4947         /*
4948          * TODO: test suspend/resume
4949          *
4950          * AI chip doesn't restore bar0win2 on
4951          * hibernation/resume, need sw fixup
4952          */
4953
4954         /*
4955          * Inform phy that a POR reset has occurred so
4956          * it does a complete phy init
4957          */
4958         wlc_phy_por_inform(wlc_hw->band->pi);
4959
4960         wlc_hw->ucode_loaded = false;
4961         wlc_hw->wlc->pub->hw_up = true;
4962
4963         if ((wlc_hw->boardflags & BFL_FEM)
4964             && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4965                 if (!
4966                     (wlc_hw->boardrev >= 0x1250
4967                      && (wlc_hw->boardflags & BFL_FEM_BT)))
4968                         ai_epa_4313war(wlc_hw->sih);
4969         }
4970 }
4971
4972 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4973 {
4974         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4975
4976         /*
4977          * Enable pll and xtal, initialize the power control registers,
4978          * and force fastclock for the remainder of brcms_c_up().
4979          */
4980         brcms_b_xtal(wlc_hw, ON);
4981         ai_clkctl_init(wlc_hw->sih);
4982         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4983
4984         /*
4985          * Configure pci/pcmcia here instead of in brcms_c_attach()
4986          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
4987          */
4988         bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4989                               true);
4990
4991         /*
4992          * Need to read the hwradio status here to cover the case where the
4993          * system is loaded with the hw radio disabled. We do not want to
4994          * bring the driver up in this case.
4995          */
4996         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4997                 /* put SB PCI in down state again */
4998                 ai_pci_down(wlc_hw->sih);
4999                 brcms_b_xtal(wlc_hw, OFF);
5000                 return -ENOMEDIUM;
5001         }
5002
5003         ai_pci_up(wlc_hw->sih);
5004
5005         /* reset the d11 core */
5006         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5007
5008         return 0;
5009 }
5010
5011 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5012 {
5013         wlc_hw->up = true;
5014         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5015
5016         /* FULLY enable dynamic power control and d11 core interrupt */
5017         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5018         brcms_intrson(wlc_hw->wlc->wl);
5019         return 0;
5020 }
5021
5022 /*
5023  * Write WME tunable parameters for retransmit/max rate
5024  * from wlc struct to ucode
5025  */
5026 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5027 {
5028         int ac;
5029
5030         /* Need clock to do this */
5031         if (!wlc->clk)
5032                 return;
5033
5034         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5035                 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5036                                   wlc->wme_retries[ac]);
5037 }
5038
5039 /* make interface operational */
5040 int brcms_c_up(struct brcms_c_info *wlc)
5041 {
5042         struct ieee80211_channel *ch;
5043
5044         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5045
5046         /* HW is turned off so don't try to access it */
5047         if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5048                 return -ENOMEDIUM;
5049
5050         if (!wlc->pub->hw_up) {
5051                 brcms_b_hw_up(wlc->hw);
5052                 wlc->pub->hw_up = true;
5053         }
5054
5055         if ((wlc->pub->boardflags & BFL_FEM)
5056             && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5057                 if (wlc->pub->boardrev >= 0x1250
5058                     && (wlc->pub->boardflags & BFL_FEM_BT))
5059                         brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5060                                 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5061                 else
5062                         brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5063                                     MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5064         }
5065
5066         /*
5067          * Need to read the hwradio status here to cover the case where the
5068          * system is loaded with the hw radio disabled. We do not want to bring
5069          * the driver up in this case. If radio is disabled, abort up, lower
5070          * power, start radio timer and return 0(for NDIS) don't call
5071          * radio_update to avoid looping brcms_c_up.
5072          *
5073          * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5074          */
5075         if (!wlc->pub->radio_disabled) {
5076                 int status = brcms_b_up_prep(wlc->hw);
5077                 if (status == -ENOMEDIUM) {
5078                         if (!mboolisset
5079                             (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5080                                 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5081                                 mboolset(wlc->pub->radio_disabled,
5082                                          WL_RADIO_HW_DISABLE);
5083                                 if (bsscfg->type == BRCMS_TYPE_STATION ||
5084                                     bsscfg->type == BRCMS_TYPE_ADHOC)
5085                                         brcms_err(wlc->hw->d11core,
5086                                                   "wl%d: up: rfdisable -> "
5087                                                   "bsscfg_disable()\n",
5088                                                    wlc->pub->unit);
5089                         }
5090                 }
5091         }
5092
5093         if (wlc->pub->radio_disabled) {
5094                 brcms_c_radio_monitor_start(wlc);
5095                 return 0;
5096         }
5097
5098         /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5099         wlc->clk = true;
5100
5101         brcms_c_radio_monitor_stop(wlc);
5102
5103         /* Set EDCF hostflags */
5104         brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5105
5106         brcms_init(wlc->wl);
5107         wlc->pub->up = true;
5108
5109         if (wlc->bandinit_pending) {
5110                 ch = wlc->pub->ieee_hw->conf.channel;
5111                 brcms_c_suspend_mac_and_wait(wlc);
5112                 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5113                 wlc->bandinit_pending = false;
5114                 brcms_c_enable_mac(wlc);
5115         }
5116
5117         brcms_b_up_finish(wlc->hw);
5118
5119         /* Program the TX wme params with the current settings */
5120         brcms_c_wme_retries_write(wlc);
5121
5122         /* start one second watchdog timer */
5123         brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5124         wlc->WDarmed = true;
5125
5126         /* ensure antenna config is up to date */
5127         brcms_c_stf_phy_txant_upd(wlc);
5128         /* ensure LDPC config is in sync */
5129         brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5130
5131         return 0;
5132 }
5133
5134 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5135 {
5136         uint callbacks = 0;
5137
5138         return callbacks;
5139 }
5140
5141 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5142 {
5143         bool dev_gone;
5144         uint callbacks = 0;
5145
5146         if (!wlc_hw->up)
5147                 return callbacks;
5148
5149         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5150
5151         /* disable interrupts */
5152         if (dev_gone)
5153                 wlc_hw->wlc->macintmask = 0;
5154         else {
5155                 /* now disable interrupts */
5156                 brcms_intrsoff(wlc_hw->wlc->wl);
5157
5158                 /* ensure we're running on the pll clock again */
5159                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5160         }
5161         /* down phy at the last of this stage */
5162         callbacks += wlc_phy_down(wlc_hw->band->pi);
5163
5164         return callbacks;
5165 }
5166
5167 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5168 {
5169         uint callbacks = 0;
5170         bool dev_gone;
5171
5172         if (!wlc_hw->up)
5173                 return callbacks;
5174
5175         wlc_hw->up = false;
5176         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5177
5178         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5179
5180         if (dev_gone) {
5181                 wlc_hw->sbclk = false;
5182                 wlc_hw->clk = false;
5183                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5184
5185                 /* reclaim any posted packets */
5186                 brcms_c_flushqueues(wlc_hw->wlc);
5187         } else {
5188
5189                 /* Reset and disable the core */
5190                 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5191                         if (bcma_read32(wlc_hw->d11core,
5192                                         D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5193                                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5194                         callbacks += brcms_reset(wlc_hw->wlc->wl);
5195                         brcms_c_coredisable(wlc_hw);
5196                 }
5197
5198                 /* turn off primary xtal and pll */
5199                 if (!wlc_hw->noreset) {
5200                         ai_pci_down(wlc_hw->sih);
5201                         brcms_b_xtal(wlc_hw, OFF);
5202                 }
5203         }
5204
5205         return callbacks;
5206 }
5207
5208 /*
5209  * Mark the interface nonoperational, stop the software mechanisms,
5210  * disable the hardware, free any transient buffer state.
5211  * Return a count of the number of driver callbacks still pending.
5212  */
5213 uint brcms_c_down(struct brcms_c_info *wlc)
5214 {
5215
5216         uint callbacks = 0;
5217         int i;
5218         bool dev_gone = false;
5219
5220         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5221
5222         /* check if we are already in the going down path */
5223         if (wlc->going_down) {
5224                 brcms_err(wlc->hw->d11core,
5225                           "wl%d: %s: Driver going down so return\n",
5226                           wlc->pub->unit, __func__);
5227                 return 0;
5228         }
5229         if (!wlc->pub->up)
5230                 return callbacks;
5231
5232         wlc->going_down = true;
5233
5234         callbacks += brcms_b_bmac_down_prep(wlc->hw);
5235
5236         dev_gone = brcms_deviceremoved(wlc);
5237
5238         /* Call any registered down handlers */
5239         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5240                 if (wlc->modulecb[i].down_fn)
5241                         callbacks +=
5242                             wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5243         }
5244
5245         /* cancel the watchdog timer */
5246         if (wlc->WDarmed) {
5247                 if (!brcms_del_timer(wlc->wdtimer))
5248                         callbacks++;
5249                 wlc->WDarmed = false;
5250         }
5251         /* cancel all other timers */
5252         callbacks += brcms_c_down_del_timer(wlc);
5253
5254         wlc->pub->up = false;
5255
5256         wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5257
5258         callbacks += brcms_b_down_finish(wlc->hw);
5259
5260         /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5261         wlc->clk = false;
5262
5263         wlc->going_down = false;
5264         return callbacks;
5265 }
5266
5267 /* Set the current gmode configuration */
5268 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5269 {
5270         int ret = 0;
5271         uint i;
5272         struct brcms_c_rateset rs;
5273         /* Default to 54g Auto */
5274         /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5275         s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5276         bool shortslot_restrict = false; /* Restrict association to stations
5277                                           * that support shortslot
5278                                           */
5279         bool ofdm_basic = false;        /* Make 6, 12, and 24 basic rates */
5280         /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5281         int preamble = BRCMS_PLCP_LONG;
5282         bool preamble_restrict = false; /* Restrict association to stations
5283                                          * that support short preambles
5284                                          */
5285         struct brcms_band *band;
5286
5287         /* if N-support is enabled, allow Gmode set as long as requested
5288          * Gmode is not GMODE_LEGACY_B
5289          */
5290         if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5291                 return -ENOTSUPP;
5292
5293         /* verify that we are dealing with 2G band and grab the band pointer */
5294         if (wlc->band->bandtype == BRCM_BAND_2G)
5295                 band = wlc->band;
5296         else if ((wlc->pub->_nbands > 1) &&
5297                  (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5298                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5299         else
5300                 return -EINVAL;
5301
5302         /* update configuration value */
5303         if (config)
5304                 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5305
5306         /* Clear rateset override */
5307         memset(&rs, 0, sizeof(rs));
5308
5309         switch (gmode) {
5310         case GMODE_LEGACY_B:
5311                 shortslot = BRCMS_SHORTSLOT_OFF;
5312                 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5313
5314                 break;
5315
5316         case GMODE_LRS:
5317                 break;
5318
5319         case GMODE_AUTO:
5320                 /* Accept defaults */
5321                 break;
5322
5323         case GMODE_ONLY:
5324                 ofdm_basic = true;
5325                 preamble = BRCMS_PLCP_SHORT;
5326                 preamble_restrict = true;
5327                 break;
5328
5329         case GMODE_PERFORMANCE:
5330                 shortslot = BRCMS_SHORTSLOT_ON;
5331                 shortslot_restrict = true;
5332                 ofdm_basic = true;
5333                 preamble = BRCMS_PLCP_SHORT;
5334                 preamble_restrict = true;
5335                 break;
5336
5337         default:
5338                 /* Error */
5339                 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5340                           wlc->pub->unit, __func__, gmode);
5341                 return -ENOTSUPP;
5342         }
5343
5344         band->gmode = gmode;
5345
5346         wlc->shortslot_override = shortslot;
5347
5348         /* Use the default 11g rateset */
5349         if (!rs.count)
5350                 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5351
5352         if (ofdm_basic) {
5353                 for (i = 0; i < rs.count; i++) {
5354                         if (rs.rates[i] == BRCM_RATE_6M
5355                             || rs.rates[i] == BRCM_RATE_12M
5356                             || rs.rates[i] == BRCM_RATE_24M)
5357                                 rs.rates[i] |= BRCMS_RATE_FLAG;
5358                 }
5359         }
5360
5361         /* Set default bss rateset */
5362         wlc->default_bss->rateset.count = rs.count;
5363         memcpy(wlc->default_bss->rateset.rates, rs.rates,
5364                sizeof(wlc->default_bss->rateset.rates));
5365
5366         return ret;
5367 }
5368
5369 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5370 {
5371         uint i;
5372         s32 nmode = AUTO;
5373
5374         if (wlc->stf->txstreams == WL_11N_3x3)
5375                 nmode = WL_11N_3x3;
5376         else
5377                 nmode = WL_11N_2x2;
5378
5379         /* force GMODE_AUTO if NMODE is ON */
5380         brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5381         if (nmode == WL_11N_3x3)
5382                 wlc->pub->_n_enab = SUPPORT_HT;
5383         else
5384                 wlc->pub->_n_enab = SUPPORT_11N;
5385         wlc->default_bss->flags |= BRCMS_BSS_HT;
5386         /* add the mcs rates to the default and hw ratesets */
5387         brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5388                               wlc->stf->txstreams);
5389         for (i = 0; i < wlc->pub->_nbands; i++)
5390                 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5391                        wlc->default_bss->rateset.mcs, MCSSET_LEN);
5392
5393         return 0;
5394 }
5395
5396 static int
5397 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5398                              struct brcms_c_rateset *rs_arg)
5399 {
5400         struct brcms_c_rateset rs, new;
5401         uint bandunit;
5402
5403         memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5404
5405         /* check for bad count value */
5406         if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5407                 return -EINVAL;
5408
5409         /* try the current band */
5410         bandunit = wlc->band->bandunit;
5411         memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5412         if (brcms_c_rate_hwrs_filter_sort_validate
5413             (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5414              wlc->stf->txstreams))
5415                 goto good;
5416
5417         /* try the other band */
5418         if (brcms_is_mband_unlocked(wlc)) {
5419                 bandunit = OTHERBANDUNIT(wlc);
5420                 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5421                 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5422                                                        &wlc->
5423                                                        bandstate[bandunit]->
5424                                                        hw_rateset, true,
5425                                                        wlc->stf->txstreams))
5426                         goto good;
5427         }
5428
5429         return -EBADE;
5430
5431  good:
5432         /* apply new rateset */
5433         memcpy(&wlc->default_bss->rateset, &new,
5434                sizeof(struct brcms_c_rateset));
5435         memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5436                sizeof(struct brcms_c_rateset));
5437         return 0;
5438 }
5439
5440 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5441 {
5442         u8 r;
5443         bool war = false;
5444
5445         if (wlc->pub->associated)
5446                 r = wlc->bsscfg->current_bss->rateset.rates[0];
5447         else
5448                 r = wlc->default_bss->rateset.rates[0];
5449
5450         wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5451 }
5452
5453 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5454 {
5455         u16 chspec = ch20mhz_chspec(channel);
5456
5457         if (channel < 0 || channel > MAXCHANNEL)
5458                 return -EINVAL;
5459
5460         if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5461                 return -EINVAL;
5462
5463
5464         if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5465                 if (wlc->band->bandunit != chspec_bandunit(chspec))
5466                         wlc->bandinit_pending = true;
5467                 else
5468                         wlc->bandinit_pending = false;
5469         }
5470
5471         wlc->default_bss->chanspec = chspec;
5472         /* brcms_c_BSSinit() will sanitize the rateset before
5473          * using it.. */
5474         if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5475                 brcms_c_set_home_chanspec(wlc, chspec);
5476                 brcms_c_suspend_mac_and_wait(wlc);
5477                 brcms_c_set_chanspec(wlc, chspec);
5478                 brcms_c_enable_mac(wlc);
5479         }
5480         return 0;
5481 }
5482
5483 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5484 {
5485         int ac;
5486
5487         if (srl < 1 || srl > RETRY_SHORT_MAX ||
5488             lrl < 1 || lrl > RETRY_SHORT_MAX)
5489                 return -EINVAL;
5490
5491         wlc->SRL = srl;
5492         wlc->LRL = lrl;
5493
5494         brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5495
5496         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5497                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5498                                                EDCF_SHORT,  wlc->SRL);
5499                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5500                                                EDCF_LONG, wlc->LRL);
5501         }
5502         brcms_c_wme_retries_write(wlc);
5503
5504         return 0;
5505 }
5506
5507 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5508                                  struct brcm_rateset *currs)
5509 {
5510         struct brcms_c_rateset *rs;
5511
5512         if (wlc->pub->associated)
5513                 rs = &wlc->bsscfg->current_bss->rateset;
5514         else
5515                 rs = &wlc->default_bss->rateset;
5516
5517         /* Copy only legacy rateset section */
5518         currs->count = rs->count;
5519         memcpy(&currs->rates, &rs->rates, rs->count);
5520 }
5521
5522 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5523 {
5524         struct brcms_c_rateset internal_rs;
5525         int bcmerror;
5526
5527         if (rs->count > BRCMS_NUMRATES)
5528                 return -ENOBUFS;
5529
5530         memset(&internal_rs, 0, sizeof(internal_rs));
5531
5532         /* Copy only legacy rateset section */
5533         internal_rs.count = rs->count;
5534         memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5535
5536         /* merge rateset coming in with the current mcsset */
5537         if (wlc->pub->_n_enab & SUPPORT_11N) {
5538                 struct brcms_bss_info *mcsset_bss;
5539                 if (wlc->pub->associated)
5540                         mcsset_bss = wlc->bsscfg->current_bss;
5541                 else
5542                         mcsset_bss = wlc->default_bss;
5543                 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5544                        MCSSET_LEN);
5545         }
5546
5547         bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5548         if (!bcmerror)
5549                 brcms_c_ofdm_rateset_war(wlc);
5550
5551         return bcmerror;
5552 }
5553
5554 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5555 {
5556         bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5557         /* Commit the write */
5558         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5559 }
5560
5561 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5562 {
5563         bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5564         /* Commit the write */
5565         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5566 }
5567
5568 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5569 {
5570         u32 bcnint_us;
5571
5572         if (period == 0)
5573                 return -EINVAL;
5574
5575         wlc->default_bss->beacon_period = period;
5576
5577         bcnint_us = period << 10;
5578         brcms_c_time_lock(wlc);
5579         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfprep),
5580                      (bcnint_us << CFPREP_CBI_SHIFT));
5581         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfpstart), bcnint_us);
5582         brcms_c_time_unlock(wlc);
5583
5584         return 0;
5585 }
5586
5587 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5588 {
5589         return wlc->band->phytype;
5590 }
5591
5592 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5593 {
5594         wlc->shortslot_override = sslot_override;
5595
5596         /*
5597          * shortslot is an 11g feature, so no more work if we are
5598          * currently on the 5G band
5599          */
5600         if (wlc->band->bandtype == BRCM_BAND_5G)
5601                 return;
5602
5603         if (wlc->pub->up && wlc->pub->associated) {
5604                 /* let watchdog or beacon processing update shortslot */
5605         } else if (wlc->pub->up) {
5606                 /* unassociated shortslot is off */
5607                 brcms_c_switch_shortslot(wlc, false);
5608         } else {
5609                 /* driver is down, so just update the brcms_c_info
5610                  * value */
5611                 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5612                         wlc->shortslot = false;
5613                 else
5614                         wlc->shortslot =
5615                             (wlc->shortslot_override ==
5616                              BRCMS_SHORTSLOT_ON);
5617         }
5618 }
5619
5620 /*
5621  * register watchdog and down handlers.
5622  */
5623 int brcms_c_module_register(struct brcms_pub *pub,
5624                             const char *name, struct brcms_info *hdl,
5625                             int (*d_fn)(void *handle))
5626 {
5627         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5628         int i;
5629
5630         /* find an empty entry and just add, no duplication check! */
5631         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5632                 if (wlc->modulecb[i].name[0] == '\0') {
5633                         strncpy(wlc->modulecb[i].name, name,
5634                                 sizeof(wlc->modulecb[i].name) - 1);
5635                         wlc->modulecb[i].hdl = hdl;
5636                         wlc->modulecb[i].down_fn = d_fn;
5637                         return 0;
5638                 }
5639         }
5640
5641         return -ENOSR;
5642 }
5643
5644 /* unregister module callbacks */
5645 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5646                               struct brcms_info *hdl)
5647 {
5648         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5649         int i;
5650
5651         if (wlc == NULL)
5652                 return -ENODATA;
5653
5654         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5655                 if (!strcmp(wlc->modulecb[i].name, name) &&
5656                     (wlc->modulecb[i].hdl == hdl)) {
5657                         memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5658                         return 0;
5659                 }
5660         }
5661
5662         /* table not found! */
5663         return -ENODATA;
5664 }
5665
5666 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5667 {
5668         struct pci_dev *pcidev = core->bus->host_pci;
5669         u16 vendor = pcidev->vendor;
5670         u16 device = pcidev->device;
5671
5672         if (vendor != PCI_VENDOR_ID_BROADCOM) {
5673                 pr_err("unknown vendor id %04x\n", vendor);
5674                 return false;
5675         }
5676
5677         if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5678                 return true;
5679         if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5680                 return true;
5681         if (device == BCM4313_D11N2G_ID)
5682                 return true;
5683         if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5684                 return true;
5685
5686         pr_err("unknown device id %04x\n", device);
5687         return false;
5688 }
5689
5690 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5691 {
5692         struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5693
5694         if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5695                 return true;
5696
5697         pr_err("unknown chip id %04x\n", chipinfo->id);
5698         return false;
5699 }
5700
5701 bool brcms_c_chipmatch(struct bcma_device *core)
5702 {
5703         switch (core->bus->hosttype) {
5704         case BCMA_HOSTTYPE_PCI:
5705                 return brcms_c_chipmatch_pci(core);
5706         case BCMA_HOSTTYPE_SOC:
5707                 return brcms_c_chipmatch_soc(core);
5708         default:
5709                 pr_err("unknown host type: %i\n", core->bus->hosttype);
5710                 return false;
5711         }
5712 }
5713
5714 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5715 {
5716         u16 table_ptr;
5717         u8 phy_rate, index;
5718
5719         /* get the phy specific rate encoding for the PLCP SIGNAL field */
5720         if (is_ofdm_rate(rate))
5721                 table_ptr = M_RT_DIRMAP_A;
5722         else
5723                 table_ptr = M_RT_DIRMAP_B;
5724
5725         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5726          * the index into the rate table.
5727          */
5728         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5729         index = phy_rate & 0xf;
5730
5731         /* Find the SHM pointer to the rate table entry by looking in the
5732          * Direct-map Table
5733          */
5734         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5735 }
5736
5737 /*
5738  * bcmc_fid_generate:
5739  * Generate frame ID for a BCMC packet.  The frag field is not used
5740  * for MC frames so is used as part of the sequence number.
5741  */
5742 static inline u16
5743 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5744                   struct d11txh *txh)
5745 {
5746         u16 frameid;
5747
5748         frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5749                                                   TXFID_QUEUE_MASK);
5750         frameid |=
5751             (((wlc->
5752                mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5753             TX_BCMC_FIFO;
5754
5755         return frameid;
5756 }
5757
5758 static uint
5759 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5760                       u8 preamble_type)
5761 {
5762         uint dur = 0;
5763
5764         /*
5765          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5766          * is less than or equal to the rate of the immediately previous
5767          * frame in the FES
5768          */
5769         rspec = brcms_basic_rate(wlc, rspec);
5770         /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5771         dur =
5772             brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5773                                 (DOT11_ACK_LEN + FCS_LEN));
5774         return dur;
5775 }
5776
5777 static uint
5778 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5779                       u8 preamble_type)
5780 {
5781         return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5782 }
5783
5784 static uint
5785 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5786                      u8 preamble_type)
5787 {
5788         /*
5789          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5790          * is less than or equal to the rate of the immediately previous
5791          * frame in the FES
5792          */
5793         rspec = brcms_basic_rate(wlc, rspec);
5794         /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5795         return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5796                                    (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5797                                     FCS_LEN));
5798 }
5799
5800 /* brcms_c_compute_frame_dur()
5801  *
5802  * Calculate the 802.11 MAC header DUR field for MPDU
5803  * DUR for a single frame = 1 SIFS + 1 ACK
5804  * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5805  *
5806  * rate                 MPDU rate in unit of 500kbps
5807  * next_frag_len        next MPDU length in bytes
5808  * preamble_type        use short/GF or long/MM PLCP header
5809  */
5810 static u16
5811 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5812                       u8 preamble_type, uint next_frag_len)
5813 {
5814         u16 dur, sifs;
5815
5816         sifs = get_sifs(wlc->band);
5817
5818         dur = sifs;
5819         dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5820
5821         if (next_frag_len) {
5822                 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5823                 dur *= 2;
5824                 /* add another SIFS and the frag time */
5825                 dur += sifs;
5826                 dur +=
5827                     (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5828                                                  next_frag_len);
5829         }
5830         return dur;
5831 }
5832
5833 /* The opposite of brcms_c_calc_frame_time */
5834 static uint
5835 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5836                    u8 preamble_type, uint dur)
5837 {
5838         uint nsyms, mac_len, Ndps, kNdps;
5839         uint rate = rspec2rate(ratespec);
5840
5841         if (is_mcs_rate(ratespec)) {
5842                 uint mcs = ratespec & RSPEC_RATE_MASK;
5843                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5844                 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5845                 /* payload calculation matches that of regular ofdm */
5846                 if (wlc->band->bandtype == BRCM_BAND_2G)
5847                         dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5848                 /* kNdbps = kbps * 4 */
5849                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5850                                    rspec_issgi(ratespec)) * 4;
5851                 nsyms = dur / APHY_SYMBOL_TIME;
5852                 mac_len =
5853                     ((nsyms * kNdps) -
5854                      ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5855         } else if (is_ofdm_rate(ratespec)) {
5856                 dur -= APHY_PREAMBLE_TIME;
5857                 dur -= APHY_SIGNAL_TIME;
5858                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5859                 Ndps = rate * 2;
5860                 nsyms = dur / APHY_SYMBOL_TIME;
5861                 mac_len =
5862                     ((nsyms * Ndps) -
5863                      (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5864         } else {
5865                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5866                         dur -= BPHY_PLCP_SHORT_TIME;
5867                 else
5868                         dur -= BPHY_PLCP_TIME;
5869                 mac_len = dur * rate;
5870                 /* divide out factor of 2 in rate (1/2 mbps) */
5871                 mac_len = mac_len / 8 / 2;
5872         }
5873         return mac_len;
5874 }
5875
5876 /*
5877  * Return true if the specified rate is supported by the specified band.
5878  * BRCM_BAND_AUTO indicates the current band.
5879  */
5880 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5881                     bool verbose)
5882 {
5883         struct brcms_c_rateset *hw_rateset;
5884         uint i;
5885
5886         if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5887                 hw_rateset = &wlc->band->hw_rateset;
5888         else if (wlc->pub->_nbands > 1)
5889                 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5890         else
5891                 /* other band specified and we are a single band device */
5892                 return false;
5893
5894         /* check if this is a mimo rate */
5895         if (is_mcs_rate(rspec)) {
5896                 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5897                         goto error;
5898
5899                 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5900         }
5901
5902         for (i = 0; i < hw_rateset->count; i++)
5903                 if (hw_rateset->rates[i] == rspec2rate(rspec))
5904                         return true;
5905  error:
5906         if (verbose)
5907                 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5908                           "not in hw_rateset\n", wlc->pub->unit, rspec);
5909
5910         return false;
5911 }
5912
5913 static u32
5914 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5915                        u32 int_val)
5916 {
5917         struct bcma_device *core = wlc->hw->d11core;
5918         u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5919         u8 rate = int_val & NRATE_RATE_MASK;
5920         u32 rspec;
5921         bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5922         bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5923         bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5924                                   == NRATE_OVERRIDE_MCS_ONLY);
5925         int bcmerror = 0;
5926
5927         if (!ismcs)
5928                 return (u32) rate;
5929
5930         /* validate the combination of rate/mcs/stf is allowed */
5931         if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5932                 /* mcs only allowed when nmode */
5933                 if (stf > PHY_TXC1_MODE_SDM) {
5934                         brcms_err(core, "wl%d: %s: Invalid stf\n",
5935                                   wlc->pub->unit, __func__);
5936                         bcmerror = -EINVAL;
5937                         goto done;
5938                 }
5939
5940                 /* mcs 32 is a special case, DUP mode 40 only */
5941                 if (rate == 32) {
5942                         if (!CHSPEC_IS40(wlc->home_chanspec) ||
5943                             ((stf != PHY_TXC1_MODE_SISO)
5944                              && (stf != PHY_TXC1_MODE_CDD))) {
5945                                 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5946                                           wlc->pub->unit, __func__);
5947                                 bcmerror = -EINVAL;
5948                                 goto done;
5949                         }
5950                         /* mcs > 7 must use stf SDM */
5951                 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5952                         /* mcs > 7 must use stf SDM */
5953                         if (stf != PHY_TXC1_MODE_SDM) {
5954                                 brcms_dbg_mac80211(core, "wl%d: enabling "
5955                                                    "SDM mode for mcs %d\n",
5956                                                    wlc->pub->unit, rate);
5957                                 stf = PHY_TXC1_MODE_SDM;
5958                         }
5959                 } else {
5960                         /*
5961                          * MCS 0-7 may use SISO, CDD, and for
5962                          * phy_rev >= 3 STBC
5963                          */
5964                         if ((stf > PHY_TXC1_MODE_STBC) ||
5965                             (!BRCMS_STBC_CAP_PHY(wlc)
5966                              && (stf == PHY_TXC1_MODE_STBC))) {
5967                                 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5968                                           wlc->pub->unit, __func__);
5969                                 bcmerror = -EINVAL;
5970                                 goto done;
5971                         }
5972                 }
5973         } else if (is_ofdm_rate(rate)) {
5974                 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5975                         brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5976                                   wlc->pub->unit, __func__);
5977                         bcmerror = -EINVAL;
5978                         goto done;
5979                 }
5980         } else if (is_cck_rate(rate)) {
5981                 if ((cur_band->bandtype != BRCM_BAND_2G)
5982                     || (stf != PHY_TXC1_MODE_SISO)) {
5983                         brcms_err(core, "wl%d: %s: Invalid CCK\n",
5984                                   wlc->pub->unit, __func__);
5985                         bcmerror = -EINVAL;
5986                         goto done;
5987                 }
5988         } else {
5989                 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5990                           wlc->pub->unit, __func__);
5991                 bcmerror = -EINVAL;
5992                 goto done;
5993         }
5994         /* make sure multiple antennae are available for non-siso rates */
5995         if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5996                 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5997                           "request\n", wlc->pub->unit, __func__);
5998                 bcmerror = -EINVAL;
5999                 goto done;
6000         }
6001
6002         rspec = rate;
6003         if (ismcs) {
6004                 rspec |= RSPEC_MIMORATE;
6005                 /* For STBC populate the STC field of the ratespec */
6006                 if (stf == PHY_TXC1_MODE_STBC) {
6007                         u8 stc;
6008                         stc = 1;        /* Nss for single stream is always 1 */
6009                         rspec |= (stc << RSPEC_STC_SHIFT);
6010                 }
6011         }
6012
6013         rspec |= (stf << RSPEC_STF_SHIFT);
6014
6015         if (override_mcs_only)
6016                 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6017
6018         if (issgi)
6019                 rspec |= RSPEC_SHORT_GI;
6020
6021         if ((rate != 0)
6022             && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6023                 return rate;
6024
6025         return rspec;
6026 done:
6027         return rate;
6028 }
6029
6030 /*
6031  * Compute PLCP, but only requires actual rate and length of pkt.
6032  * Rate is given in the driver standard multiple of 500 kbps.
6033  * le is set for 11 Mbps rate if necessary.
6034  * Broken out for PRQ.
6035  */
6036
6037 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6038                              uint length, u8 *plcp)
6039 {
6040         u16 usec = 0;
6041         u8 le = 0;
6042
6043         switch (rate_500) {
6044         case BRCM_RATE_1M:
6045                 usec = length << 3;
6046                 break;
6047         case BRCM_RATE_2M:
6048                 usec = length << 2;
6049                 break;
6050         case BRCM_RATE_5M5:
6051                 usec = (length << 4) / 11;
6052                 if ((length << 4) - (usec * 11) > 0)
6053                         usec++;
6054                 break;
6055         case BRCM_RATE_11M:
6056                 usec = (length << 3) / 11;
6057                 if ((length << 3) - (usec * 11) > 0) {
6058                         usec++;
6059                         if ((usec * 11) - (length << 3) >= 8)
6060                                 le = D11B_PLCP_SIGNAL_LE;
6061                 }
6062                 break;
6063
6064         default:
6065                 brcms_err(wlc->hw->d11core,
6066                           "brcms_c_cck_plcp_set: unsupported rate %d\n",
6067                           rate_500);
6068                 rate_500 = BRCM_RATE_1M;
6069                 usec = length << 3;
6070                 break;
6071         }
6072         /* PLCP signal byte */
6073         plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6074         /* PLCP service byte */
6075         plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6076         /* PLCP length u16, little endian */
6077         plcp[2] = usec & 0xff;
6078         plcp[3] = (usec >> 8) & 0xff;
6079         /* PLCP CRC16 */
6080         plcp[4] = 0;
6081         plcp[5] = 0;
6082 }
6083
6084 /* Rate: 802.11 rate code, length: PSDU length in octets */
6085 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6086 {
6087         u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6088         plcp[0] = mcs;
6089         if (rspec_is40mhz(rspec) || (mcs == 32))
6090                 plcp[0] |= MIMO_PLCP_40MHZ;
6091         BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6092         plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6093         plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6094         plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6095         plcp[5] = 0;
6096 }
6097
6098 /* Rate: 802.11 rate code, length: PSDU length in octets */
6099 static void
6100 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6101 {
6102         u8 rate_signal;
6103         u32 tmp = 0;
6104         int rate = rspec2rate(rspec);
6105
6106         /*
6107          * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6108          * transmitted first
6109          */
6110         rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6111         memset(plcp, 0, D11_PHY_HDR_LEN);
6112         D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6113
6114         tmp = (length & 0xfff) << 5;
6115         plcp[2] |= (tmp >> 16) & 0xff;
6116         plcp[1] |= (tmp >> 8) & 0xff;
6117         plcp[0] |= tmp & 0xff;
6118 }
6119
6120 /* Rate: 802.11 rate code, length: PSDU length in octets */
6121 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6122                                  uint length, u8 *plcp)
6123 {
6124         int rate = rspec2rate(rspec);
6125
6126         brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6127 }
6128
6129 static void
6130 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6131                      uint length, u8 *plcp)
6132 {
6133         if (is_mcs_rate(rspec))
6134                 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6135         else if (is_ofdm_rate(rspec))
6136                 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6137         else
6138                 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6139 }
6140
6141 /* brcms_c_compute_rtscts_dur()
6142  *
6143  * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6144  * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6145  * DUR for CTS-TO-SELF w/ frame    = 2 SIFS         + next frame time + 1 ACK
6146  *
6147  * cts                  cts-to-self or rts/cts
6148  * rts_rate             rts or cts rate in unit of 500kbps
6149  * rate                 next MPDU rate in unit of 500kbps
6150  * frame_len            next MPDU frame length in bytes
6151  */
6152 u16
6153 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6154                            u32 rts_rate,
6155                            u32 frame_rate, u8 rts_preamble_type,
6156                            u8 frame_preamble_type, uint frame_len, bool ba)
6157 {
6158         u16 dur, sifs;
6159
6160         sifs = get_sifs(wlc->band);
6161
6162         if (!cts_only) {
6163                 /* RTS/CTS */
6164                 dur = 3 * sifs;
6165                 dur +=
6166                     (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6167                                                rts_preamble_type);
6168         } else {
6169                 /* CTS-TO-SELF */
6170                 dur = 2 * sifs;
6171         }
6172
6173         dur +=
6174             (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6175                                          frame_len);
6176         if (ba)
6177                 dur +=
6178                     (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6179                                               BRCMS_SHORT_PREAMBLE);
6180         else
6181                 dur +=
6182                     (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6183                                                frame_preamble_type);
6184         return dur;
6185 }
6186
6187 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6188 {
6189         u16 phyctl1 = 0;
6190         u16 bw;
6191
6192         if (BRCMS_ISLCNPHY(wlc->band)) {
6193                 bw = PHY_TXC1_BW_20MHZ;
6194         } else {
6195                 bw = rspec_get_bw(rspec);
6196                 /* 10Mhz is not supported yet */
6197                 if (bw < PHY_TXC1_BW_20MHZ) {
6198                         brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6199                                   "not supported yet, set to 20L\n", bw);
6200                         bw = PHY_TXC1_BW_20MHZ;
6201                 }
6202         }
6203
6204         if (is_mcs_rate(rspec)) {
6205                 uint mcs = rspec & RSPEC_RATE_MASK;
6206
6207                 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6208                 phyctl1 = rspec_phytxbyte2(rspec);
6209                 /* set the upper byte of phyctl1 */
6210                 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6211         } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6212                    && !BRCMS_ISSSLPNPHY(wlc->band)) {
6213                 /*
6214                  * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6215                  * Data Rate. Eventually MIMOPHY would also be converted to
6216                  * this format
6217                  */
6218                 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6219                 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6220         } else {                /* legacy OFDM/CCK */
6221                 s16 phycfg;
6222                 /* get the phyctl byte from rate phycfg table */
6223                 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6224                 if (phycfg == -1) {
6225                         brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6226                                   "legacy OFDM/CCK rate\n");
6227                         phycfg = 0;
6228                 }
6229                 /* set the upper byte of phyctl1 */
6230                 phyctl1 =
6231                     (bw | (phycfg << 8) |
6232                      (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6233         }
6234         return phyctl1;
6235 }
6236
6237 /*
6238  * Add struct d11txh, struct cck_phy_hdr.
6239  *
6240  * 'p' data must start with 802.11 MAC header
6241  * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6242  *
6243  * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6244  *
6245  */
6246 static u16
6247 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6248                      struct sk_buff *p, struct scb *scb, uint frag,
6249                      uint nfrags, uint queue, uint next_frag_len)
6250 {
6251         struct ieee80211_hdr *h;
6252         struct d11txh *txh;
6253         u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6254         int len, phylen, rts_phylen;
6255         u16 mch, phyctl, xfts, mainrates;
6256         u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6257         u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6258         u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6259         bool use_rts = false;
6260         bool use_cts = false;
6261         bool use_rifs = false;
6262         bool short_preamble[2] = { false, false };
6263         u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6264         u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6265         u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6266         struct ieee80211_rts *rts = NULL;
6267         bool qos;
6268         uint ac;
6269         bool hwtkmic = false;
6270         u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6271 #define ANTCFG_NONE 0xFF
6272         u8 antcfg = ANTCFG_NONE;
6273         u8 fbantcfg = ANTCFG_NONE;
6274         uint phyctl1_stf = 0;
6275         u16 durid = 0;
6276         struct ieee80211_tx_rate *txrate[2];
6277         int k;
6278         struct ieee80211_tx_info *tx_info;
6279         bool is_mcs;
6280         u16 mimo_txbw;
6281         u8 mimo_preamble_type;
6282
6283         /* locate 802.11 MAC header */
6284         h = (struct ieee80211_hdr *)(p->data);
6285         qos = ieee80211_is_data_qos(h->frame_control);
6286
6287         /* compute length of frame in bytes for use in PLCP computations */
6288         len = p->len;
6289         phylen = len + FCS_LEN;
6290
6291         /* Get tx_info */
6292         tx_info = IEEE80211_SKB_CB(p);
6293
6294         /* add PLCP */
6295         plcp = skb_push(p, D11_PHY_HDR_LEN);
6296
6297         /* add Broadcom tx descriptor header */
6298         txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6299         memset(txh, 0, D11_TXH_LEN);
6300
6301         /* setup frameid */
6302         if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6303                 /* non-AP STA should never use BCMC queue */
6304                 if (queue == TX_BCMC_FIFO) {
6305                         brcms_err(wlc->hw->d11core,
6306                                   "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6307                                   wlc->pub->unit, __func__);
6308                         frameid = bcmc_fid_generate(wlc, NULL, txh);
6309                 } else {
6310                         /* Increment the counter for first fragment */
6311                         if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6312                                 scb->seqnum[p->priority]++;
6313
6314                         /* extract fragment number from frame first */
6315                         seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6316                         seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6317                         h->seq_ctrl = cpu_to_le16(seq);
6318
6319                         frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6320                             (queue & TXFID_QUEUE_MASK);
6321                 }
6322         }
6323         frameid |= queue & TXFID_QUEUE_MASK;
6324
6325         /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6326         if (ieee80211_is_beacon(h->frame_control))
6327                 mcl |= TXC_IGNOREPMQ;
6328
6329         txrate[0] = tx_info->control.rates;
6330         txrate[1] = txrate[0] + 1;
6331
6332         /*
6333          * if rate control algorithm didn't give us a fallback
6334          * rate, use the primary rate
6335          */
6336         if (txrate[1]->idx < 0)
6337                 txrate[1] = txrate[0];
6338
6339         for (k = 0; k < hw->max_rates; k++) {
6340                 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6341                 if (!is_mcs) {
6342                         if ((txrate[k]->idx >= 0)
6343                             && (txrate[k]->idx <
6344                                 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6345                                 rspec[k] =
6346                                     hw->wiphy->bands[tx_info->band]->
6347                                     bitrates[txrate[k]->idx].hw_value;
6348                                 short_preamble[k] =
6349                                     txrate[k]->
6350                                     flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6351                                     true : false;
6352                         } else {
6353                                 rspec[k] = BRCM_RATE_1M;
6354                         }
6355                 } else {
6356                         rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6357                                         NRATE_MCS_INUSE | txrate[k]->idx);
6358                 }
6359
6360                 /*
6361                  * Currently only support same setting for primay and
6362                  * fallback rates. Unify flags for each rate into a
6363                  * single value for the frame
6364                  */
6365                 use_rts |=
6366                     txrate[k]->
6367                     flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6368                 use_cts |=
6369                     txrate[k]->
6370                     flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6371
6372
6373                 /*
6374                  * (1) RATE:
6375                  *   determine and validate primary rate
6376                  *   and fallback rates
6377                  */
6378                 if (!rspec_active(rspec[k])) {
6379                         rspec[k] = BRCM_RATE_1M;
6380                 } else {
6381                         if (!is_multicast_ether_addr(h->addr1)) {
6382                                 /* set tx antenna config */
6383                                 brcms_c_antsel_antcfg_get(wlc->asi, false,
6384                                         false, 0, 0, &antcfg, &fbantcfg);
6385                         }
6386                 }
6387         }
6388
6389         phyctl1_stf = wlc->stf->ss_opmode;
6390
6391         if (wlc->pub->_n_enab & SUPPORT_11N) {
6392                 for (k = 0; k < hw->max_rates; k++) {
6393                         /*
6394                          * apply siso/cdd to single stream mcs's or ofdm
6395                          * if rspec is auto selected
6396                          */
6397                         if (((is_mcs_rate(rspec[k]) &&
6398                               is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6399                              is_ofdm_rate(rspec[k]))
6400                             && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6401                                 || !(rspec[k] & RSPEC_OVERRIDE))) {
6402                                 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6403
6404                                 /* For SISO MCS use STBC if possible */
6405                                 if (is_mcs_rate(rspec[k])
6406                                     && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6407                                         u8 stc;
6408
6409                                         /* Nss for single stream is always 1 */
6410                                         stc = 1;
6411                                         rspec[k] |= (PHY_TXC1_MODE_STBC <<
6412                                                         RSPEC_STF_SHIFT) |
6413                                                     (stc << RSPEC_STC_SHIFT);
6414                                 } else
6415                                         rspec[k] |=
6416                                             (phyctl1_stf << RSPEC_STF_SHIFT);
6417                         }
6418
6419                         /*
6420                          * Is the phy configured to use 40MHZ frames? If
6421                          * so then pick the desired txbw
6422                          */
6423                         if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6424                                 /* default txbw is 20in40 SB */
6425                                 mimo_ctlchbw = mimo_txbw =
6426                                    CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6427                                                                  wlc->band->pi))
6428                                    ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6429
6430                                 if (is_mcs_rate(rspec[k])) {
6431                                         /* mcs 32 must be 40b/w DUP */
6432                                         if ((rspec[k] & RSPEC_RATE_MASK)
6433                                             == 32) {
6434                                                 mimo_txbw =
6435                                                     PHY_TXC1_BW_40MHZ_DUP;
6436                                                 /* use override */
6437                                         } else if (wlc->mimo_40txbw != AUTO)
6438                                                 mimo_txbw = wlc->mimo_40txbw;
6439                                         /* else check if dst is using 40 Mhz */
6440                                         else if (scb->flags & SCB_IS40)
6441                                                 mimo_txbw = PHY_TXC1_BW_40MHZ;
6442                                 } else if (is_ofdm_rate(rspec[k])) {
6443                                         if (wlc->ofdm_40txbw != AUTO)
6444                                                 mimo_txbw = wlc->ofdm_40txbw;
6445                                 } else if (wlc->cck_40txbw != AUTO) {
6446                                         mimo_txbw = wlc->cck_40txbw;
6447                                 }
6448                         } else {
6449                                 /*
6450                                  * mcs32 is 40 b/w only.
6451                                  * This is possible for probe packets on
6452                                  * a STA during SCAN
6453                                  */
6454                                 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6455                                         /* mcs 0 */
6456                                         rspec[k] = RSPEC_MIMORATE;
6457
6458                                 mimo_txbw = PHY_TXC1_BW_20MHZ;
6459                         }
6460
6461                         /* Set channel width */
6462                         rspec[k] &= ~RSPEC_BW_MASK;
6463                         if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6464                                 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6465                         else
6466                                 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6467
6468                         /* Disable short GI, not supported yet */
6469                         rspec[k] &= ~RSPEC_SHORT_GI;
6470
6471                         mimo_preamble_type = BRCMS_MM_PREAMBLE;
6472                         if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6473                                 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6474
6475                         if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6476                             && (!is_mcs_rate(rspec[k]))) {
6477                                 brcms_warn(wlc->hw->d11core,
6478                                            "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6479                                            wlc->pub->unit, __func__);
6480                         }
6481
6482                         if (is_mcs_rate(rspec[k])) {
6483                                 preamble_type[k] = mimo_preamble_type;
6484
6485                                 /*
6486                                  * if SGI is selected, then forced mm
6487                                  * for single stream
6488                                  */
6489                                 if ((rspec[k] & RSPEC_SHORT_GI)
6490                                     && is_single_stream(rspec[k] &
6491                                                         RSPEC_RATE_MASK))
6492                                         preamble_type[k] = BRCMS_MM_PREAMBLE;
6493                         }
6494
6495                         /* should be better conditionalized */
6496                         if (!is_mcs_rate(rspec[0])
6497                             && (tx_info->control.rates[0].
6498                                 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6499                                 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6500                 }
6501         } else {
6502                 for (k = 0; k < hw->max_rates; k++) {
6503                         /* Set ctrlchbw as 20Mhz */
6504                         rspec[k] &= ~RSPEC_BW_MASK;
6505                         rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6506
6507                         /* for nphy, stf of ofdm frames must follow policies */
6508                         if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6509                                 rspec[k] &= ~RSPEC_STF_MASK;
6510                                 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6511                         }
6512                 }
6513         }
6514
6515         /* Reset these for use with AMPDU's */
6516         txrate[0]->count = 0;
6517         txrate[1]->count = 0;
6518
6519         /* (2) PROTECTION, may change rspec */
6520         if ((ieee80211_is_data(h->frame_control) ||
6521             ieee80211_is_mgmt(h->frame_control)) &&
6522             (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6523                 use_rts = true;
6524
6525         /* (3) PLCP: determine PLCP header and MAC duration,
6526          * fill struct d11txh */
6527         brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6528         brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6529         memcpy(&txh->FragPLCPFallback,
6530                plcp_fallback, sizeof(txh->FragPLCPFallback));
6531
6532         /* Length field now put in CCK FBR CRC field */
6533         if (is_cck_rate(rspec[1])) {
6534                 txh->FragPLCPFallback[4] = phylen & 0xff;
6535                 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6536         }
6537
6538         /* MIMO-RATE: need validation ?? */
6539         mainrates = is_ofdm_rate(rspec[0]) ?
6540                         D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6541                         plcp[0];
6542
6543         /* DUR field for main rate */
6544         if (!ieee80211_is_pspoll(h->frame_control) &&
6545             !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6546                 durid =
6547                     brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6548                                           next_frag_len);
6549                 h->duration_id = cpu_to_le16(durid);
6550         } else if (use_rifs) {
6551                 /* NAV protect to end of next max packet size */
6552                 durid =
6553                     (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6554                                                  preamble_type[0],
6555                                                  DOT11_MAX_FRAG_LEN);
6556                 durid += RIFS_11N_TIME;
6557                 h->duration_id = cpu_to_le16(durid);
6558         }
6559
6560         /* DUR field for fallback rate */
6561         if (ieee80211_is_pspoll(h->frame_control))
6562                 txh->FragDurFallback = h->duration_id;
6563         else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6564                 txh->FragDurFallback = 0;
6565         else {
6566                 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6567                                               preamble_type[1], next_frag_len);
6568                 txh->FragDurFallback = cpu_to_le16(durid);
6569         }
6570
6571         /* (4) MAC-HDR: MacTxControlLow */
6572         if (frag == 0)
6573                 mcl |= TXC_STARTMSDU;
6574
6575         if (!is_multicast_ether_addr(h->addr1))
6576                 mcl |= TXC_IMMEDACK;
6577
6578         if (wlc->band->bandtype == BRCM_BAND_5G)
6579                 mcl |= TXC_FREQBAND_5G;
6580
6581         if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6582                 mcl |= TXC_BW_40;
6583
6584         /* set AMIC bit if using hardware TKIP MIC */
6585         if (hwtkmic)
6586                 mcl |= TXC_AMIC;
6587
6588         txh->MacTxControlLow = cpu_to_le16(mcl);
6589
6590         /* MacTxControlHigh */
6591         mch = 0;
6592
6593         /* Set fallback rate preamble type */
6594         if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6595             (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6596                 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6597                         mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6598         }
6599
6600         /* MacFrameControl */
6601         memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6602         txh->TxFesTimeNormal = cpu_to_le16(0);
6603
6604         txh->TxFesTimeFallback = cpu_to_le16(0);
6605
6606         /* TxFrameRA */
6607         memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6608
6609         /* TxFrameID */
6610         txh->TxFrameID = cpu_to_le16(frameid);
6611
6612         /*
6613          * TxStatus, Note the case of recreating the first frag of a suppressed
6614          * frame then we may need to reset the retry cnt's via the status reg
6615          */
6616         txh->TxStatus = cpu_to_le16(status);
6617
6618         /*
6619          * extra fields for ucode AMPDU aggregation, the new fields are added to
6620          * the END of previous structure so that it's compatible in driver.
6621          */
6622         txh->MaxNMpdus = cpu_to_le16(0);
6623         txh->MaxABytes_MRT = cpu_to_le16(0);
6624         txh->MaxABytes_FBR = cpu_to_le16(0);
6625         txh->MinMBytes = cpu_to_le16(0);
6626
6627         /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6628          * furnish struct d11txh */
6629         /* RTS PLCP header and RTS frame */
6630         if (use_rts || use_cts) {
6631                 if (use_rts && use_cts)
6632                         use_cts = false;
6633
6634                 for (k = 0; k < 2; k++) {
6635                         rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6636                                                               false,
6637                                                               mimo_ctlchbw);
6638                 }
6639
6640                 if (!is_ofdm_rate(rts_rspec[0]) &&
6641                     !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6642                       (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6643                         rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6644                         mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6645                 }
6646
6647                 if (!is_ofdm_rate(rts_rspec[1]) &&
6648                     !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6649                       (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6650                         rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6651                         mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6652                 }
6653
6654                 /* RTS/CTS additions to MacTxControlLow */
6655                 if (use_cts) {
6656                         txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6657                 } else {
6658                         txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6659                         txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6660                 }
6661
6662                 /* RTS PLCP header */
6663                 rts_plcp = txh->RTSPhyHeader;
6664                 if (use_cts)
6665                         rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6666                 else
6667                         rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6668
6669                 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6670
6671                 /* fallback rate version of RTS PLCP header */
6672                 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6673                                  rts_plcp_fallback);
6674                 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6675                        sizeof(txh->RTSPLCPFallback));
6676
6677                 /* RTS frame fields... */
6678                 rts = (struct ieee80211_rts *)&txh->rts_frame;
6679
6680                 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6681                                                rspec[0], rts_preamble_type[0],
6682                                                preamble_type[0], phylen, false);
6683                 rts->duration = cpu_to_le16(durid);
6684                 /* fallback rate version of RTS DUR field */
6685                 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6686                                                rts_rspec[1], rspec[1],
6687                                                rts_preamble_type[1],
6688                                                preamble_type[1], phylen, false);
6689                 txh->RTSDurFallback = cpu_to_le16(durid);
6690
6691                 if (use_cts) {
6692                         rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6693                                                          IEEE80211_STYPE_CTS);
6694
6695                         memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6696                 } else {
6697                         rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6698                                                          IEEE80211_STYPE_RTS);
6699
6700                         memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6701                 }
6702
6703                 /* mainrate
6704                  *    low 8 bits: main frag rate/mcs,
6705                  *    high 8 bits: rts/cts rate/mcs
6706                  */
6707                 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6708                                 D11A_PHY_HDR_GRATE(
6709                                         (struct ofdm_phy_hdr *) rts_plcp) :
6710                                 rts_plcp[0]) << 8;
6711         } else {
6712                 memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6713                 memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6714                 memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6715                 txh->RTSDurFallback = 0;
6716         }
6717
6718 #ifdef SUPPORT_40MHZ
6719         /* add null delimiter count */
6720         if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6721                 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6722                    brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6723
6724 #endif
6725
6726         /*
6727          * Now that RTS/RTS FB preamble types are updated, write
6728          * the final value
6729          */
6730         txh->MacTxControlHigh = cpu_to_le16(mch);
6731
6732         /*
6733          * MainRates (both the rts and frag plcp rates have
6734          * been calculated now)
6735          */
6736         txh->MainRates = cpu_to_le16(mainrates);
6737
6738         /* XtraFrameTypes */
6739         xfts = frametype(rspec[1], wlc->mimoft);
6740         xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6741         xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6742         xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6743                                                              XFTS_CHANNEL_SHIFT;
6744         txh->XtraFrameTypes = cpu_to_le16(xfts);
6745
6746         /* PhyTxControlWord */
6747         phyctl = frametype(rspec[0], wlc->mimoft);
6748         if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6749             (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6750                 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6751                         phyctl |= PHY_TXC_SHORT_HDR;
6752         }
6753
6754         /* phytxant is properly bit shifted */
6755         phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6756         txh->PhyTxControlWord = cpu_to_le16(phyctl);
6757
6758         /* PhyTxControlWord_1 */
6759         if (BRCMS_PHY_11N_CAP(wlc->band)) {
6760                 u16 phyctl1 = 0;
6761
6762                 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6763                 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6764                 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6765                 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6766
6767                 if (use_rts || use_cts) {
6768                         phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6769                         txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6770                         phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6771                         txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6772                 }
6773
6774                 /*
6775                  * For mcs frames, if mixedmode(overloaded with long preamble)
6776                  * is going to be set, fill in non-zero MModeLen and/or
6777                  * MModeFbrLen it will be unnecessary if they are separated
6778                  */
6779                 if (is_mcs_rate(rspec[0]) &&
6780                     (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6781                         u16 mmodelen =
6782                             brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6783                         txh->MModeLen = cpu_to_le16(mmodelen);
6784                 }
6785
6786                 if (is_mcs_rate(rspec[1]) &&
6787                     (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6788                         u16 mmodefbrlen =
6789                             brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6790                         txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6791                 }
6792         }
6793
6794         ac = skb_get_queue_mapping(p);
6795         if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6796                 uint frag_dur, dur, dur_fallback;
6797
6798                 /* WME: Update TXOP threshold */
6799                 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6800                         frag_dur =
6801                             brcms_c_calc_frame_time(wlc, rspec[0],
6802                                         preamble_type[0], phylen);
6803
6804                         if (rts) {
6805                                 /* 1 RTS or CTS-to-self frame */
6806                                 dur =
6807                                     brcms_c_calc_cts_time(wlc, rts_rspec[0],
6808                                                       rts_preamble_type[0]);
6809                                 dur_fallback =
6810                                     brcms_c_calc_cts_time(wlc, rts_rspec[1],
6811                                                       rts_preamble_type[1]);
6812                                 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6813                                 dur += le16_to_cpu(rts->duration);
6814                                 dur_fallback +=
6815                                         le16_to_cpu(txh->RTSDurFallback);
6816                         } else if (use_rifs) {
6817                                 dur = frag_dur;
6818                                 dur_fallback = 0;
6819                         } else {
6820                                 /* frame + SIFS + ACK */
6821                                 dur = frag_dur;
6822                                 dur +=
6823                                     brcms_c_compute_frame_dur(wlc, rspec[0],
6824                                                           preamble_type[0], 0);
6825
6826                                 dur_fallback =
6827                                     brcms_c_calc_frame_time(wlc, rspec[1],
6828                                                         preamble_type[1],
6829                                                         phylen);
6830                                 dur_fallback +=
6831                                     brcms_c_compute_frame_dur(wlc, rspec[1],
6832                                                           preamble_type[1], 0);
6833                         }
6834                         /* NEED to set TxFesTimeNormal (hard) */
6835                         txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6836                         /*
6837                          * NEED to set fallback rate version of
6838                          * TxFesTimeNormal (hard)
6839                          */
6840                         txh->TxFesTimeFallback =
6841                                 cpu_to_le16((u16) dur_fallback);
6842
6843                         /*
6844                          * update txop byte threshold (txop minus intraframe
6845                          * overhead)
6846                          */
6847                         if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6848                                 uint newfragthresh;
6849
6850                                 newfragthresh =
6851                                     brcms_c_calc_frame_len(wlc,
6852                                         rspec[0], preamble_type[0],
6853                                         (wlc->edcf_txop[ac] -
6854                                                 (dur - frag_dur)));
6855                                 /* range bound the fragthreshold */
6856                                 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6857                                         newfragthresh =
6858                                             DOT11_MIN_FRAG_LEN;
6859                                 else if (newfragthresh >
6860                                          wlc->usr_fragthresh)
6861                                         newfragthresh =
6862                                             wlc->usr_fragthresh;
6863                                 /* update the fragthresh and do txc update */
6864                                 if (wlc->fragthresh[queue] !=
6865                                     (u16) newfragthresh)
6866                                         wlc->fragthresh[queue] =
6867                                             (u16) newfragthresh;
6868                         } else {
6869                                 brcms_warn(wlc->hw->d11core,
6870                                            "wl%d: %s txop invalid for rate %d\n",
6871                                            wlc->pub->unit, fifo_names[queue],
6872                                            rspec2rate(rspec[0]));
6873                         }
6874
6875                         if (dur > wlc->edcf_txop[ac])
6876                                 brcms_warn(wlc->hw->d11core,
6877                                            "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6878                                            wlc->pub->unit, __func__,
6879                                            fifo_names[queue],
6880                                            phylen, wlc->fragthresh[queue],
6881                                            dur, wlc->edcf_txop[ac]);
6882                 }
6883         }
6884
6885         return 0;
6886 }
6887
6888 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6889 {
6890         struct dma_pub *dma;
6891         int fifo, ret = -ENOSPC;
6892         struct d11txh *txh;
6893         u16 frameid = INVALIDFID;
6894
6895         fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6896         dma = wlc->hw->di[fifo];
6897         txh = (struct d11txh *)(skb->data);
6898
6899         if (dma->txavail == 0) {
6900                 /*
6901                  * We sometimes get a frame from mac80211 after stopping
6902                  * the queues. This only ever seems to be a single frame
6903                  * and is seems likely to be a race. TX_HEADROOM should
6904                  * ensure that we have enough space to handle these stray
6905                  * packets, so warn if there isn't. If we're out of space
6906                  * in the tx ring and the tx queue isn't stopped then
6907                  * we've really got a bug; warn loudly if that happens.
6908                  */
6909                 brcms_warn(wlc->hw->d11core,
6910                            "Received frame for tx with no space in DMA ring\n");
6911                 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6912                                                  skb_get_queue_mapping(skb)));
6913                 return -ENOSPC;
6914         }
6915
6916         /* When a BC/MC frame is being committed to the BCMC fifo
6917          * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6918          */
6919         if (fifo == TX_BCMC_FIFO)
6920                 frameid = le16_to_cpu(txh->TxFrameID);
6921
6922         /* Commit BCMC sequence number in the SHM frame ID location */
6923         if (frameid != INVALIDFID) {
6924                 /*
6925                  * To inform the ucode of the last mcast frame posted
6926                  * so that it can clear moredata bit
6927                  */
6928                 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6929         }
6930
6931         ret = brcms_c_txfifo(wlc, fifo, skb);
6932         /*
6933          * The only reason for brcms_c_txfifo to fail is because
6934          * there weren't any DMA descriptors, but we've already
6935          * checked for that. So if it does fail yell loudly.
6936          */
6937         WARN_ON_ONCE(ret);
6938
6939         return ret;
6940 }
6941
6942 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6943                               struct ieee80211_hw *hw)
6944 {
6945         uint fifo;
6946         struct scb *scb = &wlc->pri_scb;
6947
6948         fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6949         brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6950         if (!brcms_c_tx(wlc, sdu))
6951                 return true;
6952
6953         /* packet discarded */
6954         dev_kfree_skb_any(sdu);
6955         return false;
6956 }
6957
6958 int
6959 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6960 {
6961         struct dma_pub *dma = wlc->hw->di[fifo];
6962         int ret;
6963         u16 queue;
6964
6965         ret = dma_txfast(wlc, dma, p);
6966         if (ret < 0)
6967                 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6968
6969         /*
6970          * Stop queue if DMA ring is full. Reserve some free descriptors,
6971          * as we sometimes receive a frame from mac80211 after the queues
6972          * are stopped.
6973          */
6974         queue = skb_get_queue_mapping(p);
6975         if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6976             !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6977                 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6978
6979         return ret;
6980 }
6981
6982 u32
6983 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6984                            bool use_rspec, u16 mimo_ctlchbw)
6985 {
6986         u32 rts_rspec = 0;
6987
6988         if (use_rspec)
6989                 /* use frame rate as rts rate */
6990                 rts_rspec = rspec;
6991         else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6992                 /* Use 11Mbps as the g protection RTS target rate and fallback.
6993                  * Use the brcms_basic_rate() lookup to find the best basic rate
6994                  * under the target in case 11 Mbps is not Basic.
6995                  * 6 and 9 Mbps are not usually selected by rate selection, but
6996                  * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6997                  * is more robust.
6998                  */
6999                 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7000         else
7001                 /* calculate RTS rate and fallback rate based on the frame rate
7002                  * RTS must be sent at a basic rate since it is a
7003                  * control frame, sec 9.6 of 802.11 spec
7004                  */
7005                 rts_rspec = brcms_basic_rate(wlc, rspec);
7006
7007         if (BRCMS_PHY_11N_CAP(wlc->band)) {
7008                 /* set rts txbw to correct side band */
7009                 rts_rspec &= ~RSPEC_BW_MASK;
7010
7011                 /*
7012                  * if rspec/rspec_fallback is 40MHz, then send RTS on both
7013                  * 20MHz channel (DUP), otherwise send RTS on control channel
7014                  */
7015                 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7016                         rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7017                 else
7018                         rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7019
7020                 /* pick siso/cdd as default for ofdm */
7021                 if (is_ofdm_rate(rts_rspec)) {
7022                         rts_rspec &= ~RSPEC_STF_MASK;
7023                         rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7024                 }
7025         }
7026         return rts_rspec;
7027 }
7028
7029 /* Update beacon listen interval in shared memory */
7030 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7031 {
7032         /* wake up every DTIM is the default */
7033         if (wlc->bcn_li_dtim == 1)
7034                 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7035         else
7036                 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7037                               (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7038 }
7039
7040 static void
7041 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7042                   u32 *tsf_h_ptr)
7043 {
7044         struct bcma_device *core = wlc_hw->d11core;
7045
7046         /* read the tsf timer low, then high to get an atomic read */
7047         *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7048         *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7049 }
7050
7051 /*
7052  * recover 64bit TSF value from the 16bit TSF value in the rx header
7053  * given the assumption that the TSF passed in header is within 65ms
7054  * of the current tsf.
7055  *
7056  * 6       5       4       4       3       2       1
7057  * 3.......6.......8.......0.......2.......4.......6.......8......0
7058  * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7059  *
7060  * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7061  * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7062  * receive call sequence after rx interrupt. Only the higher 16 bits
7063  * are used. Finally, the tsf_h is read from the tsf register.
7064  */
7065 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7066                                  struct d11rxhdr *rxh)
7067 {
7068         u32 tsf_h, tsf_l;
7069         u16 rx_tsf_0_15, rx_tsf_16_31;
7070
7071         brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7072
7073         rx_tsf_16_31 = (u16)(tsf_l >> 16);
7074         rx_tsf_0_15 = rxh->RxTSFTime;
7075
7076         /*
7077          * a greater tsf time indicates the low 16 bits of
7078          * tsf_l wrapped, so decrement the high 16 bits.
7079          */
7080         if ((u16)tsf_l < rx_tsf_0_15) {
7081                 rx_tsf_16_31 -= 1;
7082                 if (rx_tsf_16_31 == 0xffff)
7083                         tsf_h -= 1;
7084         }
7085
7086         return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7087 }
7088
7089 static void
7090 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7091                      struct sk_buff *p,
7092                      struct ieee80211_rx_status *rx_status)
7093 {
7094         int preamble;
7095         int channel;
7096         u32 rspec;
7097         unsigned char *plcp;
7098
7099         /* fill in TSF and flag its presence */
7100         rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7101         rx_status->flag |= RX_FLAG_MACTIME_START;
7102
7103         channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7104
7105         rx_status->band =
7106                 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7107         rx_status->freq =
7108                 ieee80211_channel_to_frequency(channel, rx_status->band);
7109
7110         rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7111
7112         /* noise */
7113         /* qual */
7114         rx_status->antenna =
7115                 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7116
7117         plcp = p->data;
7118
7119         rspec = brcms_c_compute_rspec(rxh, plcp);
7120         if (is_mcs_rate(rspec)) {
7121                 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7122                 rx_status->flag |= RX_FLAG_HT;
7123                 if (rspec_is40mhz(rspec))
7124                         rx_status->flag |= RX_FLAG_40MHZ;
7125         } else {
7126                 switch (rspec2rate(rspec)) {
7127                 case BRCM_RATE_1M:
7128                         rx_status->rate_idx = 0;
7129                         break;
7130                 case BRCM_RATE_2M:
7131                         rx_status->rate_idx = 1;
7132                         break;
7133                 case BRCM_RATE_5M5:
7134                         rx_status->rate_idx = 2;
7135                         break;
7136                 case BRCM_RATE_11M:
7137                         rx_status->rate_idx = 3;
7138                         break;
7139                 case BRCM_RATE_6M:
7140                         rx_status->rate_idx = 4;
7141                         break;
7142                 case BRCM_RATE_9M:
7143                         rx_status->rate_idx = 5;
7144                         break;
7145                 case BRCM_RATE_12M:
7146                         rx_status->rate_idx = 6;
7147                         break;
7148                 case BRCM_RATE_18M:
7149                         rx_status->rate_idx = 7;
7150                         break;
7151                 case BRCM_RATE_24M:
7152                         rx_status->rate_idx = 8;
7153                         break;
7154                 case BRCM_RATE_36M:
7155                         rx_status->rate_idx = 9;
7156                         break;
7157                 case BRCM_RATE_48M:
7158                         rx_status->rate_idx = 10;
7159                         break;
7160                 case BRCM_RATE_54M:
7161                         rx_status->rate_idx = 11;
7162                         break;
7163                 default:
7164                         brcms_err(wlc->hw->d11core,
7165                                   "%s: Unknown rate\n", __func__);
7166                 }
7167
7168                 /*
7169                  * For 5GHz, we should decrease the index as it is
7170                  * a subset of the 2.4G rates. See bitrates field
7171                  * of brcms_band_5GHz_nphy (in mac80211_if.c).
7172                  */
7173                 if (rx_status->band == IEEE80211_BAND_5GHZ)
7174                         rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7175
7176                 /* Determine short preamble and rate_idx */
7177                 preamble = 0;
7178                 if (is_cck_rate(rspec)) {
7179                         if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7180                                 rx_status->flag |= RX_FLAG_SHORTPRE;
7181                 } else if (is_ofdm_rate(rspec)) {
7182                         rx_status->flag |= RX_FLAG_SHORTPRE;
7183                 } else {
7184                         brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7185                                   __func__);
7186                 }
7187         }
7188
7189         if (plcp3_issgi(plcp[3]))
7190                 rx_status->flag |= RX_FLAG_SHORT_GI;
7191
7192         if (rxh->RxStatus1 & RXS_DECERR) {
7193                 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7194                 brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_PLCP_CRC\n",
7195                           __func__);
7196         }
7197         if (rxh->RxStatus1 & RXS_FCSERR) {
7198                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7199                 brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_FCS_CRC\n",
7200                           __func__);
7201         }
7202 }
7203
7204 static void
7205 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7206                 struct sk_buff *p)
7207 {
7208         int len_mpdu;
7209         struct ieee80211_rx_status rx_status;
7210         struct ieee80211_hdr *hdr;
7211
7212         memset(&rx_status, 0, sizeof(rx_status));
7213         prep_mac80211_status(wlc, rxh, p, &rx_status);
7214
7215         /* mac header+body length, exclude CRC and plcp header */
7216         len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7217         skb_pull(p, D11_PHY_HDR_LEN);
7218         __skb_trim(p, len_mpdu);
7219
7220         /* unmute transmit */
7221         if (wlc->hw->suspended_fifos) {
7222                 hdr = (struct ieee80211_hdr *)p->data;
7223                 if (ieee80211_is_beacon(hdr->frame_control))
7224                         brcms_b_mute(wlc->hw, false);
7225         }
7226
7227         memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7228         ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7229 }
7230
7231 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7232  * number of bytes goes in the length field
7233  *
7234  * Formula given by HT PHY Spec v 1.13
7235  *   len = 3(nsyms + nstream + 3) - 3
7236  */
7237 u16
7238 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7239                       uint mac_len)
7240 {
7241         uint nsyms, len = 0, kNdps;
7242
7243         if (is_mcs_rate(ratespec)) {
7244                 uint mcs = ratespec & RSPEC_RATE_MASK;
7245                 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7246                                   rspec_stc(ratespec);
7247
7248                 /*
7249                  * the payload duration calculation matches that
7250                  * of regular ofdm
7251                  */
7252                 /* 1000Ndbps = kbps * 4 */
7253                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7254                                    rspec_issgi(ratespec)) * 4;
7255
7256                 if (rspec_stc(ratespec) == 0)
7257                         nsyms =
7258                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7259                                   APHY_TAIL_NBITS) * 1000, kNdps);
7260                 else
7261                         /* STBC needs to have even number of symbols */
7262                         nsyms =
7263                             2 *
7264                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7265                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7266
7267                 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7268                 nsyms += (tot_streams + 3);
7269                 /*
7270                  * 3 bytes/symbol @ legacy 6Mbps rate
7271                  * (-3) excluding service bits and tail bits
7272                  */
7273                 len = (3 * nsyms) - 3;
7274         }
7275
7276         return (u16) len;
7277 }
7278
7279 static void
7280 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7281 {
7282         const struct brcms_c_rateset *rs_dflt;
7283         struct brcms_c_rateset rs;
7284         u8 rate;
7285         u16 entry_ptr;
7286         u8 plcp[D11_PHY_HDR_LEN];
7287         u16 dur, sifs;
7288         uint i;
7289
7290         sifs = get_sifs(wlc->band);
7291
7292         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7293
7294         brcms_c_rateset_copy(rs_dflt, &rs);
7295         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7296
7297         /*
7298          * walk the phy rate table and update MAC core SHM
7299          * basic rate table entries
7300          */
7301         for (i = 0; i < rs.count; i++) {
7302                 rate = rs.rates[i] & BRCMS_RATE_MASK;
7303
7304                 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7305
7306                 /* Calculate the Probe Response PLCP for the given rate */
7307                 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7308
7309                 /*
7310                  * Calculate the duration of the Probe Response
7311                  * frame plus SIFS for the MAC
7312                  */
7313                 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7314                                                 BRCMS_LONG_PREAMBLE, frame_len);
7315                 dur += sifs;
7316
7317                 /* Update the SHM Rate Table entry Probe Response values */
7318                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7319                               (u16) (plcp[0] + (plcp[1] << 8)));
7320                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7321                               (u16) (plcp[2] + (plcp[3] << 8)));
7322                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7323         }
7324 }
7325
7326 /*      Max buffering needed for beacon template/prb resp template is 142 bytes.
7327  *
7328  *      PLCP header is 6 bytes.
7329  *      802.11 A3 header is 24 bytes.
7330  *      Max beacon frame body template length is 112 bytes.
7331  *      Max probe resp frame body template length is 110 bytes.
7332  *
7333  *      *len on input contains the max length of the packet available.
7334  *
7335  *      The *len value is set to the number of bytes in buf used, and starts
7336  *      with the PLCP and included up to, but not including, the 4 byte FCS.
7337  */
7338 static void
7339 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7340                          u32 bcn_rspec,
7341                          struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7342 {
7343         static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7344         struct cck_phy_hdr *plcp;
7345         struct ieee80211_mgmt *h;
7346         int hdr_len, body_len;
7347
7348         hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7349
7350         /* calc buffer size provided for frame body */
7351         body_len = *len - hdr_len;
7352         /* return actual size */
7353         *len = hdr_len + body_len;
7354
7355         /* format PHY and MAC headers */
7356         memset(buf, 0, hdr_len);
7357
7358         plcp = (struct cck_phy_hdr *) buf;
7359
7360         /*
7361          * PLCP for Probe Response frames are filled in from
7362          * core's rate table
7363          */
7364         if (type == IEEE80211_STYPE_BEACON)
7365                 /* fill in PLCP */
7366                 brcms_c_compute_plcp(wlc, bcn_rspec,
7367                                  (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7368                                  (u8 *) plcp);
7369
7370         /* "Regular" and 16 MBSS but not for 4 MBSS */
7371         /* Update the phytxctl for the beacon based on the rspec */
7372         brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7373
7374         h = (struct ieee80211_mgmt *)&plcp[1];
7375
7376         /* fill in 802.11 header */
7377         h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7378
7379         /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7380         /* A1 filled in by MAC for prb resp, broadcast for bcn */
7381         if (type == IEEE80211_STYPE_BEACON)
7382                 memcpy(&h->da, &ether_bcast, ETH_ALEN);
7383         memcpy(&h->sa, &wlc->pub->cur_etheraddr, ETH_ALEN);
7384         memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7385
7386         /* SEQ filled in by MAC */
7387 }
7388
7389 int brcms_c_get_header_len(void)
7390 {
7391         return TXOFF;
7392 }
7393
7394 static void brcms_c_beacon_write(struct brcms_c_info *wlc,
7395                                  struct sk_buff *beacon, u16 tim_offset,
7396                                  u16 dtim_period, bool bcn0, bool bcn1)
7397 {
7398         size_t len;
7399         struct ieee80211_tx_info *tx_info;
7400         struct brcms_hardware *wlc_hw = wlc->hw;
7401         struct ieee80211_hw *ieee_hw = brcms_c_pub(wlc)->ieee_hw;
7402
7403         /* Get tx_info */
7404         tx_info = IEEE80211_SKB_CB(beacon);
7405
7406         len = min_t(size_t, beacon->len, BCN_TMPL_LEN);
7407         wlc->bcn_rspec = ieee80211_get_tx_rate(ieee_hw, tx_info)->hw_value;
7408
7409         brcms_c_compute_plcp(wlc, wlc->bcn_rspec,
7410                              len + FCS_LEN - D11_PHY_HDR_LEN, beacon->data);
7411
7412         /* "Regular" and 16 MBSS but not for 4 MBSS */
7413         /* Update the phytxctl for the beacon based on the rspec */
7414         brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
7415
7416         if (bcn0) {
7417                 /* write the probe response into the template region */
7418                 brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE,
7419                                             (len + 3) & ~3, beacon->data);
7420
7421                 /* write beacon length to SCR */
7422                 brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
7423         }
7424         if (bcn1) {
7425                 /* write the probe response into the template region */
7426                 brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE,
7427                                             (len + 3) & ~3, beacon->data);
7428
7429                 /* write beacon length to SCR */
7430                 brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
7431         }
7432
7433         if (tim_offset != 0) {
7434                 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7435                                   tim_offset + D11B_PHY_HDR_LEN);
7436                 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period);
7437         } else {
7438                 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7439                                   len + D11B_PHY_HDR_LEN);
7440                 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0);
7441         }
7442 }
7443
7444 static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc,
7445                                      struct sk_buff *beacon, u16 tim_offset,
7446                                      u16 dtim_period)
7447 {
7448         struct brcms_hardware *wlc_hw = wlc->hw;
7449         struct bcma_device *core = wlc_hw->d11core;
7450
7451         /* Hardware beaconing for this config */
7452         u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
7453
7454         /* Check if both templates are in use, if so sched. an interrupt
7455          *      that will call back into this routine
7456          */
7457         if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid)
7458                 /* clear any previous status */
7459                 bcma_write32(core, D11REGOFFS(macintstatus), MI_BCNTPL);
7460
7461         if (wlc->beacon_template_virgin) {
7462                 wlc->beacon_template_virgin = false;
7463                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7464                                      true);
7465                 /* mark beacon0 valid */
7466                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7467                 return;
7468         }
7469
7470         /* Check that after scheduling the interrupt both of the
7471          *      templates are still busy. if not clear the int. & remask
7472          */
7473         if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) {
7474                 wlc->defmacintmask |= MI_BCNTPL;
7475                 return;
7476         }
7477
7478         if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN0VLD)) {
7479                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7480                                      false);
7481                 /* mark beacon0 valid */
7482                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7483                 return;
7484         }
7485         if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN1VLD)) {
7486                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period,
7487                                      false, true);
7488                 /* mark beacon0 valid */
7489                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN1VLD);
7490                 return;
7491         }
7492         return;
7493 }
7494
7495 /*
7496  * Update all beacons for the system.
7497  */
7498 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7499 {
7500         struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7501
7502         if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7503                              bsscfg->type == BRCMS_TYPE_ADHOC)) {
7504                 /* Clear the soft intmask */
7505                 wlc->defmacintmask &= ~MI_BCNTPL;
7506                 if (!wlc->beacon)
7507                         return;
7508                 brcms_c_update_beacon_hw(wlc, wlc->beacon,
7509                                          wlc->beacon_tim_offset,
7510                                          wlc->beacon_dtim_period);
7511         }
7512 }
7513
7514 void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon,
7515                             u16 tim_offset, u16 dtim_period)
7516 {
7517         if (!beacon)
7518                 return;
7519         if (wlc->beacon)
7520                 dev_kfree_skb_any(wlc->beacon);
7521         wlc->beacon = beacon;
7522
7523         /* add PLCP */
7524         skb_push(wlc->beacon, D11_PHY_HDR_LEN);
7525         wlc->beacon_tim_offset = tim_offset;
7526         wlc->beacon_dtim_period = dtim_period;
7527         brcms_c_update_beacon(wlc);
7528 }
7529
7530 /* Write ssid into shared memory */
7531 static void
7532 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7533 {
7534         u8 *ssidptr = cfg->SSID;
7535         u16 base = M_SSID;
7536         u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7537
7538         /* padding the ssid with zero and copy it into shm */
7539         memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7540         memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7541
7542         brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7543         brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7544 }
7545
7546 static void
7547 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7548                               struct brcms_bss_cfg *cfg,
7549                               bool suspend)
7550 {
7551         u16 *prb_resp;
7552         int len = BCN_TMPL_LEN;
7553
7554         prb_resp = kmalloc(BCN_TMPL_LEN, GFP_ATOMIC);
7555         if (!prb_resp)
7556                 return;
7557
7558         /*
7559          * write the probe response to hardware, or save in
7560          * the config structure
7561          */
7562
7563         /* create the probe response template */
7564         brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7565                                  cfg, prb_resp, &len);
7566
7567         if (suspend)
7568                 brcms_c_suspend_mac_and_wait(wlc);
7569
7570         /* write the probe response into the template region */
7571         brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7572                                     (len + 3) & ~3, prb_resp);
7573
7574         /* write the length of the probe response frame (+PLCP/-FCS) */
7575         brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7576
7577         /* write the SSID and SSID length */
7578         brcms_c_shm_ssid_upd(wlc, cfg);
7579
7580         /*
7581          * Write PLCP headers and durations for probe response frames
7582          * at all rates. Use the actual frame length covered by the
7583          * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7584          * by subtracting the PLCP len and adding the FCS.
7585          */
7586         len += (-D11_PHY_HDR_LEN + FCS_LEN);
7587         brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7588
7589         if (suspend)
7590                 brcms_c_enable_mac(wlc);
7591
7592         kfree(prb_resp);
7593 }
7594
7595 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7596 {
7597         struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7598
7599         /* update AP or IBSS probe responses */
7600         if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7601                              bsscfg->type == BRCMS_TYPE_ADHOC))
7602                 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7603 }
7604
7605 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7606                            uint *blocks)
7607 {
7608         if (fifo >= NFIFO)
7609                 return -EINVAL;
7610
7611         *blocks = wlc_hw->xmtfifo_sz[fifo];
7612
7613         return 0;
7614 }
7615
7616 void
7617 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7618                   const u8 *addr)
7619 {
7620         brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7621         if (match_reg_offset == RCM_BSSID_OFFSET)
7622                 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7623 }
7624
7625 /*
7626  * Flag 'scan in progress' to withhold dynamic phy calibration
7627  */
7628 void brcms_c_scan_start(struct brcms_c_info *wlc)
7629 {
7630         wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7631 }
7632
7633 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7634 {
7635         wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7636 }
7637
7638 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7639 {
7640         wlc->pub->associated = state;
7641 }
7642
7643 /*
7644  * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7645  * AMPDU traffic, packets pending in hardware have to be invalidated so that
7646  * when later on hardware releases them, they can be handled appropriately.
7647  */
7648 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7649                                struct ieee80211_sta *sta,
7650                                void (*dma_callback_fn))
7651 {
7652         struct dma_pub *dmah;
7653         int i;
7654         for (i = 0; i < NFIFO; i++) {
7655                 dmah = hw->di[i];
7656                 if (dmah != NULL)
7657                         dma_walk_packets(dmah, dma_callback_fn, sta);
7658         }
7659 }
7660
7661 int brcms_c_get_curband(struct brcms_c_info *wlc)
7662 {
7663         return wlc->band->bandunit;
7664 }
7665
7666 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7667 {
7668         int i;
7669
7670         /* Kick DMA to send any pending AMPDU */
7671         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7672                 if (wlc->hw->di[i])
7673                         dma_kick_tx(wlc->hw->di[i]);
7674
7675         return !brcms_txpktpendtot(wlc);
7676 }
7677
7678 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7679 {
7680         wlc->bcn_li_bcn = interval;
7681         if (wlc->pub->up)
7682                 brcms_c_bcn_li_upd(wlc);
7683 }
7684
7685 u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
7686 {
7687         u32 tsf_h, tsf_l;
7688         u64 tsf;
7689
7690         brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7691
7692         tsf = tsf_h;
7693         tsf <<= 32;
7694         tsf |= tsf_l;
7695
7696         return tsf;
7697 }
7698
7699 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
7700 {
7701         u32 tsf_h, tsf_l;
7702
7703         brcms_c_time_lock(wlc);
7704
7705         tsf_l = tsf;
7706         tsf_h = (tsf >> 32);
7707
7708         /* read the tsf timer low, then high to get an atomic read */
7709         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
7710         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
7711
7712         brcms_c_time_unlock(wlc);
7713 }
7714
7715 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7716 {
7717         uint qdbm;
7718
7719         /* Remove override bit and clip to max qdbm value */
7720         qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7721         return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7722 }
7723
7724 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7725 {
7726         uint qdbm;
7727         bool override;
7728
7729         wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7730
7731         /* Return qdbm units */
7732         return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7733 }
7734
7735 /* Process received frames */
7736 /*
7737  * Return true if more frames need to be processed. false otherwise.
7738  * Param 'bound' indicates max. # frames to process before break out.
7739  */
7740 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7741 {
7742         struct d11rxhdr *rxh;
7743         struct ieee80211_hdr *h;
7744         uint len;
7745         bool is_amsdu;
7746
7747         /* frame starts with rxhdr */
7748         rxh = (struct d11rxhdr *) (p->data);
7749
7750         /* strip off rxhdr */
7751         skb_pull(p, BRCMS_HWRXOFF);
7752
7753         /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7754         if (rxh->RxStatus1 & RXS_PBPRES) {
7755                 if (p->len < 2) {
7756                         brcms_err(wlc->hw->d11core,
7757                                   "wl%d: recv: rcvd runt of len %d\n",
7758                                   wlc->pub->unit, p->len);
7759                         goto toss;
7760                 }
7761                 skb_pull(p, 2);
7762         }
7763
7764         h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7765         len = p->len;
7766
7767         if (rxh->RxStatus1 & RXS_FCSERR) {
7768                 if (!(wlc->filter_flags & FIF_FCSFAIL))
7769                         goto toss;
7770         }
7771
7772         /* check received pkt has at least frame control field */
7773         if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7774                 goto toss;
7775
7776         /* not supporting A-MSDU */
7777         is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7778         if (is_amsdu)
7779                 goto toss;
7780
7781         brcms_c_recvctl(wlc, rxh, p);
7782         return;
7783
7784  toss:
7785         brcmu_pkt_buf_free_skb(p);
7786 }
7787
7788 /* Process received frames */
7789 /*
7790  * Return true if more frames need to be processed. false otherwise.
7791  * Param 'bound' indicates max. # frames to process before break out.
7792  */
7793 static bool
7794 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7795 {
7796         struct sk_buff *p;
7797         struct sk_buff *next = NULL;
7798         struct sk_buff_head recv_frames;
7799
7800         uint n = 0;
7801         uint bound_limit = bound ? RXBND : -1;
7802         bool morepending = false;
7803
7804         skb_queue_head_init(&recv_frames);
7805
7806         /* gather received frames */
7807         do {
7808                 /* !give others some time to run! */
7809                 if (n >= bound_limit)
7810                         break;
7811
7812                 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7813                 n++;
7814         } while (morepending);
7815
7816         /* post more rbufs */
7817         dma_rxfill(wlc_hw->di[fifo]);
7818
7819         /* process each frame */
7820         skb_queue_walk_safe(&recv_frames, p, next) {
7821                 struct d11rxhdr_le *rxh_le;
7822                 struct d11rxhdr *rxh;
7823
7824                 skb_unlink(p, &recv_frames);
7825                 rxh_le = (struct d11rxhdr_le *)p->data;
7826                 rxh = (struct d11rxhdr *)p->data;
7827
7828                 /* fixup rx header endianness */
7829                 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7830                 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7831                 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7832                 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7833                 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7834                 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7835                 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7836                 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7837                 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7838                 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7839                 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7840
7841                 brcms_c_recv(wlc_hw->wlc, p);
7842         }
7843
7844         return morepending;
7845 }
7846
7847 /* second-level interrupt processing
7848  *   Return true if another dpc needs to be re-scheduled. false otherwise.
7849  *   Param 'bounded' indicates if applicable loops should be bounded.
7850  */
7851 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7852 {
7853         u32 macintstatus;
7854         struct brcms_hardware *wlc_hw = wlc->hw;
7855         struct bcma_device *core = wlc_hw->d11core;
7856
7857         if (brcms_deviceremoved(wlc)) {
7858                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7859                           __func__);
7860                 brcms_down(wlc->wl);
7861                 return false;
7862         }
7863
7864         /* grab and clear the saved software intstatus bits */
7865         macintstatus = wlc->macintstatus;
7866         wlc->macintstatus = 0;
7867
7868         brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7869                       wlc_hw->unit, macintstatus);
7870
7871         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7872
7873         /* tx status */
7874         if (macintstatus & MI_TFS) {
7875                 bool fatal;
7876                 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7877                         wlc->macintstatus |= MI_TFS;
7878                 if (fatal) {
7879                         brcms_err(core, "MI_TFS: fatal\n");
7880                         goto fatal;
7881                 }
7882         }
7883
7884         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7885                 brcms_c_tbtt(wlc);
7886
7887         /* ATIM window end */
7888         if (macintstatus & MI_ATIMWINEND) {
7889                 brcms_dbg_info(core, "end of ATIM window\n");
7890                 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7891                 wlc->qvalid = 0;
7892         }
7893
7894         /*
7895          * received data or control frame, MI_DMAINT is
7896          * indication of RX_FIFO interrupt
7897          */
7898         if (macintstatus & MI_DMAINT)
7899                 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7900                         wlc->macintstatus |= MI_DMAINT;
7901
7902         /* noise sample collected */
7903         if (macintstatus & MI_BG_NOISE)
7904                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7905
7906         if (macintstatus & MI_GP0) {
7907                 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7908                           "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7909
7910                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7911                             __func__, ai_get_chip_id(wlc_hw->sih),
7912                             ai_get_chiprev(wlc_hw->sih));
7913                 brcms_fatal_error(wlc_hw->wlc->wl);
7914         }
7915
7916         /* gptimer timeout */
7917         if (macintstatus & MI_TO)
7918                 bcma_write32(core, D11REGOFFS(gptimer), 0);
7919
7920         if (macintstatus & MI_RFDISABLE) {
7921                 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7922                                " RF Disable Input\n", wlc_hw->unit);
7923                 brcms_rfkill_set_hw_state(wlc->wl);
7924         }
7925
7926         /* BCN template is available */
7927         if (macintstatus & MI_BCNTPL)
7928                 brcms_c_update_beacon(wlc);
7929
7930         /* it isn't done and needs to be resched if macintstatus is non-zero */
7931         return wlc->macintstatus != 0;
7932
7933  fatal:
7934         brcms_fatal_error(wlc_hw->wlc->wl);
7935         return wlc->macintstatus != 0;
7936 }
7937
7938 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7939 {
7940         struct bcma_device *core = wlc->hw->d11core;
7941         struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7942         u16 chanspec;
7943
7944         brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7945
7946         chanspec = ch20mhz_chspec(ch->hw_value);
7947
7948         brcms_b_init(wlc->hw, chanspec);
7949
7950         /* update beacon listen interval */
7951         brcms_c_bcn_li_upd(wlc);
7952
7953         /* write ethernet address to core */
7954         brcms_c_set_mac(wlc->bsscfg);
7955         brcms_c_set_bssid(wlc->bsscfg);
7956
7957         /* Update tsf_cfprep if associated and up */
7958         if (wlc->pub->associated && wlc->pub->up) {
7959                 u32 bi;
7960
7961                 /* get beacon period and convert to uS */
7962                 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7963                 /*
7964                  * update since init path would reset
7965                  * to default value
7966                  */
7967                 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7968                              bi << CFPREP_CBI_SHIFT);
7969
7970                 /* Update maccontrol PM related bits */
7971                 brcms_c_set_ps_ctrl(wlc);
7972         }
7973
7974         brcms_c_bandinit_ordered(wlc, chanspec);
7975
7976         /* init probe response timeout */
7977         brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7978
7979         /* init max burst txop (framebursting) */
7980         brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7981                       (wlc->
7982                        _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7983
7984         /* initialize maximum allowed duty cycle */
7985         brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7986         brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7987
7988         /*
7989          * Update some shared memory locations related to
7990          * max AMPDU size allowed to received
7991          */
7992         brcms_c_ampdu_shm_upd(wlc->ampdu);
7993
7994         /* band-specific inits */
7995         brcms_c_bsinit(wlc);
7996
7997         /* Enable EDCF mode (while the MAC is suspended) */
7998         bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7999         brcms_c_edcf_setparams(wlc, false);
8000
8001         /* read the ucode version if we have not yet done so */
8002         if (wlc->ucode_rev == 0) {
8003                 u16 rev;
8004                 u16 patch;
8005
8006                 rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
8007                 patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
8008                 wlc->ucode_rev = (rev << NBITS(u16)) | patch;
8009                 snprintf(wlc->wiphy->fw_version,
8010                          sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
8011         }
8012
8013         /* ..now really unleash hell (allow the MAC out of suspend) */
8014         brcms_c_enable_mac(wlc);
8015
8016         /* suspend the tx fifos and mute the phy for preism cac time */
8017         if (mute_tx)
8018                 brcms_b_mute(wlc->hw, true);
8019
8020         /* enable the RF Disable Delay timer */
8021         bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8022
8023         /*
8024          * Initialize WME parameters; if they haven't been set by some other
8025          * mechanism (IOVar, etc) then read them from the hardware.
8026          */
8027         if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8028                 /* Uninitialized; read from HW */
8029                 int ac;
8030
8031                 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8032                         wlc->wme_retries[ac] =
8033                             brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8034         }
8035 }
8036
8037 /*
8038  * The common driver entry routine. Error codes should be unique
8039  */
8040 struct brcms_c_info *
8041 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8042                bool piomode, uint *perr)
8043 {
8044         struct brcms_c_info *wlc;
8045         uint err = 0;
8046         uint i, j;
8047         struct brcms_pub *pub;
8048
8049         /* allocate struct brcms_c_info state and its substructures */
8050         wlc = brcms_c_attach_malloc(unit, &err, 0);
8051         if (wlc == NULL)
8052                 goto fail;
8053         wlc->wiphy = wl->wiphy;
8054         pub = wlc->pub;
8055
8056 #if defined(DEBUG)
8057         wlc_info_dbg = wlc;
8058 #endif
8059
8060         wlc->band = wlc->bandstate[0];
8061         wlc->core = wlc->corestate;
8062         wlc->wl = wl;
8063         pub->unit = unit;
8064         pub->_piomode = piomode;
8065         wlc->bandinit_pending = false;
8066         wlc->beacon_template_virgin = true;
8067
8068         /* populate struct brcms_c_info with default values  */
8069         brcms_c_info_init(wlc, unit);
8070
8071         /* update sta/ap related parameters */
8072         brcms_c_ap_upd(wlc);
8073
8074         /*
8075          * low level attach steps(all hw accesses go
8076          * inside, no more in rest of the attach)
8077          */
8078         err = brcms_b_attach(wlc, core, unit, piomode);
8079         if (err)
8080                 goto fail;
8081
8082         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8083
8084         pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8085
8086         /* disable allowed duty cycle */
8087         wlc->tx_duty_cycle_ofdm = 0;
8088         wlc->tx_duty_cycle_cck = 0;
8089
8090         brcms_c_stf_phy_chain_calc(wlc);
8091
8092         /* txchain 1: txant 0, txchain 2: txant 1 */
8093         if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8094                 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8095
8096         /* push to BMAC driver */
8097         wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8098                                wlc->stf->hw_rxchain);
8099
8100         /* pull up some info resulting from the low attach */
8101         for (i = 0; i < NFIFO; i++)
8102                 wlc->core->txavail[i] = wlc->hw->txavail[i];
8103
8104         memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8105         memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8106
8107         for (j = 0; j < wlc->pub->_nbands; j++) {
8108                 wlc->band = wlc->bandstate[j];
8109
8110                 if (!brcms_c_attach_stf_ant_init(wlc)) {
8111                         err = 24;
8112                         goto fail;
8113                 }
8114
8115                 /* default contention windows size limits */
8116                 wlc->band->CWmin = APHY_CWMIN;
8117                 wlc->band->CWmax = PHY_CWMAX;
8118
8119                 /* init gmode value */
8120                 if (wlc->band->bandtype == BRCM_BAND_2G) {
8121                         wlc->band->gmode = GMODE_AUTO;
8122                         brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8123                                            wlc->band->gmode);
8124                 }
8125
8126                 /* init _n_enab supported mode */
8127                 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8128                         pub->_n_enab = SUPPORT_11N;
8129                         brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8130                                                    ((pub->_n_enab ==
8131                                                      SUPPORT_11N) ? WL_11N_2x2 :
8132                                                     WL_11N_3x3));
8133                 }
8134
8135                 /* init per-band default rateset, depend on band->gmode */
8136                 brcms_default_rateset(wlc, &wlc->band->defrateset);
8137
8138                 /* fill in hw_rateset */
8139                 brcms_c_rateset_filter(&wlc->band->defrateset,
8140                                    &wlc->band->hw_rateset, false,
8141                                    BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8142                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8143         }
8144
8145         /*
8146          * update antenna config due to
8147          * wlc->stf->txant/txchain/ant_rx_ovr change
8148          */
8149         brcms_c_stf_phy_txant_upd(wlc);
8150
8151         /* attach each modules */
8152         err = brcms_c_attach_module(wlc);
8153         if (err != 0)
8154                 goto fail;
8155
8156         if (!brcms_c_timers_init(wlc, unit)) {
8157                 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8158                           __func__);
8159                 err = 32;
8160                 goto fail;
8161         }
8162
8163         /* depend on rateset, gmode */
8164         wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8165         if (!wlc->cmi) {
8166                 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8167                           "\n", unit, __func__);
8168                 err = 33;
8169                 goto fail;
8170         }
8171
8172         /* init default when all parameters are ready, i.e. ->rateset */
8173         brcms_c_bss_default_init(wlc);
8174
8175         /*
8176          * Complete the wlc default state initializations..
8177          */
8178
8179         wlc->bsscfg->wlc = wlc;
8180
8181         wlc->mimoft = FT_HT;
8182         wlc->mimo_40txbw = AUTO;
8183         wlc->ofdm_40txbw = AUTO;
8184         wlc->cck_40txbw = AUTO;
8185         brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8186
8187         /* Set default values of SGI */
8188         if (BRCMS_SGI_CAP_PHY(wlc)) {
8189                 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8190                                                BRCMS_N_SGI_40));
8191         } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8192                 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8193                                                BRCMS_N_SGI_40));
8194         } else {
8195                 brcms_c_ht_update_sgi_rx(wlc, 0);
8196         }
8197
8198         brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8199
8200         if (perr)
8201                 *perr = 0;
8202
8203         return wlc;
8204
8205  fail:
8206         wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8207                   unit, __func__, err);
8208         if (wlc)
8209                 brcms_c_detach(wlc);
8210
8211         if (perr)
8212                 *perr = err;
8213         return NULL;
8214 }