2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_PHY_INT_H_
18 #define _BRCM_PHY_INT_H_
21 #include <brcmu_utils.h>
22 #include <brcmu_wifi.h>
24 #define PHY_VERSION { 1, 82, 8, 0 }
26 #define LCNXN_BASEREV 16
30 struct brcms_phy_srom_fem {
31 /* TSSI positive slope, 1: positive, 0: negative */
33 /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
35 /* support 32 combinations of different Pdet dynamic ranges */
37 /* TR switch isolation */
39 /* antswctrl lookup table configuration: 32 possible choices */
43 #define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
44 #define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
46 #define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
47 #define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
48 #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
49 #define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
50 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
51 #define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
52 #define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
57 #define A_HIGH_CHANS 2
61 #define FIRST_REF5_CHANNUM 149
62 #define LAST_REF5_CHANNUM 165
63 #define FIRST_5G_CHAN 14
64 #define LAST_5G_CHAN 50
65 #define FIRST_MID_5G_CHAN 14
66 #define LAST_MID_5G_CHAN 35
67 #define FIRST_HIGH_5G_CHAN 36
68 #define LAST_HIGH_5G_CHAN 41
69 #define FIRST_LOW_5G_CHAN 42
70 #define LAST_LOW_5G_CHAN 50
72 #define BASE_LOW_5G_CHAN 4900
73 #define BASE_MID_5G_CHAN 5100
74 #define BASE_HIGH_5G_CHAN 5500
76 #define CHAN5G_FREQ(chan) (5000 + chan*5)
77 #define CHAN2G_FREQ(chan) (2407 + chan*5)
79 #define TXP_FIRST_CCK 0
80 #define TXP_LAST_CCK 3
81 #define TXP_FIRST_OFDM 4
82 #define TXP_LAST_OFDM 11
83 #define TXP_FIRST_OFDM_20_CDD 12
84 #define TXP_LAST_OFDM_20_CDD 19
85 #define TXP_FIRST_MCS_20_SISO 20
86 #define TXP_LAST_MCS_20_SISO 27
87 #define TXP_FIRST_MCS_20_CDD 28
88 #define TXP_LAST_MCS_20_CDD 35
89 #define TXP_FIRST_MCS_20_STBC 36
90 #define TXP_LAST_MCS_20_STBC 43
91 #define TXP_FIRST_MCS_20_SDM 44
92 #define TXP_LAST_MCS_20_SDM 51
93 #define TXP_FIRST_OFDM_40_SISO 52
94 #define TXP_LAST_OFDM_40_SISO 59
95 #define TXP_FIRST_OFDM_40_CDD 60
96 #define TXP_LAST_OFDM_40_CDD 67
97 #define TXP_FIRST_MCS_40_SISO 68
98 #define TXP_LAST_MCS_40_SISO 75
99 #define TXP_FIRST_MCS_40_CDD 76
100 #define TXP_LAST_MCS_40_CDD 83
101 #define TXP_FIRST_MCS_40_STBC 84
102 #define TXP_LAST_MCS_40_STBC 91
103 #define TXP_FIRST_MCS_40_SDM 92
104 #define TXP_LAST_MCS_40_SDM 99
105 #define TXP_MCS_32 100
106 #define TXP_NUM_RATES 101
107 #define ADJ_PWR_TBL_LEN 84
109 #define TXP_FIRST_SISO_MCS_20 20
110 #define TXP_LAST_SISO_MCS_20 27
112 #define PHY_CORE_NUM_1 1
113 #define PHY_CORE_NUM_2 2
114 #define PHY_CORE_NUM_3 3
115 #define PHY_CORE_NUM_4 4
116 #define PHY_CORE_MAX PHY_CORE_NUM_4
122 #define MA_WINDOW_SZ 8
124 #define PHY_NOISE_SAMPLE_MON 1
125 #define PHY_NOISE_SAMPLE_EXTERNAL 2
126 #define PHY_NOISE_WINDOW_SZ 16
127 #define PHY_NOISE_GLITCH_INIT_MA 10
128 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
129 #define PHY_NOISE_STATE_MON 0x1
130 #define PHY_NOISE_STATE_EXTERNAL 0x2
131 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
132 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
134 #define PHY_NOISE_OFFSETFACT_4322 (-103)
135 #define PHY_NOISE_MA_WINDOW_SZ 2
137 #define PHY_RSSI_TABLE_SIZE 64
138 #define RSSI_ANT_MERGE_MAX 0
139 #define RSSI_ANT_MERGE_MIN 1
140 #define RSSI_ANT_MERGE_AVG 2
142 #define PHY_TSSI_TABLE_SIZE 64
143 #define APHY_TSSI_TABLE_SIZE 256
144 #define TX_GAIN_TABLE_LENGTH 64
145 #define DEFAULT_11A_TXP_IDX 24
146 #define NUM_TSSI_FRAMES 4
147 #define NULL_TSSI 0x7f
148 #define NULL_TSSI_W 0x7f7f
150 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
152 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
154 #define PHY_TXPWR_MIN 10
155 #define PHY_TXPWR_MIN_NPHY 8
156 #define RADIOPWR_OVERRIDE_DEF (-1)
158 #define PWRTBL_NUM_COEFF 3
160 #define SPURAVOID_DISABLE 0
161 #define SPURAVOID_AUTO 1
162 #define SPURAVOID_FORCEON 2
163 #define SPURAVOID_FORCEON2 3
165 #define PHY_SW_TIMER_FAST 15
166 #define PHY_SW_TIMER_SLOW 60
167 #define PHY_SW_TIMER_GLACIAL 120
169 #define PHY_PERICAL_AUTO 0
170 #define PHY_PERICAL_FULL 1
171 #define PHY_PERICAL_PARTIAL 2
173 #define PHY_PERICAL_NODELAY 0
174 #define PHY_PERICAL_INIT_DELAY 5
175 #define PHY_PERICAL_ASSOC_DELAY 5
176 #define PHY_PERICAL_WDOG_DELAY 5
178 #define MPHASE_TXCAL_NUMCMDS 2
180 #define PHY_PERICAL_MPHASE_PENDING(pi) \
181 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
184 MPHASE_CAL_STATE_IDLE = 0,
185 MPHASE_CAL_STATE_INIT = 1,
186 MPHASE_CAL_STATE_TXPHASE0,
187 MPHASE_CAL_STATE_TXPHASE1,
188 MPHASE_CAL_STATE_TXPHASE2,
189 MPHASE_CAL_STATE_TXPHASE3,
190 MPHASE_CAL_STATE_TXPHASE4,
191 MPHASE_CAL_STATE_TXPHASE5,
192 MPHASE_CAL_STATE_PAPDCAL,
193 MPHASE_CAL_STATE_RXCAL,
194 MPHASE_CAL_STATE_RSSICAL,
195 MPHASE_CAL_STATE_IDLETSSI
209 #define RDR_TIER_SIZE 64
210 #define RDR_LIST_SIZE (512/3)
211 #define RDR_EPOCH_SIZE 40
212 #define RDR_NANTENNAS 2
213 #define RDR_NTIER_SIZE RDR_LIST_SIZE
214 #define RDR_LP_BUFFER_SIZE 64
215 #define LP_LEN_HIS_SIZE 10
217 #define STATIC_NUM_RF 32
218 #define STATIC_NUM_BB 9
220 #define BB_MULT_MASK 0x0000ffff
221 #define BB_MULT_VALID_MASK 0x80000000
223 #define CORDIC_AG 39797
225 #define FIXED(X) ((s32)((X) << 16))
228 (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
230 #define PHY_CHAIN_TX_DISABLE_TEMP 115
231 #define PHY_HYSTERESIS_DELTATEMP 5
233 #define SCAN_INPROG_PHY(pi) \
234 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
236 #define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
238 #define ASSOC_INPROG_PHY(pi) \
239 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
241 #define SCAN_RM_IN_PROGRESS(pi) \
242 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
244 #define PHY_MUTED(pi) \
245 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
247 #define PUB_NOT_ASSOC(pi) \
248 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
250 struct phy_table_info {
264 struct interference_info {
265 u8 curr_home_channel;
266 u16 crsminpwrthld_40_stored;
267 u16 crsminpwrthld_20L_stored;
268 u16 crsminpwrthld_20U_stored;
269 u16 init_gain_code_core1_stored;
270 u16 init_gain_code_core2_stored;
271 u16 init_gain_codeb_core1_stored;
272 u16 init_gain_codeb_core2_stored;
273 u16 init_gain_table_stored[4];
275 u16 clip1_hi_gain_code_core1_stored;
276 u16 clip1_hi_gain_code_core2_stored;
277 u16 clip1_hi_gain_codeb_core1_stored;
278 u16 clip1_hi_gain_codeb_core2_stored;
279 u16 nb_clip_thresh_core1_stored;
280 u16 nb_clip_thresh_core2_stored;
281 u16 init_ofdmlna2gainchange_stored[4];
282 u16 init_ccklna2gainchange_stored[4];
283 u16 clip1_lo_gain_code_core1_stored;
284 u16 clip1_lo_gain_code_core2_stored;
285 u16 clip1_lo_gain_codeb_core1_stored;
286 u16 clip1_lo_gain_codeb_core2_stored;
287 u16 w1_clip_thresh_core1_stored;
288 u16 w1_clip_thresh_core2_stored;
289 u16 radio_2056_core1_rssi_gain_stored;
290 u16 radio_2056_core2_rssi_gain_stored;
291 u16 energy_drop_timeout_len_stored;
293 u16 ed_crs40_assertthld0_stored;
294 u16 ed_crs40_assertthld1_stored;
295 u16 ed_crs40_deassertthld0_stored;
296 u16 ed_crs40_deassertthld1_stored;
297 u16 ed_crs20L_assertthld0_stored;
298 u16 ed_crs20L_assertthld1_stored;
299 u16 ed_crs20L_deassertthld0_stored;
300 u16 ed_crs20L_deassertthld1_stored;
301 u16 ed_crs20U_assertthld0_stored;
302 u16 ed_crs20U_assertthld1_stored;
303 u16 ed_crs20U_deassertthld0_stored;
304 u16 ed_crs20U_deassertthld1_stored;
307 u16 badplcp_ma_previous;
308 u16 badplcp_ma_total;
309 u16 badplcp_ma_list[MA_WINDOW_SZ];
310 int badplcp_ma_index;
312 s16 bphy_pre_badplcp_cnt;
316 u16 init_gainb_core1;
317 u16 init_gainb_core2;
318 u16 init_gain_rfseq[4];
326 u16 radio_2057_core1_rssi_wb1a_gc_stored;
327 u16 radio_2057_core2_rssi_wb1a_gc_stored;
328 u16 radio_2057_core1_rssi_wb1g_gc_stored;
329 u16 radio_2057_core2_rssi_wb1g_gc_stored;
330 u16 radio_2057_core1_rssi_wb2_gc_stored;
331 u16 radio_2057_core2_rssi_wb2_gc_stored;
332 u16 radio_2057_core1_rssi_nb_gc_stored;
333 u16 radio_2057_core2_rssi_nb_gc_stored;
336 struct aci_save_gphy {
346 u16 div_search_gn_change;
354 u16 clip_pwdn_thresh;
355 u16 clip_n1p1_thresh;
356 u16 clip_n1_pwdn_thresh;
360 u16 clip_p1_p2_thresh;
367 u16 div_srch_gn_back;
372 struct lo_complex_abgphy_info {
377 struct nphy_iq_comp {
384 struct nphy_txpwrindex {
387 s8 index_internal_save;
397 struct txiqcal_cache {
399 u16 txcal_coeffs_2G[8];
400 u16 txcal_radio_regs_2G[8];
401 struct nphy_iq_comp rxcal_coeffs_2G;
403 u16 txcal_coeffs_5G[8];
404 u16 txcal_radio_regs_5G[8];
405 struct nphy_iq_comp rxcal_coeffs_5G;
408 struct nphy_pwrctrl {
437 struct nphy_txgains {
445 #define PHY_NOISEVAR_BUFSIZE 10
447 struct nphy_noisevar_buf {
449 int tone_id[PHY_NOISEVAR_BUFSIZE];
450 u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
451 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
454 struct rssical_cache {
455 u16 rssical_radio_regs_2G[2];
456 u16 rssical_phyregs_2G[12];
458 u16 rssical_radio_regs_5G[2];
459 u16 rssical_phyregs_5G[12];
462 struct lcnphy_cal_results {
472 u16 txiqlocal_bestcoeffs[11];
473 u16 txiqlocal_bestcoeffs_valid;
475 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
482 u16 sslpnCalibClkEnCtrl;
484 u16 rxiqcal_coeff_a0;
485 u16 rxiqcal_coeff_b0;
489 struct brcms_phy *phy_head;
491 struct phy_shim_info *physhim;
511 s8 phy_noise_window[MA_WINDOW_SZ];
512 uint phy_noise_index;
521 struct brcms_phy_pub {
534 struct phy_func_ptr {
535 void (*init)(struct brcms_phy *);
536 void (*calinit)(struct brcms_phy *);
537 void (*chanset)(struct brcms_phy *, u16 chanspec);
538 void (*txpwrrecalc)(struct brcms_phy *);
539 int (*longtrn)(struct brcms_phy *, int);
540 void (*txiqccget)(struct brcms_phy *, u16 *, u16 *);
541 void (*txiqccset)(struct brcms_phy *, u16, u16);
542 u16 (*txloccget)(struct brcms_phy *);
543 void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *);
544 void (*carrsuppr)(struct brcms_phy *);
545 s32 (*rxsigpwr)(struct brcms_phy *, s32);
546 void (*detach)(struct brcms_phy *);
550 struct brcms_phy_pub pubpi_ro;
551 struct shared_phy *sh;
552 struct phy_func_ptr pi_fptr;
555 struct brcms_phy_lcnphy *pi_lcnphy;
557 bool user_txpwr_at_rfport;
559 struct bcma_device *d11core;
560 struct brcms_phy *next;
561 struct brcms_phy_pub pubpi;
565 bool ofdm_rateset_war;
566 bool bf_preempt_4306;
573 bool init_in_progress;
577 bool watchdog_override;
580 int phynoise_chan_watchdog;
581 bool phynoise_polling;
585 s16 txpa_2g[PWRTBL_NUM_COEFF];
586 s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
587 s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
588 s16 txpa_5g_low[PWRTBL_NUM_COEFF];
589 s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
590 s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
593 u8 tx_srom_max_5g_low;
594 u8 tx_srom_max_5g_mid;
595 u8 tx_srom_max_5g_hi;
596 u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
597 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
598 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
599 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
600 u8 tx_user_target[TXP_NUM_RATES];
601 s8 tx_power_offset[TXP_NUM_RATES];
602 u8 tx_power_target[TXP_NUM_RATES];
604 struct brcms_phy_srom_fem srom_fem2g;
605 struct brcms_phy_srom_fem srom_fem5g;
608 u8 tx_power_max_rate_ind;
617 s8 n_preamble_override;
621 s8 idle_tssi[CH_5G_GROUP];
625 u8 txpwr_limit[TXP_NUM_RATES];
626 u8 txpwr_env_limit[TXP_NUM_RATES];
627 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
629 bool channel_14_wide_filter;
632 bool txpwridx_override_aphy;
633 s16 radiopwr_override;
637 bool edcrs_threshold_lock;
642 s16 ofdm_analog_filt_bw_override;
643 s16 cck_analog_filt_bw_override;
644 s16 ofdm_rccal_override;
645 s16 cck_rccal_override;
648 uint interference_mode_crs_time;
650 bool interference_mode_crs;
652 u32 phy_tx_tone_freq;
655 bool phy_fixed_noise;
658 s8 carrier_suppr_disable;
665 s16 phy_txcore_disable_temp;
666 s16 phy_txcore_enable_temp;
667 s8 phy_tempsense_offset;
668 bool phy_txcore_heatedup;
676 struct lo_complex_abgphy_info gphy_locomp_iq
677 [STATIC_NUM_RF][STATIC_NUM_BB];
678 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
679 u16 gain_table[TX_GAIN_TABLE_LENGTH];
681 s16 max_lpback_gain_hdB;
682 s16 trsw_rx_gain_hdB;
686 int nrssi_table_delta;
687 int nrssi_slope_scale;
688 int nrssi_slope_offset;
695 u8 a_band_high_disable;
698 u16 global_tx_bb_dc_bias_loft;
718 u16 freqtrack_saved_regs[2];
719 int cur_interference_mode;
720 bool hwpwrctrl_capable;
721 bool temppwrctrl_capable;
730 bool nphy_tableloaded;
732 u32 nphy_bb_mult_save;
733 u16 nphy_txiqlocal_bestc[11];
734 bool nphy_txiqlocal_coeffsvalid;
735 struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
736 struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
762 u32 nphy_rxcalparams;
765 bool phy_isspuravoid;
771 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
774 bool nphy_gain_boost;
775 bool nphy_elna_gain_config;
777 u16 old_bphy_testcontrol;
783 uint nphy_perical_last;
784 u8 cal_type_override;
785 u8 mphase_cal_phase_id;
786 u8 mphase_txcal_cmdidx;
787 u8 mphase_txcal_numcmds;
788 u16 mphase_txcal_bestcoeffs[11];
789 u16 nphy_txiqlocal_chanspec;
790 u16 nphy_iqcal_chanspec_2G;
791 u16 nphy_iqcal_chanspec_5G;
792 u16 nphy_rssical_chanspec_2G;
793 u16 nphy_rssical_chanspec_5G;
794 struct wlapi_timer *phycal_timer;
795 bool use_int_tx_iqlo_cal_nphy;
796 bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
797 s16 nphy_lastcal_temp;
799 struct txiqcal_cache calibration_cache;
800 struct rssical_cache rssical_cache;
802 u8 nphy_txpwr_idx[2];
803 u8 nphy_papd_cal_type;
804 uint nphy_papd_last_cal;
805 u16 nphy_papd_tx_gain_at_last_cal[2];
806 u8 nphy_papd_cal_gain_index[2];
807 s16 nphy_papd_epsilon_offset[2];
808 bool nphy_papd_recal_enable;
809 u32 nphy_papd_recal_counter;
810 bool nphy_force_papd_cal;
815 u16 classifier_state;
817 uint nphy_deaf_count;
821 u16 rfctrlIntc1_save;
822 u16 rfctrlIntc2_save;
823 bool first_cal_after_assoc;
824 u16 tx_rx_cal_radio_saveregs[22];
825 u16 tx_rx_cal_phy_saveregs[15];
827 u8 nphy_cal_orig_pwr_idx[2];
828 u8 nphy_txcal_pwr_idx[2];
829 u8 nphy_rxcal_pwr_idx[2];
830 u16 nphy_cal_orig_tx_gain[2];
831 struct nphy_txgains nphy_cal_target_gain;
832 u16 nphy_txcal_bbmult;
835 u16 nphy_saved_bbconf;
837 bool nphy_gband_spurwar_en;
838 bool nphy_gband_spurwar2_en;
839 bool nphy_aband_spurwar_en;
840 u16 nphy_rccal_value;
841 u16 nphy_crsminpwr[3];
842 struct nphy_noisevar_buf nphy_saved_noisevars;
843 bool nphy_anarxlpf_adjusted;
844 bool nphy_crsminpwr_adjusted;
845 bool nphy_noisevars_adjusted;
847 bool nphy_rxcal_active;
848 u16 radar_percal_mask;
849 bool dfs_lp_buffer_nphy;
851 u16 nphy_fineclockgatecontrol;
858 s16 noise_crsminpwr_index;
861 u16 init_gainb_core1;
862 u16 init_gainb_core2;
863 u8 aci_noise_curr_channel;
864 u16 init_gain_rfseq[4];
868 bool nphy_sample_play_lpf_bw_ctl_ovr;
875 uint tbl_save_offset;
878 s8 txpwrindex[PHY_CORE_MAX];
899 struct radio_20xx_regs {
905 struct lcnphy_radio_regs {
913 extern u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
914 extern void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
915 extern void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
916 extern void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
917 extern void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
919 extern u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
920 extern void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
921 extern void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
922 extern void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask,
924 extern void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
926 extern void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
928 extern void wlc_phyreg_enter(struct brcms_phy_pub *pih);
929 extern void wlc_phyreg_exit(struct brcms_phy_pub *pih);
930 extern void wlc_radioreg_enter(struct brcms_phy_pub *pih);
931 extern void wlc_radioreg_exit(struct brcms_phy_pub *pih);
933 extern void wlc_phy_read_table(struct brcms_phy *pi,
934 const struct phytbl_info *ptbl_info,
935 u16 tblAddr, u16 tblDataHi,
937 extern void wlc_phy_write_table(struct brcms_phy *pi,
938 const struct phytbl_info *ptbl_info,
939 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
940 extern void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id,
941 uint tbl_offset, u16 tblAddr, u16 tblDataHi,
943 extern void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
945 extern void write_phy_channel_reg(struct brcms_phy *pi, uint val);
946 extern void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
948 extern u8 wlc_phy_nbits(s32 value);
949 extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
951 extern uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
952 struct radio_20xx_regs *radioregs);
953 extern uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
954 const struct radio_regs *radioregs,
957 extern void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
959 extern void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
960 extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
963 extern void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
964 extern void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
966 extern bool wlc_phy_attach_nphy(struct brcms_phy *pi);
967 extern bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
969 extern void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
971 extern void wlc_phy_init_nphy(struct brcms_phy *pi);
972 extern void wlc_phy_init_lcnphy(struct brcms_phy *pi);
974 extern void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
975 extern void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
977 extern void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi,
979 extern void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi,
981 extern void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi,
983 extern int wlc_phy_channel2freq(uint channel);
984 extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
985 extern int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
987 extern void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
988 extern s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
990 extern void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
991 extern void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
992 extern void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
994 extern void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
995 extern void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
996 extern void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
997 extern void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz,
998 u16 max_val, bool iqcalmode);
1000 extern void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
1001 u8 *max_pwr, u8 rate_id);
1002 extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1004 u8 rate_ofdm_start);
1005 extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1010 extern u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
1011 extern s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
1012 extern s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
1013 extern s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
1014 extern void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
1015 extern void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
1016 extern void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
1017 extern void wlc_2064_vco_cal(struct brcms_phy *pi);
1019 extern void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
1021 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
1022 #define LCNPHY_TX_POWER_TABLE_SIZE 128
1023 #define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1024 #define LCNPHY_TBL_ID_TXPWRCTL 0x07
1025 #define LCNPHY_TX_PWR_CTRL_OFF 0
1026 #define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
1027 #define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
1031 #define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
1033 extern void wlc_lcnphy_write_table(struct brcms_phy *pi,
1034 const struct phytbl_info *pti);
1035 extern void wlc_lcnphy_read_table(struct brcms_phy *pi,
1036 struct phytbl_info *pti);
1037 extern void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1038 extern void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1039 extern void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1040 extern u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1041 extern void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0,
1042 u8 *eq0, u8 *fi0, u8 *fq0);
1043 extern void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1044 extern void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1045 extern bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1046 extern void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1047 extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1048 extern void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr,
1050 extern void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1052 extern s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1054 #define NPHY_MAX_HPVGA1_INDEX 10
1055 #define NPHY_DEF_HPVGA1_INDEXLIMIT 7
1063 extern void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi,
1065 extern void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1067 #define wlc_phy_write_table_nphy(pi, pti) \
1068 wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
1070 #define wlc_phy_read_table_nphy(pi, pti) \
1071 wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73)
1073 #define wlc_nphy_table_addr(pi, id, off) \
1074 wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73)
1076 #define wlc_nphy_table_data_write(pi, w, v) \
1077 wlc_phy_table_data_write((pi), (w), (v))
1079 extern void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o,
1081 extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
1084 #define PHY_IPA(pi) \
1085 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1086 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1088 #define BRCMS_PHY_WAR_PR51571(pi) \
1089 if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
1090 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol))
1092 extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1093 extern void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1094 extern void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1096 extern u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1097 extern void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1099 extern void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1101 extern void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1102 extern s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1104 extern u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1106 extern void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1107 u16 num_samps, u8 wait_time,
1110 extern void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1111 struct nphy_iq_comp *comp);
1112 extern void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1114 extern void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih,
1116 extern u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1118 extern void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1119 extern void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1120 extern void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1121 extern void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1122 extern u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1124 extern struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1125 extern int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1126 struct nphy_txgains target_gain,
1128 extern int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi,
1129 struct nphy_txgains target_gain,
1131 extern void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1132 s8 txpwrindex, bool res);
1133 extern void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1134 extern int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1135 s32 *rssi_buf, u8 nsamps);
1136 extern void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1137 extern int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1138 extern void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi,
1139 s32 dBm_targetpower, bool debug);
1140 extern int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
1142 extern void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1143 extern void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1145 extern void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1147 extern int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi,
1148 struct d11rxhdr *rxh);
1150 #define NPHY_TESTPATTERN_BPHY_EVM 0
1151 #define NPHY_TESTPATTERN_BPHY_RFCS 1
1153 extern void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1155 void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1157 extern s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi,
1160 extern bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1161 #endif /* _BRCM_PHY_INT_H_ */