2 * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
4 * Copyright (c) 2010, ST-Ericsson
5 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
8 * ST-Ericsson UMAC CW1200 driver which is
9 * Copyright (c) 2010, ST-Ericsson
10 * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/vmalloc.h>
18 #include <linux/sched.h>
19 #include <linux/firmware.h>
27 static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
30 u32 silicon_type = (config_reg_val >> 24) & 0x7;
31 u32 silicon_vers = (config_reg_val >> 31) & 0x1;
33 switch (silicon_type) {
36 hw_type = HIF_9000_SILICON_VERSATILE;
39 case 0x02: /* CW1x00 */
40 case 0x04: /* CW1x60 */
41 *major_revision = silicon_type;
43 hw_type = HIF_8601_VERSATILE;
45 hw_type = HIF_8601_SILICON;
54 static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
56 int ret, block, num_blocks;
62 const struct firmware *firmware = NULL;
64 /* Macroses are local. */
65 #define APB_WRITE(reg, val) \
67 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
71 #define APB_WRITE2(reg, val) \
73 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
77 #define APB_READ(reg, val) \
79 ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
83 #define REG_WRITE(reg, val) \
85 ret = cw1200_reg_write_32(priv, (reg), (val)); \
89 #define REG_READ(reg, val) \
91 ret = cw1200_reg_read_32(priv, (reg), &(val)); \
96 switch (priv->hw_revision) {
97 case CW1200_HW_REV_CUT10:
98 fw_path = FIRMWARE_CUT10;
100 priv->sdd_path = SDD_FILE_10;
102 case CW1200_HW_REV_CUT11:
103 fw_path = FIRMWARE_CUT11;
105 priv->sdd_path = SDD_FILE_11;
107 case CW1200_HW_REV_CUT20:
108 fw_path = FIRMWARE_CUT20;
110 priv->sdd_path = SDD_FILE_20;
112 case CW1200_HW_REV_CUT22:
113 fw_path = FIRMWARE_CUT22;
115 priv->sdd_path = SDD_FILE_22;
118 fw_path = FIRMWARE_CW1X60;
120 priv->sdd_path = SDD_FILE_CW1X60;
123 pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
127 /* Initialize common registers */
128 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
129 APB_WRITE(DOWNLOAD_PUT_REG, 0);
130 APB_WRITE(DOWNLOAD_GET_REG, 0);
131 APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
132 APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
134 /* Write the NOP Instruction */
135 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
136 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
138 /* Release CPU from RESET */
139 REG_READ(ST90TDS_CONFIG_REG_ID, val32);
140 val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
141 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
144 val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
145 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
147 /* Load a firmware file */
148 ret = request_firmware(&firmware, fw_path, priv->pdev);
150 pr_err("Can't load firmware file %s.\n", fw_path);
154 buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
156 pr_err("Can't allocate firmware load buffer.\n");
158 goto firmware_release;
161 /* Check if the bootloader is ready */
162 for (i = 0; i < 100; i += 1 + i / 2) {
163 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
164 if (val32 == DOWNLOAD_I_AM_HERE)
167 } /* End of for loop */
169 if (val32 != DOWNLOAD_I_AM_HERE) {
170 pr_err("Bootloader is not ready.\n");
175 /* Calculcate number of download blocks */
176 num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
178 /* Updating the length in Download Ctrl Area */
179 val32 = firmware->size; /* Explicit cast from size_t to u32 */
180 APB_WRITE2(DOWNLOAD_IMAGE_SIZE_REG, val32);
182 /* Firmware downloading loop */
183 for (block = 0; block < num_blocks; block++) {
187 /* check the download status */
188 APB_READ(DOWNLOAD_STATUS_REG, val32);
189 if (val32 != DOWNLOAD_PENDING) {
190 pr_err("Bootloader reported error %d.\n", val32);
195 /* loop until put - get <= 24K */
196 for (i = 0; i < 100; i++) {
197 APB_READ(DOWNLOAD_GET_REG, get);
199 (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
204 if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
205 pr_err("Timeout waiting for FIFO.\n");
210 /* calculate the block size */
211 tx_size = block_size = min_t(size_t, firmware->size - put,
212 DOWNLOAD_BLOCK_SIZE);
214 memcpy(buf, &firmware->data[put], block_size);
215 if (block_size < DOWNLOAD_BLOCK_SIZE) {
216 memset(&buf[block_size], 0,
217 DOWNLOAD_BLOCK_SIZE - block_size);
218 tx_size = DOWNLOAD_BLOCK_SIZE;
221 /* send the block to sram */
222 ret = cw1200_apb_write(priv,
223 CW1200_APB(DOWNLOAD_FIFO_OFFSET +
224 (put & (DOWNLOAD_FIFO_SIZE - 1))),
227 pr_err("Can't write firmware block @ %d!\n",
228 put & (DOWNLOAD_FIFO_SIZE - 1));
232 /* update the put register */
234 APB_WRITE2(DOWNLOAD_PUT_REG, put);
235 } /* End of firmware download loop */
237 /* Wait for the download completion */
238 for (i = 0; i < 300; i += 1 + i / 2) {
239 APB_READ(DOWNLOAD_STATUS_REG, val32);
240 if (val32 != DOWNLOAD_PENDING)
244 if (val32 != DOWNLOAD_SUCCESS) {
245 pr_err("Wait for download completion failed: 0x%.8X\n", val32);
249 pr_info("Firmware download completed.\n");
256 release_firmware(firmware);
268 static int config_reg_read(struct cw1200_common *priv, u32 *val)
270 switch (priv->hw_type) {
271 case HIF_9000_SILICON_VERSATILE: {
273 int ret = cw1200_reg_read_16(priv,
274 ST90TDS_CONFIG_REG_ID,
281 case HIF_8601_VERSATILE:
282 case HIF_8601_SILICON:
284 cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
290 static int config_reg_write(struct cw1200_common *priv, u32 val)
292 switch (priv->hw_type) {
293 case HIF_9000_SILICON_VERSATILE:
294 return cw1200_reg_write_16(priv,
295 ST90TDS_CONFIG_REG_ID,
297 case HIF_8601_VERSATILE:
298 case HIF_8601_SILICON:
300 return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
305 int cw1200_load_firmware(struct cw1200_common *priv)
311 int major_revision = -1;
313 /* Read CONFIG Register */
314 ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
316 pr_err("Can't read config register.\n");
320 if (val32 == 0 || val32 == 0xffffffff) {
321 pr_err("Bad config register value (0x%08x)\n", val32);
326 priv->hw_type = cw1200_get_hw_type(val32, &major_revision);
327 if (priv->hw_type < 0) {
328 pr_err("Can't deduce hardware type.\n");
333 /* Set DPLL Reg value, and read back to confirm writes work */
334 ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
335 cw1200_dpll_from_clk(priv->hw_refclk));
337 pr_err("Can't write DPLL register.\n");
343 ret = cw1200_reg_read_32(priv,
344 ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
346 pr_err("Can't read DPLL register.\n");
350 if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
351 pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
352 cw1200_dpll_from_clk(priv->hw_refclk), val32);
357 /* Set wakeup bit in device */
358 ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
360 pr_err("set_wakeup: can't read control register.\n");
364 ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
365 val16 | ST90TDS_CONT_WUP_BIT);
367 pr_err("set_wakeup: can't write control register.\n");
371 /* Wait for wakeup */
372 for (i = 0; i < 300; i += (1 + i / 2)) {
373 ret = cw1200_reg_read_16(priv,
374 ST90TDS_CONTROL_REG_ID, &val16);
376 pr_err("wait_for_wakeup: can't read control register.\n");
380 if (val16 & ST90TDS_CONT_RDY_BIT)
386 if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
387 pr_err("wait_for_wakeup: device is not responding.\n");
392 switch (major_revision) {
394 /* CW1200 Hardware detection logic : Check for CUT1.1 */
395 ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
397 pr_err("HW detection: can't read CUT ID.\n");
402 case CW1200_CUT_11_ID_STR:
403 pr_info("CW1x00 Cut 1.1 silicon detected.\n");
404 priv->hw_revision = CW1200_HW_REV_CUT11;
407 pr_info("CW1x00 Cut 1.0 silicon detected.\n");
408 priv->hw_revision = CW1200_HW_REV_CUT10;
412 /* According to ST-E, CUT<2.0 has busted BA TID0-3.
413 Just disable it entirely...
415 priv->ba_rx_tid_mask = 0;
416 priv->ba_tx_tid_mask = 0;
420 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
422 pr_err("(1) HW detection: can't read CUT ID\n");
425 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
427 pr_err("(2) HW detection: can't read CUT ID.\n");
431 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
433 pr_err("(3) HW detection: can't read CUT ID.\n");
437 if (ar1 == CW1200_CUT_22_ID_STR1 &&
438 ar2 == CW1200_CUT_22_ID_STR2 &&
439 ar3 == CW1200_CUT_22_ID_STR3) {
440 pr_info("CW1x00 Cut 2.2 silicon detected.\n");
441 priv->hw_revision = CW1200_HW_REV_CUT22;
443 pr_info("CW1x00 Cut 2.0 silicon detected.\n");
444 priv->hw_revision = CW1200_HW_REV_CUT20;
449 pr_info("CW1x60 silicon detected.\n");
450 priv->hw_revision = CW1X60_HW_REV;
453 pr_err("Unsupported silicon major revision %d.\n",
459 /* Checking for access mode */
460 ret = config_reg_read(priv, &val32);
462 pr_err("Can't read config register.\n");
466 if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
467 pr_err("Device is already in QUEUE mode!\n");
472 switch (priv->hw_type) {
473 case HIF_8601_SILICON:
474 if (priv->hw_revision == CW1X60_HW_REV) {
475 pr_err("Can't handle CW1160/1260 firmware load yet.\n");
479 ret = cw1200_load_firmware_cw1200(priv);
482 pr_err("Can't perform firmware load for hw type %d.\n",
488 pr_err("Firmware load error.\n");
492 /* Enable interrupt signalling */
493 priv->hwbus_ops->lock(priv->hwbus_priv);
494 ret = __cw1200_irq_enable(priv, 1);
495 priv->hwbus_ops->unlock(priv->hwbus_priv);
499 /* Configure device for MESSSAGE MODE */
500 ret = config_reg_read(priv, &val32);
502 pr_err("Can't read config register.\n");
505 ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
507 pr_err("Can't write config register.\n");
511 /* Unless we read the CONFIG Register we are
512 * not able to get an interrupt
515 config_reg_read(priv, &val32);
521 /* Disable interrupt signalling */
522 priv->hwbus_ops->lock(priv->hwbus_priv);
523 ret = __cw1200_irq_enable(priv, 0);
524 priv->hwbus_ops->unlock(priv->hwbus_priv);