drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/slab.h>
  31 #include <linux/sched.h>
  32
  33 /* TODO: remove include to iwl-dev.h */
  34 #include "iwl-dev.h"
  35 #include "iwl-debug.h"
  36 #include "iwl-csr.h"
  37 #include "iwl-prph.h"
  38 #include "iwl-io.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-helpers.h"
  41 #include "iwl-trans-pcie-int.h"
  42
  43 #define IWL_TX_CRC_SIZE 4
  44 #define IWL_TX_DELIMITER_SIZE 4
  45
  46 /**
  47  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  48  */
  49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  50                                            struct iwl_tx_queue *txq,
  51                                            u16 byte_cnt)
  52 {
  53         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
  54         struct iwl_trans_pcie *trans_pcie =
  55                 IWL_TRANS_GET_PCIE_TRANS(trans);
  56         int write_ptr = txq->q.write_ptr;
  57         int txq_id = txq->q.id;
  58         u8 sec_ctl = 0;
  59         u8 sta_id = 0;
  60         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  61         __le16 bc_ent;
  62         struct iwl_tx_cmd *tx_cmd =
  63                 (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload;
  64
  65         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
  66
  67         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  68
  69         sta_id = tx_cmd->sta_id;
  70         sec_ctl = tx_cmd->sec_ctl;
  71
  72         switch (sec_ctl & TX_CMD_SEC_MSK) {
  73         case TX_CMD_SEC_CCM:
  74                 len += CCMP_MIC_LEN;
  75                 break;
  76         case TX_CMD_SEC_TKIP:
  77                 len += TKIP_ICV_LEN;
  78                 break;
  79         case TX_CMD_SEC_WEP:
  80                 len += WEP_IV_LEN + WEP_ICV_LEN;
  81                 break;
  82         }
  83
  84         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
  85
  86         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  87
  88         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  89                 scd_bc_tbl[txq_id].
  90                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  91 }
  92
  93 /**
  94  * iwl_txq_update_write_ptr - Send new write index to hardware
  95  */
  96 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
  97 {
  98         u32 reg = 0;
  99         int txq_id = txq->q.id;
 100
 101         if (txq->need_update == 0)
 102                 return;
 103
 104         if (hw_params(trans).shadow_reg_enable) {
 105                 /* shadow register enabled */
 106                 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 107                             txq->q.write_ptr | (txq_id << 8));
 108         } else {
 109                 /* if we're trying to save power */
 110                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 111                         /* wake up nic if it's powered down ...
 112                          * uCode will wake up, and interrupt us again, so next
 113                          * time we'll skip this part. */
 114                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 115
 116                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 117                                 IWL_DEBUG_INFO(trans,
 118                                         "Tx queue %d requesting wakeup,"
 119                                         " GP1 = 0x%x\n", txq_id, reg);
 120                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 121                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 122                                 return;
 123                         }
 124
 125                         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 126                                      txq->q.write_ptr | (txq_id << 8));
 127
 128                 /*
 129                  * else not in power-save mode,
 130                  * uCode will never sleep when we're
 131                  * trying to tx (during RFKILL, we're not trying to tx).
 132                  */
 133                 } else
 134                         iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 135                                     txq->q.write_ptr | (txq_id << 8));
 136         }
 137         txq->need_update = 0;
 138 }
 139
 140 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 141 {
 142         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 143
 144         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 145         if (sizeof(dma_addr_t) > sizeof(u32))
 146                 addr |=
 147                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 148
 149         return addr;
 150 }
 151
 152 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 153 {
 154         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 155
 156         return le16_to_cpu(tb->hi_n_len) >> 4;
 157 }
 158
 159 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 160                                   dma_addr_t addr, u16 len)
 161 {
 162         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 163         u16 hi_n_len = len << 4;
 164
 165         put_unaligned_le32(addr, &tb->lo);
 166         if (sizeof(dma_addr_t) > sizeof(u32))
 167                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 168
 169         tb->hi_n_len = cpu_to_le16(hi_n_len);
 170
 171         tfd->num_tbs = idx + 1;
 172 }
 173
 174 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 175 {
 176         return tfd->num_tbs & 0x1f;
 177 }
 178
 179 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
 180                      struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
 181 {
 182         int i;
 183         int num_tbs;
 184
 185         /* Sanity check on number of chunks */
 186         num_tbs = iwl_tfd_get_num_tbs(tfd);
 187
 188         if (num_tbs >= IWL_NUM_OF_TBS) {
 189                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 190                 /* @todo issue fatal error, it is quite serious situation */
 191                 return;
 192         }
 193
 194         /* Unmap tx_cmd */
 195         if (num_tbs)
 196                 dma_unmap_single(bus(trans)->dev,
 197                                 dma_unmap_addr(meta, mapping),
 198                                 dma_unmap_len(meta, len),
 199                                 DMA_BIDIRECTIONAL);
 200
 201         /* Unmap chunks, if any. */
 202         for (i = 1; i < num_tbs; i++)
 203                 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
 204                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
 205 }
 206
 207 /**
 208  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 209  * @trans - transport private data
 210  * @txq - tx queue
 211  * @index - the index of the TFD to be freed
 212  *@dma_dir - the direction of the DMA mapping
 213  *
 214  * Does NOT advance any TFD circular buffer read/write indexes
 215  * Does NOT free the TFD itself (which is within circular buffer)
 216  */
 217 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 218         int index, enum dma_data_direction dma_dir)
 219 {
 220         struct iwl_tfd *tfd_tmp = txq->tfds;
 221
 222         iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir);
 223
 224         /* free SKB */
 225         if (txq->skbs) {
 226                 struct sk_buff *skb;
 227
 228                 skb = txq->skbs[index];
 229
 230                 /* Can be called from irqs-disabled context
 231                  * If skb is not NULL, it means that the whole queue is being
 232                  * freed and that the queue is not empty - free the skb
 233                  */
 234                 if (skb) {
 235                         iwl_free_skb(priv(trans), skb);
 236                         txq->skbs[index] = NULL;
 237                 }
 238         }
 239 }
 240
 241 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 242                                  struct iwl_tx_queue *txq,
 243                                  dma_addr_t addr, u16 len,
 244                                  u8 reset)
 245 {
 246         struct iwl_queue *q;
 247         struct iwl_tfd *tfd, *tfd_tmp;
 248         u32 num_tbs;
 249
 250         q = &txq->q;
 251         tfd_tmp = txq->tfds;
 252         tfd = &tfd_tmp[q->write_ptr];
 253
 254         if (reset)
 255                 memset(tfd, 0, sizeof(*tfd));
 256
 257         num_tbs = iwl_tfd_get_num_tbs(tfd);
 258
 259         /* Each TFD can point to a maximum 20 Tx buffers */
 260         if (num_tbs >= IWL_NUM_OF_TBS) {
 261                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 262                           IWL_NUM_OF_TBS);
 263                 return -EINVAL;
 264         }
 265
 266         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 267                 return -EINVAL;
 268
 269         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 270                 IWL_ERR(trans, "Unaligned address = %llx\n",
 271                           (unsigned long long)addr);
 272
 273         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 274
 275         return 0;
 276 }
 277
 278 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 279  * DMA services
 280  *
 281  * Theory of operation
 282  *
 283  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 284  * of buffer descriptors, each of which points to one or more data buffers for
 285  * the device to read from or fill.  Driver and device exchange status of each
 286  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 287  * entries in each circular buffer, to protect against confusing empty and full
 288  * queue states.
 289  *
 290  * The device reads or writes the data in the queues via the device's several
 291  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 292  *
 293  * For Tx queue, there are low mark and high mark limits. If, after queuing
 294  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 295  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 296  * Tx queue resumed.
 297  *
 298  ***************************************************/
 299
 300 int iwl_queue_space(const struct iwl_queue *q)
 301 {
 302         int s = q->read_ptr - q->write_ptr;
 303
 304         if (q->read_ptr > q->write_ptr)
 305                 s -= q->n_bd;
 306
 307         if (s <= 0)
 308                 s += q->n_window;
 309         /* keep some reserve to not confuse empty and full situations */
 310         s -= 2;
 311         if (s < 0)
 312                 s = 0;
 313         return s;
 314 }
 315
 316 /**
 317  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 318  */
 319 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
 320 {
 321         q->n_bd = count;
 322         q->n_window = slots_num;
 323         q->id = id;
 324
 325         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
 326          * and iwl_queue_dec_wrap are broken. */
 327         if (WARN_ON(!is_power_of_2(count)))
 328                 return -EINVAL;
 329
 330         /* slots_num must be power-of-two size, otherwise
 331          * get_cmd_index is broken. */
 332         if (WARN_ON(!is_power_of_2(slots_num)))
 333                 return -EINVAL;
 334
 335         q->low_mark = q->n_window / 4;
 336         if (q->low_mark < 4)
 337                 q->low_mark = 4;
 338
 339         q->high_mark = q->n_window / 8;
 340         if (q->high_mark < 2)
 341                 q->high_mark = 2;
 342
 343         q->write_ptr = q->read_ptr = 0;
 344
 345         return 0;
 346 }
 347
 348 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 349                                           struct iwl_tx_queue *txq)
 350 {
 351         struct iwl_trans_pcie *trans_pcie =
 352                 IWL_TRANS_GET_PCIE_TRANS(trans);
 353         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 354         int txq_id = txq->q.id;
 355         int read_ptr = txq->q.read_ptr;
 356         u8 sta_id = 0;
 357         __le16 bc_ent;
 358         struct iwl_tx_cmd *tx_cmd =
 359                 (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload;
 360
 361         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 362
 363         if (txq_id != trans->shrd->cmd_queue)
 364                 sta_id = tx_cmd->sta_id;
 365
 366         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 367         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 368
 369         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 370                 scd_bc_tbl[txq_id].
 371                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 372 }
 373
 374 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
 375                                         u16 txq_id)
 376 {
 377         u32 tbl_dw_addr;
 378         u32 tbl_dw;
 379         u16 scd_q2ratid;
 380
 381         struct iwl_trans_pcie *trans_pcie =
 382                 IWL_TRANS_GET_PCIE_TRANS(trans);
 383
 384         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 385
 386         tbl_dw_addr = trans_pcie->scd_base_addr +
 387                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 388
 389         tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
 390
 391         if (txq_id & 0x1)
 392                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 393         else
 394                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 395
 396         iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
 397
 398         return 0;
 399 }
 400
 401 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 402 {
 403         /* Simply stop the queue, but don't change any configuration;
 404          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 405         iwl_write_prph(bus(trans),
 406                 SCD_QUEUE_STATUS_BITS(txq_id),
 407                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 408                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 409 }
 410
 411 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
 412                                 int txq_id, u32 index)
 413 {
 414         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 415                         (index & 0xff) | (txq_id << 8));
 416         iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
 417 }
 418
 419 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
 420                                         struct iwl_tx_queue *txq,
 421                                         int tx_fifo_id, int scd_retry)
 422 {
 423         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 424         int txq_id = txq->q.id;
 425         int active =
 426                 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
 427
 428         iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
 429                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 430                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
 431                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
 432                         SCD_QUEUE_STTS_REG_MSK);
 433
 434         txq->sched_retry = scd_retry;
 435
 436         IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
 437                        active ? "Activate" : "Deactivate",
 438                        scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
 439 }
 440
 441 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
 442                                     u8 ctx, u16 tid)
 443 {
 444         const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
 445         if (likely(tid < ARRAY_SIZE(tid_to_ac)))
 446                 return ac_to_fifo[tid_to_ac[tid]];
 447
 448         /* no support for TIDs 8-15 yet */
 449         return -EINVAL;
 450 }
 451
 452 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
 453                                  enum iwl_rxon_context_id ctx, int sta_id,
 454                                  int tid, int frame_limit)
 455 {
 456         int tx_fifo, txq_id, ssn_idx;
 457         u16 ra_tid;
 458         unsigned long flags;
 459         struct iwl_tid_data *tid_data;
 460
 461         struct iwl_trans_pcie *trans_pcie =
 462                 IWL_TRANS_GET_PCIE_TRANS(trans);
 463
 464         if (WARN_ON(sta_id == IWL_INVALID_STATION))
 465                 return;
 466         if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
 467                 return;
 468
 469         tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
 470         if (WARN_ON(tx_fifo < 0)) {
 471                 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
 472                 return;
 473         }
 474
 475         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 476         tid_data = &trans->shrd->tid_data[sta_id][tid];
 477         ssn_idx = SEQ_TO_SN(tid_data->seq_number);
 478         txq_id = tid_data->agg.txq_id;
 479         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 480
 481         ra_tid = BUILD_RAxTID(sta_id, tid);
 482
 483         spin_lock_irqsave(&trans->shrd->lock, flags);
 484
 485         /* Stop this Tx queue before configuring it */
 486         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 487
 488         /* Map receiver-address / traffic-ID to this queue */
 489         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 490
 491         /* Set this queue as a chain-building queue */
 492         iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
 493
 494         /* enable aggregations for the queue */
 495         iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
 496
 497         /* Place first TFD at index corresponding to start sequence number.
 498          * Assumes that ssn_idx is valid (!= 0xFFF) */
 499         trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 500         trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 501         iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
 502
 503         /* Set up Tx window size and frame limit for this queue */
 504         iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 505                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 506                         sizeof(u32),
 507                         ((frame_limit <<
 508                         SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 509                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 510                         ((frame_limit <<
 511                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 512                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 513
 514         iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
 515
 516         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 517         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 518                                         tx_fifo, 1);
 519
 520         trans_pcie->txq[txq_id].sta_id = sta_id;
 521         trans_pcie->txq[txq_id].tid = tid;
 522
 523         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 524 }
 525
 526 /*
 527  * Find first available (lowest unused) Tx Queue, mark it "active".
 528  * Called only when finding queue for aggregation.
 529  * Should never return anything < 7, because they should already
 530  * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
 531  */
 532 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
 533 {
 534         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 535         int txq_id;
 536
 537         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 538                 if (!test_and_set_bit(txq_id,
 539                                         &trans_pcie->txq_ctx_active_msk))
 540                         return txq_id;
 541         return -1;
 542 }
 543
 544 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
 545                                 enum iwl_rxon_context_id ctx, int sta_id,
 546                                 int tid, u16 *ssn)
 547 {
 548         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 549         struct iwl_tid_data *tid_data;
 550         unsigned long flags;
 551         int txq_id;
 552
 553         txq_id = iwlagn_txq_ctx_activate_free(trans);
 554         if (txq_id == -1) {
 555                 IWL_ERR(trans, "No free aggregation queue available\n");
 556                 return -ENXIO;
 557         }
 558
 559         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 560         tid_data = &trans->shrd->tid_data[sta_id][tid];
 561         *ssn = SEQ_TO_SN(tid_data->seq_number);
 562         tid_data->agg.txq_id = txq_id;
 563         iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
 564
 565         tid_data = &trans->shrd->tid_data[sta_id][tid];
 566         if (tid_data->tfds_in_queue == 0) {
 567                 IWL_DEBUG_HT(trans, "HW queue is empty\n");
 568                 tid_data->agg.state = IWL_AGG_ON;
 569                 iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
 570         } else {
 571                 IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW"
 572                              "queue\n", tid_data->tfds_in_queue);
 573                 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
 574         }
 575         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 576
 577         return 0;
 578 }
 579
 580 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
 581 {
 582         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 583         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 584
 585         iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id));
 586
 587         trans_pcie->txq[txq_id].q.read_ptr = 0;
 588         trans_pcie->txq[txq_id].q.write_ptr = 0;
 589         /* supposes that ssn_idx is valid (!= 0xFFF) */
 590         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
 591
 592         iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
 593         iwl_txq_ctx_deactivate(trans_pcie, txq_id);
 594         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
 595 }
 596
 597 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
 598                                   enum iwl_rxon_context_id ctx, int sta_id,
 599                                   int tid)
 600 {
 601         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 602         unsigned long flags;
 603         int read_ptr, write_ptr;
 604         struct iwl_tid_data *tid_data;
 605         int txq_id;
 606
 607         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 608
 609         tid_data = &trans->shrd->tid_data[sta_id][tid];
 610         txq_id = tid_data->agg.txq_id;
 611
 612         if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
 613             (IWLAGN_FIRST_AMPDU_QUEUE +
 614                 hw_params(trans).num_ampdu_queues <= txq_id)) {
 615                 IWL_ERR(trans,
 616                         "queue number out of range: %d, must be %d to %d\n",
 617                         txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
 618                         IWLAGN_FIRST_AMPDU_QUEUE +
 619                         hw_params(trans).num_ampdu_queues - 1);
 620                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 621                 return -EINVAL;
 622         }
 623
 624         switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
 625         case IWL_EMPTYING_HW_QUEUE_ADDBA:
 626                 /*
 627                 * This can happen if the peer stops aggregation
 628                 * again before we've had a chance to drain the
 629                 * queue we selected previously, i.e. before the
 630                 * session was really started completely.
 631                 */
 632                 IWL_DEBUG_HT(trans, "AGG stop before setup done\n");
 633                 goto turn_off;
 634         case IWL_AGG_ON:
 635                 break;
 636         default:
 637                 IWL_WARN(trans, "Stopping AGG while state not ON"
 638                                 "or starting\n");
 639                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 640                 return 0;
 641         }
 642
 643         write_ptr = trans_pcie->txq[txq_id].q.write_ptr;
 644         read_ptr = trans_pcie->txq[txq_id].q.read_ptr;
 645
 646         /* The queue is not empty */
 647         if (write_ptr != read_ptr) {
 648                 IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n");
 649                 trans->shrd->tid_data[sta_id][tid].agg.state =
 650                         IWL_EMPTYING_HW_QUEUE_DELBA;
 651                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 652                 return 0;
 653         }
 654
 655         IWL_DEBUG_HT(trans, "HW queue is empty\n");
 656 turn_off:
 657         trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF;
 658
 659         /* do not restore/save irqs */
 660         spin_unlock(&trans->shrd->sta_lock);
 661         spin_lock(&trans->shrd->lock);
 662
 663         iwl_trans_pcie_txq_agg_disable(trans, txq_id);
 664
 665         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 666
 667         iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
 668
 669         return 0;
 670 }
 671
 672 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
 673
 674 /**
 675  * iwl_enqueue_hcmd - enqueue a uCode command
 676  * @priv: device private data point
 677  * @cmd: a point to the ucode command structure
 678  *
 679  * The function returns < 0 values to indicate the operation is
 680  * failed. On success, it turns the index (> 0) of command in the
 681  * command queue.
 682  */
 683 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 684 {
 685         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 686         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 687         struct iwl_queue *q = &txq->q;
 688         struct iwl_device_cmd *out_cmd;
 689         struct iwl_cmd_meta *out_meta;
 690         dma_addr_t phys_addr;
 691         unsigned long flags;
 692         u32 idx;
 693         u16 copy_size, cmd_size;
 694         bool is_ct_kill = false;
 695         bool had_nocopy = false;
 696         int i;
 697         u8 *cmd_dest;
 698 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 699         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
 700         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
 701         int trace_idx;
 702 #endif
 703
 704         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
 705                 IWL_WARN(trans, "fw recovery, no hcmd send\n");
 706                 return -EIO;
 707         }
 708
 709         if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
 710             !(cmd->flags & CMD_ON_DEMAND)) {
 711                 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
 712                 return -EIO;
 713         }
 714
 715         copy_size = sizeof(out_cmd->hdr);
 716         cmd_size = sizeof(out_cmd->hdr);
 717
 718         /* need one for the header if the first is NOCOPY */
 719         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
 720
 721         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 722                 if (!cmd->len[i])
 723                         continue;
 724                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
 725                         had_nocopy = true;
 726                 } else {
 727                         /* NOCOPY must not be followed by normal! */
 728                         if (WARN_ON(had_nocopy))
 729                                 return -EINVAL;
 730                         copy_size += cmd->len[i];
 731                 }
 732                 cmd_size += cmd->len[i];
 733         }
 734
 735         /*
 736          * If any of the command structures end up being larger than
 737          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
 738          * allocated into separate TFDs, then we will need to
 739          * increase the size of the buffers.
 740          */
 741         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
 742                 return -EINVAL;
 743
 744         if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
 745                 IWL_WARN(trans, "Not sending command - %s KILL\n",
 746                          iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
 747                 return -EIO;
 748         }
 749
 750         spin_lock_irqsave(&trans->hcmd_lock, flags);
 751
 752         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
 753                 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 754
 755                 IWL_ERR(trans, "No space in command queue\n");
 756                 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
 757                 if (!is_ct_kill) {
 758                         IWL_ERR(trans, "Restarting adapter queue is full\n");
 759                         iwlagn_fw_error(priv(trans), false);
 760                 }
 761                 return -ENOSPC;
 762         }
 763
 764         idx = get_cmd_index(q, q->write_ptr);
 765         out_cmd = txq->cmd[idx];
 766         out_meta = &txq->meta[idx];
 767
 768         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
 769         if (cmd->flags & CMD_WANT_SKB)
 770                 out_meta->source = cmd;
 771
 772         /* set up the header */
 773
 774         out_cmd->hdr.cmd = cmd->id;
 775         out_cmd->hdr.flags = 0;
 776         out_cmd->hdr.sequence =
 777                 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
 778                                          INDEX_TO_SEQ(q->write_ptr));
 779
 780         /* and copy the data that needs to be copied */
 781
 782         cmd_dest = out_cmd->payload;
 783         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 784                 if (!cmd->len[i])
 785                         continue;
 786                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
 787                         break;
 788                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
 789                 cmd_dest += cmd->len[i];
 790         }
 791
 792         IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
 793                         "%d bytes at %d[%d]:%d\n",
 794                         get_cmd_string(out_cmd->hdr.cmd),
 795                         out_cmd->hdr.cmd,
 796                         le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
 797                         q->write_ptr, idx, trans->shrd->cmd_queue);
 798
 799         phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
 800                                 DMA_BIDIRECTIONAL);
 801         if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
 802                 idx = -ENOMEM;
 803                 goto out;
 804         }
 805
 806         dma_unmap_addr_set(out_meta, mapping, phys_addr);
 807         dma_unmap_len_set(out_meta, len, copy_size);
 808
 809         iwlagn_txq_attach_buf_to_tfd(trans, txq,
 810                                         phys_addr, copy_size, 1);
 811 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 812         trace_bufs[0] = &out_cmd->hdr;
 813         trace_lens[0] = copy_size;
 814         trace_idx = 1;
 815 #endif
 816
 817         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 818                 if (!cmd->len[i])
 819                         continue;
 820                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
 821                         continue;
 822                 phys_addr = dma_map_single(bus(trans)->dev,
 823                                            (void *)cmd->data[i],
 824                                            cmd->len[i], DMA_BIDIRECTIONAL);
 825                 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
 826                         iwlagn_unmap_tfd(trans, out_meta,
 827                                          &txq->tfds[q->write_ptr],
 828                                          DMA_BIDIRECTIONAL);
 829                         idx = -ENOMEM;
 830                         goto out;
 831                 }
 832
 833                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
 834                                              cmd->len[i], 0);
 835 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 836                 trace_bufs[trace_idx] = cmd->data[i];
 837                 trace_lens[trace_idx] = cmd->len[i];
 838                 trace_idx++;
 839 #endif
 840         }
 841
 842         out_meta->flags = cmd->flags;
 843
 844         txq->need_update = 1;
 845
 846         /* check that tracing gets all possible blocks */
 847         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
 848 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 849         trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
 850                                trace_bufs[0], trace_lens[0],
 851                                trace_bufs[1], trace_lens[1],
 852                                trace_bufs[2], trace_lens[2]);
 853 #endif
 854
 855         /* Increment and update queue's write index */
 856         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
 857         iwl_txq_update_write_ptr(trans, txq);
 858
 859  out:
 860         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 861         return idx;
 862 }
 863
 864 /**
 865  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 866  *
 867  * When FW advances 'R' index, all entries between old and new 'R' index
 868  * need to be reclaimed. As result, some free space forms.  If there is
 869  * enough free space (> low mark), wake the stack that feeds us.
 870  */
 871 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
 872                                    int idx)
 873 {
 874         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 875         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 876         struct iwl_queue *q = &txq->q;
 877         int nfreed = 0;
 878
 879         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
 880                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
 881                           "index %d is out of range [0-%d] %d %d.\n", __func__,
 882                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
 883                 return;
 884         }
 885
 886         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
 887              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 888
 889                 if (nfreed++ > 0) {
 890                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
 891                                         q->write_ptr, q->read_ptr);
 892                         iwlagn_fw_error(priv(trans), false);
 893                 }
 894
 895         }
 896 }
 897
 898 /**
 899  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 900  * @rxb: Rx buffer to reclaim
 901  * @handler_status: return value of the handler of the command
 902  *      (put in setup_rx_handlers)
 903  *
 904  * If an Rx buffer has an async callback associated with it the callback
 905  * will be executed.  The attached skb (if present) will only be freed
 906  * if the callback returns 1
 907  */
 908 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb,
 909                          int handler_status)
 910 {
 911         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 912         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 913         int txq_id = SEQ_TO_QUEUE(sequence);
 914         int index = SEQ_TO_INDEX(sequence);
 915         int cmd_index;
 916         struct iwl_device_cmd *cmd;
 917         struct iwl_cmd_meta *meta;
 918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 919         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 920         unsigned long flags;
 921
 922         /* If a Tx command is being handled and it isn't in the actual
 923          * command queue then there a command routing bug has been introduced
 924          * in the queue management code. */
 925         if (WARN(txq_id != trans->shrd->cmd_queue,
 926                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
 927                   txq_id, trans->shrd->cmd_queue, sequence,
 928                   trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
 929                   trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
 930                 iwl_print_hex_error(trans, pkt, 32);
 931                 return;
 932         }
 933
 934         cmd_index = get_cmd_index(&txq->q, index);
 935         cmd = txq->cmd[cmd_index];
 936         meta = &txq->meta[cmd_index];
 937
 938         txq->time_stamp = jiffies;
 939
 940         iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
 941                          DMA_BIDIRECTIONAL);
 942
 943         /* Input error checking is done when commands are added to queue. */
 944         if (meta->flags & CMD_WANT_SKB) {
 945                 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
 946                 meta->source->handler_status = handler_status;
 947                 rxb->page = NULL;
 948         }
 949
 950         spin_lock_irqsave(&trans->hcmd_lock, flags);
 951
 952         iwl_hcmd_queue_reclaim(trans, txq_id, index);
 953
 954         if (!(meta->flags & CMD_ASYNC)) {
 955                 if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
 956                         IWL_WARN(trans,
 957                                  "HCMD_ACTIVE already clear for command %s\n",
 958                                  get_cmd_string(cmd->hdr.cmd));
 959                 }
 960                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 961                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
 962                                get_cmd_string(cmd->hdr.cmd));
 963                 wake_up(&trans->shrd->wait_command_queue);
 964         }
 965
 966         meta->flags = 0;
 967
 968         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 969 }
 970
 971 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
 972
 973 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 974 {
 975         int ret;
 976
 977         /* An asynchronous command can not expect an SKB to be set. */
 978         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
 979                 return -EINVAL;
 980
 981
 982         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 983                 return -EBUSY;
 984
 985         ret = iwl_enqueue_hcmd(trans, cmd);
 986         if (ret < 0) {
 987                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
 988                           get_cmd_string(cmd->id), ret);
 989                 return ret;
 990         }
 991         return 0;
 992 }
 993
 994 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 995 {
 996         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 997         int cmd_idx;
 998         int ret;
 999
1000         lockdep_assert_held(&trans->shrd->mutex);
1001
1002         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1003                         get_cmd_string(cmd->id));
1004
1005         set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1006         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1007                         get_cmd_string(cmd->id));
1008
1009         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
1010         if (cmd_idx < 0) {
1011                 ret = cmd_idx;
1012                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1013                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1014                           get_cmd_string(cmd->id), ret);
1015                 return ret;
1016         }
1017
1018         ret = wait_event_timeout(trans->shrd->wait_command_queue,
1019                         !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
1020                         HOST_COMPLETE_TIMEOUT);
1021         if (!ret) {
1022                 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
1023                         struct iwl_priv *priv = priv(trans);
1024                         struct iwl_tx_queue *txq =
1025                                 &trans_pcie->txq[priv->shrd->cmd_queue];
1026                         struct iwl_queue *q = &txq->q;
1027
1028                         IWL_ERR(trans,
1029                                 "Error sending %s: time out after %dms.\n",
1030                                 get_cmd_string(cmd->id),
1031                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1032
1033                         IWL_ERR(trans,
1034                                 "Current CMD queue read_ptr %d write_ptr %d\n",
1035                                 q->read_ptr, q->write_ptr);
1036
1037                         clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1038                         IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1039                                  "%s\n", get_cmd_string(cmd->id));
1040                         ret = -ETIMEDOUT;
1041                         goto cancel;
1042                 }
1043         }
1044
1045         if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
1046                 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
1047                                get_cmd_string(cmd->id));
1048                 ret = -ECANCELED;
1049                 goto fail;
1050         }
1051         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1052                 IWL_ERR(trans, "Command %s failed: FW Error\n",
1053                                get_cmd_string(cmd->id));
1054                 ret = -EIO;
1055                 goto fail;
1056         }
1057         if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1058                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1059                           get_cmd_string(cmd->id));
1060                 ret = -EIO;
1061                 goto cancel;
1062         }
1063
1064         return 0;
1065
1066 cancel:
1067         if (cmd->flags & CMD_WANT_SKB) {
1068                 /*
1069                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1070                  * TX cmd queue. Otherwise in case the cmd comes
1071                  * in later, it will possibly set an invalid
1072                  * address (cmd->meta.source).
1073                  */
1074                 trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1075                                                         ~CMD_WANT_SKB;
1076         }
1077 fail:
1078         if (cmd->reply_page) {
1079                 iwl_free_pages(trans->shrd, cmd->reply_page);
1080                 cmd->reply_page = 0;
1081         }
1082
1083         return ret;
1084 }
1085
1086 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1087 {
1088         if (cmd->flags & CMD_ASYNC)
1089                 return iwl_send_cmd_async(trans, cmd);
1090
1091         return iwl_send_cmd_sync(trans, cmd);
1092 }
1093
1094 /* Frees buffers until index _not_ inclusive */
1095 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1096                          struct sk_buff_head *skbs)
1097 {
1098         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1099         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1100         struct iwl_queue *q = &txq->q;
1101         int last_to_free;
1102         int freed = 0;
1103
1104         /* This function is not meant to release cmd queue*/
1105         if (WARN_ON(txq_id == trans->shrd->cmd_queue))
1106                 return 0;
1107
1108         /*Since we free until index _not_ inclusive, the one before index is
1109          * the last we will free. This one must be used */
1110         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1111
1112         if ((index >= q->n_bd) ||
1113            (iwl_queue_used(q, last_to_free) == 0)) {
1114                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1115                           "last_to_free %d is out of range [0-%d] %d %d.\n",
1116                           __func__, txq_id, last_to_free, q->n_bd,
1117                           q->write_ptr, q->read_ptr);
1118                 return 0;
1119         }
1120
1121         IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1122                            q->read_ptr, index);
1123
1124         if (WARN_ON(!skb_queue_empty(skbs)))
1125                 return 0;
1126
1127         for (;
1128              q->read_ptr != index;
1129              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1130
1131                 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1132                         continue;
1133
1134                 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1135
1136                 txq->skbs[txq->q.read_ptr] = NULL;
1137
1138                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1139
1140                 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE);
1141                 freed++;
1142         }
1143         return freed;
1144 }