1 /******************************************************************************
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #ifndef __iwl_trans_int_pcie_h__
31 #define __iwl_trans_int_pcie_h__
33 #include <linux/spinlock.h>
34 #include <linux/interrupt.h>
35 #include <linux/skbuff.h>
36 #include <linux/wait.h>
37 #include <linux/pci.h>
38 #include <linux/timer.h>
42 #include "iwl-trans.h"
43 #include "iwl-debug.h"
45 #include "iwl-op-mode.h"
48 * RX related structures and functions
50 #define RX_NUM_QUEUES 1
51 #define RX_POST_REQ_ALLOC 2
52 #define RX_CLAIM_REQ_ALLOC 8
53 #define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES)
54 #define RX_LOW_WATERMARK 8
58 /*This file includes the declaration that are internal to the
61 struct iwl_rx_mem_buffer {
64 struct list_head list;
68 * struct isr_statistics - interrupt statistics
71 struct isr_statistics {
86 * struct iwl_rxq - Rx queue
87 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
88 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
89 * @read: Shared index to newest available Rx buffer
90 * @write: Shared index to oldest written Rx packet
91 * @free_count: Number of pre-allocated buffers in rx_free
92 * @used_count: Number of RBDs handled to allocator to use for allocation
94 * @rx_free: list of RBDs with allocated RB ready for use
95 * @rx_used: list of RBDs with no RB attached
96 * @need_update: flag to indicate we need to update read/write index
97 * @rb_stts: driver's pointer to receive buffer status
98 * @rb_stts_dma: bus address of receive buffer status
100 * @pool: initial pool of iwl_rx_mem_buffer for the queue
101 * @queue: actual rx queue
103 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
113 struct list_head rx_free;
114 struct list_head rx_used;
116 struct iwl_rb_status *rb_stts;
117 dma_addr_t rb_stts_dma;
119 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE];
120 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
124 * struct iwl_rb_allocator - Rx allocator
125 * @pool: initial pool of allocator
126 * @req_pending: number of requests the allcator had not processed yet
127 * @req_ready: number of requests honored and ready for claiming
128 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
129 * the queue. This is a list of &struct iwl_rx_mem_buffer
130 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
131 * of &struct iwl_rx_mem_buffer
132 * @lock: protects the rbd_allocated and rbd_empty lists
133 * @alloc_wq: work queue for background calls
134 * @rx_alloc: work struct for background calls
136 struct iwl_rb_allocator {
137 struct iwl_rx_mem_buffer pool[RX_POOL_SIZE];
138 atomic_t req_pending;
140 struct list_head rbd_allocated;
141 struct list_head rbd_empty;
143 struct workqueue_struct *alloc_wq;
144 struct work_struct rx_alloc;
154 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
155 * @index -- current index
157 static inline int iwl_queue_inc_wrap(int index)
159 return ++index & (TFD_QUEUE_SIZE_MAX - 1);
163 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
164 * @index -- current index
166 static inline int iwl_queue_dec_wrap(int index)
168 return --index & (TFD_QUEUE_SIZE_MAX - 1);
171 struct iwl_cmd_meta {
172 /* only for SYNC commands, iff the reply skb is wanted */
173 struct iwl_host_cmd *source;
178 * Generic queue structure
180 * Contains common data for Rx and Tx queues.
182 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
183 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
184 * there might be HW changes in the future). For the normal TX
185 * queues, n_window, which is the size of the software queue data
186 * is also 256; however, for the command queue, n_window is only
187 * 32 since we don't need so many commands pending. Since the HW
188 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,
189 * the software buffers (in the variables @meta, @txb in struct
190 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
191 * the same struct) have 256.
192 * This means that we end up with the following:
193 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
194 * SW entries: | 0 | ... | 31 |
195 * where N is a number between 0 and 7. This means that the SW
196 * data is a window overlayed over the HW queue.
199 int write_ptr; /* 1-st empty entry (index) host_w*/
200 int read_ptr; /* last used entry (index) host_r*/
201 /* use for monitoring and recovering the stuck queue */
202 dma_addr_t dma_addr; /* physical addr for BD's */
203 int n_window; /* safe queue window */
205 int low_mark; /* low watermark, resume queue if free
206 * space more than this */
207 int high_mark; /* high watermark, stop queue if free
208 * space less than this */
211 #define TFD_TX_CMD_SLOTS 256
212 #define TFD_CMD_SLOTS 32
215 * The FH will write back to the first TB only, so we need
216 * to copy some data into the buffer regardless of whether
217 * it should be mapped or not. This indicates how big the
218 * first TB must be to include the scratch buffer. Since
219 * the scratch is 4 bytes at offset 12, it's 16 now. If we
220 * make it bigger then allocations will be bigger and copy
221 * slower, so that's probably not useful.
223 #define IWL_HCMD_SCRATCHBUF_SIZE 16
225 struct iwl_pcie_txq_entry {
226 struct iwl_device_cmd *cmd;
228 /* buffer to free after command completes */
229 const void *free_buf;
230 struct iwl_cmd_meta meta;
233 struct iwl_pcie_txq_scratch_buf {
234 struct iwl_cmd_header hdr;
240 * struct iwl_txq - Tx Queue for DMA
241 * @q: generic Rx/Tx queue descriptor
242 * @tfds: transmit frame descriptors (DMA memory)
243 * @scratchbufs: start of command headers, including scratch buffers, for
244 * the writeback -- this is DMA memory and an array holding one buffer
245 * for each command on the queue
246 * @scratchbufs_dma: DMA address for the scratchbufs start
247 * @entries: transmit entries (driver state)
249 * @stuck_timer: timer that fires if queue gets stuck
250 * @trans_pcie: pointer back to transport (for timer)
251 * @need_update: indicates need to update read/write index
252 * @active: stores if queue is active
253 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
254 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
255 * @frozen: tx stuck queue timer is frozen
256 * @frozen_expiry_remainder: remember how long until the timer fires
258 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
259 * descriptors) and required locking structures.
263 struct iwl_tfd *tfds;
264 struct iwl_pcie_txq_scratch_buf *scratchbufs;
265 dma_addr_t scratchbufs_dma;
266 struct iwl_pcie_txq_entry *entries;
268 unsigned long frozen_expiry_remainder;
269 struct timer_list stuck_timer;
270 struct iwl_trans_pcie *trans_pcie;
275 unsigned long wd_timeout;
278 static inline dma_addr_t
279 iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
281 return txq->scratchbufs_dma +
282 sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
286 * struct iwl_trans_pcie - PCIe transport specific data
287 * @rxq: all the RX queue data
288 * @rba: allocator for RX replenishing
289 * @drv - pointer to iwl_drv
290 * @trans: pointer to the generic transport area
291 * @scd_base_addr: scheduler sram base address in SRAM
292 * @scd_bc_tbls: pointer to the byte count table of the scheduler
293 * @kw: keep warm address
294 * @pci_dev: basic pci-network driver stuff
295 * @hw_base: pci hardware address support
296 * @ucode_write_complete: indicates that the ucode has been copied.
297 * @ucode_write_waitq: wait queue for uCode load
298 * @cmd_queue - command queue number
299 * @rx_buf_size_8k: 8 kB RX buffer size
300 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
301 * @scd_set_active: should the transport configure the SCD for HCMD queue
302 * @rx_page_order: page order for receive buffer size
303 * @reg_lock: protect hw register access
304 * @cmd_in_flight: true when we have a host command in flight
305 * @fw_mon_phys: physical address of the buffer for the firmware monitor
306 * @fw_mon_page: points to the first page of the buffer for the firmware monitor
307 * @fw_mon_size: size of the buffer for the firmware monitor
309 struct iwl_trans_pcie {
311 struct iwl_rb_allocator rba;
312 struct iwl_trans *trans;
315 struct net_device napi_dev;
316 struct napi_struct napi;
320 dma_addr_t ict_tbl_dma;
323 struct isr_statistics isr_stats;
328 struct iwl_dma_ptr scd_bc_tbls;
329 struct iwl_dma_ptr kw;
332 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
333 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
335 /* PCI bus related data */
336 struct pci_dev *pci_dev;
337 void __iomem *hw_base;
339 bool ucode_write_complete;
340 wait_queue_head_t ucode_write_waitq;
341 wait_queue_head_t wait_command_queue;
345 unsigned int cmd_q_wdg_timeout;
346 u8 n_no_reclaim_cmds;
347 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
354 const char *const *command_names;
356 /*protect hw register */
358 bool cmd_hold_nic_awake;
359 bool ref_cmd_in_flight;
361 /* protect ref counter */
365 dma_addr_t fw_mon_phys;
366 struct page *fw_mon_page;
370 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
371 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
373 static inline struct iwl_trans *
374 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
376 return container_of((void *)trans_pcie, struct iwl_trans,
381 * Convention: trans API functions: iwl_trans_pcie_XXX
382 * Other functions: iwl_pcie_XXX
384 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
385 const struct pci_device_id *ent,
386 const struct iwl_cfg *cfg);
387 void iwl_trans_pcie_free(struct iwl_trans *trans);
389 /*****************************************************
391 ******************************************************/
392 int iwl_pcie_rx_init(struct iwl_trans *trans);
393 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
394 int iwl_pcie_rx_stop(struct iwl_trans *trans);
395 void iwl_pcie_rx_free(struct iwl_trans *trans);
397 /*****************************************************
398 * ICT - interrupt handling
399 ******************************************************/
400 irqreturn_t iwl_pcie_isr(int irq, void *data);
401 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
402 void iwl_pcie_free_ict(struct iwl_trans *trans);
403 void iwl_pcie_reset_ict(struct iwl_trans *trans);
404 void iwl_pcie_disable_ict(struct iwl_trans *trans);
406 /*****************************************************
408 ******************************************************/
409 int iwl_pcie_tx_init(struct iwl_trans *trans);
410 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
411 int iwl_pcie_tx_stop(struct iwl_trans *trans);
412 void iwl_pcie_tx_free(struct iwl_trans *trans);
413 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
414 const struct iwl_trans_txq_scd_cfg *cfg,
415 unsigned int wdg_timeout);
416 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
418 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
419 struct iwl_device_cmd *dev_cmd, int txq_id);
420 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
421 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
422 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
423 struct iwl_rx_cmd_buffer *rxb, int handler_status);
424 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
425 struct sk_buff_head *skbs);
426 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
428 void iwl_trans_pcie_ref(struct iwl_trans *trans);
429 void iwl_trans_pcie_unref(struct iwl_trans *trans);
431 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
433 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
435 return le16_to_cpu(tb->hi_n_len) >> 4;
438 /*****************************************************
440 ******************************************************/
441 void iwl_pcie_dump_csr(struct iwl_trans *trans);
443 /*****************************************************
445 ******************************************************/
446 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
448 clear_bit(STATUS_INT_ENABLED, &trans->status);
450 /* disable interrupts from uCode/NIC to host */
451 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
453 /* acknowledge/clear/reset any interrupts still pending
454 * from uCode or flow handler (Rx/Tx DMA) */
455 iwl_write32(trans, CSR_INT, 0xffffffff);
456 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
457 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
460 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
464 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
465 set_bit(STATUS_INT_ENABLED, &trans->status);
466 trans_pcie->inta_mask = CSR_INI_SET_MASK;
467 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
470 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
472 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
474 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
475 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
476 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
479 static inline void iwl_wake_queue(struct iwl_trans *trans,
482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
484 if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
485 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
486 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
490 static inline void iwl_stop_queue(struct iwl_trans *trans,
493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
495 if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
496 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
497 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
499 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
503 static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
505 return q->write_ptr >= q->read_ptr ?
506 (i >= q->read_ptr && i < q->write_ptr) :
507 !(i < q->read_ptr && i >= q->write_ptr);
510 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
512 return index & (q->n_window - 1);
515 static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
518 if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
520 return trans_pcie->command_names[cmd];
523 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
525 return !(iwl_read32(trans, CSR_GP_CNTRL) &
526 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
529 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
530 u32 reg, u32 mask, u32 value)
534 #ifdef CONFIG_IWLWIFI_DEBUG
535 WARN_ON_ONCE(value & ~mask);
538 v = iwl_read32(trans, reg);
541 iwl_write32(trans, reg, v);
544 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
547 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
550 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
553 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
556 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
558 #endif /* __iwl_trans_int_pcie_h__ */