drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  50  *    from this software without specific prior written permission.
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  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page = NULL;
 108         dma_addr_t phys;
 109         u32 size = 0;
 110         u8 power;
 111
 112         if (!max_power) {
 113                 /* default max_power is maximum */
 114                 max_power = 26;
 115         } else {
 116                 max_power += 11;
 117         }
 118
 119         if (WARN(max_power > 26,
 120                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 121                  max_power))
 122                 return;
 123
 124         if (trans_pcie->fw_mon_page) {
 125                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 126                                            trans_pcie->fw_mon_size,
 127                                            DMA_FROM_DEVICE);
 128                 return;
 129         }
 130
 131         phys = 0;
 132         for (power = max_power; power >= 11; power--) {
 133                 int order;
 134
 135                 size = BIT(power);
 136                 order = get_order(size);
 137                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 138                                    order);
 139                 if (!page)
 140                         continue;
 141
 142                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 143                                     DMA_FROM_DEVICE);
 144                 if (dma_mapping_error(trans->dev, phys)) {
 145                         __free_pages(page, order);
 146                         page = NULL;
 147                         continue;
 148                 }
 149                 IWL_INFO(trans,
 150                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 151                          size, order);
 152                 break;
 153         }
 154
 155         if (WARN_ON_ONCE(!page))
 156                 return;
 157
 158         if (power != max_power)
 159                 IWL_ERR(trans,
 160                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 161                         (unsigned long)BIT(power - 10),
 162                         (unsigned long)BIT(max_power - 10));
 163
 164         trans_pcie->fw_mon_page = page;
 165         trans_pcie->fw_mon_phys = phys;
 166         trans_pcie->fw_mon_size = size;
 167 }
 168
 169 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 170 {
 171         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 172                     ((reg & 0x0000ffff) | (2 << 28)));
 173         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 174 }
 175
 176 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 177 {
 178         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 179         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 180                     ((reg & 0x0000ffff) | (3 << 28)));
 181 }
 182
 183 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 184 {
 185         if (!trans->cfg->apmg_not_supported)
 186                 return;
 187
 188         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 189                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 190                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 191                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 192         else
 193                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 194                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 195                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 196 }
 197
 198 /* PCI registers */
 199 #define PCI_CFG_RETRY_TIMEOUT   0x041
 200
 201 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 202 {
 203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 204         u16 lctl;
 205         u16 cap;
 206
 207         /*
 208          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 209          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 210          * If so (likely), disable L0S, so device moves directly L0->L1;
 211          *    costs negligible amount of power savings.
 212          * If not (unlikely), enable L0S, so there is at least some
 213          *    power savings, even without L1.
 214          */
 215         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 216         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 217                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 218         else
 219                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 220         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 221
 222         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 223         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 224         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 225                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 226                  trans->ltr_enabled ? "En" : "Dis");
 227 }
 228
 229 /*
 230  * Start up NIC's basic functionality after it has been reset
 231  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 232  * NOTE:  This does not load uCode nor start the embedded processor
 233  */
 234 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 235 {
 236         int ret = 0;
 237         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 238
 239         /*
 240          * Use "set_bit" below rather than "write", to preserve any hardware
 241          * bits already set by default after reset.
 242          */
 243
 244         /* Disable L0S exit timer (platform NMI Work/Around) */
 245         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 246                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 247                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 248
 249         /*
 250          * Disable L0s without affecting L1;
 251          *  don't wait for ICH L0s (ICH bug W/A)
 252          */
 253         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 254                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 255
 256         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 257         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 258
 259         /*
 260          * Enable HAP INTA (interrupt from management bus) to
 261          * wake device's PCI Express link L1a -> L0s
 262          */
 263         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 264                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 265
 266         iwl_pcie_apm_config(trans);
 267
 268         /* Configure analog phase-lock-loop before activating to D0A */
 269         if (trans->cfg->base_params->pll_cfg_val)
 270                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 271                             trans->cfg->base_params->pll_cfg_val);
 272
 273         /*
 274          * Set "initialization complete" bit to move adapter from
 275          * D0U* --> D0A* (powered-up active) state.
 276          */
 277         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 278
 279         /*
 280          * Wait for clock stabilization; once stabilized, access to
 281          * device-internal resources is supported, e.g. iwl_write_prph()
 282          * and accesses to uCode SRAM.
 283          */
 284         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 285                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 286                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 287         if (ret < 0) {
 288                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 289                 goto out;
 290         }
 291
 292         if (trans->cfg->host_interrupt_operation_mode) {
 293                 /*
 294                  * This is a bit of an abuse - This is needed for 7260 / 3160
 295                  * only check host_interrupt_operation_mode even if this is
 296                  * not related to host_interrupt_operation_mode.
 297                  *
 298                  * Enable the oscillator to count wake up time for L1 exit. This
 299                  * consumes slightly more power (100uA) - but allows to be sure
 300                  * that we wake up from L1 on time.
 301                  *
 302                  * This looks weird: read twice the same register, discard the
 303                  * value, set a bit, and yet again, read that same register
 304                  * just to discard the value. But that's the way the hardware
 305                  * seems to like it.
 306                  */
 307                 iwl_read_prph(trans, OSC_CLK);
 308                 iwl_read_prph(trans, OSC_CLK);
 309                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_read_prph(trans, OSC_CLK);
 312         }
 313
 314         /*
 315          * Enable DMA clock and wait for it to stabilize.
 316          *
 317          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 318          * bits do not disable clocks.  This preserves any hardware
 319          * bits already set by default in "CLK_CTRL_REG" after reset.
 320          */
 321         if (!trans->cfg->apmg_not_supported) {
 322                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 323                                APMG_CLK_VAL_DMA_CLK_RQT);
 324                 udelay(20);
 325
 326                 /* Disable L1-Active */
 327                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 328                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 329
 330                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 331                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 332                                APMG_RTC_INT_STT_RFKILL);
 333         }
 334
 335         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 336
 337 out:
 338         return ret;
 339 }
 340
 341 /*
 342  * Enable LP XTAL to avoid HW bug where device may consume much power if
 343  * FW is not loaded after device reset. LP XTAL is disabled by default
 344  * after device HW reset. Do it only if XTAL is fed by internal source.
 345  * Configure device's "persistence" mode to avoid resetting XTAL again when
 346  * SHRD_HW_RST occurs in S3.
 347  */
 348 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 349 {
 350         int ret;
 351         u32 apmg_gp1_reg;
 352         u32 apmg_xtal_cfg_reg;
 353         u32 dl_cfg_reg;
 354
 355         /* Force XTAL ON */
 356         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 357                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 358
 359         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 360         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 361
 362         udelay(10);
 363
 364         /*
 365          * Set "initialization complete" bit to move adapter from
 366          * D0U* --> D0A* (powered-up active) state.
 367          */
 368         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 369
 370         /*
 371          * Wait for clock stabilization; once stabilized, access to
 372          * device-internal resources is possible.
 373          */
 374         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 375                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            25000);
 378         if (WARN_ON(ret < 0)) {
 379                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 380                 /* Release XTAL ON request */
 381                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 382                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 383                 return;
 384         }
 385
 386         /*
 387          * Clear "disable persistence" to avoid LP XTAL resetting when
 388          * SHRD_HW_RST is applied in S3.
 389          */
 390         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 391                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 392
 393         /*
 394          * Force APMG XTAL to be active to prevent its disabling by HW
 395          * caused by APMG idle state.
 396          */
 397         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 398                                                     SHR_APMG_XTAL_CFG_REG);
 399         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 400                                  apmg_xtal_cfg_reg |
 401                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 402
 403         /*
 404          * Reset entire device again - do controller reset (results in
 405          * SHRD_HW_RST). Turn MAC off before proceeding.
 406          */
 407         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 408
 409         udelay(10);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 482                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 483                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 484                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 485                 mdelay(5);
 486         }
 487
 488         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 489
 490         /* Stop device's DMA activity */
 491         iwl_pcie_apm_stop_master(trans);
 492
 493         if (trans->cfg->lp_xtal_workaround) {
 494                 iwl_pcie_apm_lp_xtal_enable(trans);
 495                 return;
 496         }
 497
 498         /* Reset the entire device */
 499         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 500
 501         udelay(10);
 502
 503         /*
 504          * Clear "initialization complete" bit to move adapter from
 505          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 506          */
 507         iwl_clear_bit(trans, CSR_GP_CNTRL,
 508                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 509 }
 510
 511 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 512 {
 513         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 514
 515         /* nic_init */
 516         spin_lock(&trans_pcie->irq_lock);
 517         iwl_pcie_apm_init(trans);
 518
 519         spin_unlock(&trans_pcie->irq_lock);
 520
 521         iwl_pcie_set_pwr(trans, false);
 522
 523         iwl_op_mode_nic_config(trans->op_mode);
 524
 525         /* Allocate the RX queue, or reset if it is already allocated */
 526         iwl_pcie_rx_init(trans);
 527
 528         /* Allocate or reset and init all Tx and Command queues */
 529         if (iwl_pcie_tx_init(trans))
 530                 return -ENOMEM;
 531
 532         if (trans->cfg->base_params->shadow_reg_enable) {
 533                 /* enable shadow regs in HW */
 534                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 535                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 536         }
 537
 538         return 0;
 539 }
 540
 541 #define HW_READY_TIMEOUT (50)
 542
 543 /* Note: returns poll_bit return value, which is >= 0 if success */
 544 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 545 {
 546         int ret;
 547
 548         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 549                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 550
 551         /* See if we got it */
 552         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 553                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 554                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 555                            HW_READY_TIMEOUT);
 556
 557         if (ret >= 0)
 558                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 559
 560         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 561         return ret;
 562 }
 563
 564 /* Note: returns standard 0/-ERROR code */
 565 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 566 {
 567         int ret;
 568         int t = 0;
 569         int iter;
 570
 571         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 572
 573         ret = iwl_pcie_set_hw_ready(trans);
 574         /* If the card is ready, exit 0 */
 575         if (ret >= 0)
 576                 return 0;
 577
 578         for (iter = 0; iter < 10; iter++) {
 579                 /* If HW is not ready, prepare the conditions to check again */
 580                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 581                             CSR_HW_IF_CONFIG_REG_PREPARE);
 582
 583                 do {
 584                         ret = iwl_pcie_set_hw_ready(trans);
 585                         if (ret >= 0)
 586                                 return 0;
 587
 588                         usleep_range(200, 1000);
 589                         t += 200;
 590                 } while (t < 150000);
 591                 msleep(25);
 592         }
 593
 594         IWL_ERR(trans, "Couldn't prepare the card\n");
 595
 596         return ret;
 597 }
 598
 599 /*
 600  * ucode
 601  */
 602 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 603                                    dma_addr_t phy_addr, u32 byte_cnt)
 604 {
 605         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 606         int ret;
 607
 608         trans_pcie->ucode_write_complete = false;
 609
 610         iwl_write_direct32(trans,
 611                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 612                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 613
 614         iwl_write_direct32(trans,
 615                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 616                            dst_addr);
 617
 618         iwl_write_direct32(trans,
 619                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 620                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 621
 622         iwl_write_direct32(trans,
 623                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 624                            (iwl_get_dma_hi_addr(phy_addr)
 625                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 626
 627         iwl_write_direct32(trans,
 628                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 629                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 630                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 631                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 632
 633         iwl_write_direct32(trans,
 634                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 635                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 636                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 637                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 638
 639         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 640                                  trans_pcie->ucode_write_complete, 5 * HZ);
 641         if (!ret) {
 642                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 643                 return -ETIMEDOUT;
 644         }
 645
 646         return 0;
 647 }
 648
 649 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 650                             const struct fw_desc *section)
 651 {
 652         u8 *v_addr;
 653         dma_addr_t p_addr;
 654         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 655         int ret = 0;
 656
 657         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 658                      section_num);
 659
 660         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 661                                     GFP_KERNEL | __GFP_NOWARN);
 662         if (!v_addr) {
 663                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 664                 chunk_sz = PAGE_SIZE;
 665                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 666                                             &p_addr, GFP_KERNEL);
 667                 if (!v_addr)
 668                         return -ENOMEM;
 669         }
 670
 671         for (offset = 0; offset < section->len; offset += chunk_sz) {
 672                 u32 copy_size, dst_addr;
 673                 bool extended_addr = false;
 674
 675                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 676                 dst_addr = section->offset + offset;
 677
 678                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 679                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 680                         extended_addr = true;
 681
 682                 if (extended_addr)
 683                         iwl_set_bits_prph(trans, LMPM_CHICK,
 684                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 685
 686                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 687                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 688                                                    copy_size);
 689
 690                 if (extended_addr)
 691                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 692                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 693
 694                 if (ret) {
 695                         IWL_ERR(trans,
 696                                 "Could not load the [%d] uCode section\n",
 697                                 section_num);
 698                         break;
 699                 }
 700         }
 701
 702         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 703         return ret;
 704 }
 705
 706 /*
 707  * Driver Takes the ownership on secure machine before FW load
 708  * and prevent race with the BT load.
 709  * W/A for ROM bug. (should be remove in the next Si step)
 710  */
 711 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 712 {
 713         u32 val, loop = 1000;
 714
 715         /*
 716          * Check the RSA semaphore is accessible.
 717          * If the HW isn't locked and the rsa semaphore isn't accessible,
 718          * we are in trouble.
 719          */
 720         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 721         if (val & (BIT(1) | BIT(17))) {
 722                 IWL_INFO(trans,
 723                          "can't access the RSA semaphore it is write protected\n");
 724                 return 0;
 725         }
 726
 727         /* take ownership on the AUX IF */
 728         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 729         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 730
 731         do {
 732                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 733                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 734                 if (val == 0x1) {
 735                         iwl_write_prph(trans, RSA_ENABLE, 0);
 736                         return 0;
 737                 }
 738
 739                 udelay(10);
 740                 loop--;
 741         } while (loop > 0);
 742
 743         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 744         return -EIO;
 745 }
 746
 747 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 748                                            const struct fw_img *image,
 749                                            int cpu,
 750                                            int *first_ucode_section)
 751 {
 752         int shift_param;
 753         int i, ret = 0, sec_num = 0x1;
 754         u32 val, last_read_idx = 0;
 755
 756         if (cpu == 1) {
 757                 shift_param = 0;
 758                 *first_ucode_section = 0;
 759         } else {
 760                 shift_param = 16;
 761                 (*first_ucode_section)++;
 762         }
 763
 764         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 765                 last_read_idx = i;
 766
 767                 if (!image->sec[i].data ||
 768                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 769                         IWL_DEBUG_FW(trans,
 770                                      "Break since Data not valid or Empty section, sec = %d\n",
 771                                      i);
 772                         break;
 773                 }
 774
 775                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 776                 if (ret)
 777                         return ret;
 778
 779                 /* Notify the ucode of the loaded section number and status */
 780                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 781                 val = val | (sec_num << shift_param);
 782                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 783                 sec_num = (sec_num << 1) | 0x1;
 784         }
 785
 786         *first_ucode_section = last_read_idx;
 787
 788         if (cpu == 1)
 789                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 790         else
 791                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 792
 793         return 0;
 794 }
 795
 796 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 797                                       const struct fw_img *image,
 798                                       int cpu,
 799                                       int *first_ucode_section)
 800 {
 801         int shift_param;
 802         int i, ret = 0;
 803         u32 last_read_idx = 0;
 804
 805         if (cpu == 1) {
 806                 shift_param = 0;
 807                 *first_ucode_section = 0;
 808         } else {
 809                 shift_param = 16;
 810                 (*first_ucode_section)++;
 811         }
 812
 813         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 814                 last_read_idx = i;
 815
 816                 if (!image->sec[i].data ||
 817                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 818                         IWL_DEBUG_FW(trans,
 819                                      "Break since Data not valid or Empty section, sec = %d\n",
 820                                      i);
 821                         break;
 822                 }
 823
 824                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 825                 if (ret)
 826                         return ret;
 827         }
 828
 829         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 830                 iwl_set_bits_prph(trans,
 831                                   CSR_UCODE_LOAD_STATUS_ADDR,
 832                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 833                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 834                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 835                                         shift_param);
 836
 837         *first_ucode_section = last_read_idx;
 838
 839         return 0;
 840 }
 841
 842 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 843 {
 844         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 845         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 846         int i;
 847
 848         if (dest->version)
 849                 IWL_ERR(trans,
 850                         "DBG DEST version is %d - expect issues\n",
 851                         dest->version);
 852
 853         IWL_INFO(trans, "Applying debug destination %s\n",
 854                  get_fw_dbg_mode_string(dest->monitor_mode));
 855
 856         if (dest->monitor_mode == EXTERNAL_MODE)
 857                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 858         else
 859                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 860
 861         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 862                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 863                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 864
 865                 switch (dest->reg_ops[i].op) {
 866                 case CSR_ASSIGN:
 867                         iwl_write32(trans, addr, val);
 868                         break;
 869                 case CSR_SETBIT:
 870                         iwl_set_bit(trans, addr, BIT(val));
 871                         break;
 872                 case CSR_CLEARBIT:
 873                         iwl_clear_bit(trans, addr, BIT(val));
 874                         break;
 875                 case PRPH_ASSIGN:
 876                         iwl_write_prph(trans, addr, val);
 877                         break;
 878                 case PRPH_SETBIT:
 879                         iwl_set_bits_prph(trans, addr, BIT(val));
 880                         break;
 881                 case PRPH_CLEARBIT:
 882                         iwl_clear_bits_prph(trans, addr, BIT(val));
 883                         break;
 884                 default:
 885                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 886                                 dest->reg_ops[i].op);
 887                         break;
 888                 }
 889         }
 890
 891         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 892                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 893                                trans_pcie->fw_mon_phys >> dest->base_shift);
 894                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 895                                (trans_pcie->fw_mon_phys +
 896                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 897         }
 898 }
 899
 900 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 901                                 const struct fw_img *image)
 902 {
 903         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 904         int ret = 0;
 905         int first_ucode_section;
 906
 907         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 908                      image->is_dual_cpus ? "Dual" : "Single");
 909
 910         /* load to FW the binary non secured sections of CPU1 */
 911         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 912         if (ret)
 913                 return ret;
 914
 915         if (image->is_dual_cpus) {
 916                 /* set CPU2 header address */
 917                 iwl_write_prph(trans,
 918                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 919                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 920
 921                 /* load to FW the binary sections of CPU2 */
 922                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 923                                                  &first_ucode_section);
 924                 if (ret)
 925                         return ret;
 926         }
 927
 928         /* supported for 7000 only for the moment */
 929         if (iwlwifi_mod_params.fw_monitor &&
 930             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 931                 iwl_pcie_alloc_fw_monitor(trans, 0);
 932
 933                 if (trans_pcie->fw_mon_size) {
 934                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 935                                        trans_pcie->fw_mon_phys >> 4);
 936                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 937                                        (trans_pcie->fw_mon_phys +
 938                                         trans_pcie->fw_mon_size) >> 4);
 939                 }
 940         } else if (trans->dbg_dest_tlv) {
 941                 iwl_pcie_apply_destination(trans);
 942         }
 943
 944         /* release CPU reset */
 945         iwl_write32(trans, CSR_RESET, 0);
 946
 947         return 0;
 948 }
 949
 950 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 951                                           const struct fw_img *image)
 952 {
 953         int ret = 0;
 954         int first_ucode_section;
 955
 956         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 957                      image->is_dual_cpus ? "Dual" : "Single");
 958
 959         if (trans->dbg_dest_tlv)
 960                 iwl_pcie_apply_destination(trans);
 961
 962         /* TODO: remove in the next Si step */
 963         ret = iwl_pcie_rsa_race_bug_wa(trans);
 964         if (ret)
 965                 return ret;
 966
 967         /* configure the ucode to be ready to get the secured image */
 968         /* release CPU reset */
 969         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 970
 971         /* load to FW the binary Secured sections of CPU1 */
 972         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 973                                               &first_ucode_section);
 974         if (ret)
 975                 return ret;
 976
 977         /* load to FW the binary sections of CPU2 */
 978         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 979                                                &first_ucode_section);
 980 }
 981
 982 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 983                                    const struct fw_img *fw, bool run_in_rfkill)
 984 {
 985         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 986         bool hw_rfkill;
 987         int ret;
 988
 989         mutex_lock(&trans_pcie->mutex);
 990
 991         /* Someone called stop_device, don't try to start_fw */
 992         if (trans_pcie->is_down) {
 993                 IWL_WARN(trans,
 994                          "Can't start_fw since the HW hasn't been started\n");
 995                 ret = EIO;
 996                 goto out;
 997         }
 998
 999         /* This may fail if AMT took ownership of the device */
1000         if (iwl_pcie_prepare_card_hw(trans)) {
1001                 IWL_WARN(trans, "Exit HW not ready\n");
1002                 ret = -EIO;
1003                 goto out;
1004         }
1005
1006         iwl_enable_rfkill_int(trans);
1007
1008         /* If platform's RF_KILL switch is NOT set to KILL */
1009         hw_rfkill = iwl_is_rfkill_set(trans);
1010         if (hw_rfkill)
1011                 set_bit(STATUS_RFKILL, &trans->status);
1012         else
1013                 clear_bit(STATUS_RFKILL, &trans->status);
1014         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1015         if (hw_rfkill && !run_in_rfkill) {
1016                 ret = -ERFKILL;
1017                 goto out;
1018         }
1019
1020         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1021
1022         ret = iwl_pcie_nic_init(trans);
1023         if (ret) {
1024                 IWL_ERR(trans, "Unable to init nic\n");
1025                 goto out;
1026         }
1027
1028         /* make sure rfkill handshake bits are cleared */
1029         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1030         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1031                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1032
1033         /* clear (again), then enable host interrupts */
1034         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1035         iwl_enable_interrupts(trans);
1036
1037         /* really make sure rfkill handshake bits are cleared */
1038         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1039         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1040
1041         /* Load the given image to the HW */
1042         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1043                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1044         else
1045                 ret = iwl_pcie_load_given_ucode(trans, fw);
1046
1047 out:
1048         mutex_unlock(&trans_pcie->mutex);
1049         return ret;
1050 }
1051
1052 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1053 {
1054         iwl_pcie_reset_ict(trans);
1055         iwl_pcie_tx_start(trans, scd_addr);
1056 }
1057
1058 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1059 {
1060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061         bool hw_rfkill, was_hw_rfkill;
1062
1063         lockdep_assert_held(&trans_pcie->mutex);
1064
1065         if (trans_pcie->is_down)
1066                 return;
1067
1068         trans_pcie->is_down = true;
1069
1070         was_hw_rfkill = iwl_is_rfkill_set(trans);
1071
1072         /* tell the device to stop sending interrupts */
1073         spin_lock(&trans_pcie->irq_lock);
1074         iwl_disable_interrupts(trans);
1075         spin_unlock(&trans_pcie->irq_lock);
1076
1077         /* device going down, Stop using ICT table */
1078         iwl_pcie_disable_ict(trans);
1079
1080         /*
1081          * If a HW restart happens during firmware loading,
1082          * then the firmware loading might call this function
1083          * and later it might be called again due to the
1084          * restart. So don't process again if the device is
1085          * already dead.
1086          */
1087         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1088                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1089                 iwl_pcie_tx_stop(trans);
1090                 iwl_pcie_rx_stop(trans);
1091
1092                 /* Power-down device's busmaster DMA clocks */
1093                 if (!trans->cfg->apmg_not_supported) {
1094                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1095                                        APMG_CLK_VAL_DMA_CLK_RQT);
1096                         udelay(5);
1097                 }
1098         }
1099
1100         /* Make sure (redundant) we've released our request to stay awake */
1101         iwl_clear_bit(trans, CSR_GP_CNTRL,
1102                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1103
1104         /* Stop the device, and put it in low power state */
1105         iwl_pcie_apm_stop(trans, false);
1106
1107         /* stop and reset the on-board processor */
1108         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1109         udelay(20);
1110
1111         /*
1112          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1113          * This is a bug in certain verions of the hardware.
1114          * Certain devices also keep sending HW RF kill interrupt all
1115          * the time, unless the interrupt is ACKed even if the interrupt
1116          * should be masked. Re-ACK all the interrupts here.
1117          */
1118         spin_lock(&trans_pcie->irq_lock);
1119         iwl_disable_interrupts(trans);
1120         spin_unlock(&trans_pcie->irq_lock);
1121
1122
1123         /* clear all status bits */
1124         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1125         clear_bit(STATUS_INT_ENABLED, &trans->status);
1126         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1127         clear_bit(STATUS_RFKILL, &trans->status);
1128
1129         /*
1130          * Even if we stop the HW, we still want the RF kill
1131          * interrupt
1132          */
1133         iwl_enable_rfkill_int(trans);
1134
1135         /*
1136          * Check again since the RF kill state may have changed while
1137          * all the interrupts were disabled, in this case we couldn't
1138          * receive the RF kill interrupt and update the state in the
1139          * op_mode.
1140          * Don't call the op_mode if the rkfill state hasn't changed.
1141          * This allows the op_mode to call stop_device from the rfkill
1142          * notification without endless recursion. Under very rare
1143          * circumstances, we might have a small recursion if the rfkill
1144          * state changed exactly now while we were called from stop_device.
1145          * This is very unlikely but can happen and is supported.
1146          */
1147         hw_rfkill = iwl_is_rfkill_set(trans);
1148         if (hw_rfkill)
1149                 set_bit(STATUS_RFKILL, &trans->status);
1150         else
1151                 clear_bit(STATUS_RFKILL, &trans->status);
1152         if (hw_rfkill != was_hw_rfkill)
1153                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1154
1155         /* re-take ownership to prevent other users from stealing the deivce */
1156         iwl_pcie_prepare_card_hw(trans);
1157 }
1158
1159 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1160 {
1161         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1162
1163         mutex_lock(&trans_pcie->mutex);
1164         _iwl_trans_pcie_stop_device(trans, low_power);
1165         mutex_unlock(&trans_pcie->mutex);
1166 }
1167
1168 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1169 {
1170         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1171                 IWL_TRANS_GET_PCIE_TRANS(trans);
1172
1173         lockdep_assert_held(&trans_pcie->mutex);
1174
1175         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1176                 _iwl_trans_pcie_stop_device(trans, true);
1177 }
1178
1179 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1180 {
1181         iwl_disable_interrupts(trans);
1182
1183         /*
1184          * in testing mode, the host stays awake and the
1185          * hardware won't be reset (not even partially)
1186          */
1187         if (test)
1188                 return;
1189
1190         iwl_pcie_disable_ict(trans);
1191
1192         iwl_clear_bit(trans, CSR_GP_CNTRL,
1193                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1194         iwl_clear_bit(trans, CSR_GP_CNTRL,
1195                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1196
1197         /*
1198          * reset TX queues -- some of their registers reset during S3
1199          * so if we don't reset everything here the D3 image would try
1200          * to execute some invalid memory upon resume
1201          */
1202         iwl_trans_pcie_tx_reset(trans);
1203
1204         iwl_pcie_set_pwr(trans, true);
1205 }
1206
1207 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1208                                     enum iwl_d3_status *status,
1209                                     bool test)
1210 {
1211         u32 val;
1212         int ret;
1213
1214         if (test) {
1215                 iwl_enable_interrupts(trans);
1216                 *status = IWL_D3_STATUS_ALIVE;
1217                 return 0;
1218         }
1219
1220         /*
1221          * Also enables interrupts - none will happen as the device doesn't
1222          * know we're waking it up, only when the opmode actually tells it
1223          * after this call.
1224          */
1225         iwl_pcie_reset_ict(trans);
1226
1227         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1228         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1229
1230         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1231                 udelay(2);
1232
1233         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1234                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1235                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1236                            25000);
1237         if (ret < 0) {
1238                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1239                 return ret;
1240         }
1241
1242         iwl_pcie_set_pwr(trans, false);
1243
1244         iwl_trans_pcie_tx_reset(trans);
1245
1246         ret = iwl_pcie_rx_init(trans);
1247         if (ret) {
1248                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1249                 return ret;
1250         }
1251
1252         val = iwl_read32(trans, CSR_RESET);
1253         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1254                 *status = IWL_D3_STATUS_RESET;
1255         else
1256                 *status = IWL_D3_STATUS_ALIVE;
1257
1258         return 0;
1259 }
1260
1261 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1262 {
1263         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1264         bool hw_rfkill;
1265         int err;
1266
1267         lockdep_assert_held(&trans_pcie->mutex);
1268
1269         err = iwl_pcie_prepare_card_hw(trans);
1270         if (err) {
1271                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1272                 return err;
1273         }
1274
1275         /* Reset the entire device */
1276         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1277
1278         usleep_range(10, 15);
1279
1280         iwl_pcie_apm_init(trans);
1281
1282         /* From now on, the op_mode will be kept updated about RF kill state */
1283         iwl_enable_rfkill_int(trans);
1284
1285         /* Set is_down to false here so that...*/
1286         trans_pcie->is_down = false;
1287
1288         hw_rfkill = iwl_is_rfkill_set(trans);
1289         if (hw_rfkill)
1290                 set_bit(STATUS_RFKILL, &trans->status);
1291         else
1292                 clear_bit(STATUS_RFKILL, &trans->status);
1293         /* ... rfkill can call stop_device and set it false if needed */
1294         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1295
1296         return 0;
1297 }
1298
1299 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1300 {
1301         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1302         int ret;
1303
1304         mutex_lock(&trans_pcie->mutex);
1305         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1306         mutex_unlock(&trans_pcie->mutex);
1307
1308         return ret;
1309 }
1310
1311 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1312 {
1313         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1314
1315         mutex_lock(&trans_pcie->mutex);
1316
1317         /* disable interrupts - don't enable HW RF kill interrupt */
1318         spin_lock(&trans_pcie->irq_lock);
1319         iwl_disable_interrupts(trans);
1320         spin_unlock(&trans_pcie->irq_lock);
1321
1322         iwl_pcie_apm_stop(trans, true);
1323
1324         spin_lock(&trans_pcie->irq_lock);
1325         iwl_disable_interrupts(trans);
1326         spin_unlock(&trans_pcie->irq_lock);
1327
1328         iwl_pcie_disable_ict(trans);
1329         mutex_unlock(&trans_pcie->mutex);
1330 }
1331
1332 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1333 {
1334         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1335 }
1336
1337 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1338 {
1339         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1340 }
1341
1342 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1343 {
1344         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1345 }
1346
1347 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1348 {
1349         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1350                                ((reg & 0x000FFFFF) | (3 << 24)));
1351         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1352 }
1353
1354 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1355                                       u32 val)
1356 {
1357         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1358                                ((addr & 0x000FFFFF) | (3 << 24)));
1359         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1360 }
1361
1362 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1363 {
1364         WARN_ON(1);
1365         return 0;
1366 }
1367
1368 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1369                                      const struct iwl_trans_config *trans_cfg)
1370 {
1371         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1372
1373         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1374         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1375         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1376         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1377                 trans_pcie->n_no_reclaim_cmds = 0;
1378         else
1379                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1380         if (trans_pcie->n_no_reclaim_cmds)
1381                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1382                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1383
1384         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1385         if (trans_pcie->rx_buf_size_8k)
1386                 trans_pcie->rx_page_order = get_order(8 * 1024);
1387         else
1388                 trans_pcie->rx_page_order = get_order(4 * 1024);
1389
1390         trans_pcie->command_names = trans_cfg->command_names;
1391         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1392         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1393
1394         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1395         trans_pcie->ref_count = 1;
1396
1397         /* Initialize NAPI here - it should be before registering to mac80211
1398          * in the opmode but after the HW struct is allocated.
1399          * As this function may be called again in some corner cases don't
1400          * do anything if NAPI was already initialized.
1401          */
1402         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1403                 init_dummy_netdev(&trans_pcie->napi_dev);
1404                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1405                                      &trans_pcie->napi_dev,
1406                                      iwl_pcie_dummy_napi_poll, 64);
1407         }
1408 }
1409
1410 void iwl_trans_pcie_free(struct iwl_trans *trans)
1411 {
1412         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1413
1414         synchronize_irq(trans_pcie->pci_dev->irq);
1415
1416         iwl_pcie_tx_free(trans);
1417         iwl_pcie_rx_free(trans);
1418
1419         free_irq(trans_pcie->pci_dev->irq, trans);
1420         iwl_pcie_free_ict(trans);
1421
1422         pci_disable_msi(trans_pcie->pci_dev);
1423         iounmap(trans_pcie->hw_base);
1424         pci_release_regions(trans_pcie->pci_dev);
1425         pci_disable_device(trans_pcie->pci_dev);
1426
1427         if (trans_pcie->napi.poll)
1428                 netif_napi_del(&trans_pcie->napi);
1429
1430         iwl_pcie_free_fw_monitor(trans);
1431
1432         iwl_trans_free(trans);
1433 }
1434
1435 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1436 {
1437         if (state)
1438                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1439         else
1440                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1441 }
1442
1443 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1444                                                 unsigned long *flags)
1445 {
1446         int ret;
1447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1448
1449         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1450
1451         if (trans_pcie->cmd_hold_nic_awake)
1452                 goto out;
1453
1454         /* this bit wakes up the NIC */
1455         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1456                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1457         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1458                 udelay(2);
1459
1460         /*
1461          * These bits say the device is running, and should keep running for
1462          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1463          * but they do not indicate that embedded SRAM is restored yet;
1464          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1465          * to/from host DRAM when sleeping/waking for power-saving.
1466          * Each direction takes approximately 1/4 millisecond; with this
1467          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1468          * series of register accesses are expected (e.g. reading Event Log),
1469          * to keep device from sleeping.
1470          *
1471          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1472          * SRAM is okay/restored.  We don't check that here because this call
1473          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1474          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1475          *
1476          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1477          * and do not save/restore SRAM when power cycling.
1478          */
1479         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1480                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1481                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1482                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1483         if (unlikely(ret < 0)) {
1484                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1485                 if (!silent) {
1486                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1487                         WARN_ONCE(1,
1488                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1489                                   val);
1490                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1491                         return false;
1492                 }
1493         }
1494
1495 out:
1496         /*
1497          * Fool sparse by faking we release the lock - sparse will
1498          * track nic_access anyway.
1499          */
1500         __release(&trans_pcie->reg_lock);
1501         return true;
1502 }
1503
1504 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1505                                               unsigned long *flags)
1506 {
1507         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1508
1509         lockdep_assert_held(&trans_pcie->reg_lock);
1510
1511         /*
1512          * Fool sparse by faking we acquiring the lock - sparse will
1513          * track nic_access anyway.
1514          */
1515         __acquire(&trans_pcie->reg_lock);
1516
1517         if (trans_pcie->cmd_hold_nic_awake)
1518                 goto out;
1519
1520         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1521                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1522         /*
1523          * Above we read the CSR_GP_CNTRL register, which will flush
1524          * any previous writes, but we need the write that clears the
1525          * MAC_ACCESS_REQ bit to be performed before any other writes
1526          * scheduled on different CPUs (after we drop reg_lock).
1527          */
1528         mmiowb();
1529 out:
1530         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1531 }
1532
1533 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1534                                    void *buf, int dwords)
1535 {
1536         unsigned long flags;
1537         int offs, ret = 0;
1538         u32 *vals = buf;
1539
1540         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1541                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1542                 for (offs = 0; offs < dwords; offs++)
1543                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1544                 iwl_trans_release_nic_access(trans, &flags);
1545         } else {
1546                 ret = -EBUSY;
1547         }
1548         return ret;
1549 }
1550
1551 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1552                                     const void *buf, int dwords)
1553 {
1554         unsigned long flags;
1555         int offs, ret = 0;
1556         const u32 *vals = buf;
1557
1558         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1559                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1560                 for (offs = 0; offs < dwords; offs++)
1561                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1562                                     vals ? vals[offs] : 0);
1563                 iwl_trans_release_nic_access(trans, &flags);
1564         } else {
1565                 ret = -EBUSY;
1566         }
1567         return ret;
1568 }
1569
1570 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1571                                             unsigned long txqs,
1572                                             bool freeze)
1573 {
1574         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1575         int queue;
1576
1577         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1578                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1579                 unsigned long now;
1580
1581                 spin_lock_bh(&txq->lock);
1582
1583                 now = jiffies;
1584
1585                 if (txq->frozen == freeze)
1586                         goto next_queue;
1587
1588                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1589                                     freeze ? "Freezing" : "Waking", queue);
1590
1591                 txq->frozen = freeze;
1592
1593                 if (txq->q.read_ptr == txq->q.write_ptr)
1594                         goto next_queue;
1595
1596                 if (freeze) {
1597                         if (unlikely(time_after(now,
1598                                                 txq->stuck_timer.expires))) {
1599                                 /*
1600                                  * The timer should have fired, maybe it is
1601                                  * spinning right now on the lock.
1602                                  */
1603                                 goto next_queue;
1604                         }
1605                         /* remember how long until the timer fires */
1606                         txq->frozen_expiry_remainder =
1607                                 txq->stuck_timer.expires - now;
1608                         del_timer(&txq->stuck_timer);
1609                         goto next_queue;
1610                 }
1611
1612                 /*
1613                  * Wake a non-empty queue -> arm timer with the
1614                  * remainder before it froze
1615                  */
1616                 mod_timer(&txq->stuck_timer,
1617                           now + txq->frozen_expiry_remainder);
1618
1619 next_queue:
1620                 spin_unlock_bh(&txq->lock);
1621         }
1622 }
1623
1624 #define IWL_FLUSH_WAIT_MS       2000
1625
1626 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1627 {
1628         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1629         struct iwl_txq *txq;
1630         struct iwl_queue *q;
1631         int cnt;
1632         unsigned long now = jiffies;
1633         u32 scd_sram_addr;
1634         u8 buf[16];
1635         int ret = 0;
1636
1637         /* waiting for all the tx frames complete might take a while */
1638         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1639                 u8 wr_ptr;
1640
1641                 if (cnt == trans_pcie->cmd_queue)
1642                         continue;
1643                 if (!test_bit(cnt, trans_pcie->queue_used))
1644                         continue;
1645                 if (!(BIT(cnt) & txq_bm))
1646                         continue;
1647
1648                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1649                 txq = &trans_pcie->txq[cnt];
1650                 q = &txq->q;
1651                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1652
1653                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1654                        !time_after(jiffies,
1655                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1656                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1657
1658                         if (WARN_ONCE(wr_ptr != write_ptr,
1659                                       "WR pointer moved while flushing %d -> %d\n",
1660                                       wr_ptr, write_ptr))
1661                                 return -ETIMEDOUT;
1662                         msleep(1);
1663                 }
1664
1665                 if (q->read_ptr != q->write_ptr) {
1666                         IWL_ERR(trans,
1667                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1668                         ret = -ETIMEDOUT;
1669                         break;
1670                 }
1671                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1672         }
1673
1674         if (!ret)
1675                 return 0;
1676
1677         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1678                 txq->q.read_ptr, txq->q.write_ptr);
1679
1680         scd_sram_addr = trans_pcie->scd_base_addr +
1681                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1682         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1683
1684         iwl_print_hex_error(trans, buf, sizeof(buf));
1685
1686         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1687                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1688                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1689
1690         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1691                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1692                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1693                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1694                 u32 tbl_dw =
1695                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1696                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1697
1698                 if (cnt & 0x1)
1699                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1700                 else
1701                         tbl_dw = tbl_dw & 0x0000FFFF;
1702
1703                 IWL_ERR(trans,
1704                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1705                         cnt, active ? "" : "in", fifo, tbl_dw,
1706                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1707                                 (TFD_QUEUE_SIZE_MAX - 1),
1708                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1709         }
1710
1711         return ret;
1712 }
1713
1714 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1715                                          u32 mask, u32 value)
1716 {
1717         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1718         unsigned long flags;
1719
1720         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1721         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1722         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1723 }
1724
1725 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1726 {
1727         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728         unsigned long flags;
1729
1730         if (iwlwifi_mod_params.d0i3_disable)
1731                 return;
1732
1733         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1734         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1735         trans_pcie->ref_count++;
1736         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1737 }
1738
1739 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1740 {
1741         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1742         unsigned long flags;
1743
1744         if (iwlwifi_mod_params.d0i3_disable)
1745                 return;
1746
1747         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1748         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1749         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1750                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1751                 return;
1752         }
1753         trans_pcie->ref_count--;
1754         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1755 }
1756
1757 static const char *get_csr_string(int cmd)
1758 {
1759 #define IWL_CMD(x) case x: return #x
1760         switch (cmd) {
1761         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1762         IWL_CMD(CSR_INT_COALESCING);
1763         IWL_CMD(CSR_INT);
1764         IWL_CMD(CSR_INT_MASK);
1765         IWL_CMD(CSR_FH_INT_STATUS);
1766         IWL_CMD(CSR_GPIO_IN);
1767         IWL_CMD(CSR_RESET);
1768         IWL_CMD(CSR_GP_CNTRL);
1769         IWL_CMD(CSR_HW_REV);
1770         IWL_CMD(CSR_EEPROM_REG);
1771         IWL_CMD(CSR_EEPROM_GP);
1772         IWL_CMD(CSR_OTP_GP_REG);
1773         IWL_CMD(CSR_GIO_REG);
1774         IWL_CMD(CSR_GP_UCODE_REG);
1775         IWL_CMD(CSR_GP_DRIVER_REG);
1776         IWL_CMD(CSR_UCODE_DRV_GP1);
1777         IWL_CMD(CSR_UCODE_DRV_GP2);
1778         IWL_CMD(CSR_LED_REG);
1779         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1780         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1781         IWL_CMD(CSR_ANA_PLL_CFG);
1782         IWL_CMD(CSR_HW_REV_WA_REG);
1783         IWL_CMD(CSR_MONITOR_STATUS_REG);
1784         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1785         default:
1786                 return "UNKNOWN";
1787         }
1788 #undef IWL_CMD
1789 }
1790
1791 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1792 {
1793         int i;
1794         static const u32 csr_tbl[] = {
1795                 CSR_HW_IF_CONFIG_REG,
1796                 CSR_INT_COALESCING,
1797                 CSR_INT,
1798                 CSR_INT_MASK,
1799                 CSR_FH_INT_STATUS,
1800                 CSR_GPIO_IN,
1801                 CSR_RESET,
1802                 CSR_GP_CNTRL,
1803                 CSR_HW_REV,
1804                 CSR_EEPROM_REG,
1805                 CSR_EEPROM_GP,
1806                 CSR_OTP_GP_REG,
1807                 CSR_GIO_REG,
1808                 CSR_GP_UCODE_REG,
1809                 CSR_GP_DRIVER_REG,
1810                 CSR_UCODE_DRV_GP1,
1811                 CSR_UCODE_DRV_GP2,
1812                 CSR_LED_REG,
1813                 CSR_DRAM_INT_TBL_REG,
1814                 CSR_GIO_CHICKEN_BITS,
1815                 CSR_ANA_PLL_CFG,
1816                 CSR_MONITOR_STATUS_REG,
1817                 CSR_HW_REV_WA_REG,
1818                 CSR_DBG_HPET_MEM_REG
1819         };
1820         IWL_ERR(trans, "CSR values:\n");
1821         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1822                 "CSR_INT_PERIODIC_REG)\n");
1823         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1824                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1825                         get_csr_string(csr_tbl[i]),
1826                         iwl_read32(trans, csr_tbl[i]));
1827         }
1828 }
1829
1830 #ifdef CONFIG_IWLWIFI_DEBUGFS
1831 /* create and remove of files */
1832 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1833         if (!debugfs_create_file(#name, mode, parent, trans,            \
1834                                  &iwl_dbgfs_##name##_ops))              \
1835                 goto err;                                               \
1836 } while (0)
1837
1838 /* file operation */
1839 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1840 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1841         .read = iwl_dbgfs_##name##_read,                                \
1842         .open = simple_open,                                            \
1843         .llseek = generic_file_llseek,                                  \
1844 };
1845
1846 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1847 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1848         .write = iwl_dbgfs_##name##_write,                              \
1849         .open = simple_open,                                            \
1850         .llseek = generic_file_llseek,                                  \
1851 };
1852
1853 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1854 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1855         .write = iwl_dbgfs_##name##_write,                              \
1856         .read = iwl_dbgfs_##name##_read,                                \
1857         .open = simple_open,                                            \
1858         .llseek = generic_file_llseek,                                  \
1859 };
1860
1861 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1862                                        char __user *user_buf,
1863                                        size_t count, loff_t *ppos)
1864 {
1865         struct iwl_trans *trans = file->private_data;
1866         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1867         struct iwl_txq *txq;
1868         struct iwl_queue *q;
1869         char *buf;
1870         int pos = 0;
1871         int cnt;
1872         int ret;
1873         size_t bufsz;
1874
1875         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1876
1877         if (!trans_pcie->txq)
1878                 return -EAGAIN;
1879
1880         buf = kzalloc(bufsz, GFP_KERNEL);
1881         if (!buf)
1882                 return -ENOMEM;
1883
1884         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1885                 txq = &trans_pcie->txq[cnt];
1886                 q = &txq->q;
1887                 pos += scnprintf(buf + pos, bufsz - pos,
1888                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1889                                 cnt, q->read_ptr, q->write_ptr,
1890                                 !!test_bit(cnt, trans_pcie->queue_used),
1891                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1892                                  txq->need_update, txq->frozen,
1893                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1894         }
1895         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1896         kfree(buf);
1897         return ret;
1898 }
1899
1900 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1901                                        char __user *user_buf,
1902                                        size_t count, loff_t *ppos)
1903 {
1904         struct iwl_trans *trans = file->private_data;
1905         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1906         struct iwl_rxq *rxq = &trans_pcie->rxq;
1907         char buf[256];
1908         int pos = 0;
1909         const size_t bufsz = sizeof(buf);
1910
1911         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1912                                                 rxq->read);
1913         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1914                                                 rxq->write);
1915         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1916                                                 rxq->write_actual);
1917         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1918                                                 rxq->need_update);
1919         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1920                                                 rxq->free_count);
1921         if (rxq->rb_stts) {
1922                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1923                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1924         } else {
1925                 pos += scnprintf(buf + pos, bufsz - pos,
1926                                         "closed_rb_num: Not Allocated\n");
1927         }
1928         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1929 }
1930
1931 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1932                                         char __user *user_buf,
1933                                         size_t count, loff_t *ppos)
1934 {
1935         struct iwl_trans *trans = file->private_data;
1936         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1937         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1938
1939         int pos = 0;
1940         char *buf;
1941         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1942         ssize_t ret;
1943
1944         buf = kzalloc(bufsz, GFP_KERNEL);
1945         if (!buf)
1946                 return -ENOMEM;
1947
1948         pos += scnprintf(buf + pos, bufsz - pos,
1949                         "Interrupt Statistics Report:\n");
1950
1951         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1952                 isr_stats->hw);
1953         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1954                 isr_stats->sw);
1955         if (isr_stats->sw || isr_stats->hw) {
1956                 pos += scnprintf(buf + pos, bufsz - pos,
1957                         "\tLast Restarting Code:  0x%X\n",
1958                         isr_stats->err_code);
1959         }
1960 #ifdef CONFIG_IWLWIFI_DEBUG
1961         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1962                 isr_stats->sch);
1963         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1964                 isr_stats->alive);
1965 #endif
1966         pos += scnprintf(buf + pos, bufsz - pos,
1967                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1968
1969         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1970                 isr_stats->ctkill);
1971
1972         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1973                 isr_stats->wakeup);
1974
1975         pos += scnprintf(buf + pos, bufsz - pos,
1976                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1977
1978         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1979                 isr_stats->tx);
1980
1981         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1982                 isr_stats->unhandled);
1983
1984         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1985         kfree(buf);
1986         return ret;
1987 }
1988
1989 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1990                                          const char __user *user_buf,
1991                                          size_t count, loff_t *ppos)
1992 {
1993         struct iwl_trans *trans = file->private_data;
1994         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1995         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1996
1997         char buf[8];
1998         int buf_size;
1999         u32 reset_flag;
2000
2001         memset(buf, 0, sizeof(buf));
2002         buf_size = min(count, sizeof(buf) -  1);
2003         if (copy_from_user(buf, user_buf, buf_size))
2004                 return -EFAULT;
2005         if (sscanf(buf, "%x", &reset_flag) != 1)
2006                 return -EFAULT;
2007         if (reset_flag == 0)
2008                 memset(isr_stats, 0, sizeof(*isr_stats));
2009
2010         return count;
2011 }
2012
2013 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2014                                    const char __user *user_buf,
2015                                    size_t count, loff_t *ppos)
2016 {
2017         struct iwl_trans *trans = file->private_data;
2018         char buf[8];
2019         int buf_size;
2020         int csr;
2021
2022         memset(buf, 0, sizeof(buf));
2023         buf_size = min(count, sizeof(buf) -  1);
2024         if (copy_from_user(buf, user_buf, buf_size))
2025                 return -EFAULT;
2026         if (sscanf(buf, "%d", &csr) != 1)
2027                 return -EFAULT;
2028
2029         iwl_pcie_dump_csr(trans);
2030
2031         return count;
2032 }
2033
2034 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2035                                      char __user *user_buf,
2036                                      size_t count, loff_t *ppos)
2037 {
2038         struct iwl_trans *trans = file->private_data;
2039         char *buf = NULL;
2040         ssize_t ret;
2041
2042         ret = iwl_dump_fh(trans, &buf);
2043         if (ret < 0)
2044                 return ret;
2045         if (!buf)
2046                 return -EINVAL;
2047         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2048         kfree(buf);
2049         return ret;
2050 }
2051
2052 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2053 DEBUGFS_READ_FILE_OPS(fh_reg);
2054 DEBUGFS_READ_FILE_OPS(rx_queue);
2055 DEBUGFS_READ_FILE_OPS(tx_queue);
2056 DEBUGFS_WRITE_FILE_OPS(csr);
2057
2058 /*
2059  * Create the debugfs files and directories
2060  *
2061  */
2062 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2063                                          struct dentry *dir)
2064 {
2065         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2066         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2067         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2068         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2069         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2070         return 0;
2071
2072 err:
2073         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2074         return -ENOMEM;
2075 }
2076 #else
2077 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2078                                          struct dentry *dir)
2079 {
2080         return 0;
2081 }
2082 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2083
2084 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2085 {
2086         u32 cmdlen = 0;
2087         int i;
2088
2089         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2090                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2091
2092         return cmdlen;
2093 }
2094
2095 static const struct {
2096         u32 start, end;
2097 } iwl_prph_dump_addr[] = {
2098         { .start = 0x00a00000, .end = 0x00a00000 },
2099         { .start = 0x00a0000c, .end = 0x00a00024 },
2100         { .start = 0x00a0002c, .end = 0x00a0003c },
2101         { .start = 0x00a00410, .end = 0x00a00418 },
2102         { .start = 0x00a00420, .end = 0x00a00420 },
2103         { .start = 0x00a00428, .end = 0x00a00428 },
2104         { .start = 0x00a00430, .end = 0x00a0043c },
2105         { .start = 0x00a00444, .end = 0x00a00444 },
2106         { .start = 0x00a004c0, .end = 0x00a004cc },
2107         { .start = 0x00a004d8, .end = 0x00a004d8 },
2108         { .start = 0x00a004e0, .end = 0x00a004f0 },
2109         { .start = 0x00a00840, .end = 0x00a00840 },
2110         { .start = 0x00a00850, .end = 0x00a00858 },
2111         { .start = 0x00a01004, .end = 0x00a01008 },
2112         { .start = 0x00a01010, .end = 0x00a01010 },
2113         { .start = 0x00a01018, .end = 0x00a01018 },
2114         { .start = 0x00a01024, .end = 0x00a01024 },
2115         { .start = 0x00a0102c, .end = 0x00a01034 },
2116         { .start = 0x00a0103c, .end = 0x00a01040 },
2117         { .start = 0x00a01048, .end = 0x00a01094 },
2118         { .start = 0x00a01c00, .end = 0x00a01c20 },
2119         { .start = 0x00a01c58, .end = 0x00a01c58 },
2120         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2121         { .start = 0x00a01c28, .end = 0x00a01c54 },
2122         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2123         { .start = 0x00a01c60, .end = 0x00a01cdc },
2124         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2125         { .start = 0x00a01d18, .end = 0x00a01d20 },
2126         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2127         { .start = 0x00a01d40, .end = 0x00a01d5c },
2128         { .start = 0x00a01d80, .end = 0x00a01d80 },
2129         { .start = 0x00a01d98, .end = 0x00a01d9c },
2130         { .start = 0x00a01da8, .end = 0x00a01da8 },
2131         { .start = 0x00a01db8, .end = 0x00a01df4 },
2132         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2133         { .start = 0x00a01e00, .end = 0x00a01e2c },
2134         { .start = 0x00a01e40, .end = 0x00a01e60 },
2135         { .start = 0x00a01e68, .end = 0x00a01e6c },
2136         { .start = 0x00a01e74, .end = 0x00a01e74 },
2137         { .start = 0x00a01e84, .end = 0x00a01e90 },
2138         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2139         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2140         { .start = 0x00a01f00, .end = 0x00a01f1c },
2141         { .start = 0x00a01f44, .end = 0x00a01ffc },
2142         { .start = 0x00a02000, .end = 0x00a02048 },
2143         { .start = 0x00a02068, .end = 0x00a020f0 },
2144         { .start = 0x00a02100, .end = 0x00a02118 },
2145         { .start = 0x00a02140, .end = 0x00a0214c },
2146         { .start = 0x00a02168, .end = 0x00a0218c },
2147         { .start = 0x00a021c0, .end = 0x00a021c0 },
2148         { .start = 0x00a02400, .end = 0x00a02410 },
2149         { .start = 0x00a02418, .end = 0x00a02420 },
2150         { .start = 0x00a02428, .end = 0x00a0242c },
2151         { .start = 0x00a02434, .end = 0x00a02434 },
2152         { .start = 0x00a02440, .end = 0x00a02460 },
2153         { .start = 0x00a02468, .end = 0x00a024b0 },
2154         { .start = 0x00a024c8, .end = 0x00a024cc },
2155         { .start = 0x00a02500, .end = 0x00a02504 },
2156         { .start = 0x00a0250c, .end = 0x00a02510 },
2157         { .start = 0x00a02540, .end = 0x00a02554 },
2158         { .start = 0x00a02580, .end = 0x00a025f4 },
2159         { .start = 0x00a02600, .end = 0x00a0260c },
2160         { .start = 0x00a02648, .end = 0x00a02650 },
2161         { .start = 0x00a02680, .end = 0x00a02680 },
2162         { .start = 0x00a026c0, .end = 0x00a026d0 },
2163         { .start = 0x00a02700, .end = 0x00a0270c },
2164         { .start = 0x00a02804, .end = 0x00a02804 },
2165         { .start = 0x00a02818, .end = 0x00a0281c },
2166         { .start = 0x00a02c00, .end = 0x00a02db4 },
2167         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2168         { .start = 0x00a03000, .end = 0x00a03014 },
2169         { .start = 0x00a0301c, .end = 0x00a0302c },
2170         { .start = 0x00a03034, .end = 0x00a03038 },
2171         { .start = 0x00a03040, .end = 0x00a03048 },
2172         { .start = 0x00a03060, .end = 0x00a03068 },
2173         { .start = 0x00a03070, .end = 0x00a03074 },
2174         { .start = 0x00a0307c, .end = 0x00a0307c },
2175         { .start = 0x00a03080, .end = 0x00a03084 },
2176         { .start = 0x00a0308c, .end = 0x00a03090 },
2177         { .start = 0x00a03098, .end = 0x00a03098 },
2178         { .start = 0x00a030a0, .end = 0x00a030a0 },
2179         { .start = 0x00a030a8, .end = 0x00a030b4 },
2180         { .start = 0x00a030bc, .end = 0x00a030bc },
2181         { .start = 0x00a030c0, .end = 0x00a0312c },
2182         { .start = 0x00a03c00, .end = 0x00a03c5c },
2183         { .start = 0x00a04400, .end = 0x00a04454 },
2184         { .start = 0x00a04460, .end = 0x00a04474 },
2185         { .start = 0x00a044c0, .end = 0x00a044ec },
2186         { .start = 0x00a04500, .end = 0x00a04504 },
2187         { .start = 0x00a04510, .end = 0x00a04538 },
2188         { .start = 0x00a04540, .end = 0x00a04548 },
2189         { .start = 0x00a04560, .end = 0x00a0457c },
2190         { .start = 0x00a04590, .end = 0x00a04598 },
2191         { .start = 0x00a045c0, .end = 0x00a045f4 },
2192 };
2193
2194 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2195                                     struct iwl_fw_error_dump_data **data)
2196 {
2197         struct iwl_fw_error_dump_prph *prph;
2198         unsigned long flags;
2199         u32 prph_len = 0, i;
2200
2201         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2202                 return 0;
2203
2204         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2205                 /* The range includes both boundaries */
2206                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2207                          iwl_prph_dump_addr[i].start + 4;
2208                 int reg;
2209                 __le32 *val;
2210
2211                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2212
2213                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2214                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2215                                         num_bytes_in_chunk);
2216                 prph = (void *)(*data)->data;
2217                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2218                 val = (void *)prph->data;
2219
2220                 for (reg = iwl_prph_dump_addr[i].start;
2221                      reg <= iwl_prph_dump_addr[i].end;
2222                      reg += 4)
2223                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2224                                                                       reg));
2225                 *data = iwl_fw_error_next_data(*data);
2226         }
2227
2228         iwl_trans_release_nic_access(trans, &flags);
2229
2230         return prph_len;
2231 }
2232
2233 #define IWL_CSR_TO_DUMP (0x250)
2234
2235 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2236                                    struct iwl_fw_error_dump_data **data)
2237 {
2238         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2239         __le32 *val;
2240         int i;
2241
2242         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2243         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2244         val = (void *)(*data)->data;
2245
2246         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2247                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2248
2249         *data = iwl_fw_error_next_data(*data);
2250
2251         return csr_len;
2252 }
2253
2254 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2255                                        struct iwl_fw_error_dump_data **data)
2256 {
2257         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2258         unsigned long flags;
2259         __le32 *val;
2260         int i;
2261
2262         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2263                 return 0;
2264
2265         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2266         (*data)->len = cpu_to_le32(fh_regs_len);
2267         val = (void *)(*data)->data;
2268
2269         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2270                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2271
2272         iwl_trans_release_nic_access(trans, &flags);
2273
2274         *data = iwl_fw_error_next_data(*data);
2275
2276         return sizeof(**data) + fh_regs_len;
2277 }
2278
2279 static u32
2280 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2281                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2282                                  u32 monitor_len)
2283 {
2284         u32 buf_size_in_dwords = (monitor_len >> 2);
2285         u32 *buffer = (u32 *)fw_mon_data->data;
2286         unsigned long flags;
2287         u32 i;
2288
2289         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2290                 return 0;
2291
2292         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2293         for (i = 0; i < buf_size_in_dwords; i++)
2294                 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2295         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2296
2297         iwl_trans_release_nic_access(trans, &flags);
2298
2299         return monitor_len;
2300 }
2301
2302 static
2303 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2304 {
2305         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2306         struct iwl_fw_error_dump_data *data;
2307         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2308         struct iwl_fw_error_dump_txcmd *txcmd;
2309         struct iwl_trans_dump_data *dump_data;
2310         u32 len;
2311         u32 monitor_len;
2312         int i, ptr;
2313
2314         /* transport dump header */
2315         len = sizeof(*dump_data);
2316
2317         /* host commands */
2318         len += sizeof(*data) +
2319                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2320
2321         /* CSR registers */
2322         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2323
2324         /* PRPH registers */
2325         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2326                 /* The range includes both boundaries */
2327                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2328                         iwl_prph_dump_addr[i].start + 4;
2329
2330                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2331                         num_bytes_in_chunk;
2332         }
2333
2334         /* FH registers */
2335         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2336
2337         /* FW monitor */
2338         if (trans_pcie->fw_mon_page) {
2339                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2340                        trans_pcie->fw_mon_size;
2341                 monitor_len = trans_pcie->fw_mon_size;
2342         } else if (trans->dbg_dest_tlv) {
2343                 u32 base, end;
2344
2345                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2346                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2347
2348                 base = iwl_read_prph(trans, base) <<
2349                        trans->dbg_dest_tlv->base_shift;
2350                 end = iwl_read_prph(trans, end) <<
2351                       trans->dbg_dest_tlv->end_shift;
2352
2353                 /* Make "end" point to the actual end */
2354                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2355                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2356                         end += (1 << trans->dbg_dest_tlv->end_shift);
2357                 monitor_len = end - base;
2358                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2359                        monitor_len;
2360         } else {
2361                 monitor_len = 0;
2362         }
2363
2364         dump_data = vzalloc(len);
2365         if (!dump_data)
2366                 return NULL;
2367
2368         len = 0;
2369         data = (void *)dump_data->data;
2370         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2371         txcmd = (void *)data->data;
2372         spin_lock_bh(&cmdq->lock);
2373         ptr = cmdq->q.write_ptr;
2374         for (i = 0; i < cmdq->q.n_window; i++) {
2375                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2376                 u32 caplen, cmdlen;
2377
2378                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2379                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2380
2381                 if (cmdlen) {
2382                         len += sizeof(*txcmd) + caplen;
2383                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2384                         txcmd->caplen = cpu_to_le32(caplen);
2385                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2386                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2387                 }
2388
2389                 ptr = iwl_queue_dec_wrap(ptr);
2390         }
2391         spin_unlock_bh(&cmdq->lock);
2392
2393         data->len = cpu_to_le32(len);
2394         len += sizeof(*data);
2395         data = iwl_fw_error_next_data(data);
2396
2397         len += iwl_trans_pcie_dump_prph(trans, &data);
2398         len += iwl_trans_pcie_dump_csr(trans, &data);
2399         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2400         /* data is already pointing to the next section */
2401
2402         if ((trans_pcie->fw_mon_page &&
2403              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2404             trans->dbg_dest_tlv) {
2405                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2406                 u32 base, write_ptr, wrap_cnt;
2407
2408                 /* If there was a dest TLV - use the values from there */
2409                 if (trans->dbg_dest_tlv) {
2410                         write_ptr =
2411                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2412                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2413                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2414                 } else {
2415                         base = MON_BUFF_BASE_ADDR;
2416                         write_ptr = MON_BUFF_WRPTR;
2417                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2418                 }
2419
2420                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2421                 fw_mon_data = (void *)data->data;
2422                 fw_mon_data->fw_mon_wr_ptr =
2423                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2424                 fw_mon_data->fw_mon_cycle_cnt =
2425                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2426                 fw_mon_data->fw_mon_base_ptr =
2427                         cpu_to_le32(iwl_read_prph(trans, base));
2428
2429                 len += sizeof(*data) + sizeof(*fw_mon_data);
2430                 if (trans_pcie->fw_mon_page) {
2431                         /*
2432                          * The firmware is now asserted, it won't write anything
2433                          * to the buffer. CPU can take ownership to fetch the
2434                          * data. The buffer will be handed back to the device
2435                          * before the firmware will be restarted.
2436                          */
2437                         dma_sync_single_for_cpu(trans->dev,
2438                                                 trans_pcie->fw_mon_phys,
2439                                                 trans_pcie->fw_mon_size,
2440                                                 DMA_FROM_DEVICE);
2441                         memcpy(fw_mon_data->data,
2442                                page_address(trans_pcie->fw_mon_page),
2443                                trans_pcie->fw_mon_size);
2444
2445                         monitor_len = trans_pcie->fw_mon_size;
2446                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2447                         /*
2448                          * Update pointers to reflect actual values after
2449                          * shifting
2450                          */
2451                         base = iwl_read_prph(trans, base) <<
2452                                trans->dbg_dest_tlv->base_shift;
2453                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2454                                            monitor_len / sizeof(u32));
2455                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2456                         monitor_len =
2457                                 iwl_trans_pci_dump_marbh_monitor(trans,
2458                                                                  fw_mon_data,
2459                                                                  monitor_len);
2460                 } else {
2461                         /* Didn't match anything - output no monitor data */
2462                         monitor_len = 0;
2463                 }
2464
2465                 len += monitor_len;
2466                 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2467         }
2468
2469         dump_data->len = len;
2470
2471         return dump_data;
2472 }
2473
2474 static const struct iwl_trans_ops trans_ops_pcie = {
2475         .start_hw = iwl_trans_pcie_start_hw,
2476         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2477         .fw_alive = iwl_trans_pcie_fw_alive,
2478         .start_fw = iwl_trans_pcie_start_fw,
2479         .stop_device = iwl_trans_pcie_stop_device,
2480
2481         .d3_suspend = iwl_trans_pcie_d3_suspend,
2482         .d3_resume = iwl_trans_pcie_d3_resume,
2483
2484         .send_cmd = iwl_trans_pcie_send_hcmd,
2485
2486         .tx = iwl_trans_pcie_tx,
2487         .reclaim = iwl_trans_pcie_reclaim,
2488
2489         .txq_disable = iwl_trans_pcie_txq_disable,
2490         .txq_enable = iwl_trans_pcie_txq_enable,
2491
2492         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2493
2494         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2495         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2496
2497         .write8 = iwl_trans_pcie_write8,
2498         .write32 = iwl_trans_pcie_write32,
2499         .read32 = iwl_trans_pcie_read32,
2500         .read_prph = iwl_trans_pcie_read_prph,
2501         .write_prph = iwl_trans_pcie_write_prph,
2502         .read_mem = iwl_trans_pcie_read_mem,
2503         .write_mem = iwl_trans_pcie_write_mem,
2504         .configure = iwl_trans_pcie_configure,
2505         .set_pmi = iwl_trans_pcie_set_pmi,
2506         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2507         .release_nic_access = iwl_trans_pcie_release_nic_access,
2508         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2509
2510         .ref = iwl_trans_pcie_ref,
2511         .unref = iwl_trans_pcie_unref,
2512
2513         .dump_data = iwl_trans_pcie_dump_data,
2514 };
2515
2516 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2517                                        const struct pci_device_id *ent,
2518                                        const struct iwl_cfg *cfg)
2519 {
2520         struct iwl_trans_pcie *trans_pcie;
2521         struct iwl_trans *trans;
2522         u16 pci_cmd;
2523         int err;
2524
2525         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2526                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2527         if (!trans)
2528                 return ERR_PTR(-ENOMEM);
2529
2530         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2531
2532         trans_pcie->trans = trans;
2533         spin_lock_init(&trans_pcie->irq_lock);
2534         spin_lock_init(&trans_pcie->reg_lock);
2535         spin_lock_init(&trans_pcie->ref_lock);
2536         mutex_init(&trans_pcie->mutex);
2537         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2538
2539         err = pci_enable_device(pdev);
2540         if (err)
2541                 goto out_no_pci;
2542
2543         if (!cfg->base_params->pcie_l1_allowed) {
2544                 /*
2545                  * W/A - seems to solve weird behavior. We need to remove this
2546                  * if we don't want to stay in L1 all the time. This wastes a
2547                  * lot of power.
2548                  */
2549                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2550                                        PCIE_LINK_STATE_L1 |
2551                                        PCIE_LINK_STATE_CLKPM);
2552         }
2553
2554         pci_set_master(pdev);
2555
2556         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2557         if (!err)
2558                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2559         if (err) {
2560                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2561                 if (!err)
2562                         err = pci_set_consistent_dma_mask(pdev,
2563                                                           DMA_BIT_MASK(32));
2564                 /* both attempts failed: */
2565                 if (err) {
2566                         dev_err(&pdev->dev, "No suitable DMA available\n");
2567                         goto out_pci_disable_device;
2568                 }
2569         }
2570
2571         err = pci_request_regions(pdev, DRV_NAME);
2572         if (err) {
2573                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2574                 goto out_pci_disable_device;
2575         }
2576
2577         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2578         if (!trans_pcie->hw_base) {
2579                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2580                 err = -ENODEV;
2581                 goto out_pci_release_regions;
2582         }
2583
2584         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2585          * PCI Tx retries from interfering with C3 CPU state */
2586         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2587
2588         trans->dev = &pdev->dev;
2589         trans_pcie->pci_dev = pdev;
2590         iwl_disable_interrupts(trans);
2591
2592         err = pci_enable_msi(pdev);
2593         if (err) {
2594                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2595                 /* enable rfkill interrupt: hw bug w/a */
2596                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2597                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2598                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2599                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2600                 }
2601         }
2602
2603         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2604         /*
2605          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2606          * changed, and now the revision step also includes bit 0-1 (no more
2607          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2608          * in the old format.
2609          */
2610         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2611                 unsigned long flags;
2612                 int ret;
2613
2614                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2615                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2616
2617                 /*
2618                  * in-order to recognize C step driver should read chip version
2619                  * id located at the AUX bus MISC address space.
2620                  */
2621                 iwl_set_bit(trans, CSR_GP_CNTRL,
2622                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2623                 udelay(2);
2624
2625                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2626                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2627                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2628                                    25000);
2629                 if (ret < 0) {
2630                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2631                         goto out_pci_disable_msi;
2632                 }
2633
2634                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2635                         u32 hw_step;
2636
2637                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2638                         hw_step |= ENABLE_WFPM;
2639                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2640                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2641                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2642                         if (hw_step == 0x3)
2643                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2644                                                 (SILICON_C_STEP << 2);
2645                         iwl_trans_release_nic_access(trans, &flags);
2646                 }
2647         }
2648
2649         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2650         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2651                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2652
2653         /* Initialize the wait queue for commands */
2654         init_waitqueue_head(&trans_pcie->wait_command_queue);
2655
2656         if (iwl_pcie_alloc_ict(trans))
2657                 goto out_pci_disable_msi;
2658
2659         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2660                                    iwl_pcie_irq_handler,
2661                                    IRQF_SHARED, DRV_NAME, trans);
2662         if (err) {
2663                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2664                 goto out_free_ict;
2665         }
2666
2667         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2668         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2669
2670         return trans;
2671
2672 out_free_ict:
2673         iwl_pcie_free_ict(trans);
2674 out_pci_disable_msi:
2675         pci_disable_msi(pdev);
2676 out_pci_release_regions:
2677         pci_release_regions(pdev);
2678 out_pci_disable_device:
2679         pci_disable_device(pdev);
2680 out_no_pci:
2681         iwl_trans_free(trans);
2682         return ERR_PTR(err);
2683 }