drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  78 #include "dvm/commands.h"
  79
  80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  81         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  82         (~(1<<(trans_pcie)->cmd_queue)))
  83
  84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  85 {
  86         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                           rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                        PAGE_SIZE << trans_pcie->rx_page_order,
 133                                        DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      trans_pcie->rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (trans_pcie->rx_buf_size_8k)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwl_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                 struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                 struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 297 {
 298         struct iwl_tx_queue *txq = (void *)data;
 299         struct iwl_queue *q = &txq->q;
 300         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 301         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 302         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 303                 SCD_TX_STTS_MEM_LOWER_BOUND + (16 * txq->q.id);
 304         u8 buf[16];
 305         int i;
 306
 307         spin_lock(&txq->lock);
 308         /* check if triggered erroneously */
 309         if (txq->q.read_ptr == txq->q.write_ptr) {
 310                 spin_unlock(&txq->lock);
 311                 return;
 312         }
 313         spin_unlock(&txq->lock);
 314
 315         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 316                 jiffies_to_msecs(trans_pcie->wd_timeout));
 317         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 318                 txq->q.read_ptr, txq->q.write_ptr);
 319
 320         iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 321
 322         iwl_print_hex_error(trans, buf, sizeof(buf));
 323
 324         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 325                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 326                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 327
 328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 329                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 330                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 331                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 332                 u32 tbl_dw =
 333                         iwl_read_targ_mem(trans,
 334                                           trans_pcie->scd_base_addr +
 335                                           SCD_TRANS_TBL_OFFSET_QUEUE(i));
 336
 337                 if (i & 0x1)
 338                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 339                 else
 340                         tbl_dw = tbl_dw & 0x0000FFFF;
 341
 342                 IWL_ERR(trans,
 343                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 344                         i, active ? "" : "in", fifo, tbl_dw,
 345                         iwl_read_prph(trans,
 346                                       SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
 347                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 348         }
 349
 350         for (i = q->read_ptr; i != q->write_ptr;
 351              i = iwl_queue_inc_wrap(i, q->n_bd)) {
 352                 struct iwl_tx_cmd *tx_cmd =
 353                         (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
 354                 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
 355                         get_unaligned_le32(&tx_cmd->scratch));
 356         }
 357
 358         iwl_op_mode_nic_error(trans->op_mode);
 359 }
 360
 361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 362                                struct iwl_tx_queue *txq, int slots_num,
 363                                u32 txq_id)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 367         int i;
 368
 369         if (WARN_ON(txq->entries || txq->tfds))
 370                 return -EINVAL;
 371
 372         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 373                     (unsigned long)txq);
 374         txq->trans_pcie = trans_pcie;
 375
 376         txq->q.n_window = slots_num;
 377
 378         txq->entries = kcalloc(slots_num,
 379                                sizeof(struct iwl_pcie_tx_queue_entry),
 380                                GFP_KERNEL);
 381
 382         if (!txq->entries)
 383                 goto error;
 384
 385         if (txq_id == trans_pcie->cmd_queue)
 386                 for (i = 0; i < slots_num; i++) {
 387                         txq->entries[i].cmd =
 388                                 kmalloc(sizeof(struct iwl_device_cmd),
 389                                         GFP_KERNEL);
 390                         if (!txq->entries[i].cmd)
 391                                 goto error;
 392                 }
 393
 394         /* Circular buffer of transmit frame descriptors (TFDs),
 395          * shared with device */
 396         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 397                                        &txq->q.dma_addr, GFP_KERNEL);
 398         if (!txq->tfds) {
 399                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 400                 goto error;
 401         }
 402         txq->q.id = txq_id;
 403
 404         return 0;
 405 error:
 406         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 407                 for (i = 0; i < slots_num; i++)
 408                         kfree(txq->entries[i].cmd);
 409         kfree(txq->entries);
 410         txq->entries = NULL;
 411
 412         return -ENOMEM;
 413
 414 }
 415
 416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 417                               int slots_num, u32 txq_id)
 418 {
 419         int ret;
 420
 421         txq->need_update = 0;
 422
 423         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 424          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 425         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 426
 427         /* Initialize queue's high/low-water marks, and head/tail indexes */
 428         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 429                         txq_id);
 430         if (ret)
 431                 return ret;
 432
 433         spin_lock_init(&txq->lock);
 434
 435         /*
 436          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 437          * given Tx queue, and enable the DMA channel used for that queue.
 438          * Circular buffer (TFD queue in DRAM) physical base address */
 439         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 440                              txq->q.dma_addr >> 8);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 447  */
 448 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 449 {
 450         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 451         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 452         struct iwl_queue *q = &txq->q;
 453         enum dma_data_direction dma_dir;
 454
 455         if (!q->n_bd)
 456                 return;
 457
 458         /* In the command queue, all the TBs are mapped as BIDI
 459          * so unmap them as such.
 460          */
 461         if (txq_id == trans_pcie->cmd_queue)
 462                 dma_dir = DMA_BIDIRECTIONAL;
 463         else
 464                 dma_dir = DMA_TO_DEVICE;
 465
 466         spin_lock_bh(&txq->lock);
 467         while (q->write_ptr != q->read_ptr) {
 468                 iwl_txq_free_tfd(trans, txq, dma_dir);
 469                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 470         }
 471         spin_unlock_bh(&txq->lock);
 472 }
 473
 474 /**
 475  * iwl_tx_queue_free - Deallocate DMA queue.
 476  * @txq: Transmit queue to deallocate.
 477  *
 478  * Empty queue by removing and destroying all BD's.
 479  * Free all buffers.
 480  * 0-fill, but do not free "txq" descriptor structure.
 481  */
 482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 483 {
 484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 485         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 486         struct device *dev = trans->dev;
 487         int i;
 488
 489         if (WARN_ON(!txq))
 490                 return;
 491
 492         iwl_tx_queue_unmap(trans, txq_id);
 493
 494         /* De-alloc array of command/tx buffers */
 495         if (txq_id == trans_pcie->cmd_queue)
 496                 for (i = 0; i < txq->q.n_window; i++) {
 497                         kfree(txq->entries[i].cmd);
 498                         kfree(txq->entries[i].copy_cmd);
 499                 }
 500
 501         /* De-alloc circular buffer of TFDs */
 502         if (txq->q.n_bd) {
 503                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 504                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 505                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 506         }
 507
 508         kfree(txq->entries);
 509         txq->entries = NULL;
 510
 511         del_timer_sync(&txq->stuck_timer);
 512
 513         /* 0-fill queue descriptor structure */
 514         memset(txq, 0, sizeof(*txq));
 515 }
 516
 517 /**
 518  * iwl_trans_tx_free - Free TXQ Context
 519  *
 520  * Destroy all TX DMA queues and structures
 521  */
 522 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 523 {
 524         int txq_id;
 525         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 526
 527         /* Tx queues */
 528         if (trans_pcie->txq) {
 529                 for (txq_id = 0;
 530                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 531                         iwl_tx_queue_free(trans, txq_id);
 532         }
 533
 534         kfree(trans_pcie->txq);
 535         trans_pcie->txq = NULL;
 536
 537         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 538
 539         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 540 }
 541
 542 /**
 543  * iwl_trans_tx_alloc - allocate TX context
 544  * Allocate all Tx DMA structures and initialize them
 545  *
 546  * @param priv
 547  * @return error code
 548  */
 549 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 550 {
 551         int ret;
 552         int txq_id, slots_num;
 553         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 554
 555         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 556                         sizeof(struct iwlagn_scd_bc_tbl);
 557
 558         /*It is not allowed to alloc twice, so warn when this happens.
 559          * We cannot rely on the previous allocation, so free and fail */
 560         if (WARN_ON(trans_pcie->txq)) {
 561                 ret = -EINVAL;
 562                 goto error;
 563         }
 564
 565         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 566                                    scd_bc_tbls_size);
 567         if (ret) {
 568                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 569                 goto error;
 570         }
 571
 572         /* Alloc keep-warm buffer */
 573         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 574         if (ret) {
 575                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 576                 goto error;
 577         }
 578
 579         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 580                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 581         if (!trans_pcie->txq) {
 582                 IWL_ERR(trans, "Not enough memory for txq\n");
 583                 ret = ENOMEM;
 584                 goto error;
 585         }
 586
 587         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 588         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 589              txq_id++) {
 590                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 591                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 592                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 593                                           slots_num, txq_id);
 594                 if (ret) {
 595                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 596                         goto error;
 597                 }
 598         }
 599
 600         return 0;
 601
 602 error:
 603         iwl_trans_pcie_tx_free(trans);
 604
 605         return ret;
 606 }
 607 static int iwl_tx_init(struct iwl_trans *trans)
 608 {
 609         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 610         int ret;
 611         int txq_id, slots_num;
 612         unsigned long flags;
 613         bool alloc = false;
 614
 615         if (!trans_pcie->txq) {
 616                 ret = iwl_trans_tx_alloc(trans);
 617                 if (ret)
 618                         goto error;
 619                 alloc = true;
 620         }
 621
 622         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 623
 624         /* Turn off all Tx DMA fifos */
 625         iwl_write_prph(trans, SCD_TXFACT, 0);
 626
 627         /* Tell NIC where to find the "keep warm" buffer */
 628         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 629                            trans_pcie->kw.dma >> 4);
 630
 631         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 632
 633         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 634         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 635              txq_id++) {
 636                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 637                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 638                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 639                                          slots_num, txq_id);
 640                 if (ret) {
 641                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 642                         goto error;
 643                 }
 644         }
 645
 646         return 0;
 647 error:
 648         /*Upon error, free only if we allocated something */
 649         if (alloc)
 650                 iwl_trans_pcie_tx_free(trans);
 651         return ret;
 652 }
 653
 654 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 655 {
 656 /*
 657  * (for documentation purposes)
 658  * to set power to V_AUX, do:
 659
 660                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 661                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 662                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 663                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 664  */
 665
 666         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 667                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 668                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 669 }
 670
 671 /* PCI registers */
 672 #define PCI_CFG_RETRY_TIMEOUT   0x041
 673 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 674 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 675
 676 static void iwl_apm_config(struct iwl_trans *trans)
 677 {
 678         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 679         u16 lctl;
 680
 681         /*
 682          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 683          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 684          * If so (likely), disable L0S, so device moves directly L0->L1;
 685          *    costs negligible amount of power savings.
 686          * If not (unlikely), enable L0S, so there is at least some
 687          *    power savings, even without L1.
 688          */
 689
 690         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 691         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 692                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 693                 /* L1-ASPM enabled; disable(!) L0S */
 694                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 695                 dev_printk(KERN_INFO, trans->dev,
 696                            "L1 Enabled; Disabling L0S\n");
 697         } else {
 698                 /* L1-ASPM disabled; enable(!) L0S */
 699                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 700                 dev_printk(KERN_INFO, trans->dev,
 701                            "L1 Disabled; Enabling L0S\n");
 702         }
 703         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 704 }
 705
 706 /*
 707  * Start up NIC's basic functionality after it has been reset
 708  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 709  * NOTE:  This does not load uCode nor start the embedded processor
 710  */
 711 static int iwl_apm_init(struct iwl_trans *trans)
 712 {
 713         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 714         int ret = 0;
 715         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 716
 717         /*
 718          * Use "set_bit" below rather than "write", to preserve any hardware
 719          * bits already set by default after reset.
 720          */
 721
 722         /* Disable L0S exit timer (platform NMI Work/Around) */
 723         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 724                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 725
 726         /*
 727          * Disable L0s without affecting L1;
 728          *  don't wait for ICH L0s (ICH bug W/A)
 729          */
 730         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 731                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 732
 733         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 734         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 735
 736         /*
 737          * Enable HAP INTA (interrupt from management bus) to
 738          * wake device's PCI Express link L1a -> L0s
 739          */
 740         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 741                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 742
 743         iwl_apm_config(trans);
 744
 745         /* Configure analog phase-lock-loop before activating to D0A */
 746         if (trans->cfg->base_params->pll_cfg_val)
 747                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 748                             trans->cfg->base_params->pll_cfg_val);
 749
 750         /*
 751          * Set "initialization complete" bit to move adapter from
 752          * D0U* --> D0A* (powered-up active) state.
 753          */
 754         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 755
 756         /*
 757          * Wait for clock stabilization; once stabilized, access to
 758          * device-internal resources is supported, e.g. iwl_write_prph()
 759          * and accesses to uCode SRAM.
 760          */
 761         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 762                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 763                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 764         if (ret < 0) {
 765                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 766                 goto out;
 767         }
 768
 769         /*
 770          * Enable DMA clock and wait for it to stabilize.
 771          *
 772          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 773          * do not disable clocks.  This preserves any hardware bits already
 774          * set by default in "CLK_CTRL_REG" after reset.
 775          */
 776         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 777         udelay(20);
 778
 779         /* Disable L1-Active */
 780         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 781                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 782
 783         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 784
 785 out:
 786         return ret;
 787 }
 788
 789 static int iwl_apm_stop_master(struct iwl_trans *trans)
 790 {
 791         int ret = 0;
 792
 793         /* stop device's busmaster DMA activity */
 794         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 795
 796         ret = iwl_poll_bit(trans, CSR_RESET,
 797                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 798                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 799         if (ret)
 800                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 801
 802         IWL_DEBUG_INFO(trans, "stop master\n");
 803
 804         return ret;
 805 }
 806
 807 static void iwl_apm_stop(struct iwl_trans *trans)
 808 {
 809         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 810         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 811
 812         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 813
 814         /* Stop device's DMA activity */
 815         iwl_apm_stop_master(trans);
 816
 817         /* Reset the entire device */
 818         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 819
 820         udelay(10);
 821
 822         /*
 823          * Clear "initialization complete" bit to move adapter from
 824          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 825          */
 826         iwl_clear_bit(trans, CSR_GP_CNTRL,
 827                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 828 }
 829
 830 static int iwl_nic_init(struct iwl_trans *trans)
 831 {
 832         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 833         unsigned long flags;
 834
 835         /* nic_init */
 836         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 837         iwl_apm_init(trans);
 838
 839         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 840         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 841
 842         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 843
 844         iwl_set_pwr_vmain(trans);
 845
 846         iwl_op_mode_nic_config(trans->op_mode);
 847
 848         /* Allocate the RX queue, or reset if it is already allocated */
 849         iwl_rx_init(trans);
 850
 851         /* Allocate or reset and init all Tx and Command queues */
 852         if (iwl_tx_init(trans))
 853                 return -ENOMEM;
 854
 855         if (trans->cfg->base_params->shadow_reg_enable) {
 856                 /* enable shadow regs in HW */
 857                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 858                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 859         }
 860
 861         return 0;
 862 }
 863
 864 #define HW_READY_TIMEOUT (50)
 865
 866 /* Note: returns poll_bit return value, which is >= 0 if success */
 867 static int iwl_set_hw_ready(struct iwl_trans *trans)
 868 {
 869         int ret;
 870
 871         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 872                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 873
 874         /* See if we got it */
 875         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 876                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 877                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 878                            HW_READY_TIMEOUT);
 879
 880         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 881         return ret;
 882 }
 883
 884 /* Note: returns standard 0/-ERROR code */
 885 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 886 {
 887         int ret;
 888         int t = 0;
 889
 890         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 891
 892         ret = iwl_set_hw_ready(trans);
 893         /* If the card is ready, exit 0 */
 894         if (ret >= 0)
 895                 return 0;
 896
 897         /* If HW is not ready, prepare the conditions to check again */
 898         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 899                     CSR_HW_IF_CONFIG_REG_PREPARE);
 900
 901         do {
 902                 ret = iwl_set_hw_ready(trans);
 903                 if (ret >= 0)
 904                         return 0;
 905
 906                 usleep_range(200, 1000);
 907                 t += 200;
 908         } while (t < 150000);
 909
 910         return ret;
 911 }
 912
 913 /*
 914  * ucode
 915  */
 916 static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 917                                    dma_addr_t phy_addr, u32 byte_cnt)
 918 {
 919         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 920         int ret;
 921
 922         trans_pcie->ucode_write_complete = false;
 923
 924         iwl_write_direct32(trans,
 925                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 926                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 927
 928         iwl_write_direct32(trans,
 929                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 930                            dst_addr);
 931
 932         iwl_write_direct32(trans,
 933                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 934                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 935
 936         iwl_write_direct32(trans,
 937                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 938                            (iwl_get_dma_hi_addr(phy_addr)
 939                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 940
 941         iwl_write_direct32(trans,
 942                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 943                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 944                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 945                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 946
 947         iwl_write_direct32(trans,
 948                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 949                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 950                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 951                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 952
 953         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 954                                  trans_pcie->ucode_write_complete, 5 * HZ);
 955         if (!ret) {
 956                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 957                 return -ETIMEDOUT;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 964                             const struct fw_desc *section)
 965 {
 966         u8 *v_addr;
 967         dma_addr_t p_addr;
 968         u32 offset;
 969         int ret = 0;
 970
 971         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 972                      section_num);
 973
 974         v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
 975         if (!v_addr)
 976                 return -ENOMEM;
 977
 978         for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
 979                 u32 copy_size;
 980
 981                 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
 982
 983                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 984                 ret = iwl_load_firmware_chunk(trans, section->offset + offset,
 985                                               p_addr, copy_size);
 986                 if (ret) {
 987                         IWL_ERR(trans,
 988                                 "Could not load the [%d] uCode section\n",
 989                                 section_num);
 990                         break;
 991                 }
 992         }
 993
 994         dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
 995         return ret;
 996 }
 997
 998 static int iwl_load_given_ucode(struct iwl_trans *trans,
 999                                 const struct fw_img *image)
1000 {
1001         int i, ret = 0;
1002
1003         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1004                 if (!image->sec[i].data)
1005                         break;
1006
1007                 ret = iwl_load_section(trans, i, &image->sec[i]);
1008                 if (ret)
1009                         return ret;
1010         }
1011
1012         /* Remove all resets to allow NIC to operate */
1013         iwl_write32(trans, CSR_RESET, 0);
1014
1015         return 0;
1016 }
1017
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1019                                    const struct fw_img *fw)
1020 {
1021         int ret;
1022         bool hw_rfkill;
1023
1024         /* This may fail if AMT took ownership of the device */
1025         if (iwl_prepare_card_hw(trans)) {
1026                 IWL_WARN(trans, "Exit HW not ready\n");
1027                 return -EIO;
1028         }
1029
1030         iwl_enable_rfkill_int(trans);
1031
1032         /* If platform's RF_KILL switch is NOT set to KILL */
1033         hw_rfkill = iwl_is_rfkill_set(trans);
1034         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1035         if (hw_rfkill)
1036                 return -ERFKILL;
1037
1038         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1039
1040         ret = iwl_nic_init(trans);
1041         if (ret) {
1042                 IWL_ERR(trans, "Unable to init nic\n");
1043                 return ret;
1044         }
1045
1046         /* make sure rfkill handshake bits are cleared */
1047         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1048         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1049                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1050
1051         /* clear (again), then enable host interrupts */
1052         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1053         iwl_enable_interrupts(trans);
1054
1055         /* really make sure rfkill handshake bits are cleared */
1056         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1057         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1058
1059         /* Load the given image to the HW */
1060         return iwl_load_given_ucode(trans, fw);
1061 }
1062
1063 /*
1064  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1065  */
1066 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1067 {
1068         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1069                 IWL_TRANS_GET_PCIE_TRANS(trans);
1070
1071         iwl_write_prph(trans, SCD_TXFACT, mask);
1072 }
1073
1074 static void iwl_tx_start(struct iwl_trans *trans)
1075 {
1076         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1077         u32 a;
1078         int chan;
1079         u32 reg_val;
1080
1081         /* make sure all queue are not stopped/used */
1082         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1083         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1084
1085         trans_pcie->scd_base_addr =
1086                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1087         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1088         /* reset conext data memory */
1089         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1090                 a += 4)
1091                 iwl_write_targ_mem(trans, a, 0);
1092         /* reset tx status memory */
1093         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1094                 a += 4)
1095                 iwl_write_targ_mem(trans, a, 0);
1096         for (; a < trans_pcie->scd_base_addr +
1097                SCD_TRANS_TBL_OFFSET_QUEUE(
1098                                 trans->cfg->base_params->num_of_queues);
1099                a += 4)
1100                 iwl_write_targ_mem(trans, a, 0);
1101
1102         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1103                        trans_pcie->scd_bc_tbls.dma >> 10);
1104
1105         /* The chain extension of the SCD doesn't work well. This feature is
1106          * enabled by default by the HW, so we need to disable it manually.
1107          */
1108         iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1109
1110         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1111                                 trans_pcie->cmd_fifo);
1112
1113         /* Activate all Tx DMA/FIFO channels */
1114         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1115
1116         /* Enable DMA channel */
1117         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1118                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1119                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1120                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1121
1122         /* Update FH chicken bits */
1123         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1124         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1125                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1126
1127         /* Enable L1-Active */
1128         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1129                             APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1130 }
1131
1132 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1133 {
1134         iwl_reset_ict(trans);
1135         iwl_tx_start(trans);
1136 }
1137
1138 /**
1139  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1140  */
1141 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1142 {
1143         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1144         int ch, txq_id, ret;
1145         unsigned long flags;
1146
1147         /* Turn off all Tx DMA fifos */
1148         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1149
1150         iwl_trans_txq_set_sched(trans, 0);
1151
1152         /* Stop each Tx DMA channel, and wait for it to be idle */
1153         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1154                 iwl_write_direct32(trans,
1155                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1156                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1157                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1158                 if (ret < 0)
1159                         IWL_ERR(trans,
1160                                 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1161                                 ch,
1162                                 iwl_read_direct32(trans,
1163                                                   FH_TSSR_TX_STATUS_REG));
1164         }
1165         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1166
1167         if (!trans_pcie->txq) {
1168                 IWL_WARN(trans,
1169                          "Stopping tx queues that aren't allocated...\n");
1170                 return 0;
1171         }
1172
1173         /* Unmap DMA from host system and free skb's */
1174         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1175              txq_id++)
1176                 iwl_tx_queue_unmap(trans, txq_id);
1177
1178         return 0;
1179 }
1180
1181 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1182 {
1183         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1184         unsigned long flags;
1185
1186         /* tell the device to stop sending interrupts */
1187         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1188         iwl_disable_interrupts(trans);
1189         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1190
1191         /* device going down, Stop using ICT table */
1192         iwl_disable_ict(trans);
1193
1194         /*
1195          * If a HW restart happens during firmware loading,
1196          * then the firmware loading might call this function
1197          * and later it might be called again due to the
1198          * restart. So don't process again if the device is
1199          * already dead.
1200          */
1201         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1202                 iwl_trans_tx_stop(trans);
1203                 iwl_trans_rx_stop(trans);
1204
1205                 /* Power-down device's busmaster DMA clocks */
1206                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1207                                APMG_CLK_VAL_DMA_CLK_RQT);
1208                 udelay(5);
1209         }
1210
1211         /* Make sure (redundant) we've released our request to stay awake */
1212         iwl_clear_bit(trans, CSR_GP_CNTRL,
1213                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1214
1215         /* Stop the device, and put it in low power state */
1216         iwl_apm_stop(trans);
1217
1218         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1219          * Clean again the interrupt here
1220          */
1221         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1222         iwl_disable_interrupts(trans);
1223         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1224
1225         iwl_enable_rfkill_int(trans);
1226
1227         /* wait to make sure we flush pending tasklet*/
1228         synchronize_irq(trans_pcie->irq);
1229         tasklet_kill(&trans_pcie->irq_tasklet);
1230
1231         cancel_work_sync(&trans_pcie->rx_replenish);
1232
1233         /* stop and reset the on-board processor */
1234         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1235
1236         /* clear all status bits */
1237         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1238         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1239         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1240         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1241 }
1242
1243 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1244 {
1245         /* let the ucode operate on its own */
1246         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1247                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1248
1249         iwl_disable_interrupts(trans);
1250         iwl_clear_bit(trans, CSR_GP_CNTRL,
1251                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1252 }
1253
1254 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1255                              struct iwl_device_cmd *dev_cmd, int txq_id)
1256 {
1257         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1258         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1259         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1260         struct iwl_cmd_meta *out_meta;
1261         struct iwl_tx_queue *txq;
1262         struct iwl_queue *q;
1263         dma_addr_t phys_addr = 0;
1264         dma_addr_t txcmd_phys;
1265         dma_addr_t scratch_phys;
1266         u16 len, firstlen, secondlen;
1267         u8 wait_write_ptr = 0;
1268         __le16 fc = hdr->frame_control;
1269         u8 hdr_len = ieee80211_hdrlen(fc);
1270         u16 __maybe_unused wifi_seq;
1271
1272         txq = &trans_pcie->txq[txq_id];
1273         q = &txq->q;
1274
1275         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1276                 WARN_ON_ONCE(1);
1277                 return -EINVAL;
1278         }
1279
1280         spin_lock(&txq->lock);
1281
1282         /* In AGG mode, the index in the ring must correspond to the WiFi
1283          * sequence number. This is a HW requirements to help the SCD to parse
1284          * the BA.
1285          * Check here that the packets are in the right place on the ring.
1286          */
1287 #ifdef CONFIG_IWLWIFI_DEBUG
1288         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1289         WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1290                   ((wifi_seq & 0xff) != q->write_ptr),
1291                   "Q: %d WiFi Seq %d tfdNum %d",
1292                   txq_id, wifi_seq, q->write_ptr);
1293 #endif
1294
1295         /* Set up driver data for this TFD */
1296         txq->entries[q->write_ptr].skb = skb;
1297         txq->entries[q->write_ptr].cmd = dev_cmd;
1298
1299         dev_cmd->hdr.cmd = REPLY_TX;
1300         dev_cmd->hdr.sequence =
1301                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1302                             INDEX_TO_SEQ(q->write_ptr)));
1303
1304         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1305         out_meta = &txq->entries[q->write_ptr].meta;
1306
1307         /*
1308          * Use the first empty entry in this queue's command buffer array
1309          * to contain the Tx command and MAC header concatenated together
1310          * (payload data will be in another buffer).
1311          * Size of this varies, due to varying MAC header length.
1312          * If end is not dword aligned, we'll have 2 extra bytes at the end
1313          * of the MAC header (device reads on dword boundaries).
1314          * We'll tell device about this padding later.
1315          */
1316         len = sizeof(struct iwl_tx_cmd) +
1317                 sizeof(struct iwl_cmd_header) + hdr_len;
1318         firstlen = (len + 3) & ~3;
1319
1320         /* Tell NIC about any 2-byte padding after MAC header */
1321         if (firstlen != len)
1322                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1323
1324         /* Physical address of this Tx command's header (not MAC header!),
1325          * within command buffer array. */
1326         txcmd_phys = dma_map_single(trans->dev,
1327                                     &dev_cmd->hdr, firstlen,
1328                                     DMA_BIDIRECTIONAL);
1329         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1330                 goto out_err;
1331         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1332         dma_unmap_len_set(out_meta, len, firstlen);
1333
1334         if (!ieee80211_has_morefrags(fc)) {
1335                 txq->need_update = 1;
1336         } else {
1337                 wait_write_ptr = 1;
1338                 txq->need_update = 0;
1339         }
1340
1341         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1342          * if any (802.11 null frames have no payload). */
1343         secondlen = skb->len - hdr_len;
1344         if (secondlen > 0) {
1345                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1346                                            secondlen, DMA_TO_DEVICE);
1347                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1348                         dma_unmap_single(trans->dev,
1349                                          dma_unmap_addr(out_meta, mapping),
1350                                          dma_unmap_len(out_meta, len),
1351                                          DMA_BIDIRECTIONAL);
1352                         goto out_err;
1353                 }
1354         }
1355
1356         /* Attach buffers to TFD */
1357         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1358         if (secondlen > 0)
1359                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1360                                              secondlen, 0);
1361
1362         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1363                                 offsetof(struct iwl_tx_cmd, scratch);
1364
1365         /* take back ownership of DMA buffer to enable update */
1366         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1367                                 DMA_BIDIRECTIONAL);
1368         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1369         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1370
1371         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1372                      le16_to_cpu(dev_cmd->hdr.sequence));
1373         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1374
1375         /* Set up entry for this TFD in Tx byte-count array */
1376         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1377
1378         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1379                                    DMA_BIDIRECTIONAL);
1380
1381         trace_iwlwifi_dev_tx(trans->dev,
1382                              &txq->tfds[txq->q.write_ptr],
1383                              sizeof(struct iwl_tfd),
1384                              &dev_cmd->hdr, firstlen,
1385                              skb->data + hdr_len, secondlen);
1386
1387         /* start timer if queue currently empty */
1388         if (txq->need_update && q->read_ptr == q->write_ptr &&
1389             trans_pcie->wd_timeout)
1390                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1391
1392         /* Tell device the write index *just past* this latest filled TFD */
1393         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1394         iwl_txq_update_write_ptr(trans, txq);
1395
1396         /*
1397          * At this point the frame is "transmitted" successfully
1398          * and we will get a TX status notification eventually,
1399          * regardless of the value of ret. "ret" only indicates
1400          * whether or not we should update the write pointer.
1401          */
1402         if (iwl_queue_space(q) < q->high_mark) {
1403                 if (wait_write_ptr) {
1404                         txq->need_update = 1;
1405                         iwl_txq_update_write_ptr(trans, txq);
1406                 } else {
1407                         iwl_stop_queue(trans, txq);
1408                 }
1409         }
1410         spin_unlock(&txq->lock);
1411         return 0;
1412  out_err:
1413         spin_unlock(&txq->lock);
1414         return -1;
1415 }
1416
1417 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1418 {
1419         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1420         int err;
1421         bool hw_rfkill;
1422
1423         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1424
1425         if (!trans_pcie->irq_requested) {
1426                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1427                         iwl_irq_tasklet, (unsigned long)trans);
1428
1429                 iwl_alloc_isr_ict(trans);
1430
1431                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1432                                   DRV_NAME, trans);
1433                 if (err) {
1434                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1435                                 trans_pcie->irq);
1436                         goto error;
1437                 }
1438
1439                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1440                 trans_pcie->irq_requested = true;
1441         }
1442
1443         err = iwl_prepare_card_hw(trans);
1444         if (err) {
1445                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1446                 goto err_free_irq;
1447         }
1448
1449         iwl_apm_init(trans);
1450
1451         /* From now on, the op_mode will be kept updated about RF kill state */
1452         iwl_enable_rfkill_int(trans);
1453
1454         hw_rfkill = iwl_is_rfkill_set(trans);
1455         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1456
1457         return err;
1458
1459 err_free_irq:
1460         trans_pcie->irq_requested = false;
1461         free_irq(trans_pcie->irq, trans);
1462 error:
1463         iwl_free_isr_ict(trans);
1464         tasklet_kill(&trans_pcie->irq_tasklet);
1465         return err;
1466 }
1467
1468 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1469                                    bool op_mode_leaving)
1470 {
1471         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472         bool hw_rfkill;
1473         unsigned long flags;
1474
1475         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1476         iwl_disable_interrupts(trans);
1477         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1478
1479         iwl_apm_stop(trans);
1480
1481         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1482         iwl_disable_interrupts(trans);
1483         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1484
1485         if (!op_mode_leaving) {
1486                 /*
1487                  * Even if we stop the HW, we still want the RF kill
1488                  * interrupt
1489                  */
1490                 iwl_enable_rfkill_int(trans);
1491
1492                 /*
1493                  * Check again since the RF kill state may have changed while
1494                  * all the interrupts were disabled, in this case we couldn't
1495                  * receive the RF kill interrupt and update the state in the
1496                  * op_mode.
1497                  */
1498                 hw_rfkill = iwl_is_rfkill_set(trans);
1499                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1500         }
1501 }
1502
1503 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1504                                    struct sk_buff_head *skbs)
1505 {
1506         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1507         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1508         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1509         int tfd_num = ssn & (txq->q.n_bd - 1);
1510         int freed = 0;
1511
1512         spin_lock(&txq->lock);
1513
1514         if (txq->q.read_ptr != tfd_num) {
1515                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1516                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1517                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1518                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1519                         iwl_wake_queue(trans, txq);
1520         }
1521
1522         spin_unlock(&txq->lock);
1523 }
1524
1525 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1526 {
1527         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1528 }
1529
1530 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1531 {
1532         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1533 }
1534
1535 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1536 {
1537         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1538 }
1539
1540 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1541                                      const struct iwl_trans_config *trans_cfg)
1542 {
1543         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1544
1545         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1546         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1547         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1548                 trans_pcie->n_no_reclaim_cmds = 0;
1549         else
1550                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1551         if (trans_pcie->n_no_reclaim_cmds)
1552                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1553                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1554
1555         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1556         if (trans_pcie->rx_buf_size_8k)
1557                 trans_pcie->rx_page_order = get_order(8 * 1024);
1558         else
1559                 trans_pcie->rx_page_order = get_order(4 * 1024);
1560
1561         trans_pcie->wd_timeout =
1562                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1563
1564         trans_pcie->command_names = trans_cfg->command_names;
1565 }
1566
1567 void iwl_trans_pcie_free(struct iwl_trans *trans)
1568 {
1569         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1570
1571         iwl_trans_pcie_tx_free(trans);
1572         iwl_trans_pcie_rx_free(trans);
1573
1574         if (trans_pcie->irq_requested == true) {
1575                 free_irq(trans_pcie->irq, trans);
1576                 iwl_free_isr_ict(trans);
1577         }
1578
1579         pci_disable_msi(trans_pcie->pci_dev);
1580         iounmap(trans_pcie->hw_base);
1581         pci_release_regions(trans_pcie->pci_dev);
1582         pci_disable_device(trans_pcie->pci_dev);
1583         kmem_cache_destroy(trans->dev_cmd_pool);
1584
1585         kfree(trans);
1586 }
1587
1588 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1589 {
1590         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1591
1592         if (state)
1593                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1594         else
1595                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1596 }
1597
1598 #ifdef CONFIG_PM_SLEEP
1599 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1600 {
1601         return 0;
1602 }
1603
1604 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1605 {
1606         bool hw_rfkill;
1607
1608         iwl_enable_rfkill_int(trans);
1609
1610         hw_rfkill = iwl_is_rfkill_set(trans);
1611         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1612
1613         if (!hw_rfkill)
1614                 iwl_enable_interrupts(trans);
1615
1616         return 0;
1617 }
1618 #endif /* CONFIG_PM_SLEEP */
1619
1620 #define IWL_FLUSH_WAIT_MS       2000
1621
1622 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1623 {
1624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1625         struct iwl_tx_queue *txq;
1626         struct iwl_queue *q;
1627         int cnt;
1628         unsigned long now = jiffies;
1629         int ret = 0;
1630
1631         /* waiting for all the tx frames complete might take a while */
1632         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1633                 if (cnt == trans_pcie->cmd_queue)
1634                         continue;
1635                 txq = &trans_pcie->txq[cnt];
1636                 q = &txq->q;
1637                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1638                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1639                         msleep(1);
1640
1641                 if (q->read_ptr != q->write_ptr) {
1642                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1643                         ret = -ETIMEDOUT;
1644                         break;
1645                 }
1646         }
1647         return ret;
1648 }
1649
1650 static const char *get_fh_string(int cmd)
1651 {
1652 #define IWL_CMD(x) case x: return #x
1653         switch (cmd) {
1654         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1655         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1656         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1657         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1658         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1659         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1660         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1661         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1662         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1663         default:
1664                 return "UNKNOWN";
1665         }
1666 #undef IWL_CMD
1667 }
1668
1669 int iwl_dump_fh(struct iwl_trans *trans, char **buf)
1670 {
1671         int i;
1672         static const u32 fh_tbl[] = {
1673                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1674                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1675                 FH_RSCSR_CHNL0_WPTR,
1676                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1677                 FH_MEM_RSSR_SHARED_CTRL_REG,
1678                 FH_MEM_RSSR_RX_STATUS_REG,
1679                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1680                 FH_TSSR_TX_STATUS_REG,
1681                 FH_TSSR_TX_ERROR_REG
1682         };
1683
1684 #ifdef CONFIG_IWLWIFI_DEBUGFS
1685         if (buf) {
1686                 int pos = 0;
1687                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1688
1689                 *buf = kmalloc(bufsz, GFP_KERNEL);
1690                 if (!*buf)
1691                         return -ENOMEM;
1692
1693                 pos += scnprintf(*buf + pos, bufsz - pos,
1694                                 "FH register values:\n");
1695
1696                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1697                         pos += scnprintf(*buf + pos, bufsz - pos,
1698                                 "  %34s: 0X%08x\n",
1699                                 get_fh_string(fh_tbl[i]),
1700                                 iwl_read_direct32(trans, fh_tbl[i]));
1701
1702                 return pos;
1703         }
1704 #endif
1705
1706         IWL_ERR(trans, "FH register values:\n");
1707         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1708                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1709                         get_fh_string(fh_tbl[i]),
1710                         iwl_read_direct32(trans, fh_tbl[i]));
1711
1712         return 0;
1713 }
1714
1715 static const char *get_csr_string(int cmd)
1716 {
1717 #define IWL_CMD(x) case x: return #x
1718         switch (cmd) {
1719         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1720         IWL_CMD(CSR_INT_COALESCING);
1721         IWL_CMD(CSR_INT);
1722         IWL_CMD(CSR_INT_MASK);
1723         IWL_CMD(CSR_FH_INT_STATUS);
1724         IWL_CMD(CSR_GPIO_IN);
1725         IWL_CMD(CSR_RESET);
1726         IWL_CMD(CSR_GP_CNTRL);
1727         IWL_CMD(CSR_HW_REV);
1728         IWL_CMD(CSR_EEPROM_REG);
1729         IWL_CMD(CSR_EEPROM_GP);
1730         IWL_CMD(CSR_OTP_GP_REG);
1731         IWL_CMD(CSR_GIO_REG);
1732         IWL_CMD(CSR_GP_UCODE_REG);
1733         IWL_CMD(CSR_GP_DRIVER_REG);
1734         IWL_CMD(CSR_UCODE_DRV_GP1);
1735         IWL_CMD(CSR_UCODE_DRV_GP2);
1736         IWL_CMD(CSR_LED_REG);
1737         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1738         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1739         IWL_CMD(CSR_ANA_PLL_CFG);
1740         IWL_CMD(CSR_HW_REV_WA_REG);
1741         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1742         default:
1743                 return "UNKNOWN";
1744         }
1745 #undef IWL_CMD
1746 }
1747
1748 void iwl_dump_csr(struct iwl_trans *trans)
1749 {
1750         int i;
1751         static const u32 csr_tbl[] = {
1752                 CSR_HW_IF_CONFIG_REG,
1753                 CSR_INT_COALESCING,
1754                 CSR_INT,
1755                 CSR_INT_MASK,
1756                 CSR_FH_INT_STATUS,
1757                 CSR_GPIO_IN,
1758                 CSR_RESET,
1759                 CSR_GP_CNTRL,
1760                 CSR_HW_REV,
1761                 CSR_EEPROM_REG,
1762                 CSR_EEPROM_GP,
1763                 CSR_OTP_GP_REG,
1764                 CSR_GIO_REG,
1765                 CSR_GP_UCODE_REG,
1766                 CSR_GP_DRIVER_REG,
1767                 CSR_UCODE_DRV_GP1,
1768                 CSR_UCODE_DRV_GP2,
1769                 CSR_LED_REG,
1770                 CSR_DRAM_INT_TBL_REG,
1771                 CSR_GIO_CHICKEN_BITS,
1772                 CSR_ANA_PLL_CFG,
1773                 CSR_HW_REV_WA_REG,
1774                 CSR_DBG_HPET_MEM_REG
1775         };
1776         IWL_ERR(trans, "CSR values:\n");
1777         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1778                 "CSR_INT_PERIODIC_REG)\n");
1779         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1780                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1781                         get_csr_string(csr_tbl[i]),
1782                         iwl_read32(trans, csr_tbl[i]));
1783         }
1784 }
1785
1786 #ifdef CONFIG_IWLWIFI_DEBUGFS
1787 /* create and remove of files */
1788 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1789         if (!debugfs_create_file(#name, mode, parent, trans,            \
1790                                  &iwl_dbgfs_##name##_ops))              \
1791                 goto err;                                               \
1792 } while (0)
1793
1794 /* file operation */
1795 #define DEBUGFS_READ_FUNC(name)                                         \
1796 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1797                                         char __user *user_buf,          \
1798                                         size_t count, loff_t *ppos);
1799
1800 #define DEBUGFS_WRITE_FUNC(name)                                        \
1801 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1802                                         const char __user *user_buf,    \
1803                                         size_t count, loff_t *ppos);
1804
1805
1806 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1807         DEBUGFS_READ_FUNC(name);                                        \
1808 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1809         .read = iwl_dbgfs_##name##_read,                                \
1810         .open = simple_open,                                            \
1811         .llseek = generic_file_llseek,                                  \
1812 };
1813
1814 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1815         DEBUGFS_WRITE_FUNC(name);                                       \
1816 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1817         .write = iwl_dbgfs_##name##_write,                              \
1818         .open = simple_open,                                            \
1819         .llseek = generic_file_llseek,                                  \
1820 };
1821
1822 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1823         DEBUGFS_READ_FUNC(name);                                        \
1824         DEBUGFS_WRITE_FUNC(name);                                       \
1825 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1826         .write = iwl_dbgfs_##name##_write,                              \
1827         .read = iwl_dbgfs_##name##_read,                                \
1828         .open = simple_open,                                            \
1829         .llseek = generic_file_llseek,                                  \
1830 };
1831
1832 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1833                                        char __user *user_buf,
1834                                        size_t count, loff_t *ppos)
1835 {
1836         struct iwl_trans *trans = file->private_data;
1837         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1838         struct iwl_tx_queue *txq;
1839         struct iwl_queue *q;
1840         char *buf;
1841         int pos = 0;
1842         int cnt;
1843         int ret;
1844         size_t bufsz;
1845
1846         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1847
1848         if (!trans_pcie->txq)
1849                 return -EAGAIN;
1850
1851         buf = kzalloc(bufsz, GFP_KERNEL);
1852         if (!buf)
1853                 return -ENOMEM;
1854
1855         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1856                 txq = &trans_pcie->txq[cnt];
1857                 q = &txq->q;
1858                 pos += scnprintf(buf + pos, bufsz - pos,
1859                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1860                                 cnt, q->read_ptr, q->write_ptr,
1861                                 !!test_bit(cnt, trans_pcie->queue_used),
1862                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1863         }
1864         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1865         kfree(buf);
1866         return ret;
1867 }
1868
1869 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1870                                        char __user *user_buf,
1871                                        size_t count, loff_t *ppos)
1872 {
1873         struct iwl_trans *trans = file->private_data;
1874         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1875         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1876         char buf[256];
1877         int pos = 0;
1878         const size_t bufsz = sizeof(buf);
1879
1880         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1881                                                 rxq->read);
1882         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1883                                                 rxq->write);
1884         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1885                                                 rxq->free_count);
1886         if (rxq->rb_stts) {
1887                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1888                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1889         } else {
1890                 pos += scnprintf(buf + pos, bufsz - pos,
1891                                         "closed_rb_num: Not Allocated\n");
1892         }
1893         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1894 }
1895
1896 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1897                                         char __user *user_buf,
1898                                         size_t count, loff_t *ppos)
1899 {
1900         struct iwl_trans *trans = file->private_data;
1901         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1902         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1903
1904         int pos = 0;
1905         char *buf;
1906         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1907         ssize_t ret;
1908
1909         buf = kzalloc(bufsz, GFP_KERNEL);
1910         if (!buf)
1911                 return -ENOMEM;
1912
1913         pos += scnprintf(buf + pos, bufsz - pos,
1914                         "Interrupt Statistics Report:\n");
1915
1916         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1917                 isr_stats->hw);
1918         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1919                 isr_stats->sw);
1920         if (isr_stats->sw || isr_stats->hw) {
1921                 pos += scnprintf(buf + pos, bufsz - pos,
1922                         "\tLast Restarting Code:  0x%X\n",
1923                         isr_stats->err_code);
1924         }
1925 #ifdef CONFIG_IWLWIFI_DEBUG
1926         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1927                 isr_stats->sch);
1928         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1929                 isr_stats->alive);
1930 #endif
1931         pos += scnprintf(buf + pos, bufsz - pos,
1932                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1933
1934         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1935                 isr_stats->ctkill);
1936
1937         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1938                 isr_stats->wakeup);
1939
1940         pos += scnprintf(buf + pos, bufsz - pos,
1941                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1942
1943         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1944                 isr_stats->tx);
1945
1946         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1947                 isr_stats->unhandled);
1948
1949         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1950         kfree(buf);
1951         return ret;
1952 }
1953
1954 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1955                                          const char __user *user_buf,
1956                                          size_t count, loff_t *ppos)
1957 {
1958         struct iwl_trans *trans = file->private_data;
1959         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1960         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1961
1962         char buf[8];
1963         int buf_size;
1964         u32 reset_flag;
1965
1966         memset(buf, 0, sizeof(buf));
1967         buf_size = min(count, sizeof(buf) -  1);
1968         if (copy_from_user(buf, user_buf, buf_size))
1969                 return -EFAULT;
1970         if (sscanf(buf, "%x", &reset_flag) != 1)
1971                 return -EFAULT;
1972         if (reset_flag == 0)
1973                 memset(isr_stats, 0, sizeof(*isr_stats));
1974
1975         return count;
1976 }
1977
1978 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1979                                    const char __user *user_buf,
1980                                    size_t count, loff_t *ppos)
1981 {
1982         struct iwl_trans *trans = file->private_data;
1983         char buf[8];
1984         int buf_size;
1985         int csr;
1986
1987         memset(buf, 0, sizeof(buf));
1988         buf_size = min(count, sizeof(buf) -  1);
1989         if (copy_from_user(buf, user_buf, buf_size))
1990                 return -EFAULT;
1991         if (sscanf(buf, "%d", &csr) != 1)
1992                 return -EFAULT;
1993
1994         iwl_dump_csr(trans);
1995
1996         return count;
1997 }
1998
1999 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2000                                      char __user *user_buf,
2001                                      size_t count, loff_t *ppos)
2002 {
2003         struct iwl_trans *trans = file->private_data;
2004         char *buf = NULL;
2005         int pos = 0;
2006         ssize_t ret = -EFAULT;
2007
2008         ret = pos = iwl_dump_fh(trans, &buf);
2009         if (buf) {
2010                 ret = simple_read_from_buffer(user_buf,
2011                                               count, ppos, buf, pos);
2012                 kfree(buf);
2013         }
2014
2015         return ret;
2016 }
2017
2018 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2019                                           const char __user *user_buf,
2020                                           size_t count, loff_t *ppos)
2021 {
2022         struct iwl_trans *trans = file->private_data;
2023
2024         if (!trans->op_mode)
2025                 return -EAGAIN;
2026
2027         local_bh_disable();
2028         iwl_op_mode_nic_error(trans->op_mode);
2029         local_bh_enable();
2030
2031         return count;
2032 }
2033
2034 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2035 DEBUGFS_READ_FILE_OPS(fh_reg);
2036 DEBUGFS_READ_FILE_OPS(rx_queue);
2037 DEBUGFS_READ_FILE_OPS(tx_queue);
2038 DEBUGFS_WRITE_FILE_OPS(csr);
2039 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2040
2041 /*
2042  * Create the debugfs files and directories
2043  *
2044  */
2045 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2046                                          struct dentry *dir)
2047 {
2048         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2049         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2050         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2051         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2052         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2053         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2054         return 0;
2055
2056 err:
2057         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2058         return -ENOMEM;
2059 }
2060 #else
2061 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2062                                          struct dentry *dir)
2063 {
2064         return 0;
2065 }
2066 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2067
2068 static const struct iwl_trans_ops trans_ops_pcie = {
2069         .start_hw = iwl_trans_pcie_start_hw,
2070         .stop_hw = iwl_trans_pcie_stop_hw,
2071         .fw_alive = iwl_trans_pcie_fw_alive,
2072         .start_fw = iwl_trans_pcie_start_fw,
2073         .stop_device = iwl_trans_pcie_stop_device,
2074
2075         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2076
2077         .send_cmd = iwl_trans_pcie_send_cmd,
2078
2079         .tx = iwl_trans_pcie_tx,
2080         .reclaim = iwl_trans_pcie_reclaim,
2081
2082         .txq_disable = iwl_trans_pcie_txq_disable,
2083         .txq_enable = iwl_trans_pcie_txq_enable,
2084
2085         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2086
2087         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2088
2089 #ifdef CONFIG_PM_SLEEP
2090         .suspend = iwl_trans_pcie_suspend,
2091         .resume = iwl_trans_pcie_resume,
2092 #endif
2093         .write8 = iwl_trans_pcie_write8,
2094         .write32 = iwl_trans_pcie_write32,
2095         .read32 = iwl_trans_pcie_read32,
2096         .configure = iwl_trans_pcie_configure,
2097         .set_pmi = iwl_trans_pcie_set_pmi,
2098 };
2099
2100 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2101                                        const struct pci_device_id *ent,
2102                                        const struct iwl_cfg *cfg)
2103 {
2104         struct iwl_trans_pcie *trans_pcie;
2105         struct iwl_trans *trans;
2106         u16 pci_cmd;
2107         int err;
2108
2109         trans = kzalloc(sizeof(struct iwl_trans) +
2110                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2111
2112         if (WARN_ON(!trans))
2113                 return NULL;
2114
2115         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2116
2117         trans->ops = &trans_ops_pcie;
2118         trans->cfg = cfg;
2119         trans_pcie->trans = trans;
2120         spin_lock_init(&trans_pcie->irq_lock);
2121         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2122
2123         /* W/A - seems to solve weird behavior. We need to remove this if we
2124          * don't want to stay in L1 all the time. This wastes a lot of power */
2125         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2126                                PCIE_LINK_STATE_CLKPM);
2127
2128         if (pci_enable_device(pdev)) {
2129                 err = -ENODEV;
2130                 goto out_no_pci;
2131         }
2132
2133         pci_set_master(pdev);
2134
2135         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2136         if (!err)
2137                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2138         if (err) {
2139                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2140                 if (!err)
2141                         err = pci_set_consistent_dma_mask(pdev,
2142                                                           DMA_BIT_MASK(32));
2143                 /* both attempts failed: */
2144                 if (err) {
2145                         dev_printk(KERN_ERR, &pdev->dev,
2146                                    "No suitable DMA available.\n");
2147                         goto out_pci_disable_device;
2148                 }
2149         }
2150
2151         err = pci_request_regions(pdev, DRV_NAME);
2152         if (err) {
2153                 dev_printk(KERN_ERR, &pdev->dev,
2154                            "pci_request_regions failed\n");
2155                 goto out_pci_disable_device;
2156         }
2157
2158         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2159         if (!trans_pcie->hw_base) {
2160                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2161                 err = -ENODEV;
2162                 goto out_pci_release_regions;
2163         }
2164
2165         dev_printk(KERN_INFO, &pdev->dev,
2166                    "pci_resource_len = 0x%08llx\n",
2167                    (unsigned long long) pci_resource_len(pdev, 0));
2168         dev_printk(KERN_INFO, &pdev->dev,
2169                    "pci_resource_base = %p\n", trans_pcie->hw_base);
2170
2171         dev_printk(KERN_INFO, &pdev->dev,
2172                    "HW Revision ID = 0x%X\n", pdev->revision);
2173
2174         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2175          * PCI Tx retries from interfering with C3 CPU state */
2176         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2177
2178         err = pci_enable_msi(pdev);
2179         if (err)
2180                 dev_printk(KERN_ERR, &pdev->dev,
2181                            "pci_enable_msi failed(0X%x)\n", err);
2182
2183         trans->dev = &pdev->dev;
2184         trans_pcie->irq = pdev->irq;
2185         trans_pcie->pci_dev = pdev;
2186         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2187         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2188         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2189                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2190
2191         /* TODO: Move this away, not needed if not MSI */
2192         /* enable rfkill interrupt: hw bug w/a */
2193         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2194         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2195                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2196                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2197         }
2198
2199         /* Initialize the wait queue for commands */
2200         init_waitqueue_head(&trans->wait_command_queue);
2201         spin_lock_init(&trans->reg_lock);
2202
2203         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2204                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2205
2206         trans->dev_cmd_headroom = 0;
2207         trans->dev_cmd_pool =
2208                 kmem_cache_create(trans->dev_cmd_pool_name,
2209                                   sizeof(struct iwl_device_cmd)
2210                                   + trans->dev_cmd_headroom,
2211                                   sizeof(void *),
2212                                   SLAB_HWCACHE_ALIGN,
2213                                   NULL);
2214
2215         if (!trans->dev_cmd_pool)
2216                 goto out_pci_disable_msi;
2217
2218         return trans;
2219
2220 out_pci_disable_msi:
2221         pci_disable_msi(pdev);
2222 out_pci_release_regions:
2223         pci_release_regions(pdev);
2224 out_pci_disable_device:
2225         pci_disable_device(pdev);
2226 out_no_pci:
2227         kfree(trans);
2228         return NULL;
2229 }