drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
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  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  78 #include "dvm/commands.h"
  79
  80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  81         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  82         (~(1<<(trans_pcie)->cmd_queue)))
  83
  84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  85 {
  86         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                           rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                        PAGE_SIZE << trans_pcie->rx_page_order,
 133                                        DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      trans_pcie->rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (trans_pcie->rx_buf_size_8k)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwlagn_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                 struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                 struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 297 {
 298         struct iwl_tx_queue *txq = (void *)data;
 299         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 300         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 301
 302         spin_lock(&txq->lock);
 303         /* check if triggered erroneously */
 304         if (txq->q.read_ptr == txq->q.write_ptr) {
 305                 spin_unlock(&txq->lock);
 306                 return;
 307         }
 308         spin_unlock(&txq->lock);
 309
 310
 311         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 312                 jiffies_to_msecs(trans_pcie->wd_timeout));
 313         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 314                 txq->q.read_ptr, txq->q.write_ptr);
 315         IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
 316                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
 317                                         & (TFD_QUEUE_SIZE_MAX - 1),
 318                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
 319
 320         iwl_op_mode_nic_error(trans->op_mode);
 321 }
 322
 323 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 324                                struct iwl_tx_queue *txq, int slots_num,
 325                                u32 txq_id)
 326 {
 327         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 328         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 329         int i;
 330
 331         if (WARN_ON(txq->entries || txq->tfds))
 332                 return -EINVAL;
 333
 334         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 335                     (unsigned long)txq);
 336         txq->trans_pcie = trans_pcie;
 337
 338         txq->q.n_window = slots_num;
 339
 340         txq->entries = kcalloc(slots_num,
 341                                sizeof(struct iwl_pcie_tx_queue_entry),
 342                                GFP_KERNEL);
 343
 344         if (!txq->entries)
 345                 goto error;
 346
 347         if (txq_id == trans_pcie->cmd_queue)
 348                 for (i = 0; i < slots_num; i++) {
 349                         txq->entries[i].cmd =
 350                                 kmalloc(sizeof(struct iwl_device_cmd),
 351                                         GFP_KERNEL);
 352                         if (!txq->entries[i].cmd)
 353                                 goto error;
 354                 }
 355
 356         /* Circular buffer of transmit frame descriptors (TFDs),
 357          * shared with device */
 358         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 359                                        &txq->q.dma_addr, GFP_KERNEL);
 360         if (!txq->tfds) {
 361                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 362                 goto error;
 363         }
 364         txq->q.id = txq_id;
 365
 366         return 0;
 367 error:
 368         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 369                 for (i = 0; i < slots_num; i++)
 370                         kfree(txq->entries[i].cmd);
 371         kfree(txq->entries);
 372         txq->entries = NULL;
 373
 374         return -ENOMEM;
 375
 376 }
 377
 378 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 379                               int slots_num, u32 txq_id)
 380 {
 381         int ret;
 382
 383         txq->need_update = 0;
 384
 385         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 386          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 387         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 388
 389         /* Initialize queue's high/low-water marks, and head/tail indexes */
 390         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 391                         txq_id);
 392         if (ret)
 393                 return ret;
 394
 395         spin_lock_init(&txq->lock);
 396
 397         /*
 398          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 399          * given Tx queue, and enable the DMA channel used for that queue.
 400          * Circular buffer (TFD queue in DRAM) physical base address */
 401         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 402                              txq->q.dma_addr >> 8);
 403
 404         return 0;
 405 }
 406
 407 /**
 408  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 409  */
 410 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 411 {
 412         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 413         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 414         struct iwl_queue *q = &txq->q;
 415         enum dma_data_direction dma_dir;
 416
 417         if (!q->n_bd)
 418                 return;
 419
 420         /* In the command queue, all the TBs are mapped as BIDI
 421          * so unmap them as such.
 422          */
 423         if (txq_id == trans_pcie->cmd_queue)
 424                 dma_dir = DMA_BIDIRECTIONAL;
 425         else
 426                 dma_dir = DMA_TO_DEVICE;
 427
 428         spin_lock_bh(&txq->lock);
 429         while (q->write_ptr != q->read_ptr) {
 430                 iwl_txq_free_tfd(trans, txq, dma_dir);
 431                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 432         }
 433         spin_unlock_bh(&txq->lock);
 434 }
 435
 436 /**
 437  * iwl_tx_queue_free - Deallocate DMA queue.
 438  * @txq: Transmit queue to deallocate.
 439  *
 440  * Empty queue by removing and destroying all BD's.
 441  * Free all buffers.
 442  * 0-fill, but do not free "txq" descriptor structure.
 443  */
 444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 448         struct device *dev = trans->dev;
 449         int i;
 450
 451         if (WARN_ON(!txq))
 452                 return;
 453
 454         iwl_tx_queue_unmap(trans, txq_id);
 455
 456         /* De-alloc array of command/tx buffers */
 457
 458         if (txq_id == trans_pcie->cmd_queue)
 459                 for (i = 0; i < txq->q.n_window; i++)
 460                         kfree(txq->entries[i].cmd);
 461
 462         /* De-alloc circular buffer of TFDs */
 463         if (txq->q.n_bd) {
 464                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 465                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 466                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 467         }
 468
 469         kfree(txq->entries);
 470         txq->entries = NULL;
 471
 472         del_timer_sync(&txq->stuck_timer);
 473
 474         /* 0-fill queue descriptor structure */
 475         memset(txq, 0, sizeof(*txq));
 476 }
 477
 478 /**
 479  * iwl_trans_tx_free - Free TXQ Context
 480  *
 481  * Destroy all TX DMA queues and structures
 482  */
 483 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 484 {
 485         int txq_id;
 486         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 487
 488         /* Tx queues */
 489         if (trans_pcie->txq) {
 490                 for (txq_id = 0;
 491                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 492                         iwl_tx_queue_free(trans, txq_id);
 493         }
 494
 495         kfree(trans_pcie->txq);
 496         trans_pcie->txq = NULL;
 497
 498         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 499
 500         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 501 }
 502
 503 /**
 504  * iwl_trans_tx_alloc - allocate TX context
 505  * Allocate all Tx DMA structures and initialize them
 506  *
 507  * @param priv
 508  * @return error code
 509  */
 510 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 511 {
 512         int ret;
 513         int txq_id, slots_num;
 514         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 515
 516         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 517                         sizeof(struct iwlagn_scd_bc_tbl);
 518
 519         /*It is not allowed to alloc twice, so warn when this happens.
 520          * We cannot rely on the previous allocation, so free and fail */
 521         if (WARN_ON(trans_pcie->txq)) {
 522                 ret = -EINVAL;
 523                 goto error;
 524         }
 525
 526         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 527                                    scd_bc_tbls_size);
 528         if (ret) {
 529                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 530                 goto error;
 531         }
 532
 533         /* Alloc keep-warm buffer */
 534         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 535         if (ret) {
 536                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 537                 goto error;
 538         }
 539
 540         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 541                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 542         if (!trans_pcie->txq) {
 543                 IWL_ERR(trans, "Not enough memory for txq\n");
 544                 ret = ENOMEM;
 545                 goto error;
 546         }
 547
 548         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 549         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 550              txq_id++) {
 551                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 552                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 553                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 554                                           slots_num, txq_id);
 555                 if (ret) {
 556                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 557                         goto error;
 558                 }
 559         }
 560
 561         return 0;
 562
 563 error:
 564         iwl_trans_pcie_tx_free(trans);
 565
 566         return ret;
 567 }
 568 static int iwl_tx_init(struct iwl_trans *trans)
 569 {
 570         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 571         int ret;
 572         int txq_id, slots_num;
 573         unsigned long flags;
 574         bool alloc = false;
 575
 576         if (!trans_pcie->txq) {
 577                 ret = iwl_trans_tx_alloc(trans);
 578                 if (ret)
 579                         goto error;
 580                 alloc = true;
 581         }
 582
 583         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 584
 585         /* Turn off all Tx DMA fifos */
 586         iwl_write_prph(trans, SCD_TXFACT, 0);
 587
 588         /* Tell NIC where to find the "keep warm" buffer */
 589         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 590                            trans_pcie->kw.dma >> 4);
 591
 592         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 593
 594         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 595         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 596              txq_id++) {
 597                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 598                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 599                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 600                                          slots_num, txq_id);
 601                 if (ret) {
 602                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 603                         goto error;
 604                 }
 605         }
 606
 607         return 0;
 608 error:
 609         /*Upon error, free only if we allocated something */
 610         if (alloc)
 611                 iwl_trans_pcie_tx_free(trans);
 612         return ret;
 613 }
 614
 615 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 616 {
 617 /*
 618  * (for documentation purposes)
 619  * to set power to V_AUX, do:
 620
 621                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 622                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 623                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 624                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 625  */
 626
 627         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 628                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 629                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 630 }
 631
 632 /* PCI registers */
 633 #define PCI_CFG_RETRY_TIMEOUT   0x041
 634 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 635 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 636
 637 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 638 {
 639         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 640         int pos;
 641         u16 pci_lnk_ctl;
 642
 643         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 644
 645         pos = pci_pcie_cap(pci_dev);
 646         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 647         return pci_lnk_ctl;
 648 }
 649
 650 static void iwl_apm_config(struct iwl_trans *trans)
 651 {
 652         /*
 653          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 654          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 655          * If so (likely), disable L0S, so device moves directly L0->L1;
 656          *    costs negligible amount of power savings.
 657          * If not (unlikely), enable L0S, so there is at least some
 658          *    power savings, even without L1.
 659          */
 660         u16 lctl = iwl_pciexp_link_ctrl(trans);
 661
 662         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 663                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 664                 /* L1-ASPM enabled; disable(!) L0S */
 665                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 666                 dev_printk(KERN_INFO, trans->dev,
 667                            "L1 Enabled; Disabling L0S\n");
 668         } else {
 669                 /* L1-ASPM disabled; enable(!) L0S */
 670                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 671                 dev_printk(KERN_INFO, trans->dev,
 672                            "L1 Disabled; Enabling L0S\n");
 673         }
 674         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 675 }
 676
 677 /*
 678  * Start up NIC's basic functionality after it has been reset
 679  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 680  * NOTE:  This does not load uCode nor start the embedded processor
 681  */
 682 static int iwl_apm_init(struct iwl_trans *trans)
 683 {
 684         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 685         int ret = 0;
 686         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 687
 688         /*
 689          * Use "set_bit" below rather than "write", to preserve any hardware
 690          * bits already set by default after reset.
 691          */
 692
 693         /* Disable L0S exit timer (platform NMI Work/Around) */
 694         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 695                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 696
 697         /*
 698          * Disable L0s without affecting L1;
 699          *  don't wait for ICH L0s (ICH bug W/A)
 700          */
 701         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 702                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 703
 704         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 705         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 706
 707         /*
 708          * Enable HAP INTA (interrupt from management bus) to
 709          * wake device's PCI Express link L1a -> L0s
 710          */
 711         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 712                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 713
 714         iwl_apm_config(trans);
 715
 716         /* Configure analog phase-lock-loop before activating to D0A */
 717         if (trans->cfg->base_params->pll_cfg_val)
 718                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 719                             trans->cfg->base_params->pll_cfg_val);
 720
 721         /*
 722          * Set "initialization complete" bit to move adapter from
 723          * D0U* --> D0A* (powered-up active) state.
 724          */
 725         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 726
 727         /*
 728          * Wait for clock stabilization; once stabilized, access to
 729          * device-internal resources is supported, e.g. iwl_write_prph()
 730          * and accesses to uCode SRAM.
 731          */
 732         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 733                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 734                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 735         if (ret < 0) {
 736                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 737                 goto out;
 738         }
 739
 740         /*
 741          * Enable DMA clock and wait for it to stabilize.
 742          *
 743          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 744          * do not disable clocks.  This preserves any hardware bits already
 745          * set by default in "CLK_CTRL_REG" after reset.
 746          */
 747         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 748         udelay(20);
 749
 750         /* Disable L1-Active */
 751         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 752                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 753
 754         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 755
 756 out:
 757         return ret;
 758 }
 759
 760 static int iwl_apm_stop_master(struct iwl_trans *trans)
 761 {
 762         int ret = 0;
 763
 764         /* stop device's busmaster DMA activity */
 765         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 766
 767         ret = iwl_poll_bit(trans, CSR_RESET,
 768                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 769                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 770         if (ret)
 771                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 772
 773         IWL_DEBUG_INFO(trans, "stop master\n");
 774
 775         return ret;
 776 }
 777
 778 static void iwl_apm_stop(struct iwl_trans *trans)
 779 {
 780         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 781         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 782
 783         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 784
 785         /* Stop device's DMA activity */
 786         iwl_apm_stop_master(trans);
 787
 788         /* Reset the entire device */
 789         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 790
 791         udelay(10);
 792
 793         /*
 794          * Clear "initialization complete" bit to move adapter from
 795          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 796          */
 797         iwl_clear_bit(trans, CSR_GP_CNTRL,
 798                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 799 }
 800
 801 static int iwl_nic_init(struct iwl_trans *trans)
 802 {
 803         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 804         unsigned long flags;
 805
 806         /* nic_init */
 807         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 808         iwl_apm_init(trans);
 809
 810         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 811         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 812
 813         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 814
 815         iwl_set_pwr_vmain(trans);
 816
 817         iwl_op_mode_nic_config(trans->op_mode);
 818
 819 #ifndef CONFIG_IWLWIFI_IDI
 820         /* Allocate the RX queue, or reset if it is already allocated */
 821         iwl_rx_init(trans);
 822 #endif
 823
 824         /* Allocate or reset and init all Tx and Command queues */
 825         if (iwl_tx_init(trans))
 826                 return -ENOMEM;
 827
 828         if (trans->cfg->base_params->shadow_reg_enable) {
 829                 /* enable shadow regs in HW */
 830                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 831                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 832         }
 833
 834         return 0;
 835 }
 836
 837 #define HW_READY_TIMEOUT (50)
 838
 839 /* Note: returns poll_bit return value, which is >= 0 if success */
 840 static int iwl_set_hw_ready(struct iwl_trans *trans)
 841 {
 842         int ret;
 843
 844         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 845                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 846
 847         /* See if we got it */
 848         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 849                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 850                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 851                            HW_READY_TIMEOUT);
 852
 853         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 854         return ret;
 855 }
 856
 857 /* Note: returns standard 0/-ERROR code */
 858 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 859 {
 860         int ret;
 861
 862         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 863
 864         ret = iwl_set_hw_ready(trans);
 865         /* If the card is ready, exit 0 */
 866         if (ret >= 0)
 867                 return 0;
 868
 869         /* If HW is not ready, prepare the conditions to check again */
 870         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 871                     CSR_HW_IF_CONFIG_REG_PREPARE);
 872
 873         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 874                            ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 875                            CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 876
 877         if (ret < 0)
 878                 return ret;
 879
 880         /* HW should be ready by now, check again. */
 881         ret = iwl_set_hw_ready(trans);
 882         if (ret >= 0)
 883                 return 0;
 884         return ret;
 885 }
 886
 887 /*
 888  * ucode
 889  */
 890 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 891                             const struct fw_desc *section)
 892 {
 893         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 894         dma_addr_t phy_addr = section->p_addr;
 895         u32 byte_cnt = section->len;
 896         u32 dst_addr = section->offset;
 897         int ret;
 898
 899         trans_pcie->ucode_write_complete = false;
 900
 901         iwl_write_direct32(trans,
 902                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 903                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 904
 905         iwl_write_direct32(trans,
 906                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 907                            dst_addr);
 908
 909         iwl_write_direct32(trans,
 910                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 911                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 912
 913         iwl_write_direct32(trans,
 914                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 915                            (iwl_get_dma_hi_addr(phy_addr)
 916                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 917
 918         iwl_write_direct32(trans,
 919                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 920                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 921                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 922                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 923
 924         iwl_write_direct32(trans,
 925                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 926                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 927                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 928                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 929
 930         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 931                      section_num);
 932         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 933                                  trans_pcie->ucode_write_complete, 5 * HZ);
 934         if (!ret) {
 935                 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
 936                         section_num);
 937                 return -ETIMEDOUT;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int iwl_load_given_ucode(struct iwl_trans *trans,
 944                                 const struct fw_img *image)
 945 {
 946         int ret = 0;
 947                 int i;
 948
 949                 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 950                         if (!image->sec[i].p_addr)
 951                                 break;
 952
 953                         ret = iwl_load_section(trans, i, &image->sec[i]);
 954                         if (ret)
 955                                 return ret;
 956                 }
 957
 958         /* Remove all resets to allow NIC to operate */
 959         iwl_write32(trans, CSR_RESET, 0);
 960
 961         return 0;
 962 }
 963
 964 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 965                                    const struct fw_img *fw)
 966 {
 967         int ret;
 968         bool hw_rfkill;
 969
 970         /* This may fail if AMT took ownership of the device */
 971         if (iwl_prepare_card_hw(trans)) {
 972                 IWL_WARN(trans, "Exit HW not ready\n");
 973                 return -EIO;
 974         }
 975
 976         iwl_enable_rfkill_int(trans);
 977
 978         /* If platform's RF_KILL switch is NOT set to KILL */
 979         hw_rfkill = iwl_is_rfkill_set(trans);
 980         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 981         if (hw_rfkill)
 982                 return -ERFKILL;
 983
 984         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 985
 986         ret = iwl_nic_init(trans);
 987         if (ret) {
 988                 IWL_ERR(trans, "Unable to init nic\n");
 989                 return ret;
 990         }
 991
 992         /* make sure rfkill handshake bits are cleared */
 993         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 994         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 995                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 996
 997         /* clear (again), then enable host interrupts */
 998         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 999         iwl_enable_interrupts(trans);
1000
1001         /* really make sure rfkill handshake bits are cleared */
1002         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1003         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1004
1005         /* Load the given image to the HW */
1006         return iwl_load_given_ucode(trans, fw);
1007 }
1008
1009 /*
1010  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1011  * must be called under the irq lock and with MAC access
1012  */
1013 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1014 {
1015         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1016                 IWL_TRANS_GET_PCIE_TRANS(trans);
1017
1018         lockdep_assert_held(&trans_pcie->irq_lock);
1019
1020         iwl_write_prph(trans, SCD_TXFACT, mask);
1021 }
1022
1023 static void iwl_tx_start(struct iwl_trans *trans)
1024 {
1025         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1026         u32 a;
1027         unsigned long flags;
1028         int i, chan;
1029         u32 reg_val;
1030
1031         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1032
1033         /* make sure all queue are not stopped/used */
1034         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1035         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1036
1037         trans_pcie->scd_base_addr =
1038                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1039         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1040         /* reset conext data memory */
1041         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1042                 a += 4)
1043                 iwl_write_targ_mem(trans, a, 0);
1044         /* reset tx status memory */
1045         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1046                 a += 4)
1047                 iwl_write_targ_mem(trans, a, 0);
1048         for (; a < trans_pcie->scd_base_addr +
1049                SCD_TRANS_TBL_OFFSET_QUEUE(
1050                                 trans->cfg->base_params->num_of_queues);
1051                a += 4)
1052                 iwl_write_targ_mem(trans, a, 0);
1053
1054         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1055                        trans_pcie->scd_bc_tbls.dma >> 10);
1056
1057         for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1058                 int fifo = trans_pcie->setup_q_to_fifo[i];
1059
1060                 __iwl_trans_pcie_txq_enable(trans, i, fifo, IWL_INVALID_STATION,
1061                                             IWL_TID_NON_QOS,
1062                                             SCD_FRAME_LIMIT, 0);
1063         }
1064
1065         /* Activate all Tx DMA/FIFO channels */
1066         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1067
1068         /* Enable DMA channel */
1069         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1070                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1071                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1072                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1073
1074         /* Update FH chicken bits */
1075         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1076         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1077                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1078
1079         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1080
1081         /* Enable L1-Active */
1082         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1083                             APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1084 }
1085
1086 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1087 {
1088         iwl_reset_ict(trans);
1089         iwl_tx_start(trans);
1090 }
1091
1092 /**
1093  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1094  */
1095 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1096 {
1097         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1098         int ch, txq_id, ret;
1099         unsigned long flags;
1100
1101         /* Turn off all Tx DMA fifos */
1102         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1103
1104         iwl_trans_txq_set_sched(trans, 0);
1105
1106         /* Stop each Tx DMA channel, and wait for it to be idle */
1107         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1108                 iwl_write_direct32(trans,
1109                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1110                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1111                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1112                 if (ret < 0)
1113                         IWL_ERR(trans,
1114                                 "Failing on timeout while stopping DMA channel %d [0x%08x]",
1115                                 ch,
1116                                 iwl_read_direct32(trans,
1117                                                   FH_TSSR_TX_STATUS_REG));
1118         }
1119         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1120
1121         if (!trans_pcie->txq) {
1122                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1123                 return 0;
1124         }
1125
1126         /* Unmap DMA from host system and free skb's */
1127         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1128              txq_id++)
1129                 iwl_tx_queue_unmap(trans, txq_id);
1130
1131         return 0;
1132 }
1133
1134 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1135 {
1136         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1137         unsigned long flags;
1138
1139         /* tell the device to stop sending interrupts */
1140         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1141         iwl_disable_interrupts(trans);
1142         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1143
1144         /* device going down, Stop using ICT table */
1145         iwl_disable_ict(trans);
1146
1147         /*
1148          * If a HW restart happens during firmware loading,
1149          * then the firmware loading might call this function
1150          * and later it might be called again due to the
1151          * restart. So don't process again if the device is
1152          * already dead.
1153          */
1154         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1155                 iwl_trans_tx_stop(trans);
1156 #ifndef CONFIG_IWLWIFI_IDI
1157                 iwl_trans_rx_stop(trans);
1158 #endif
1159                 /* Power-down device's busmaster DMA clocks */
1160                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1161                                APMG_CLK_VAL_DMA_CLK_RQT);
1162                 udelay(5);
1163         }
1164
1165         /* Make sure (redundant) we've released our request to stay awake */
1166         iwl_clear_bit(trans, CSR_GP_CNTRL,
1167                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1168
1169         /* Stop the device, and put it in low power state */
1170         iwl_apm_stop(trans);
1171
1172         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1173          * Clean again the interrupt here
1174          */
1175         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1176         iwl_disable_interrupts(trans);
1177         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1178
1179         iwl_enable_rfkill_int(trans);
1180
1181         /* wait to make sure we flush pending tasklet*/
1182         synchronize_irq(trans_pcie->irq);
1183         tasklet_kill(&trans_pcie->irq_tasklet);
1184
1185         cancel_work_sync(&trans_pcie->rx_replenish);
1186
1187         /* stop and reset the on-board processor */
1188         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1189
1190         /* clear all status bits */
1191         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1192         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1193         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1194         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1195 }
1196
1197 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1198 {
1199         /* let the ucode operate on its own */
1200         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1201                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1202
1203         iwl_disable_interrupts(trans);
1204         iwl_clear_bit(trans, CSR_GP_CNTRL,
1205                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1206 }
1207
1208 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1209                              struct iwl_device_cmd *dev_cmd, int txq_id)
1210 {
1211         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1212         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1213         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1214         struct iwl_cmd_meta *out_meta;
1215         struct iwl_tx_queue *txq;
1216         struct iwl_queue *q;
1217         dma_addr_t phys_addr = 0;
1218         dma_addr_t txcmd_phys;
1219         dma_addr_t scratch_phys;
1220         u16 len, firstlen, secondlen;
1221         u8 wait_write_ptr = 0;
1222         __le16 fc = hdr->frame_control;
1223         u8 hdr_len = ieee80211_hdrlen(fc);
1224         u16 __maybe_unused wifi_seq;
1225
1226         txq = &trans_pcie->txq[txq_id];
1227         q = &txq->q;
1228
1229         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1230                 WARN_ON_ONCE(1);
1231                 return -EINVAL;
1232         }
1233
1234         spin_lock(&txq->lock);
1235
1236         /* Set up driver data for this TFD */
1237         txq->entries[q->write_ptr].skb = skb;
1238         txq->entries[q->write_ptr].cmd = dev_cmd;
1239
1240         dev_cmd->hdr.cmd = REPLY_TX;
1241         dev_cmd->hdr.sequence =
1242                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1243                             INDEX_TO_SEQ(q->write_ptr)));
1244
1245         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1246         out_meta = &txq->entries[q->write_ptr].meta;
1247
1248         /*
1249          * Use the first empty entry in this queue's command buffer array
1250          * to contain the Tx command and MAC header concatenated together
1251          * (payload data will be in another buffer).
1252          * Size of this varies, due to varying MAC header length.
1253          * If end is not dword aligned, we'll have 2 extra bytes at the end
1254          * of the MAC header (device reads on dword boundaries).
1255          * We'll tell device about this padding later.
1256          */
1257         len = sizeof(struct iwl_tx_cmd) +
1258                 sizeof(struct iwl_cmd_header) + hdr_len;
1259         firstlen = (len + 3) & ~3;
1260
1261         /* Tell NIC about any 2-byte padding after MAC header */
1262         if (firstlen != len)
1263                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1264
1265         /* Physical address of this Tx command's header (not MAC header!),
1266          * within command buffer array. */
1267         txcmd_phys = dma_map_single(trans->dev,
1268                                     &dev_cmd->hdr, firstlen,
1269                                     DMA_BIDIRECTIONAL);
1270         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1271                 goto out_err;
1272         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1273         dma_unmap_len_set(out_meta, len, firstlen);
1274
1275         if (!ieee80211_has_morefrags(fc)) {
1276                 txq->need_update = 1;
1277         } else {
1278                 wait_write_ptr = 1;
1279                 txq->need_update = 0;
1280         }
1281
1282         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1283          * if any (802.11 null frames have no payload). */
1284         secondlen = skb->len - hdr_len;
1285         if (secondlen > 0) {
1286                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1287                                            secondlen, DMA_TO_DEVICE);
1288                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1289                         dma_unmap_single(trans->dev,
1290                                          dma_unmap_addr(out_meta, mapping),
1291                                          dma_unmap_len(out_meta, len),
1292                                          DMA_BIDIRECTIONAL);
1293                         goto out_err;
1294                 }
1295         }
1296
1297         /* Attach buffers to TFD */
1298         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1299         if (secondlen > 0)
1300                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1301                                              secondlen, 0);
1302
1303         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1304                                 offsetof(struct iwl_tx_cmd, scratch);
1305
1306         /* take back ownership of DMA buffer to enable update */
1307         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1308                                 DMA_BIDIRECTIONAL);
1309         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1310         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1311
1312         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1313                      le16_to_cpu(dev_cmd->hdr.sequence));
1314         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1315
1316         /* Set up entry for this TFD in Tx byte-count array */
1317         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1318
1319         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1320                                    DMA_BIDIRECTIONAL);
1321
1322         trace_iwlwifi_dev_tx(trans->dev,
1323                              &txq->tfds[txq->q.write_ptr],
1324                              sizeof(struct iwl_tfd),
1325                              &dev_cmd->hdr, firstlen,
1326                              skb->data + hdr_len, secondlen);
1327
1328         /* start timer if queue currently empty */
1329         if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1330                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1331
1332         /* Tell device the write index *just past* this latest filled TFD */
1333         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1334         iwl_txq_update_write_ptr(trans, txq);
1335
1336         /*
1337          * At this point the frame is "transmitted" successfully
1338          * and we will get a TX status notification eventually,
1339          * regardless of the value of ret. "ret" only indicates
1340          * whether or not we should update the write pointer.
1341          */
1342         if (iwl_queue_space(q) < q->high_mark) {
1343                 if (wait_write_ptr) {
1344                         txq->need_update = 1;
1345                         iwl_txq_update_write_ptr(trans, txq);
1346                 } else {
1347                         iwl_stop_queue(trans, txq);
1348                 }
1349         }
1350         spin_unlock(&txq->lock);
1351         return 0;
1352  out_err:
1353         spin_unlock(&txq->lock);
1354         return -1;
1355 }
1356
1357 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1358 {
1359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1360         int err;
1361         bool hw_rfkill;
1362
1363         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1364
1365         if (!trans_pcie->irq_requested) {
1366                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1367                         iwl_irq_tasklet, (unsigned long)trans);
1368
1369                 iwl_alloc_isr_ict(trans);
1370
1371                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1372                                   DRV_NAME, trans);
1373                 if (err) {
1374                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1375                                 trans_pcie->irq);
1376                         goto error;
1377                 }
1378
1379                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1380                 trans_pcie->irq_requested = true;
1381         }
1382
1383         err = iwl_prepare_card_hw(trans);
1384         if (err) {
1385                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1386                 goto err_free_irq;
1387         }
1388
1389         iwl_apm_init(trans);
1390
1391         /* From now on, the op_mode will be kept updated about RF kill state */
1392         iwl_enable_rfkill_int(trans);
1393
1394         hw_rfkill = iwl_is_rfkill_set(trans);
1395         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1396
1397         return err;
1398
1399 err_free_irq:
1400         free_irq(trans_pcie->irq, trans);
1401 error:
1402         iwl_free_isr_ict(trans);
1403         tasklet_kill(&trans_pcie->irq_tasklet);
1404         return err;
1405 }
1406
1407 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1408                                    bool op_mode_leaving)
1409 {
1410         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1411         bool hw_rfkill;
1412         unsigned long flags;
1413
1414         iwl_apm_stop(trans);
1415
1416         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1417         iwl_disable_interrupts(trans);
1418         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1419
1420         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1421
1422         if (!op_mode_leaving) {
1423                 /*
1424                  * Even if we stop the HW, we still want the RF kill
1425                  * interrupt
1426                  */
1427                 iwl_enable_rfkill_int(trans);
1428
1429                 /*
1430                  * Check again since the RF kill state may have changed while
1431                  * all the interrupts were disabled, in this case we couldn't
1432                  * receive the RF kill interrupt and update the state in the
1433                  * op_mode.
1434                  */
1435                 hw_rfkill = iwl_is_rfkill_set(trans);
1436                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1437         }
1438 }
1439
1440 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1441                                    struct sk_buff_head *skbs)
1442 {
1443         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1444         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1445         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1446         int tfd_num = ssn & (txq->q.n_bd - 1);
1447         int freed = 0;
1448
1449         spin_lock(&txq->lock);
1450
1451         if (txq->q.read_ptr != tfd_num) {
1452                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1453                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1454                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1455                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1456                         iwl_wake_queue(trans, txq);
1457         }
1458
1459         spin_unlock(&txq->lock);
1460 }
1461
1462 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1463 {
1464         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1465 }
1466
1467 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1468 {
1469         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1470 }
1471
1472 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1473 {
1474         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1475 }
1476
1477 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1478                                      const struct iwl_trans_config *trans_cfg)
1479 {
1480         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481
1482         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1483         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1484                 trans_pcie->n_no_reclaim_cmds = 0;
1485         else
1486                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1487         if (trans_pcie->n_no_reclaim_cmds)
1488                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1489                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1490
1491         trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1492
1493         if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1494                 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1495
1496         /* at least the command queue must be mapped */
1497         WARN_ON(!trans_pcie->n_q_to_fifo);
1498
1499         memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1500                trans_pcie->n_q_to_fifo * sizeof(u8));
1501
1502         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1503         if (trans_pcie->rx_buf_size_8k)
1504                 trans_pcie->rx_page_order = get_order(8 * 1024);
1505         else
1506                 trans_pcie->rx_page_order = get_order(4 * 1024);
1507
1508         trans_pcie->wd_timeout =
1509                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1510
1511         trans_pcie->command_names = trans_cfg->command_names;
1512 }
1513
1514 void iwl_trans_pcie_free(struct iwl_trans *trans)
1515 {
1516         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1517
1518         iwl_trans_pcie_tx_free(trans);
1519 #ifndef CONFIG_IWLWIFI_IDI
1520         iwl_trans_pcie_rx_free(trans);
1521 #endif
1522         if (trans_pcie->irq_requested == true) {
1523                 free_irq(trans_pcie->irq, trans);
1524                 iwl_free_isr_ict(trans);
1525         }
1526
1527         pci_disable_msi(trans_pcie->pci_dev);
1528         iounmap(trans_pcie->hw_base);
1529         pci_release_regions(trans_pcie->pci_dev);
1530         pci_disable_device(trans_pcie->pci_dev);
1531         kmem_cache_destroy(trans->dev_cmd_pool);
1532
1533         kfree(trans);
1534 }
1535
1536 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1537 {
1538         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1539
1540         if (state)
1541                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1542         else
1543                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1544 }
1545
1546 #ifdef CONFIG_PM_SLEEP
1547 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1548 {
1549         return 0;
1550 }
1551
1552 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1553 {
1554         bool hw_rfkill;
1555
1556         iwl_enable_rfkill_int(trans);
1557
1558         hw_rfkill = iwl_is_rfkill_set(trans);
1559         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1560
1561         if (!hw_rfkill)
1562                 iwl_enable_interrupts(trans);
1563
1564         return 0;
1565 }
1566 #endif /* CONFIG_PM_SLEEP */
1567
1568 #define IWL_FLUSH_WAIT_MS       2000
1569
1570 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1571 {
1572         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1573         struct iwl_tx_queue *txq;
1574         struct iwl_queue *q;
1575         int cnt;
1576         unsigned long now = jiffies;
1577         int ret = 0;
1578
1579         /* waiting for all the tx frames complete might take a while */
1580         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1581                 if (cnt == trans_pcie->cmd_queue)
1582                         continue;
1583                 txq = &trans_pcie->txq[cnt];
1584                 q = &txq->q;
1585                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1586                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1587                         msleep(1);
1588
1589                 if (q->read_ptr != q->write_ptr) {
1590                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1591                         ret = -ETIMEDOUT;
1592                         break;
1593                 }
1594         }
1595         return ret;
1596 }
1597
1598 static const char *get_fh_string(int cmd)
1599 {
1600 #define IWL_CMD(x) case x: return #x
1601         switch (cmd) {
1602         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1603         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1604         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1605         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1606         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1607         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1608         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1609         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1610         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1611         default:
1612                 return "UNKNOWN";
1613         }
1614 #undef IWL_CMD
1615 }
1616
1617 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1618 {
1619         int i;
1620 #ifdef CONFIG_IWLWIFI_DEBUG
1621         int pos = 0;
1622         size_t bufsz = 0;
1623 #endif
1624         static const u32 fh_tbl[] = {
1625                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1626                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1627                 FH_RSCSR_CHNL0_WPTR,
1628                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1629                 FH_MEM_RSSR_SHARED_CTRL_REG,
1630                 FH_MEM_RSSR_RX_STATUS_REG,
1631                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1632                 FH_TSSR_TX_STATUS_REG,
1633                 FH_TSSR_TX_ERROR_REG
1634         };
1635 #ifdef CONFIG_IWLWIFI_DEBUG
1636         if (display) {
1637                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1638                 *buf = kmalloc(bufsz, GFP_KERNEL);
1639                 if (!*buf)
1640                         return -ENOMEM;
1641                 pos += scnprintf(*buf + pos, bufsz - pos,
1642                                 "FH register values:\n");
1643                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1644                         pos += scnprintf(*buf + pos, bufsz - pos,
1645                                 "  %34s: 0X%08x\n",
1646                                 get_fh_string(fh_tbl[i]),
1647                                 iwl_read_direct32(trans, fh_tbl[i]));
1648                 }
1649                 return pos;
1650         }
1651 #endif
1652         IWL_ERR(trans, "FH register values:\n");
1653         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1654                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1655                         get_fh_string(fh_tbl[i]),
1656                         iwl_read_direct32(trans, fh_tbl[i]));
1657         }
1658         return 0;
1659 }
1660
1661 static const char *get_csr_string(int cmd)
1662 {
1663 #define IWL_CMD(x) case x: return #x
1664         switch (cmd) {
1665         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1666         IWL_CMD(CSR_INT_COALESCING);
1667         IWL_CMD(CSR_INT);
1668         IWL_CMD(CSR_INT_MASK);
1669         IWL_CMD(CSR_FH_INT_STATUS);
1670         IWL_CMD(CSR_GPIO_IN);
1671         IWL_CMD(CSR_RESET);
1672         IWL_CMD(CSR_GP_CNTRL);
1673         IWL_CMD(CSR_HW_REV);
1674         IWL_CMD(CSR_EEPROM_REG);
1675         IWL_CMD(CSR_EEPROM_GP);
1676         IWL_CMD(CSR_OTP_GP_REG);
1677         IWL_CMD(CSR_GIO_REG);
1678         IWL_CMD(CSR_GP_UCODE_REG);
1679         IWL_CMD(CSR_GP_DRIVER_REG);
1680         IWL_CMD(CSR_UCODE_DRV_GP1);
1681         IWL_CMD(CSR_UCODE_DRV_GP2);
1682         IWL_CMD(CSR_LED_REG);
1683         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1684         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1685         IWL_CMD(CSR_ANA_PLL_CFG);
1686         IWL_CMD(CSR_HW_REV_WA_REG);
1687         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1688         default:
1689                 return "UNKNOWN";
1690         }
1691 #undef IWL_CMD
1692 }
1693
1694 void iwl_dump_csr(struct iwl_trans *trans)
1695 {
1696         int i;
1697         static const u32 csr_tbl[] = {
1698                 CSR_HW_IF_CONFIG_REG,
1699                 CSR_INT_COALESCING,
1700                 CSR_INT,
1701                 CSR_INT_MASK,
1702                 CSR_FH_INT_STATUS,
1703                 CSR_GPIO_IN,
1704                 CSR_RESET,
1705                 CSR_GP_CNTRL,
1706                 CSR_HW_REV,
1707                 CSR_EEPROM_REG,
1708                 CSR_EEPROM_GP,
1709                 CSR_OTP_GP_REG,
1710                 CSR_GIO_REG,
1711                 CSR_GP_UCODE_REG,
1712                 CSR_GP_DRIVER_REG,
1713                 CSR_UCODE_DRV_GP1,
1714                 CSR_UCODE_DRV_GP2,
1715                 CSR_LED_REG,
1716                 CSR_DRAM_INT_TBL_REG,
1717                 CSR_GIO_CHICKEN_BITS,
1718                 CSR_ANA_PLL_CFG,
1719                 CSR_HW_REV_WA_REG,
1720                 CSR_DBG_HPET_MEM_REG
1721         };
1722         IWL_ERR(trans, "CSR values:\n");
1723         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1724                 "CSR_INT_PERIODIC_REG)\n");
1725         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1726                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1727                         get_csr_string(csr_tbl[i]),
1728                         iwl_read32(trans, csr_tbl[i]));
1729         }
1730 }
1731
1732 #ifdef CONFIG_IWLWIFI_DEBUGFS
1733 /* create and remove of files */
1734 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1735         if (!debugfs_create_file(#name, mode, parent, trans,            \
1736                                  &iwl_dbgfs_##name##_ops))              \
1737                 return -ENOMEM;                                         \
1738 } while (0)
1739
1740 /* file operation */
1741 #define DEBUGFS_READ_FUNC(name)                                         \
1742 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1743                                         char __user *user_buf,          \
1744                                         size_t count, loff_t *ppos);
1745
1746 #define DEBUGFS_WRITE_FUNC(name)                                        \
1747 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1748                                         const char __user *user_buf,    \
1749                                         size_t count, loff_t *ppos);
1750
1751
1752 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1753         DEBUGFS_READ_FUNC(name);                                        \
1754 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1755         .read = iwl_dbgfs_##name##_read,                                \
1756         .open = simple_open,                                            \
1757         .llseek = generic_file_llseek,                                  \
1758 };
1759
1760 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1761         DEBUGFS_WRITE_FUNC(name);                                       \
1762 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1763         .write = iwl_dbgfs_##name##_write,                              \
1764         .open = simple_open,                                            \
1765         .llseek = generic_file_llseek,                                  \
1766 };
1767
1768 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1769         DEBUGFS_READ_FUNC(name);                                        \
1770         DEBUGFS_WRITE_FUNC(name);                                       \
1771 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1772         .write = iwl_dbgfs_##name##_write,                              \
1773         .read = iwl_dbgfs_##name##_read,                                \
1774         .open = simple_open,                                            \
1775         .llseek = generic_file_llseek,                                  \
1776 };
1777
1778 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1779                                        char __user *user_buf,
1780                                        size_t count, loff_t *ppos)
1781 {
1782         struct iwl_trans *trans = file->private_data;
1783         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1784         struct iwl_tx_queue *txq;
1785         struct iwl_queue *q;
1786         char *buf;
1787         int pos = 0;
1788         int cnt;
1789         int ret;
1790         size_t bufsz;
1791
1792         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1793
1794         if (!trans_pcie->txq)
1795                 return -EAGAIN;
1796
1797         buf = kzalloc(bufsz, GFP_KERNEL);
1798         if (!buf)
1799                 return -ENOMEM;
1800
1801         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1802                 txq = &trans_pcie->txq[cnt];
1803                 q = &txq->q;
1804                 pos += scnprintf(buf + pos, bufsz - pos,
1805                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1806                                 cnt, q->read_ptr, q->write_ptr,
1807                                 !!test_bit(cnt, trans_pcie->queue_used),
1808                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1809         }
1810         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1811         kfree(buf);
1812         return ret;
1813 }
1814
1815 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1816                                        char __user *user_buf,
1817                                        size_t count, loff_t *ppos)
1818 {
1819         struct iwl_trans *trans = file->private_data;
1820         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1821         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1822         char buf[256];
1823         int pos = 0;
1824         const size_t bufsz = sizeof(buf);
1825
1826         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1827                                                 rxq->read);
1828         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1829                                                 rxq->write);
1830         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1831                                                 rxq->free_count);
1832         if (rxq->rb_stts) {
1833                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1834                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1835         } else {
1836                 pos += scnprintf(buf + pos, bufsz - pos,
1837                                         "closed_rb_num: Not Allocated\n");
1838         }
1839         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1840 }
1841
1842 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1843                                         char __user *user_buf,
1844                                         size_t count, loff_t *ppos)
1845 {
1846         struct iwl_trans *trans = file->private_data;
1847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1849
1850         int pos = 0;
1851         char *buf;
1852         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1853         ssize_t ret;
1854
1855         buf = kzalloc(bufsz, GFP_KERNEL);
1856         if (!buf)
1857                 return -ENOMEM;
1858
1859         pos += scnprintf(buf + pos, bufsz - pos,
1860                         "Interrupt Statistics Report:\n");
1861
1862         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1863                 isr_stats->hw);
1864         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1865                 isr_stats->sw);
1866         if (isr_stats->sw || isr_stats->hw) {
1867                 pos += scnprintf(buf + pos, bufsz - pos,
1868                         "\tLast Restarting Code:  0x%X\n",
1869                         isr_stats->err_code);
1870         }
1871 #ifdef CONFIG_IWLWIFI_DEBUG
1872         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1873                 isr_stats->sch);
1874         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1875                 isr_stats->alive);
1876 #endif
1877         pos += scnprintf(buf + pos, bufsz - pos,
1878                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1879
1880         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1881                 isr_stats->ctkill);
1882
1883         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1884                 isr_stats->wakeup);
1885
1886         pos += scnprintf(buf + pos, bufsz - pos,
1887                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1888
1889         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1890                 isr_stats->tx);
1891
1892         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1893                 isr_stats->unhandled);
1894
1895         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1896         kfree(buf);
1897         return ret;
1898 }
1899
1900 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1901                                          const char __user *user_buf,
1902                                          size_t count, loff_t *ppos)
1903 {
1904         struct iwl_trans *trans = file->private_data;
1905         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1906         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1907
1908         char buf[8];
1909         int buf_size;
1910         u32 reset_flag;
1911
1912         memset(buf, 0, sizeof(buf));
1913         buf_size = min(count, sizeof(buf) -  1);
1914         if (copy_from_user(buf, user_buf, buf_size))
1915                 return -EFAULT;
1916         if (sscanf(buf, "%x", &reset_flag) != 1)
1917                 return -EFAULT;
1918         if (reset_flag == 0)
1919                 memset(isr_stats, 0, sizeof(*isr_stats));
1920
1921         return count;
1922 }
1923
1924 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1925                                    const char __user *user_buf,
1926                                    size_t count, loff_t *ppos)
1927 {
1928         struct iwl_trans *trans = file->private_data;
1929         char buf[8];
1930         int buf_size;
1931         int csr;
1932
1933         memset(buf, 0, sizeof(buf));
1934         buf_size = min(count, sizeof(buf) -  1);
1935         if (copy_from_user(buf, user_buf, buf_size))
1936                 return -EFAULT;
1937         if (sscanf(buf, "%d", &csr) != 1)
1938                 return -EFAULT;
1939
1940         iwl_dump_csr(trans);
1941
1942         return count;
1943 }
1944
1945 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1946                                      char __user *user_buf,
1947                                      size_t count, loff_t *ppos)
1948 {
1949         struct iwl_trans *trans = file->private_data;
1950         char *buf;
1951         int pos = 0;
1952         ssize_t ret = -EFAULT;
1953
1954         ret = pos = iwl_dump_fh(trans, &buf, true);
1955         if (buf) {
1956                 ret = simple_read_from_buffer(user_buf,
1957                                               count, ppos, buf, pos);
1958                 kfree(buf);
1959         }
1960
1961         return ret;
1962 }
1963
1964 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1965                                           const char __user *user_buf,
1966                                           size_t count, loff_t *ppos)
1967 {
1968         struct iwl_trans *trans = file->private_data;
1969
1970         if (!trans->op_mode)
1971                 return -EAGAIN;
1972
1973         iwl_op_mode_nic_error(trans->op_mode);
1974
1975         return count;
1976 }
1977
1978 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1979 DEBUGFS_READ_FILE_OPS(fh_reg);
1980 DEBUGFS_READ_FILE_OPS(rx_queue);
1981 DEBUGFS_READ_FILE_OPS(tx_queue);
1982 DEBUGFS_WRITE_FILE_OPS(csr);
1983 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1984
1985 /*
1986  * Create the debugfs files and directories
1987  *
1988  */
1989 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1990                                          struct dentry *dir)
1991 {
1992         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1993         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1994         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1995         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1996         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1997         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1998         return 0;
1999 }
2000 #else
2001 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2002                                          struct dentry *dir)
2003 {
2004         return 0;
2005 }
2006 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2007
2008 static const struct iwl_trans_ops trans_ops_pcie = {
2009         .start_hw = iwl_trans_pcie_start_hw,
2010         .stop_hw = iwl_trans_pcie_stop_hw,
2011         .fw_alive = iwl_trans_pcie_fw_alive,
2012         .start_fw = iwl_trans_pcie_start_fw,
2013         .stop_device = iwl_trans_pcie_stop_device,
2014
2015         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2016
2017         .send_cmd = iwl_trans_pcie_send_cmd,
2018
2019         .tx = iwl_trans_pcie_tx,
2020         .reclaim = iwl_trans_pcie_reclaim,
2021
2022         .txq_disable = iwl_trans_pcie_txq_disable,
2023         .txq_enable = iwl_trans_pcie_txq_enable,
2024
2025         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2026
2027         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2028
2029 #ifdef CONFIG_PM_SLEEP
2030         .suspend = iwl_trans_pcie_suspend,
2031         .resume = iwl_trans_pcie_resume,
2032 #endif
2033         .write8 = iwl_trans_pcie_write8,
2034         .write32 = iwl_trans_pcie_write32,
2035         .read32 = iwl_trans_pcie_read32,
2036         .configure = iwl_trans_pcie_configure,
2037         .set_pmi = iwl_trans_pcie_set_pmi,
2038 };
2039
2040 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2041                                        const struct pci_device_id *ent,
2042                                        const struct iwl_cfg *cfg)
2043 {
2044         struct iwl_trans_pcie *trans_pcie;
2045         struct iwl_trans *trans;
2046         char cmd_pool_name[100];
2047         u16 pci_cmd;
2048         int err;
2049
2050         trans = kzalloc(sizeof(struct iwl_trans) +
2051                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2052
2053         if (WARN_ON(!trans))
2054                 return NULL;
2055
2056         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2057
2058         trans->ops = &trans_ops_pcie;
2059         trans->cfg = cfg;
2060         trans_pcie->trans = trans;
2061         spin_lock_init(&trans_pcie->irq_lock);
2062         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2063
2064         /* W/A - seems to solve weird behavior. We need to remove this if we
2065          * don't want to stay in L1 all the time. This wastes a lot of power */
2066         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2067                                PCIE_LINK_STATE_CLKPM);
2068
2069         if (pci_enable_device(pdev)) {
2070                 err = -ENODEV;
2071                 goto out_no_pci;
2072         }
2073
2074         pci_set_master(pdev);
2075
2076         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2077         if (!err)
2078                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2079         if (err) {
2080                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2081                 if (!err)
2082                         err = pci_set_consistent_dma_mask(pdev,
2083                                                           DMA_BIT_MASK(32));
2084                 /* both attempts failed: */
2085                 if (err) {
2086                         dev_printk(KERN_ERR, &pdev->dev,
2087                                    "No suitable DMA available.\n");
2088                         goto out_pci_disable_device;
2089                 }
2090         }
2091
2092         err = pci_request_regions(pdev, DRV_NAME);
2093         if (err) {
2094                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2095                 goto out_pci_disable_device;
2096         }
2097
2098         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2099         if (!trans_pcie->hw_base) {
2100                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2101                 err = -ENODEV;
2102                 goto out_pci_release_regions;
2103         }
2104
2105         dev_printk(KERN_INFO, &pdev->dev,
2106                    "pci_resource_len = 0x%08llx\n",
2107                    (unsigned long long) pci_resource_len(pdev, 0));
2108         dev_printk(KERN_INFO, &pdev->dev,
2109                    "pci_resource_base = %p\n", trans_pcie->hw_base);
2110
2111         dev_printk(KERN_INFO, &pdev->dev,
2112                    "HW Revision ID = 0x%X\n", pdev->revision);
2113
2114         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2115          * PCI Tx retries from interfering with C3 CPU state */
2116         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2117
2118         err = pci_enable_msi(pdev);
2119         if (err)
2120                 dev_printk(KERN_ERR, &pdev->dev,
2121                            "pci_enable_msi failed(0X%x)", err);
2122
2123         trans->dev = &pdev->dev;
2124         trans_pcie->irq = pdev->irq;
2125         trans_pcie->pci_dev = pdev;
2126         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2127         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2128         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2129                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2130
2131         /* TODO: Move this away, not needed if not MSI */
2132         /* enable rfkill interrupt: hw bug w/a */
2133         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2134         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2135                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2136                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2137         }
2138
2139         /* Initialize the wait queue for commands */
2140         init_waitqueue_head(&trans->wait_command_queue);
2141         spin_lock_init(&trans->reg_lock);
2142
2143         snprintf(cmd_pool_name, sizeof(cmd_pool_name), "iwl_cmd_pool:%s",
2144                  dev_name(trans->dev));
2145
2146         trans->dev_cmd_headroom = 0;
2147         trans->dev_cmd_pool =
2148                 kmem_cache_create(cmd_pool_name,
2149                                   sizeof(struct iwl_device_cmd)
2150                                   + trans->dev_cmd_headroom,
2151                                   sizeof(void *),
2152                                   SLAB_HWCACHE_ALIGN,
2153                                   NULL);
2154
2155         if (!trans->dev_cmd_pool)
2156                 goto out_pci_disable_msi;
2157
2158         return trans;
2159
2160 out_pci_disable_msi:
2161         pci_disable_msi(pdev);
2162 out_pci_release_regions:
2163         pci_release_regions(pdev);
2164 out_pci_disable_device:
2165         pci_disable_device(pdev);
2166 out_no_pci:
2167         kfree(trans);
2168         return NULL;
2169 }