drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  79 {
  80         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  81                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  82                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  83                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  84         else
  85                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  87                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  88 }
  89
  90 /* PCI registers */
  91 #define PCI_CFG_RETRY_TIMEOUT   0x041
  92
  93 static void iwl_pcie_apm_config(struct iwl_trans *trans)
  94 {
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         u16 lctl;
  97
  98         /*
  99          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 100          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 101          * If so (likely), disable L0S, so device moves directly L0->L1;
 102          *    costs negligible amount of power savings.
 103          * If not (unlikely), enable L0S, so there is at least some
 104          *    power savings, even without L1.
 105          */
 106         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 107         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 108                 /* L1-ASPM enabled; disable(!) L0S */
 109                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 110                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 111         } else {
 112                 /* L1-ASPM disabled; enable(!) L0S */
 113                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 114                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 115         }
 116         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 117 }
 118
 119 /*
 120  * Start up NIC's basic functionality after it has been reset
 121  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 122  * NOTE:  This does not load uCode nor start the embedded processor
 123  */
 124 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 125 {
 126         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 127         int ret = 0;
 128         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 129
 130         /*
 131          * Use "set_bit" below rather than "write", to preserve any hardware
 132          * bits already set by default after reset.
 133          */
 134
 135         /* Disable L0S exit timer (platform NMI Work/Around) */
 136         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 137                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 138
 139         /*
 140          * Disable L0s without affecting L1;
 141          *  don't wait for ICH L0s (ICH bug W/A)
 142          */
 143         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 144                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 145
 146         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 147         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 148
 149         /*
 150          * Enable HAP INTA (interrupt from management bus) to
 151          * wake device's PCI Express link L1a -> L0s
 152          */
 153         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 154                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 155
 156         iwl_pcie_apm_config(trans);
 157
 158         /* Configure analog phase-lock-loop before activating to D0A */
 159         if (trans->cfg->base_params->pll_cfg_val)
 160                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 161                             trans->cfg->base_params->pll_cfg_val);
 162
 163         /*
 164          * Set "initialization complete" bit to move adapter from
 165          * D0U* --> D0A* (powered-up active) state.
 166          */
 167         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 168
 169         /*
 170          * Wait for clock stabilization; once stabilized, access to
 171          * device-internal resources is supported, e.g. iwl_write_prph()
 172          * and accesses to uCode SRAM.
 173          */
 174         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 175                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 176                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 177         if (ret < 0) {
 178                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 179                 goto out;
 180         }
 181
 182         /*
 183          * Enable DMA clock and wait for it to stabilize.
 184          *
 185          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 186          * do not disable clocks.  This preserves any hardware bits already
 187          * set by default in "CLK_CTRL_REG" after reset.
 188          */
 189         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 190         udelay(20);
 191
 192         /* Disable L1-Active */
 193         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 194                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 195
 196         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 197
 198 out:
 199         return ret;
 200 }
 201
 202 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 203 {
 204         int ret = 0;
 205
 206         /* stop device's busmaster DMA activity */
 207         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 208
 209         ret = iwl_poll_bit(trans, CSR_RESET,
 210                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 211                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 212         if (ret)
 213                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 214
 215         IWL_DEBUG_INFO(trans, "stop master\n");
 216
 217         return ret;
 218 }
 219
 220 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 221 {
 222         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 223         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 224
 225         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 226
 227         /* Stop device's DMA activity */
 228         iwl_pcie_apm_stop_master(trans);
 229
 230         /* Reset the entire device */
 231         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 232
 233         udelay(10);
 234
 235         /*
 236          * Clear "initialization complete" bit to move adapter from
 237          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 238          */
 239         iwl_clear_bit(trans, CSR_GP_CNTRL,
 240                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 241 }
 242
 243 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 244 {
 245         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 246         unsigned long flags;
 247
 248         /* nic_init */
 249         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 250         iwl_pcie_apm_init(trans);
 251
 252         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 253         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 254
 255         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 256
 257         iwl_pcie_set_pwr(trans, false);
 258
 259         iwl_op_mode_nic_config(trans->op_mode);
 260
 261         /* Allocate the RX queue, or reset if it is already allocated */
 262         iwl_pcie_rx_init(trans);
 263
 264         /* Allocate or reset and init all Tx and Command queues */
 265         if (iwl_pcie_tx_init(trans))
 266                 return -ENOMEM;
 267
 268         if (trans->cfg->base_params->shadow_reg_enable) {
 269                 /* enable shadow regs in HW */
 270                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 271                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 272         }
 273
 274         return 0;
 275 }
 276
 277 #define HW_READY_TIMEOUT (50)
 278
 279 /* Note: returns poll_bit return value, which is >= 0 if success */
 280 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 281 {
 282         int ret;
 283
 284         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 285                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 286
 287         /* See if we got it */
 288         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 289                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 290                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 291                            HW_READY_TIMEOUT);
 292
 293         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 294         return ret;
 295 }
 296
 297 /* Note: returns standard 0/-ERROR code */
 298 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 299 {
 300         int ret;
 301         int t = 0;
 302
 303         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 304
 305         ret = iwl_pcie_set_hw_ready(trans);
 306         /* If the card is ready, exit 0 */
 307         if (ret >= 0)
 308                 return 0;
 309
 310         /* If HW is not ready, prepare the conditions to check again */
 311         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 312                     CSR_HW_IF_CONFIG_REG_PREPARE);
 313
 314         do {
 315                 ret = iwl_pcie_set_hw_ready(trans);
 316                 if (ret >= 0)
 317                         return 0;
 318
 319                 usleep_range(200, 1000);
 320                 t += 200;
 321         } while (t < 150000);
 322
 323         return ret;
 324 }
 325
 326 /*
 327  * ucode
 328  */
 329 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 330                                    dma_addr_t phy_addr, u32 byte_cnt)
 331 {
 332         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 333         int ret;
 334
 335         trans_pcie->ucode_write_complete = false;
 336
 337         iwl_write_direct32(trans,
 338                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 339                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 340
 341         iwl_write_direct32(trans,
 342                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 343                            dst_addr);
 344
 345         iwl_write_direct32(trans,
 346                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 347                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 348
 349         iwl_write_direct32(trans,
 350                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 351                            (iwl_get_dma_hi_addr(phy_addr)
 352                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 353
 354         iwl_write_direct32(trans,
 355                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 356                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 357                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 358                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 359
 360         iwl_write_direct32(trans,
 361                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 362                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 363                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 364                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 365
 366         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 367                                  trans_pcie->ucode_write_complete, 5 * HZ);
 368         if (!ret) {
 369                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 370                 return -ETIMEDOUT;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 377                             const struct fw_desc *section)
 378 {
 379         u8 *v_addr;
 380         dma_addr_t p_addr;
 381         u32 offset;
 382         int ret = 0;
 383
 384         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 385                      section_num);
 386
 387         v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
 388         if (!v_addr)
 389                 return -ENOMEM;
 390
 391         for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
 392                 u32 copy_size;
 393
 394                 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
 395
 396                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 397                 ret = iwl_pcie_load_firmware_chunk(trans,
 398                                                    section->offset + offset,
 399                                                    p_addr, copy_size);
 400                 if (ret) {
 401                         IWL_ERR(trans,
 402                                 "Could not load the [%d] uCode section\n",
 403                                 section_num);
 404                         break;
 405                 }
 406         }
 407
 408         dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
 409         return ret;
 410 }
 411
 412 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 413                                 const struct fw_img *image)
 414 {
 415         int i, ret = 0;
 416
 417         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 418                 if (!image->sec[i].data)
 419                         break;
 420
 421                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 422                 if (ret)
 423                         return ret;
 424         }
 425
 426         /* Remove all resets to allow NIC to operate */
 427         iwl_write32(trans, CSR_RESET, 0);
 428
 429         return 0;
 430 }
 431
 432 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 433                                    const struct fw_img *fw, bool run_in_rfkill)
 434 {
 435         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 436         int ret;
 437         bool hw_rfkill;
 438
 439         /* This may fail if AMT took ownership of the device */
 440         if (iwl_pcie_prepare_card_hw(trans)) {
 441                 IWL_WARN(trans, "Exit HW not ready\n");
 442                 return -EIO;
 443         }
 444
 445         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 446
 447         iwl_enable_rfkill_int(trans);
 448
 449         /* If platform's RF_KILL switch is NOT set to KILL */
 450         hw_rfkill = iwl_is_rfkill_set(trans);
 451         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 452         if (hw_rfkill && !run_in_rfkill)
 453                 return -ERFKILL;
 454
 455         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 456
 457         ret = iwl_pcie_nic_init(trans);
 458         if (ret) {
 459                 IWL_ERR(trans, "Unable to init nic\n");
 460                 return ret;
 461         }
 462
 463         /* make sure rfkill handshake bits are cleared */
 464         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 465         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 466                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 467
 468         /* clear (again), then enable host interrupts */
 469         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 470         iwl_enable_interrupts(trans);
 471
 472         /* really make sure rfkill handshake bits are cleared */
 473         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 474         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 475
 476         /* Load the given image to the HW */
 477         return iwl_pcie_load_given_ucode(trans, fw);
 478 }
 479
 480 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 481 {
 482         iwl_pcie_reset_ict(trans);
 483         iwl_pcie_tx_start(trans, scd_addr);
 484 }
 485
 486 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 487 {
 488         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 489         unsigned long flags;
 490
 491         /* tell the device to stop sending interrupts */
 492         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 493         iwl_disable_interrupts(trans);
 494         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 495
 496         /* device going down, Stop using ICT table */
 497         iwl_pcie_disable_ict(trans);
 498
 499         /*
 500          * If a HW restart happens during firmware loading,
 501          * then the firmware loading might call this function
 502          * and later it might be called again due to the
 503          * restart. So don't process again if the device is
 504          * already dead.
 505          */
 506         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 507                 iwl_pcie_tx_stop(trans);
 508                 iwl_pcie_rx_stop(trans);
 509
 510                 /* Power-down device's busmaster DMA clocks */
 511                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 512                                APMG_CLK_VAL_DMA_CLK_RQT);
 513                 udelay(5);
 514         }
 515
 516         /* Make sure (redundant) we've released our request to stay awake */
 517         iwl_clear_bit(trans, CSR_GP_CNTRL,
 518                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 519
 520         /* Stop the device, and put it in low power state */
 521         iwl_pcie_apm_stop(trans);
 522
 523         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 524          * Clean again the interrupt here
 525          */
 526         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 527         iwl_disable_interrupts(trans);
 528         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 529
 530         iwl_enable_rfkill_int(trans);
 531
 532         /* stop and reset the on-board processor */
 533         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 534
 535         /* clear all status bits */
 536         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 537         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 538         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 539         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 540         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 541 }
 542
 543 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
 544 {
 545         /* let the ucode operate on its own */
 546         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
 547                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 548
 549         iwl_disable_interrupts(trans);
 550         iwl_pcie_disable_ict(trans);
 551
 552         iwl_clear_bit(trans, CSR_GP_CNTRL,
 553                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 554         iwl_clear_bit(trans, CSR_GP_CNTRL,
 555                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 556
 557         /*
 558          * reset TX queues -- some of their registers reset during S3
 559          * so if we don't reset everything here the D3 image would try
 560          * to execute some invalid memory upon resume
 561          */
 562         iwl_trans_pcie_tx_reset(trans);
 563
 564         iwl_pcie_set_pwr(trans, true);
 565 }
 566
 567 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 568                                     enum iwl_d3_status *status)
 569 {
 570         u32 val;
 571         int ret;
 572
 573         iwl_pcie_set_pwr(trans, false);
 574
 575         val = iwl_read32(trans, CSR_RESET);
 576         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 577                 *status = IWL_D3_STATUS_RESET;
 578                 return 0;
 579         }
 580
 581         /*
 582          * Also enables interrupts - none will happen as the device doesn't
 583          * know we're waking it up, only when the opmode actually tells it
 584          * after this call.
 585          */
 586         iwl_pcie_reset_ict(trans);
 587
 588         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 589         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 590
 591         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 592                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 593                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 594                            25000);
 595         if (ret) {
 596                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 597                 return ret;
 598         }
 599
 600         iwl_trans_pcie_tx_reset(trans);
 601
 602         ret = iwl_pcie_rx_init(trans);
 603         if (ret) {
 604                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 605                 return ret;
 606         }
 607
 608         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 609                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 610
 611         *status = IWL_D3_STATUS_ALIVE;
 612         return 0;
 613 }
 614
 615 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 616 {
 617         bool hw_rfkill;
 618         int err;
 619
 620         err = iwl_pcie_prepare_card_hw(trans);
 621         if (err) {
 622                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 623                 return err;
 624         }
 625
 626         iwl_pcie_apm_init(trans);
 627
 628         /* From now on, the op_mode will be kept updated about RF kill state */
 629         iwl_enable_rfkill_int(trans);
 630
 631         hw_rfkill = iwl_is_rfkill_set(trans);
 632         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 633
 634         return 0;
 635 }
 636
 637 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 638                                    bool op_mode_leaving)
 639 {
 640         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 641         bool hw_rfkill;
 642         unsigned long flags;
 643
 644         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 645         iwl_disable_interrupts(trans);
 646         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 647
 648         iwl_pcie_apm_stop(trans);
 649
 650         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 651         iwl_disable_interrupts(trans);
 652         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 653
 654         iwl_pcie_disable_ict(trans);
 655
 656         if (!op_mode_leaving) {
 657                 /*
 658                  * Even if we stop the HW, we still want the RF kill
 659                  * interrupt
 660                  */
 661                 iwl_enable_rfkill_int(trans);
 662
 663                 /*
 664                  * Check again since the RF kill state may have changed while
 665                  * all the interrupts were disabled, in this case we couldn't
 666                  * receive the RF kill interrupt and update the state in the
 667                  * op_mode.
 668                  */
 669                 hw_rfkill = iwl_is_rfkill_set(trans);
 670                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 671         }
 672 }
 673
 674 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 675 {
 676         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 677 }
 678
 679 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 680 {
 681         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 682 }
 683
 684 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 685 {
 686         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 687 }
 688
 689 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 690 {
 691         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
 692         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 693 }
 694
 695 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 696                                       u32 val)
 697 {
 698         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 699                                ((addr & 0x0000FFFF) | (3 << 24)));
 700         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 701 }
 702
 703 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 704                                      const struct iwl_trans_config *trans_cfg)
 705 {
 706         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 707
 708         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 709         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 710         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 711                 trans_pcie->n_no_reclaim_cmds = 0;
 712         else
 713                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 714         if (trans_pcie->n_no_reclaim_cmds)
 715                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 716                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 717
 718         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 719         if (trans_pcie->rx_buf_size_8k)
 720                 trans_pcie->rx_page_order = get_order(8 * 1024);
 721         else
 722                 trans_pcie->rx_page_order = get_order(4 * 1024);
 723
 724         trans_pcie->wd_timeout =
 725                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 726
 727         trans_pcie->command_names = trans_cfg->command_names;
 728         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 729 }
 730
 731 void iwl_trans_pcie_free(struct iwl_trans *trans)
 732 {
 733         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 734
 735         synchronize_irq(trans_pcie->pci_dev->irq);
 736         tasklet_kill(&trans_pcie->irq_tasklet);
 737
 738         iwl_pcie_tx_free(trans);
 739         iwl_pcie_rx_free(trans);
 740
 741         free_irq(trans_pcie->pci_dev->irq, trans);
 742         iwl_pcie_free_ict(trans);
 743
 744         pci_disable_msi(trans_pcie->pci_dev);
 745         iounmap(trans_pcie->hw_base);
 746         pci_release_regions(trans_pcie->pci_dev);
 747         pci_disable_device(trans_pcie->pci_dev);
 748         kmem_cache_destroy(trans->dev_cmd_pool);
 749
 750         kfree(trans);
 751 }
 752
 753 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 754 {
 755         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 756
 757         if (state)
 758                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 759         else
 760                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 761 }
 762
 763 #ifdef CONFIG_PM_SLEEP
 764 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
 765 {
 766         return 0;
 767 }
 768
 769 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
 770 {
 771         bool hw_rfkill;
 772
 773         iwl_enable_rfkill_int(trans);
 774
 775         hw_rfkill = iwl_is_rfkill_set(trans);
 776         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 777
 778         return 0;
 779 }
 780 #endif /* CONFIG_PM_SLEEP */
 781
 782 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
 783 {
 784         int ret;
 785
 786         lockdep_assert_held(&trans->reg_lock);
 787
 788         /* this bit wakes up the NIC */
 789         __iwl_set_bit(trans, CSR_GP_CNTRL,
 790                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 791
 792         /*
 793          * These bits say the device is running, and should keep running for
 794          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 795          * but they do not indicate that embedded SRAM is restored yet;
 796          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 797          * to/from host DRAM when sleeping/waking for power-saving.
 798          * Each direction takes approximately 1/4 millisecond; with this
 799          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 800          * series of register accesses are expected (e.g. reading Event Log),
 801          * to keep device from sleeping.
 802          *
 803          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 804          * SRAM is okay/restored.  We don't check that here because this call
 805          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 806          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 807          *
 808          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 809          * and do not save/restore SRAM when power cycling.
 810          */
 811         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 812                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 813                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 814                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 815         if (unlikely(ret < 0)) {
 816                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 817                 if (!silent) {
 818                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 819                         WARN_ONCE(1,
 820                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 821                                   val);
 822                         return false;
 823                 }
 824         }
 825
 826         return true;
 827 }
 828
 829 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
 830 {
 831         lockdep_assert_held(&trans->reg_lock);
 832         __iwl_clear_bit(trans, CSR_GP_CNTRL,
 833                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 834         /*
 835          * Above we read the CSR_GP_CNTRL register, which will flush
 836          * any previous writes, but we need the write that clears the
 837          * MAC_ACCESS_REQ bit to be performed before any other writes
 838          * scheduled on different CPUs (after we drop reg_lock).
 839          */
 840         mmiowb();
 841 }
 842
 843 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 844                                    void *buf, int dwords)
 845 {
 846         unsigned long flags;
 847         int offs, ret = 0;
 848         u32 *vals = buf;
 849
 850         spin_lock_irqsave(&trans->reg_lock, flags);
 851         if (iwl_trans_grab_nic_access(trans, false)) {
 852                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
 853                 for (offs = 0; offs < dwords; offs++)
 854                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 855                 iwl_trans_release_nic_access(trans);
 856         } else {
 857                 ret = -EBUSY;
 858         }
 859         spin_unlock_irqrestore(&trans->reg_lock, flags);
 860         return ret;
 861 }
 862
 863 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
 864                                     void *buf, int dwords)
 865 {
 866         unsigned long flags;
 867         int offs, ret = 0;
 868         u32 *vals = buf;
 869
 870         spin_lock_irqsave(&trans->reg_lock, flags);
 871         if (iwl_trans_grab_nic_access(trans, false)) {
 872                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
 873                 for (offs = 0; offs < dwords; offs++)
 874                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
 875                                     vals ? vals[offs] : 0);
 876                 iwl_trans_release_nic_access(trans);
 877         } else {
 878                 ret = -EBUSY;
 879         }
 880         spin_unlock_irqrestore(&trans->reg_lock, flags);
 881         return ret;
 882 }
 883
 884 #define IWL_FLUSH_WAIT_MS       2000
 885
 886 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
 887 {
 888         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 889         struct iwl_txq *txq;
 890         struct iwl_queue *q;
 891         int cnt;
 892         unsigned long now = jiffies;
 893         u32 scd_sram_addr;
 894         u8 buf[16];
 895         int ret = 0;
 896
 897         /* waiting for all the tx frames complete might take a while */
 898         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 899                 if (cnt == trans_pcie->cmd_queue)
 900                         continue;
 901                 txq = &trans_pcie->txq[cnt];
 902                 q = &txq->q;
 903                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
 904                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
 905                         msleep(1);
 906
 907                 if (q->read_ptr != q->write_ptr) {
 908                         IWL_ERR(trans,
 909                                 "fail to flush all tx fifo queues Q %d\n", cnt);
 910                         ret = -ETIMEDOUT;
 911                         break;
 912                 }
 913         }
 914
 915         if (!ret)
 916                 return 0;
 917
 918         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 919                 txq->q.read_ptr, txq->q.write_ptr);
 920
 921         scd_sram_addr = trans_pcie->scd_base_addr +
 922                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 923         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 924
 925         iwl_print_hex_error(trans, buf, sizeof(buf));
 926
 927         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
 928                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
 929                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
 930
 931         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 932                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
 933                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 934                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 935                 u32 tbl_dw =
 936                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
 937                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
 938
 939                 if (cnt & 0x1)
 940                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 941                 else
 942                         tbl_dw = tbl_dw & 0x0000FFFF;
 943
 944                 IWL_ERR(trans,
 945                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 946                         cnt, active ? "" : "in", fifo, tbl_dw,
 947                         iwl_read_prph(trans,
 948                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
 949                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
 950         }
 951
 952         return ret;
 953 }
 954
 955 static const char *get_fh_string(int cmd)
 956 {
 957 #define IWL_CMD(x) case x: return #x
 958         switch (cmd) {
 959         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
 960         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
 961         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
 962         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
 963         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
 964         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
 965         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
 966         IWL_CMD(FH_TSSR_TX_STATUS_REG);
 967         IWL_CMD(FH_TSSR_TX_ERROR_REG);
 968         default:
 969                 return "UNKNOWN";
 970         }
 971 #undef IWL_CMD
 972 }
 973
 974 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
 975 {
 976         int i;
 977         static const u32 fh_tbl[] = {
 978                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
 979                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 980                 FH_RSCSR_CHNL0_WPTR,
 981                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
 982                 FH_MEM_RSSR_SHARED_CTRL_REG,
 983                 FH_MEM_RSSR_RX_STATUS_REG,
 984                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
 985                 FH_TSSR_TX_STATUS_REG,
 986                 FH_TSSR_TX_ERROR_REG
 987         };
 988
 989 #ifdef CONFIG_IWLWIFI_DEBUGFS
 990         if (buf) {
 991                 int pos = 0;
 992                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
 993
 994                 *buf = kmalloc(bufsz, GFP_KERNEL);
 995                 if (!*buf)
 996                         return -ENOMEM;
 997
 998                 pos += scnprintf(*buf + pos, bufsz - pos,
 999                                 "FH register values:\n");
1000
1001                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1002                         pos += scnprintf(*buf + pos, bufsz - pos,
1003                                 "  %34s: 0X%08x\n",
1004                                 get_fh_string(fh_tbl[i]),
1005                                 iwl_read_direct32(trans, fh_tbl[i]));
1006
1007                 return pos;
1008         }
1009 #endif
1010
1011         IWL_ERR(trans, "FH register values:\n");
1012         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1013                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1014                         get_fh_string(fh_tbl[i]),
1015                         iwl_read_direct32(trans, fh_tbl[i]));
1016
1017         return 0;
1018 }
1019
1020 static const char *get_csr_string(int cmd)
1021 {
1022 #define IWL_CMD(x) case x: return #x
1023         switch (cmd) {
1024         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1025         IWL_CMD(CSR_INT_COALESCING);
1026         IWL_CMD(CSR_INT);
1027         IWL_CMD(CSR_INT_MASK);
1028         IWL_CMD(CSR_FH_INT_STATUS);
1029         IWL_CMD(CSR_GPIO_IN);
1030         IWL_CMD(CSR_RESET);
1031         IWL_CMD(CSR_GP_CNTRL);
1032         IWL_CMD(CSR_HW_REV);
1033         IWL_CMD(CSR_EEPROM_REG);
1034         IWL_CMD(CSR_EEPROM_GP);
1035         IWL_CMD(CSR_OTP_GP_REG);
1036         IWL_CMD(CSR_GIO_REG);
1037         IWL_CMD(CSR_GP_UCODE_REG);
1038         IWL_CMD(CSR_GP_DRIVER_REG);
1039         IWL_CMD(CSR_UCODE_DRV_GP1);
1040         IWL_CMD(CSR_UCODE_DRV_GP2);
1041         IWL_CMD(CSR_LED_REG);
1042         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1043         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1044         IWL_CMD(CSR_ANA_PLL_CFG);
1045         IWL_CMD(CSR_HW_REV_WA_REG);
1046         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1047         default:
1048                 return "UNKNOWN";
1049         }
1050 #undef IWL_CMD
1051 }
1052
1053 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1054 {
1055         int i;
1056         static const u32 csr_tbl[] = {
1057                 CSR_HW_IF_CONFIG_REG,
1058                 CSR_INT_COALESCING,
1059                 CSR_INT,
1060                 CSR_INT_MASK,
1061                 CSR_FH_INT_STATUS,
1062                 CSR_GPIO_IN,
1063                 CSR_RESET,
1064                 CSR_GP_CNTRL,
1065                 CSR_HW_REV,
1066                 CSR_EEPROM_REG,
1067                 CSR_EEPROM_GP,
1068                 CSR_OTP_GP_REG,
1069                 CSR_GIO_REG,
1070                 CSR_GP_UCODE_REG,
1071                 CSR_GP_DRIVER_REG,
1072                 CSR_UCODE_DRV_GP1,
1073                 CSR_UCODE_DRV_GP2,
1074                 CSR_LED_REG,
1075                 CSR_DRAM_INT_TBL_REG,
1076                 CSR_GIO_CHICKEN_BITS,
1077                 CSR_ANA_PLL_CFG,
1078                 CSR_HW_REV_WA_REG,
1079                 CSR_DBG_HPET_MEM_REG
1080         };
1081         IWL_ERR(trans, "CSR values:\n");
1082         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1083                 "CSR_INT_PERIODIC_REG)\n");
1084         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1085                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1086                         get_csr_string(csr_tbl[i]),
1087                         iwl_read32(trans, csr_tbl[i]));
1088         }
1089 }
1090
1091 #ifdef CONFIG_IWLWIFI_DEBUGFS
1092 /* create and remove of files */
1093 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1094         if (!debugfs_create_file(#name, mode, parent, trans,            \
1095                                  &iwl_dbgfs_##name##_ops))              \
1096                 goto err;                                               \
1097 } while (0)
1098
1099 /* file operation */
1100 #define DEBUGFS_READ_FUNC(name)                                         \
1101 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1102                                         char __user *user_buf,          \
1103                                         size_t count, loff_t *ppos);
1104
1105 #define DEBUGFS_WRITE_FUNC(name)                                        \
1106 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1107                                         const char __user *user_buf,    \
1108                                         size_t count, loff_t *ppos);
1109
1110 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1111         DEBUGFS_READ_FUNC(name);                                        \
1112 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1113         .read = iwl_dbgfs_##name##_read,                                \
1114         .open = simple_open,                                            \
1115         .llseek = generic_file_llseek,                                  \
1116 };
1117
1118 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1119         DEBUGFS_WRITE_FUNC(name);                                       \
1120 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1121         .write = iwl_dbgfs_##name##_write,                              \
1122         .open = simple_open,                                            \
1123         .llseek = generic_file_llseek,                                  \
1124 };
1125
1126 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1127         DEBUGFS_READ_FUNC(name);                                        \
1128         DEBUGFS_WRITE_FUNC(name);                                       \
1129 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1130         .write = iwl_dbgfs_##name##_write,                              \
1131         .read = iwl_dbgfs_##name##_read,                                \
1132         .open = simple_open,                                            \
1133         .llseek = generic_file_llseek,                                  \
1134 };
1135
1136 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1137                                        char __user *user_buf,
1138                                        size_t count, loff_t *ppos)
1139 {
1140         struct iwl_trans *trans = file->private_data;
1141         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1142         struct iwl_txq *txq;
1143         struct iwl_queue *q;
1144         char *buf;
1145         int pos = 0;
1146         int cnt;
1147         int ret;
1148         size_t bufsz;
1149
1150         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1151
1152         if (!trans_pcie->txq)
1153                 return -EAGAIN;
1154
1155         buf = kzalloc(bufsz, GFP_KERNEL);
1156         if (!buf)
1157                 return -ENOMEM;
1158
1159         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1160                 txq = &trans_pcie->txq[cnt];
1161                 q = &txq->q;
1162                 pos += scnprintf(buf + pos, bufsz - pos,
1163                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1164                                 cnt, q->read_ptr, q->write_ptr,
1165                                 !!test_bit(cnt, trans_pcie->queue_used),
1166                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1167         }
1168         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1169         kfree(buf);
1170         return ret;
1171 }
1172
1173 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1174                                        char __user *user_buf,
1175                                        size_t count, loff_t *ppos)
1176 {
1177         struct iwl_trans *trans = file->private_data;
1178         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1179         struct iwl_rxq *rxq = &trans_pcie->rxq;
1180         char buf[256];
1181         int pos = 0;
1182         const size_t bufsz = sizeof(buf);
1183
1184         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1185                                                 rxq->read);
1186         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1187                                                 rxq->write);
1188         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1189                                                 rxq->free_count);
1190         if (rxq->rb_stts) {
1191                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1192                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1193         } else {
1194                 pos += scnprintf(buf + pos, bufsz - pos,
1195                                         "closed_rb_num: Not Allocated\n");
1196         }
1197         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1198 }
1199
1200 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1201                                         char __user *user_buf,
1202                                         size_t count, loff_t *ppos)
1203 {
1204         struct iwl_trans *trans = file->private_data;
1205         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1206         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1207
1208         int pos = 0;
1209         char *buf;
1210         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1211         ssize_t ret;
1212
1213         buf = kzalloc(bufsz, GFP_KERNEL);
1214         if (!buf)
1215                 return -ENOMEM;
1216
1217         pos += scnprintf(buf + pos, bufsz - pos,
1218                         "Interrupt Statistics Report:\n");
1219
1220         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1221                 isr_stats->hw);
1222         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1223                 isr_stats->sw);
1224         if (isr_stats->sw || isr_stats->hw) {
1225                 pos += scnprintf(buf + pos, bufsz - pos,
1226                         "\tLast Restarting Code:  0x%X\n",
1227                         isr_stats->err_code);
1228         }
1229 #ifdef CONFIG_IWLWIFI_DEBUG
1230         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1231                 isr_stats->sch);
1232         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1233                 isr_stats->alive);
1234 #endif
1235         pos += scnprintf(buf + pos, bufsz - pos,
1236                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1237
1238         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1239                 isr_stats->ctkill);
1240
1241         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1242                 isr_stats->wakeup);
1243
1244         pos += scnprintf(buf + pos, bufsz - pos,
1245                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1246
1247         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1248                 isr_stats->tx);
1249
1250         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1251                 isr_stats->unhandled);
1252
1253         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1254         kfree(buf);
1255         return ret;
1256 }
1257
1258 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1259                                          const char __user *user_buf,
1260                                          size_t count, loff_t *ppos)
1261 {
1262         struct iwl_trans *trans = file->private_data;
1263         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1264         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1265
1266         char buf[8];
1267         int buf_size;
1268         u32 reset_flag;
1269
1270         memset(buf, 0, sizeof(buf));
1271         buf_size = min(count, sizeof(buf) -  1);
1272         if (copy_from_user(buf, user_buf, buf_size))
1273                 return -EFAULT;
1274         if (sscanf(buf, "%x", &reset_flag) != 1)
1275                 return -EFAULT;
1276         if (reset_flag == 0)
1277                 memset(isr_stats, 0, sizeof(*isr_stats));
1278
1279         return count;
1280 }
1281
1282 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1283                                    const char __user *user_buf,
1284                                    size_t count, loff_t *ppos)
1285 {
1286         struct iwl_trans *trans = file->private_data;
1287         char buf[8];
1288         int buf_size;
1289         int csr;
1290
1291         memset(buf, 0, sizeof(buf));
1292         buf_size = min(count, sizeof(buf) -  1);
1293         if (copy_from_user(buf, user_buf, buf_size))
1294                 return -EFAULT;
1295         if (sscanf(buf, "%d", &csr) != 1)
1296                 return -EFAULT;
1297
1298         iwl_pcie_dump_csr(trans);
1299
1300         return count;
1301 }
1302
1303 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1304                                      char __user *user_buf,
1305                                      size_t count, loff_t *ppos)
1306 {
1307         struct iwl_trans *trans = file->private_data;
1308         char *buf = NULL;
1309         int pos = 0;
1310         ssize_t ret = -EFAULT;
1311
1312         ret = pos = iwl_pcie_dump_fh(trans, &buf);
1313         if (buf) {
1314                 ret = simple_read_from_buffer(user_buf,
1315                                               count, ppos, buf, pos);
1316                 kfree(buf);
1317         }
1318
1319         return ret;
1320 }
1321
1322 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1323                                           const char __user *user_buf,
1324                                           size_t count, loff_t *ppos)
1325 {
1326         struct iwl_trans *trans = file->private_data;
1327
1328         if (!trans->op_mode)
1329                 return -EAGAIN;
1330
1331         local_bh_disable();
1332         iwl_op_mode_nic_error(trans->op_mode);
1333         local_bh_enable();
1334
1335         return count;
1336 }
1337
1338 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1339 DEBUGFS_READ_FILE_OPS(fh_reg);
1340 DEBUGFS_READ_FILE_OPS(rx_queue);
1341 DEBUGFS_READ_FILE_OPS(tx_queue);
1342 DEBUGFS_WRITE_FILE_OPS(csr);
1343 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1344
1345 /*
1346  * Create the debugfs files and directories
1347  *
1348  */
1349 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1350                                          struct dentry *dir)
1351 {
1352         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1353         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1354         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1355         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1356         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1357         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1358         return 0;
1359
1360 err:
1361         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1362         return -ENOMEM;
1363 }
1364 #else
1365 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1366                                          struct dentry *dir)
1367 {
1368         return 0;
1369 }
1370 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1371
1372 static const struct iwl_trans_ops trans_ops_pcie = {
1373         .start_hw = iwl_trans_pcie_start_hw,
1374         .stop_hw = iwl_trans_pcie_stop_hw,
1375         .fw_alive = iwl_trans_pcie_fw_alive,
1376         .start_fw = iwl_trans_pcie_start_fw,
1377         .stop_device = iwl_trans_pcie_stop_device,
1378
1379         .d3_suspend = iwl_trans_pcie_d3_suspend,
1380         .d3_resume = iwl_trans_pcie_d3_resume,
1381
1382         .send_cmd = iwl_trans_pcie_send_hcmd,
1383
1384         .tx = iwl_trans_pcie_tx,
1385         .reclaim = iwl_trans_pcie_reclaim,
1386
1387         .txq_disable = iwl_trans_pcie_txq_disable,
1388         .txq_enable = iwl_trans_pcie_txq_enable,
1389
1390         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1391
1392         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1393
1394 #ifdef CONFIG_PM_SLEEP
1395         .suspend = iwl_trans_pcie_suspend,
1396         .resume = iwl_trans_pcie_resume,
1397 #endif
1398         .write8 = iwl_trans_pcie_write8,
1399         .write32 = iwl_trans_pcie_write32,
1400         .read32 = iwl_trans_pcie_read32,
1401         .read_prph = iwl_trans_pcie_read_prph,
1402         .write_prph = iwl_trans_pcie_write_prph,
1403         .read_mem = iwl_trans_pcie_read_mem,
1404         .write_mem = iwl_trans_pcie_write_mem,
1405         .configure = iwl_trans_pcie_configure,
1406         .set_pmi = iwl_trans_pcie_set_pmi,
1407         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1408         .release_nic_access = iwl_trans_pcie_release_nic_access
1409 };
1410
1411 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1412                                        const struct pci_device_id *ent,
1413                                        const struct iwl_cfg *cfg)
1414 {
1415         struct iwl_trans_pcie *trans_pcie;
1416         struct iwl_trans *trans;
1417         u16 pci_cmd;
1418         int err;
1419
1420         trans = kzalloc(sizeof(struct iwl_trans) +
1421                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1422
1423         if (!trans)
1424                 return NULL;
1425
1426         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1427
1428         trans->ops = &trans_ops_pcie;
1429         trans->cfg = cfg;
1430         trans_pcie->trans = trans;
1431         spin_lock_init(&trans_pcie->irq_lock);
1432         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1433
1434         /* W/A - seems to solve weird behavior. We need to remove this if we
1435          * don't want to stay in L1 all the time. This wastes a lot of power */
1436         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1437                                PCIE_LINK_STATE_CLKPM);
1438
1439         if (pci_enable_device(pdev)) {
1440                 err = -ENODEV;
1441                 goto out_no_pci;
1442         }
1443
1444         pci_set_master(pdev);
1445
1446         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1447         if (!err)
1448                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1449         if (err) {
1450                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1451                 if (!err)
1452                         err = pci_set_consistent_dma_mask(pdev,
1453                                                           DMA_BIT_MASK(32));
1454                 /* both attempts failed: */
1455                 if (err) {
1456                         dev_err(&pdev->dev, "No suitable DMA available\n");
1457                         goto out_pci_disable_device;
1458                 }
1459         }
1460
1461         err = pci_request_regions(pdev, DRV_NAME);
1462         if (err) {
1463                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1464                 goto out_pci_disable_device;
1465         }
1466
1467         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1468         if (!trans_pcie->hw_base) {
1469                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1470                 err = -ENODEV;
1471                 goto out_pci_release_regions;
1472         }
1473
1474         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1475          * PCI Tx retries from interfering with C3 CPU state */
1476         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1477
1478         err = pci_enable_msi(pdev);
1479         if (err) {
1480                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1481                 /* enable rfkill interrupt: hw bug w/a */
1482                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1483                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1484                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1485                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1486                 }
1487         }
1488
1489         trans->dev = &pdev->dev;
1490         trans_pcie->pci_dev = pdev;
1491         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1492         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1493         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1494                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1495
1496         /* Initialize the wait queue for commands */
1497         init_waitqueue_head(&trans_pcie->wait_command_queue);
1498         spin_lock_init(&trans->reg_lock);
1499
1500         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1501                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1502
1503         trans->dev_cmd_headroom = 0;
1504         trans->dev_cmd_pool =
1505                 kmem_cache_create(trans->dev_cmd_pool_name,
1506                                   sizeof(struct iwl_device_cmd)
1507                                   + trans->dev_cmd_headroom,
1508                                   sizeof(void *),
1509                                   SLAB_HWCACHE_ALIGN,
1510                                   NULL);
1511
1512         if (!trans->dev_cmd_pool)
1513                 goto out_pci_disable_msi;
1514
1515         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1516
1517         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1518                      iwl_pcie_tasklet, (unsigned long)trans);
1519
1520         if (iwl_pcie_alloc_ict(trans))
1521                 goto out_free_cmd_pool;
1522
1523         err = request_irq(pdev->irq, iwl_pcie_isr_ict,
1524                           IRQF_SHARED, DRV_NAME, trans);
1525         if (err) {
1526                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1527                 goto out_free_ict;
1528         }
1529
1530         return trans;
1531
1532 out_free_ict:
1533         iwl_pcie_free_ict(trans);
1534 out_free_cmd_pool:
1535         kmem_cache_destroy(trans->dev_cmd_pool);
1536 out_pci_disable_msi:
1537         pci_disable_msi(pdev);
1538 out_pci_release_regions:
1539         pci_release_regions(pdev);
1540 out_pci_disable_device:
1541         pci_disable_device(pdev);
1542 out_no_pci:
1543         kfree(trans);
1544         return NULL;
1545 }