drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  50  *    from this software without specific prior written permission.
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  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page = NULL;
 108         dma_addr_t phys;
 109         u32 size = 0;
 110         u8 power;
 111
 112         if (!max_power) {
 113                 /* default max_power is maximum */
 114                 max_power = 26;
 115         } else {
 116                 max_power += 11;
 117         }
 118
 119         if (WARN(max_power > 26,
 120                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 121                  max_power))
 122                 return;
 123
 124         if (trans_pcie->fw_mon_page) {
 125                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 126                                            trans_pcie->fw_mon_size,
 127                                            DMA_FROM_DEVICE);
 128                 return;
 129         }
 130
 131         phys = 0;
 132         for (power = max_power; power >= 11; power--) {
 133                 int order;
 134
 135                 size = BIT(power);
 136                 order = get_order(size);
 137                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 138                                    order);
 139                 if (!page)
 140                         continue;
 141
 142                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 143                                     DMA_FROM_DEVICE);
 144                 if (dma_mapping_error(trans->dev, phys)) {
 145                         __free_pages(page, order);
 146                         page = NULL;
 147                         continue;
 148                 }
 149                 IWL_INFO(trans,
 150                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 151                          size, order);
 152                 break;
 153         }
 154
 155         if (WARN_ON_ONCE(!page))
 156                 return;
 157
 158         if (power != max_power)
 159                 IWL_ERR(trans,
 160                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 161                         (unsigned long)BIT(power - 10),
 162                         (unsigned long)BIT(max_power - 10));
 163
 164         trans_pcie->fw_mon_page = page;
 165         trans_pcie->fw_mon_phys = phys;
 166         trans_pcie->fw_mon_size = size;
 167 }
 168
 169 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 170 {
 171         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 172                     ((reg & 0x0000ffff) | (2 << 28)));
 173         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 174 }
 175
 176 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 177 {
 178         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 179         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 180                     ((reg & 0x0000ffff) | (3 << 28)));
 181 }
 182
 183 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 184 {
 185         if (trans->cfg->apmg_not_supported)
 186                 return;
 187
 188         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 189                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 190                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 191                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 192         else
 193                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 194                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 195                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 196 }
 197
 198 /* PCI registers */
 199 #define PCI_CFG_RETRY_TIMEOUT   0x041
 200
 201 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 202 {
 203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 204         u16 lctl;
 205         u16 cap;
 206
 207         /*
 208          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 209          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 210          * If so (likely), disable L0S, so device moves directly L0->L1;
 211          *    costs negligible amount of power savings.
 212          * If not (unlikely), enable L0S, so there is at least some
 213          *    power savings, even without L1.
 214          */
 215         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 216         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 217                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 218         else
 219                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 220         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 221
 222         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 223         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 224         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 225                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 226                  trans->ltr_enabled ? "En" : "Dis");
 227 }
 228
 229 /*
 230  * Start up NIC's basic functionality after it has been reset
 231  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 232  * NOTE:  This does not load uCode nor start the embedded processor
 233  */
 234 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 235 {
 236         int ret = 0;
 237         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 238
 239         /*
 240          * Use "set_bit" below rather than "write", to preserve any hardware
 241          * bits already set by default after reset.
 242          */
 243
 244         /* Disable L0S exit timer (platform NMI Work/Around) */
 245         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 246                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 247                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 248
 249         /*
 250          * Disable L0s without affecting L1;
 251          *  don't wait for ICH L0s (ICH bug W/A)
 252          */
 253         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 254                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 255
 256         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 257         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 258
 259         /*
 260          * Enable HAP INTA (interrupt from management bus) to
 261          * wake device's PCI Express link L1a -> L0s
 262          */
 263         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 264                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 265
 266         iwl_pcie_apm_config(trans);
 267
 268         /* Configure analog phase-lock-loop before activating to D0A */
 269         if (trans->cfg->base_params->pll_cfg_val)
 270                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 271                             trans->cfg->base_params->pll_cfg_val);
 272
 273         /*
 274          * Set "initialization complete" bit to move adapter from
 275          * D0U* --> D0A* (powered-up active) state.
 276          */
 277         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 278
 279         /*
 280          * Wait for clock stabilization; once stabilized, access to
 281          * device-internal resources is supported, e.g. iwl_write_prph()
 282          * and accesses to uCode SRAM.
 283          */
 284         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 285                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 286                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 287         if (ret < 0) {
 288                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 289                 goto out;
 290         }
 291
 292         if (trans->cfg->host_interrupt_operation_mode) {
 293                 /*
 294                  * This is a bit of an abuse - This is needed for 7260 / 3160
 295                  * only check host_interrupt_operation_mode even if this is
 296                  * not related to host_interrupt_operation_mode.
 297                  *
 298                  * Enable the oscillator to count wake up time for L1 exit. This
 299                  * consumes slightly more power (100uA) - but allows to be sure
 300                  * that we wake up from L1 on time.
 301                  *
 302                  * This looks weird: read twice the same register, discard the
 303                  * value, set a bit, and yet again, read that same register
 304                  * just to discard the value. But that's the way the hardware
 305                  * seems to like it.
 306                  */
 307                 iwl_read_prph(trans, OSC_CLK);
 308                 iwl_read_prph(trans, OSC_CLK);
 309                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_read_prph(trans, OSC_CLK);
 312         }
 313
 314         /*
 315          * Enable DMA clock and wait for it to stabilize.
 316          *
 317          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 318          * bits do not disable clocks.  This preserves any hardware
 319          * bits already set by default in "CLK_CTRL_REG" after reset.
 320          */
 321         if (!trans->cfg->apmg_not_supported) {
 322                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 323                                APMG_CLK_VAL_DMA_CLK_RQT);
 324                 udelay(20);
 325
 326                 /* Disable L1-Active */
 327                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 328                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 329
 330                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 331                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 332                                APMG_RTC_INT_STT_RFKILL);
 333         }
 334
 335         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 336
 337 out:
 338         return ret;
 339 }
 340
 341 /*
 342  * Enable LP XTAL to avoid HW bug where device may consume much power if
 343  * FW is not loaded after device reset. LP XTAL is disabled by default
 344  * after device HW reset. Do it only if XTAL is fed by internal source.
 345  * Configure device's "persistence" mode to avoid resetting XTAL again when
 346  * SHRD_HW_RST occurs in S3.
 347  */
 348 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 349 {
 350         int ret;
 351         u32 apmg_gp1_reg;
 352         u32 apmg_xtal_cfg_reg;
 353         u32 dl_cfg_reg;
 354
 355         /* Force XTAL ON */
 356         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 357                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 358
 359         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 360         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 361
 362         udelay(10);
 363
 364         /*
 365          * Set "initialization complete" bit to move adapter from
 366          * D0U* --> D0A* (powered-up active) state.
 367          */
 368         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 369
 370         /*
 371          * Wait for clock stabilization; once stabilized, access to
 372          * device-internal resources is possible.
 373          */
 374         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 375                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            25000);
 378         if (WARN_ON(ret < 0)) {
 379                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 380                 /* Release XTAL ON request */
 381                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 382                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 383                 return;
 384         }
 385
 386         /*
 387          * Clear "disable persistence" to avoid LP XTAL resetting when
 388          * SHRD_HW_RST is applied in S3.
 389          */
 390         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 391                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 392
 393         /*
 394          * Force APMG XTAL to be active to prevent its disabling by HW
 395          * caused by APMG idle state.
 396          */
 397         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 398                                                     SHR_APMG_XTAL_CFG_REG);
 399         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 400                                  apmg_xtal_cfg_reg |
 401                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 402
 403         /*
 404          * Reset entire device again - do controller reset (results in
 405          * SHRD_HW_RST). Turn MAC off before proceeding.
 406          */
 407         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 408
 409         udelay(10);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 482                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 483                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 484                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 485                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 486                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 487                         mdelay(1);
 488                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 489                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 490                 }
 491                 mdelay(5);
 492         }
 493
 494         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 495
 496         /* Stop device's DMA activity */
 497         iwl_pcie_apm_stop_master(trans);
 498
 499         if (trans->cfg->lp_xtal_workaround) {
 500                 iwl_pcie_apm_lp_xtal_enable(trans);
 501                 return;
 502         }
 503
 504         /* Reset the entire device */
 505         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 506
 507         udelay(10);
 508
 509         /*
 510          * Clear "initialization complete" bit to move adapter from
 511          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 512          */
 513         iwl_clear_bit(trans, CSR_GP_CNTRL,
 514                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 515 }
 516
 517 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 518 {
 519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 520
 521         /* nic_init */
 522         spin_lock(&trans_pcie->irq_lock);
 523         iwl_pcie_apm_init(trans);
 524
 525         spin_unlock(&trans_pcie->irq_lock);
 526
 527         iwl_pcie_set_pwr(trans, false);
 528
 529         iwl_op_mode_nic_config(trans->op_mode);
 530
 531         /* Allocate the RX queue, or reset if it is already allocated */
 532         iwl_pcie_rx_init(trans);
 533
 534         /* Allocate or reset and init all Tx and Command queues */
 535         if (iwl_pcie_tx_init(trans))
 536                 return -ENOMEM;
 537
 538         if (trans->cfg->base_params->shadow_reg_enable) {
 539                 /* enable shadow regs in HW */
 540                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 541                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 542         }
 543
 544         return 0;
 545 }
 546
 547 #define HW_READY_TIMEOUT (50)
 548
 549 /* Note: returns poll_bit return value, which is >= 0 if success */
 550 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 551 {
 552         int ret;
 553
 554         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 555                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 556
 557         /* See if we got it */
 558         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 559                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 560                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 561                            HW_READY_TIMEOUT);
 562
 563         if (ret >= 0)
 564                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 565
 566         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 567         return ret;
 568 }
 569
 570 /* Note: returns standard 0/-ERROR code */
 571 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int t = 0;
 575         int iter;
 576
 577         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 578
 579         ret = iwl_pcie_set_hw_ready(trans);
 580         /* If the card is ready, exit 0 */
 581         if (ret >= 0)
 582                 return 0;
 583
 584         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 585                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 586         msleep(1);
 587
 588         for (iter = 0; iter < 10; iter++) {
 589                 /* If HW is not ready, prepare the conditions to check again */
 590                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 591                             CSR_HW_IF_CONFIG_REG_PREPARE);
 592
 593                 do {
 594                         ret = iwl_pcie_set_hw_ready(trans);
 595                         if (ret >= 0) {
 596                                 ret = 0;
 597                                 goto out;
 598                         }
 599
 600                         usleep_range(200, 1000);
 601                         t += 200;
 602                 } while (t < 150000);
 603                 msleep(25);
 604         }
 605
 606         IWL_ERR(trans, "Couldn't prepare the card\n");
 607
 608 out:
 609         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 610                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 611
 612         return ret;
 613 }
 614
 615 /*
 616  * ucode
 617  */
 618 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 619                                    dma_addr_t phy_addr, u32 byte_cnt)
 620 {
 621         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 622         int ret;
 623
 624         trans_pcie->ucode_write_complete = false;
 625
 626         iwl_write_direct32(trans,
 627                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 628                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 629
 630         iwl_write_direct32(trans,
 631                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 632                            dst_addr);
 633
 634         iwl_write_direct32(trans,
 635                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 636                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 637
 638         iwl_write_direct32(trans,
 639                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 640                            (iwl_get_dma_hi_addr(phy_addr)
 641                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 642
 643         iwl_write_direct32(trans,
 644                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 645                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 646                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 647                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 648
 649         iwl_write_direct32(trans,
 650                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 651                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 652                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 653                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 654
 655         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 656                                  trans_pcie->ucode_write_complete, 5 * HZ);
 657         if (!ret) {
 658                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 659                 return -ETIMEDOUT;
 660         }
 661
 662         return 0;
 663 }
 664
 665 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 666                             const struct fw_desc *section)
 667 {
 668         u8 *v_addr;
 669         dma_addr_t p_addr;
 670         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 671         int ret = 0;
 672
 673         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 674                      section_num);
 675
 676         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 677                                     GFP_KERNEL | __GFP_NOWARN);
 678         if (!v_addr) {
 679                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 680                 chunk_sz = PAGE_SIZE;
 681                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 682                                             &p_addr, GFP_KERNEL);
 683                 if (!v_addr)
 684                         return -ENOMEM;
 685         }
 686
 687         for (offset = 0; offset < section->len; offset += chunk_sz) {
 688                 u32 copy_size, dst_addr;
 689                 bool extended_addr = false;
 690
 691                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 692                 dst_addr = section->offset + offset;
 693
 694                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 695                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 696                         extended_addr = true;
 697
 698                 if (extended_addr)
 699                         iwl_set_bits_prph(trans, LMPM_CHICK,
 700                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 701
 702                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 703                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 704                                                    copy_size);
 705
 706                 if (extended_addr)
 707                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 708                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 709
 710                 if (ret) {
 711                         IWL_ERR(trans,
 712                                 "Could not load the [%d] uCode section\n",
 713                                 section_num);
 714                         break;
 715                 }
 716         }
 717
 718         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 719         return ret;
 720 }
 721
 722 /*
 723  * Driver Takes the ownership on secure machine before FW load
 724  * and prevent race with the BT load.
 725  * W/A for ROM bug. (should be remove in the next Si step)
 726  */
 727 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 728 {
 729         u32 val, loop = 1000;
 730
 731         /*
 732          * Check the RSA semaphore is accessible.
 733          * If the HW isn't locked and the rsa semaphore isn't accessible,
 734          * we are in trouble.
 735          */
 736         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 737         if (val & (BIT(1) | BIT(17))) {
 738                 IWL_INFO(trans,
 739                          "can't access the RSA semaphore it is write protected\n");
 740                 return 0;
 741         }
 742
 743         /* take ownership on the AUX IF */
 744         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 745         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 746
 747         do {
 748                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 749                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 750                 if (val == 0x1) {
 751                         iwl_write_prph(trans, RSA_ENABLE, 0);
 752                         return 0;
 753                 }
 754
 755                 udelay(10);
 756                 loop--;
 757         } while (loop > 0);
 758
 759         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 760         return -EIO;
 761 }
 762
 763 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 764                                            const struct fw_img *image,
 765                                            int cpu,
 766                                            int *first_ucode_section)
 767 {
 768         int shift_param;
 769         int i, ret = 0, sec_num = 0x1;
 770         u32 val, last_read_idx = 0;
 771
 772         if (cpu == 1) {
 773                 shift_param = 0;
 774                 *first_ucode_section = 0;
 775         } else {
 776                 shift_param = 16;
 777                 (*first_ucode_section)++;
 778         }
 779
 780         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 781                 last_read_idx = i;
 782
 783                 /*
 784                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 785                  * CPU1 to CPU2.
 786                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 787                  * CPU2 non paged to CPU2 paging sec.
 788                  */
 789                 if (!image->sec[i].data ||
 790                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 791                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 792                         IWL_DEBUG_FW(trans,
 793                                      "Break since Data not valid or Empty section, sec = %d\n",
 794                                      i);
 795                         break;
 796                 }
 797
 798                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 799                 if (ret)
 800                         return ret;
 801
 802                 /* Notify the ucode of the loaded section number and status */
 803                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 804                 val = val | (sec_num << shift_param);
 805                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 806                 sec_num = (sec_num << 1) | 0x1;
 807         }
 808
 809         *first_ucode_section = last_read_idx;
 810
 811         if (cpu == 1)
 812                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 813         else
 814                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 815
 816         return 0;
 817 }
 818
 819 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 820                                       const struct fw_img *image,
 821                                       int cpu,
 822                                       int *first_ucode_section)
 823 {
 824         int shift_param;
 825         int i, ret = 0;
 826         u32 last_read_idx = 0;
 827
 828         if (cpu == 1) {
 829                 shift_param = 0;
 830                 *first_ucode_section = 0;
 831         } else {
 832                 shift_param = 16;
 833                 (*first_ucode_section)++;
 834         }
 835
 836         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 837                 last_read_idx = i;
 838
 839                 /*
 840                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 841                  * CPU1 to CPU2.
 842                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 843                  * CPU2 non paged to CPU2 paging sec.
 844                  */
 845                 if (!image->sec[i].data ||
 846                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 847                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 848                         IWL_DEBUG_FW(trans,
 849                                      "Break since Data not valid or Empty section, sec = %d\n",
 850                                      i);
 851                         break;
 852                 }
 853
 854                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 855                 if (ret)
 856                         return ret;
 857         }
 858
 859         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 860                 iwl_set_bits_prph(trans,
 861                                   CSR_UCODE_LOAD_STATUS_ADDR,
 862                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 863                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 864                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 865                                         shift_param);
 866
 867         *first_ucode_section = last_read_idx;
 868
 869         return 0;
 870 }
 871
 872 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 873 {
 874         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 875         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 876         int i;
 877
 878         if (dest->version)
 879                 IWL_ERR(trans,
 880                         "DBG DEST version is %d - expect issues\n",
 881                         dest->version);
 882
 883         IWL_INFO(trans, "Applying debug destination %s\n",
 884                  get_fw_dbg_mode_string(dest->monitor_mode));
 885
 886         if (dest->monitor_mode == EXTERNAL_MODE)
 887                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 888         else
 889                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 890
 891         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 892                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 893                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 894
 895                 switch (dest->reg_ops[i].op) {
 896                 case CSR_ASSIGN:
 897                         iwl_write32(trans, addr, val);
 898                         break;
 899                 case CSR_SETBIT:
 900                         iwl_set_bit(trans, addr, BIT(val));
 901                         break;
 902                 case CSR_CLEARBIT:
 903                         iwl_clear_bit(trans, addr, BIT(val));
 904                         break;
 905                 case PRPH_ASSIGN:
 906                         iwl_write_prph(trans, addr, val);
 907                         break;
 908                 case PRPH_SETBIT:
 909                         iwl_set_bits_prph(trans, addr, BIT(val));
 910                         break;
 911                 case PRPH_CLEARBIT:
 912                         iwl_clear_bits_prph(trans, addr, BIT(val));
 913                         break;
 914                 case PRPH_BLOCKBIT:
 915                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 916                                 IWL_ERR(trans,
 917                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 918                                         val, addr);
 919                                 goto monitor;
 920                         }
 921                         break;
 922                 default:
 923                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 924                                 dest->reg_ops[i].op);
 925                         break;
 926                 }
 927         }
 928
 929 monitor:
 930         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 931                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 932                                trans_pcie->fw_mon_phys >> dest->base_shift);
 933                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 934                                (trans_pcie->fw_mon_phys +
 935                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 936         }
 937 }
 938
 939 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 940                                 const struct fw_img *image)
 941 {
 942         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 943         int ret = 0;
 944         int first_ucode_section;
 945
 946         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 947                      image->is_dual_cpus ? "Dual" : "Single");
 948
 949         /* load to FW the binary non secured sections of CPU1 */
 950         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 951         if (ret)
 952                 return ret;
 953
 954         if (image->is_dual_cpus) {
 955                 /* set CPU2 header address */
 956                 iwl_write_prph(trans,
 957                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 958                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 959
 960                 /* load to FW the binary sections of CPU2 */
 961                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 962                                                  &first_ucode_section);
 963                 if (ret)
 964                         return ret;
 965         }
 966
 967         /* supported for 7000 only for the moment */
 968         if (iwlwifi_mod_params.fw_monitor &&
 969             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 970                 iwl_pcie_alloc_fw_monitor(trans, 0);
 971
 972                 if (trans_pcie->fw_mon_size) {
 973                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 974                                        trans_pcie->fw_mon_phys >> 4);
 975                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 976                                        (trans_pcie->fw_mon_phys +
 977                                         trans_pcie->fw_mon_size) >> 4);
 978                 }
 979         } else if (trans->dbg_dest_tlv) {
 980                 iwl_pcie_apply_destination(trans);
 981         }
 982
 983         /* release CPU reset */
 984         iwl_write32(trans, CSR_RESET, 0);
 985
 986         return 0;
 987 }
 988
 989 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 990                                           const struct fw_img *image)
 991 {
 992         int ret = 0;
 993         int first_ucode_section;
 994
 995         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 996                      image->is_dual_cpus ? "Dual" : "Single");
 997
 998         if (trans->dbg_dest_tlv)
 999                 iwl_pcie_apply_destination(trans);
1000
1001         /* TODO: remove in the next Si step */
1002         ret = iwl_pcie_rsa_race_bug_wa(trans);
1003         if (ret)
1004                 return ret;
1005
1006         /* configure the ucode to be ready to get the secured image */
1007         /* release CPU reset */
1008         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1009
1010         /* load to FW the binary Secured sections of CPU1 */
1011         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1012                                               &first_ucode_section);
1013         if (ret)
1014                 return ret;
1015
1016         /* load to FW the binary sections of CPU2 */
1017         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1018                                                &first_ucode_section);
1019 }
1020
1021 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1022                                    const struct fw_img *fw, bool run_in_rfkill)
1023 {
1024         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1025         bool hw_rfkill;
1026         int ret;
1027
1028         mutex_lock(&trans_pcie->mutex);
1029
1030         /* Someone called stop_device, don't try to start_fw */
1031         if (trans_pcie->is_down) {
1032                 IWL_WARN(trans,
1033                          "Can't start_fw since the HW hasn't been started\n");
1034                 ret = EIO;
1035                 goto out;
1036         }
1037
1038         /* This may fail if AMT took ownership of the device */
1039         if (iwl_pcie_prepare_card_hw(trans)) {
1040                 IWL_WARN(trans, "Exit HW not ready\n");
1041                 ret = -EIO;
1042                 goto out;
1043         }
1044
1045         iwl_enable_rfkill_int(trans);
1046
1047         /* If platform's RF_KILL switch is NOT set to KILL */
1048         hw_rfkill = iwl_is_rfkill_set(trans);
1049         if (hw_rfkill)
1050                 set_bit(STATUS_RFKILL, &trans->status);
1051         else
1052                 clear_bit(STATUS_RFKILL, &trans->status);
1053         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1054         if (hw_rfkill && !run_in_rfkill) {
1055                 ret = -ERFKILL;
1056                 goto out;
1057         }
1058
1059         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1060
1061         ret = iwl_pcie_nic_init(trans);
1062         if (ret) {
1063                 IWL_ERR(trans, "Unable to init nic\n");
1064                 goto out;
1065         }
1066
1067         /* make sure rfkill handshake bits are cleared */
1068         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1069         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1070                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1071
1072         /* clear (again), then enable host interrupts */
1073         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1074         iwl_enable_interrupts(trans);
1075
1076         /* really make sure rfkill handshake bits are cleared */
1077         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1078         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1079
1080         /* Load the given image to the HW */
1081         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1082                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1083         else
1084                 ret = iwl_pcie_load_given_ucode(trans, fw);
1085
1086 out:
1087         mutex_unlock(&trans_pcie->mutex);
1088         return ret;
1089 }
1090
1091 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1092 {
1093         iwl_pcie_reset_ict(trans);
1094         iwl_pcie_tx_start(trans, scd_addr);
1095 }
1096
1097 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1098 {
1099         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1100         bool hw_rfkill, was_hw_rfkill;
1101
1102         lockdep_assert_held(&trans_pcie->mutex);
1103
1104         if (trans_pcie->is_down)
1105                 return;
1106
1107         trans_pcie->is_down = true;
1108
1109         was_hw_rfkill = iwl_is_rfkill_set(trans);
1110
1111         /* tell the device to stop sending interrupts */
1112         spin_lock(&trans_pcie->irq_lock);
1113         iwl_disable_interrupts(trans);
1114         spin_unlock(&trans_pcie->irq_lock);
1115
1116         /* device going down, Stop using ICT table */
1117         iwl_pcie_disable_ict(trans);
1118
1119         /*
1120          * If a HW restart happens during firmware loading,
1121          * then the firmware loading might call this function
1122          * and later it might be called again due to the
1123          * restart. So don't process again if the device is
1124          * already dead.
1125          */
1126         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1127                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1128                 iwl_pcie_tx_stop(trans);
1129                 iwl_pcie_rx_stop(trans);
1130
1131                 /* Power-down device's busmaster DMA clocks */
1132                 if (!trans->cfg->apmg_not_supported) {
1133                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1134                                        APMG_CLK_VAL_DMA_CLK_RQT);
1135                         udelay(5);
1136                 }
1137         }
1138
1139         /* Make sure (redundant) we've released our request to stay awake */
1140         iwl_clear_bit(trans, CSR_GP_CNTRL,
1141                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1142
1143         /* Stop the device, and put it in low power state */
1144         iwl_pcie_apm_stop(trans, false);
1145
1146         /* stop and reset the on-board processor */
1147         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1148         udelay(20);
1149
1150         /*
1151          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1152          * This is a bug in certain verions of the hardware.
1153          * Certain devices also keep sending HW RF kill interrupt all
1154          * the time, unless the interrupt is ACKed even if the interrupt
1155          * should be masked. Re-ACK all the interrupts here.
1156          */
1157         spin_lock(&trans_pcie->irq_lock);
1158         iwl_disable_interrupts(trans);
1159         spin_unlock(&trans_pcie->irq_lock);
1160
1161
1162         /* clear all status bits */
1163         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1164         clear_bit(STATUS_INT_ENABLED, &trans->status);
1165         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1166         clear_bit(STATUS_RFKILL, &trans->status);
1167
1168         /*
1169          * Even if we stop the HW, we still want the RF kill
1170          * interrupt
1171          */
1172         iwl_enable_rfkill_int(trans);
1173
1174         /*
1175          * Check again since the RF kill state may have changed while
1176          * all the interrupts were disabled, in this case we couldn't
1177          * receive the RF kill interrupt and update the state in the
1178          * op_mode.
1179          * Don't call the op_mode if the rkfill state hasn't changed.
1180          * This allows the op_mode to call stop_device from the rfkill
1181          * notification without endless recursion. Under very rare
1182          * circumstances, we might have a small recursion if the rfkill
1183          * state changed exactly now while we were called from stop_device.
1184          * This is very unlikely but can happen and is supported.
1185          */
1186         hw_rfkill = iwl_is_rfkill_set(trans);
1187         if (hw_rfkill)
1188                 set_bit(STATUS_RFKILL, &trans->status);
1189         else
1190                 clear_bit(STATUS_RFKILL, &trans->status);
1191         if (hw_rfkill != was_hw_rfkill)
1192                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1193
1194         /* re-take ownership to prevent other users from stealing the deivce */
1195         iwl_pcie_prepare_card_hw(trans);
1196 }
1197
1198 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1199 {
1200         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201
1202         mutex_lock(&trans_pcie->mutex);
1203         _iwl_trans_pcie_stop_device(trans, low_power);
1204         mutex_unlock(&trans_pcie->mutex);
1205 }
1206
1207 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1208 {
1209         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1210                 IWL_TRANS_GET_PCIE_TRANS(trans);
1211
1212         lockdep_assert_held(&trans_pcie->mutex);
1213
1214         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1215                 _iwl_trans_pcie_stop_device(trans, true);
1216 }
1217
1218 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1219 {
1220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1221
1222         if (trans->wowlan_d0i3) {
1223                 /* Enable persistence mode to avoid reset */
1224                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1225                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1226         }
1227
1228         iwl_disable_interrupts(trans);
1229
1230         /*
1231          * in testing mode, the host stays awake and the
1232          * hardware won't be reset (not even partially)
1233          */
1234         if (test)
1235                 return;
1236
1237         iwl_pcie_disable_ict(trans);
1238
1239         synchronize_irq(trans_pcie->pci_dev->irq);
1240
1241         iwl_clear_bit(trans, CSR_GP_CNTRL,
1242                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1243         iwl_clear_bit(trans, CSR_GP_CNTRL,
1244                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1245
1246         if (!trans->wowlan_d0i3) {
1247                 /*
1248                  * reset TX queues -- some of their registers reset during S3
1249                  * so if we don't reset everything here the D3 image would try
1250                  * to execute some invalid memory upon resume
1251                  */
1252                 iwl_trans_pcie_tx_reset(trans);
1253         }
1254
1255         iwl_pcie_set_pwr(trans, true);
1256 }
1257
1258 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1259                                     enum iwl_d3_status *status,
1260                                     bool test)
1261 {
1262         u32 val;
1263         int ret;
1264
1265         if (test) {
1266                 iwl_enable_interrupts(trans);
1267                 *status = IWL_D3_STATUS_ALIVE;
1268                 return 0;
1269         }
1270
1271         /*
1272          * Also enables interrupts - none will happen as the device doesn't
1273          * know we're waking it up, only when the opmode actually tells it
1274          * after this call.
1275          */
1276         iwl_pcie_reset_ict(trans);
1277
1278         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1280
1281         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1282                 udelay(2);
1283
1284         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1285                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1286                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1287                            25000);
1288         if (ret < 0) {
1289                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1290                 return ret;
1291         }
1292
1293         iwl_pcie_set_pwr(trans, false);
1294
1295         if (trans->wowlan_d0i3) {
1296                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1297                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1298         } else {
1299                 iwl_trans_pcie_tx_reset(trans);
1300
1301                 ret = iwl_pcie_rx_init(trans);
1302                 if (ret) {
1303                         IWL_ERR(trans,
1304                                 "Failed to resume the device (RX reset)\n");
1305                         return ret;
1306                 }
1307         }
1308
1309         val = iwl_read32(trans, CSR_RESET);
1310         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1311                 *status = IWL_D3_STATUS_RESET;
1312         else
1313                 *status = IWL_D3_STATUS_ALIVE;
1314
1315         return 0;
1316 }
1317
1318 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1319 {
1320         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1321         bool hw_rfkill;
1322         int err;
1323
1324         lockdep_assert_held(&trans_pcie->mutex);
1325
1326         err = iwl_pcie_prepare_card_hw(trans);
1327         if (err) {
1328                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1329                 return err;
1330         }
1331
1332         /* Reset the entire device */
1333         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1334
1335         usleep_range(10, 15);
1336
1337         iwl_pcie_apm_init(trans);
1338
1339         /* From now on, the op_mode will be kept updated about RF kill state */
1340         iwl_enable_rfkill_int(trans);
1341
1342         /* Set is_down to false here so that...*/
1343         trans_pcie->is_down = false;
1344
1345         hw_rfkill = iwl_is_rfkill_set(trans);
1346         if (hw_rfkill)
1347                 set_bit(STATUS_RFKILL, &trans->status);
1348         else
1349                 clear_bit(STATUS_RFKILL, &trans->status);
1350         /* ... rfkill can call stop_device and set it false if needed */
1351         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1352
1353         return 0;
1354 }
1355
1356 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1357 {
1358         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359         int ret;
1360
1361         mutex_lock(&trans_pcie->mutex);
1362         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1363         mutex_unlock(&trans_pcie->mutex);
1364
1365         return ret;
1366 }
1367
1368 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1369 {
1370         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1371
1372         mutex_lock(&trans_pcie->mutex);
1373
1374         /* disable interrupts - don't enable HW RF kill interrupt */
1375         spin_lock(&trans_pcie->irq_lock);
1376         iwl_disable_interrupts(trans);
1377         spin_unlock(&trans_pcie->irq_lock);
1378
1379         iwl_pcie_apm_stop(trans, true);
1380
1381         spin_lock(&trans_pcie->irq_lock);
1382         iwl_disable_interrupts(trans);
1383         spin_unlock(&trans_pcie->irq_lock);
1384
1385         iwl_pcie_disable_ict(trans);
1386
1387         mutex_unlock(&trans_pcie->mutex);
1388
1389         synchronize_irq(trans_pcie->pci_dev->irq);
1390 }
1391
1392 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1393 {
1394         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1395 }
1396
1397 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1398 {
1399         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1400 }
1401
1402 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1403 {
1404         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1405 }
1406
1407 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1408 {
1409         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1410                                ((reg & 0x000FFFFF) | (3 << 24)));
1411         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1412 }
1413
1414 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1415                                       u32 val)
1416 {
1417         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1418                                ((addr & 0x000FFFFF) | (3 << 24)));
1419         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1420 }
1421
1422 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1423 {
1424         WARN_ON(1);
1425         return 0;
1426 }
1427
1428 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1429                                      const struct iwl_trans_config *trans_cfg)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432
1433         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1434         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1435         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1436         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1437                 trans_pcie->n_no_reclaim_cmds = 0;
1438         else
1439                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1440         if (trans_pcie->n_no_reclaim_cmds)
1441                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1442                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1443
1444         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1445         if (trans_pcie->rx_buf_size_8k)
1446                 trans_pcie->rx_page_order = get_order(8 * 1024);
1447         else
1448                 trans_pcie->rx_page_order = get_order(4 * 1024);
1449
1450         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1451         trans_pcie->command_names = trans_cfg->command_names;
1452         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1453         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1454
1455         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1456         trans_pcie->ref_count = 1;
1457
1458         /* Initialize NAPI here - it should be before registering to mac80211
1459          * in the opmode but after the HW struct is allocated.
1460          * As this function may be called again in some corner cases don't
1461          * do anything if NAPI was already initialized.
1462          */
1463         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1464                 init_dummy_netdev(&trans_pcie->napi_dev);
1465                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1466                                      &trans_pcie->napi_dev,
1467                                      iwl_pcie_dummy_napi_poll, 64);
1468         }
1469 }
1470
1471 void iwl_trans_pcie_free(struct iwl_trans *trans)
1472 {
1473         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1474
1475         synchronize_irq(trans_pcie->pci_dev->irq);
1476
1477         iwl_pcie_tx_free(trans);
1478         iwl_pcie_rx_free(trans);
1479
1480         free_irq(trans_pcie->pci_dev->irq, trans);
1481         iwl_pcie_free_ict(trans);
1482
1483         pci_disable_msi(trans_pcie->pci_dev);
1484         iounmap(trans_pcie->hw_base);
1485         pci_release_regions(trans_pcie->pci_dev);
1486         pci_disable_device(trans_pcie->pci_dev);
1487
1488         if (trans_pcie->napi.poll)
1489                 netif_napi_del(&trans_pcie->napi);
1490
1491         iwl_pcie_free_fw_monitor(trans);
1492
1493         iwl_trans_free(trans);
1494 }
1495
1496 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1497 {
1498         if (state)
1499                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1500         else
1501                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1502 }
1503
1504 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1505                                                 unsigned long *flags)
1506 {
1507         int ret;
1508         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1509
1510         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1511
1512         if (trans_pcie->cmd_hold_nic_awake)
1513                 goto out;
1514
1515         /* this bit wakes up the NIC */
1516         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1517                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1518         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1519                 udelay(2);
1520
1521         /*
1522          * These bits say the device is running, and should keep running for
1523          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1524          * but they do not indicate that embedded SRAM is restored yet;
1525          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1526          * to/from host DRAM when sleeping/waking for power-saving.
1527          * Each direction takes approximately 1/4 millisecond; with this
1528          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1529          * series of register accesses are expected (e.g. reading Event Log),
1530          * to keep device from sleeping.
1531          *
1532          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1533          * SRAM is okay/restored.  We don't check that here because this call
1534          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1535          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1536          *
1537          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1538          * and do not save/restore SRAM when power cycling.
1539          */
1540         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1541                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1542                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1543                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1544         if (unlikely(ret < 0)) {
1545                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1546                 if (!silent) {
1547                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1548                         WARN_ONCE(1,
1549                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1550                                   val);
1551                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1552                         return false;
1553                 }
1554         }
1555
1556 out:
1557         /*
1558          * Fool sparse by faking we release the lock - sparse will
1559          * track nic_access anyway.
1560          */
1561         __release(&trans_pcie->reg_lock);
1562         return true;
1563 }
1564
1565 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1566                                               unsigned long *flags)
1567 {
1568         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1569
1570         lockdep_assert_held(&trans_pcie->reg_lock);
1571
1572         /*
1573          * Fool sparse by faking we acquiring the lock - sparse will
1574          * track nic_access anyway.
1575          */
1576         __acquire(&trans_pcie->reg_lock);
1577
1578         if (trans_pcie->cmd_hold_nic_awake)
1579                 goto out;
1580
1581         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1582                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1583         /*
1584          * Above we read the CSR_GP_CNTRL register, which will flush
1585          * any previous writes, but we need the write that clears the
1586          * MAC_ACCESS_REQ bit to be performed before any other writes
1587          * scheduled on different CPUs (after we drop reg_lock).
1588          */
1589         mmiowb();
1590 out:
1591         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1592 }
1593
1594 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1595                                    void *buf, int dwords)
1596 {
1597         unsigned long flags;
1598         int offs, ret = 0;
1599         u32 *vals = buf;
1600
1601         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1602                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1603                 for (offs = 0; offs < dwords; offs++)
1604                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1605                 iwl_trans_release_nic_access(trans, &flags);
1606         } else {
1607                 ret = -EBUSY;
1608         }
1609         return ret;
1610 }
1611
1612 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1613                                     const void *buf, int dwords)
1614 {
1615         unsigned long flags;
1616         int offs, ret = 0;
1617         const u32 *vals = buf;
1618
1619         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1620                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1621                 for (offs = 0; offs < dwords; offs++)
1622                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1623                                     vals ? vals[offs] : 0);
1624                 iwl_trans_release_nic_access(trans, &flags);
1625         } else {
1626                 ret = -EBUSY;
1627         }
1628         return ret;
1629 }
1630
1631 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1632                                             unsigned long txqs,
1633                                             bool freeze)
1634 {
1635         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1636         int queue;
1637
1638         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1639                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1640                 unsigned long now;
1641
1642                 spin_lock_bh(&txq->lock);
1643
1644                 now = jiffies;
1645
1646                 if (txq->frozen == freeze)
1647                         goto next_queue;
1648
1649                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1650                                     freeze ? "Freezing" : "Waking", queue);
1651
1652                 txq->frozen = freeze;
1653
1654                 if (txq->q.read_ptr == txq->q.write_ptr)
1655                         goto next_queue;
1656
1657                 if (freeze) {
1658                         if (unlikely(time_after(now,
1659                                                 txq->stuck_timer.expires))) {
1660                                 /*
1661                                  * The timer should have fired, maybe it is
1662                                  * spinning right now on the lock.
1663                                  */
1664                                 goto next_queue;
1665                         }
1666                         /* remember how long until the timer fires */
1667                         txq->frozen_expiry_remainder =
1668                                 txq->stuck_timer.expires - now;
1669                         del_timer(&txq->stuck_timer);
1670                         goto next_queue;
1671                 }
1672
1673                 /*
1674                  * Wake a non-empty queue -> arm timer with the
1675                  * remainder before it froze
1676                  */
1677                 mod_timer(&txq->stuck_timer,
1678                           now + txq->frozen_expiry_remainder);
1679
1680 next_queue:
1681                 spin_unlock_bh(&txq->lock);
1682         }
1683 }
1684
1685 #define IWL_FLUSH_WAIT_MS       2000
1686
1687 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1688 {
1689         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1690         struct iwl_txq *txq;
1691         struct iwl_queue *q;
1692         int cnt;
1693         unsigned long now = jiffies;
1694         u32 scd_sram_addr;
1695         u8 buf[16];
1696         int ret = 0;
1697
1698         /* waiting for all the tx frames complete might take a while */
1699         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1700                 u8 wr_ptr;
1701
1702                 if (cnt == trans_pcie->cmd_queue)
1703                         continue;
1704                 if (!test_bit(cnt, trans_pcie->queue_used))
1705                         continue;
1706                 if (!(BIT(cnt) & txq_bm))
1707                         continue;
1708
1709                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1710                 txq = &trans_pcie->txq[cnt];
1711                 q = &txq->q;
1712                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1713
1714                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1715                        !time_after(jiffies,
1716                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1717                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1718
1719                         if (WARN_ONCE(wr_ptr != write_ptr,
1720                                       "WR pointer moved while flushing %d -> %d\n",
1721                                       wr_ptr, write_ptr))
1722                                 return -ETIMEDOUT;
1723                         msleep(1);
1724                 }
1725
1726                 if (q->read_ptr != q->write_ptr) {
1727                         IWL_ERR(trans,
1728                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1729                         ret = -ETIMEDOUT;
1730                         break;
1731                 }
1732                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1733         }
1734
1735         if (!ret)
1736                 return 0;
1737
1738         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1739                 txq->q.read_ptr, txq->q.write_ptr);
1740
1741         scd_sram_addr = trans_pcie->scd_base_addr +
1742                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1743         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1744
1745         iwl_print_hex_error(trans, buf, sizeof(buf));
1746
1747         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1748                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1749                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1750
1751         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1752                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1753                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1754                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1755                 u32 tbl_dw =
1756                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1757                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1758
1759                 if (cnt & 0x1)
1760                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1761                 else
1762                         tbl_dw = tbl_dw & 0x0000FFFF;
1763
1764                 IWL_ERR(trans,
1765                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1766                         cnt, active ? "" : "in", fifo, tbl_dw,
1767                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1768                                 (TFD_QUEUE_SIZE_MAX - 1),
1769                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1770         }
1771
1772         return ret;
1773 }
1774
1775 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1776                                          u32 mask, u32 value)
1777 {
1778         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1779         unsigned long flags;
1780
1781         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1782         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1783         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1784 }
1785
1786 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1787 {
1788         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1789         unsigned long flags;
1790
1791         if (iwlwifi_mod_params.d0i3_disable)
1792                 return;
1793
1794         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1795         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1796         trans_pcie->ref_count++;
1797         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1798 }
1799
1800 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1801 {
1802         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1803         unsigned long flags;
1804
1805         if (iwlwifi_mod_params.d0i3_disable)
1806                 return;
1807
1808         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1809         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1810         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1811                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1812                 return;
1813         }
1814         trans_pcie->ref_count--;
1815         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1816 }
1817
1818 static const char *get_csr_string(int cmd)
1819 {
1820 #define IWL_CMD(x) case x: return #x
1821         switch (cmd) {
1822         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1823         IWL_CMD(CSR_INT_COALESCING);
1824         IWL_CMD(CSR_INT);
1825         IWL_CMD(CSR_INT_MASK);
1826         IWL_CMD(CSR_FH_INT_STATUS);
1827         IWL_CMD(CSR_GPIO_IN);
1828         IWL_CMD(CSR_RESET);
1829         IWL_CMD(CSR_GP_CNTRL);
1830         IWL_CMD(CSR_HW_REV);
1831         IWL_CMD(CSR_EEPROM_REG);
1832         IWL_CMD(CSR_EEPROM_GP);
1833         IWL_CMD(CSR_OTP_GP_REG);
1834         IWL_CMD(CSR_GIO_REG);
1835         IWL_CMD(CSR_GP_UCODE_REG);
1836         IWL_CMD(CSR_GP_DRIVER_REG);
1837         IWL_CMD(CSR_UCODE_DRV_GP1);
1838         IWL_CMD(CSR_UCODE_DRV_GP2);
1839         IWL_CMD(CSR_LED_REG);
1840         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1841         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1842         IWL_CMD(CSR_ANA_PLL_CFG);
1843         IWL_CMD(CSR_HW_REV_WA_REG);
1844         IWL_CMD(CSR_MONITOR_STATUS_REG);
1845         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1846         default:
1847                 return "UNKNOWN";
1848         }
1849 #undef IWL_CMD
1850 }
1851
1852 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1853 {
1854         int i;
1855         static const u32 csr_tbl[] = {
1856                 CSR_HW_IF_CONFIG_REG,
1857                 CSR_INT_COALESCING,
1858                 CSR_INT,
1859                 CSR_INT_MASK,
1860                 CSR_FH_INT_STATUS,
1861                 CSR_GPIO_IN,
1862                 CSR_RESET,
1863                 CSR_GP_CNTRL,
1864                 CSR_HW_REV,
1865                 CSR_EEPROM_REG,
1866                 CSR_EEPROM_GP,
1867                 CSR_OTP_GP_REG,
1868                 CSR_GIO_REG,
1869                 CSR_GP_UCODE_REG,
1870                 CSR_GP_DRIVER_REG,
1871                 CSR_UCODE_DRV_GP1,
1872                 CSR_UCODE_DRV_GP2,
1873                 CSR_LED_REG,
1874                 CSR_DRAM_INT_TBL_REG,
1875                 CSR_GIO_CHICKEN_BITS,
1876                 CSR_ANA_PLL_CFG,
1877                 CSR_MONITOR_STATUS_REG,
1878                 CSR_HW_REV_WA_REG,
1879                 CSR_DBG_HPET_MEM_REG
1880         };
1881         IWL_ERR(trans, "CSR values:\n");
1882         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1883                 "CSR_INT_PERIODIC_REG)\n");
1884         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1885                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1886                         get_csr_string(csr_tbl[i]),
1887                         iwl_read32(trans, csr_tbl[i]));
1888         }
1889 }
1890
1891 #ifdef CONFIG_IWLWIFI_DEBUGFS
1892 /* create and remove of files */
1893 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1894         if (!debugfs_create_file(#name, mode, parent, trans,            \
1895                                  &iwl_dbgfs_##name##_ops))              \
1896                 goto err;                                               \
1897 } while (0)
1898
1899 /* file operation */
1900 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1901 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1902         .read = iwl_dbgfs_##name##_read,                                \
1903         .open = simple_open,                                            \
1904         .llseek = generic_file_llseek,                                  \
1905 };
1906
1907 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1908 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1909         .write = iwl_dbgfs_##name##_write,                              \
1910         .open = simple_open,                                            \
1911         .llseek = generic_file_llseek,                                  \
1912 };
1913
1914 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1915 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1916         .write = iwl_dbgfs_##name##_write,                              \
1917         .read = iwl_dbgfs_##name##_read,                                \
1918         .open = simple_open,                                            \
1919         .llseek = generic_file_llseek,                                  \
1920 };
1921
1922 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1923                                        char __user *user_buf,
1924                                        size_t count, loff_t *ppos)
1925 {
1926         struct iwl_trans *trans = file->private_data;
1927         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1928         struct iwl_txq *txq;
1929         struct iwl_queue *q;
1930         char *buf;
1931         int pos = 0;
1932         int cnt;
1933         int ret;
1934         size_t bufsz;
1935
1936         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1937
1938         if (!trans_pcie->txq)
1939                 return -EAGAIN;
1940
1941         buf = kzalloc(bufsz, GFP_KERNEL);
1942         if (!buf)
1943                 return -ENOMEM;
1944
1945         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1946                 txq = &trans_pcie->txq[cnt];
1947                 q = &txq->q;
1948                 pos += scnprintf(buf + pos, bufsz - pos,
1949                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1950                                 cnt, q->read_ptr, q->write_ptr,
1951                                 !!test_bit(cnt, trans_pcie->queue_used),
1952                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1953                                  txq->need_update, txq->frozen,
1954                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1955         }
1956         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1957         kfree(buf);
1958         return ret;
1959 }
1960
1961 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1962                                        char __user *user_buf,
1963                                        size_t count, loff_t *ppos)
1964 {
1965         struct iwl_trans *trans = file->private_data;
1966         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1967         struct iwl_rxq *rxq = &trans_pcie->rxq;
1968         char buf[256];
1969         int pos = 0;
1970         const size_t bufsz = sizeof(buf);
1971
1972         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1973                                                 rxq->read);
1974         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1975                                                 rxq->write);
1976         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1977                                                 rxq->write_actual);
1978         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1979                                                 rxq->need_update);
1980         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1981                                                 rxq->free_count);
1982         if (rxq->rb_stts) {
1983                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1984                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1985         } else {
1986                 pos += scnprintf(buf + pos, bufsz - pos,
1987                                         "closed_rb_num: Not Allocated\n");
1988         }
1989         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1990 }
1991
1992 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1993                                         char __user *user_buf,
1994                                         size_t count, loff_t *ppos)
1995 {
1996         struct iwl_trans *trans = file->private_data;
1997         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1998         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1999
2000         int pos = 0;
2001         char *buf;
2002         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2003         ssize_t ret;
2004
2005         buf = kzalloc(bufsz, GFP_KERNEL);
2006         if (!buf)
2007                 return -ENOMEM;
2008
2009         pos += scnprintf(buf + pos, bufsz - pos,
2010                         "Interrupt Statistics Report:\n");
2011
2012         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2013                 isr_stats->hw);
2014         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2015                 isr_stats->sw);
2016         if (isr_stats->sw || isr_stats->hw) {
2017                 pos += scnprintf(buf + pos, bufsz - pos,
2018                         "\tLast Restarting Code:  0x%X\n",
2019                         isr_stats->err_code);
2020         }
2021 #ifdef CONFIG_IWLWIFI_DEBUG
2022         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2023                 isr_stats->sch);
2024         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2025                 isr_stats->alive);
2026 #endif
2027         pos += scnprintf(buf + pos, bufsz - pos,
2028                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2029
2030         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2031                 isr_stats->ctkill);
2032
2033         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2034                 isr_stats->wakeup);
2035
2036         pos += scnprintf(buf + pos, bufsz - pos,
2037                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2038
2039         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2040                 isr_stats->tx);
2041
2042         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2043                 isr_stats->unhandled);
2044
2045         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2046         kfree(buf);
2047         return ret;
2048 }
2049
2050 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2051                                          const char __user *user_buf,
2052                                          size_t count, loff_t *ppos)
2053 {
2054         struct iwl_trans *trans = file->private_data;
2055         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2056         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2057
2058         char buf[8];
2059         int buf_size;
2060         u32 reset_flag;
2061
2062         memset(buf, 0, sizeof(buf));
2063         buf_size = min(count, sizeof(buf) -  1);
2064         if (copy_from_user(buf, user_buf, buf_size))
2065                 return -EFAULT;
2066         if (sscanf(buf, "%x", &reset_flag) != 1)
2067                 return -EFAULT;
2068         if (reset_flag == 0)
2069                 memset(isr_stats, 0, sizeof(*isr_stats));
2070
2071         return count;
2072 }
2073
2074 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2075                                    const char __user *user_buf,
2076                                    size_t count, loff_t *ppos)
2077 {
2078         struct iwl_trans *trans = file->private_data;
2079         char buf[8];
2080         int buf_size;
2081         int csr;
2082
2083         memset(buf, 0, sizeof(buf));
2084         buf_size = min(count, sizeof(buf) -  1);
2085         if (copy_from_user(buf, user_buf, buf_size))
2086                 return -EFAULT;
2087         if (sscanf(buf, "%d", &csr) != 1)
2088                 return -EFAULT;
2089
2090         iwl_pcie_dump_csr(trans);
2091
2092         return count;
2093 }
2094
2095 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2096                                      char __user *user_buf,
2097                                      size_t count, loff_t *ppos)
2098 {
2099         struct iwl_trans *trans = file->private_data;
2100         char *buf = NULL;
2101         ssize_t ret;
2102
2103         ret = iwl_dump_fh(trans, &buf);
2104         if (ret < 0)
2105                 return ret;
2106         if (!buf)
2107                 return -EINVAL;
2108         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2109         kfree(buf);
2110         return ret;
2111 }
2112
2113 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2114 DEBUGFS_READ_FILE_OPS(fh_reg);
2115 DEBUGFS_READ_FILE_OPS(rx_queue);
2116 DEBUGFS_READ_FILE_OPS(tx_queue);
2117 DEBUGFS_WRITE_FILE_OPS(csr);
2118
2119 /*
2120  * Create the debugfs files and directories
2121  *
2122  */
2123 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2124                                          struct dentry *dir)
2125 {
2126         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2127         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2128         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2129         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2130         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2131         return 0;
2132
2133 err:
2134         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2135         return -ENOMEM;
2136 }
2137 #else
2138 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2139                                          struct dentry *dir)
2140 {
2141         return 0;
2142 }
2143 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2144
2145 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2146 {
2147         u32 cmdlen = 0;
2148         int i;
2149
2150         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2151                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2152
2153         return cmdlen;
2154 }
2155
2156 static const struct {
2157         u32 start, end;
2158 } iwl_prph_dump_addr[] = {
2159         { .start = 0x00a00000, .end = 0x00a00000 },
2160         { .start = 0x00a0000c, .end = 0x00a00024 },
2161         { .start = 0x00a0002c, .end = 0x00a0003c },
2162         { .start = 0x00a00410, .end = 0x00a00418 },
2163         { .start = 0x00a00420, .end = 0x00a00420 },
2164         { .start = 0x00a00428, .end = 0x00a00428 },
2165         { .start = 0x00a00430, .end = 0x00a0043c },
2166         { .start = 0x00a00444, .end = 0x00a00444 },
2167         { .start = 0x00a004c0, .end = 0x00a004cc },
2168         { .start = 0x00a004d8, .end = 0x00a004d8 },
2169         { .start = 0x00a004e0, .end = 0x00a004f0 },
2170         { .start = 0x00a00840, .end = 0x00a00840 },
2171         { .start = 0x00a00850, .end = 0x00a00858 },
2172         { .start = 0x00a01004, .end = 0x00a01008 },
2173         { .start = 0x00a01010, .end = 0x00a01010 },
2174         { .start = 0x00a01018, .end = 0x00a01018 },
2175         { .start = 0x00a01024, .end = 0x00a01024 },
2176         { .start = 0x00a0102c, .end = 0x00a01034 },
2177         { .start = 0x00a0103c, .end = 0x00a01040 },
2178         { .start = 0x00a01048, .end = 0x00a01094 },
2179         { .start = 0x00a01c00, .end = 0x00a01c20 },
2180         { .start = 0x00a01c58, .end = 0x00a01c58 },
2181         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2182         { .start = 0x00a01c28, .end = 0x00a01c54 },
2183         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2184         { .start = 0x00a01c60, .end = 0x00a01cdc },
2185         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2186         { .start = 0x00a01d18, .end = 0x00a01d20 },
2187         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2188         { .start = 0x00a01d40, .end = 0x00a01d5c },
2189         { .start = 0x00a01d80, .end = 0x00a01d80 },
2190         { .start = 0x00a01d98, .end = 0x00a01d9c },
2191         { .start = 0x00a01da8, .end = 0x00a01da8 },
2192         { .start = 0x00a01db8, .end = 0x00a01df4 },
2193         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2194         { .start = 0x00a01e00, .end = 0x00a01e2c },
2195         { .start = 0x00a01e40, .end = 0x00a01e60 },
2196         { .start = 0x00a01e68, .end = 0x00a01e6c },
2197         { .start = 0x00a01e74, .end = 0x00a01e74 },
2198         { .start = 0x00a01e84, .end = 0x00a01e90 },
2199         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2200         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2201         { .start = 0x00a01f00, .end = 0x00a01f1c },
2202         { .start = 0x00a01f44, .end = 0x00a01ffc },
2203         { .start = 0x00a02000, .end = 0x00a02048 },
2204         { .start = 0x00a02068, .end = 0x00a020f0 },
2205         { .start = 0x00a02100, .end = 0x00a02118 },
2206         { .start = 0x00a02140, .end = 0x00a0214c },
2207         { .start = 0x00a02168, .end = 0x00a0218c },
2208         { .start = 0x00a021c0, .end = 0x00a021c0 },
2209         { .start = 0x00a02400, .end = 0x00a02410 },
2210         { .start = 0x00a02418, .end = 0x00a02420 },
2211         { .start = 0x00a02428, .end = 0x00a0242c },
2212         { .start = 0x00a02434, .end = 0x00a02434 },
2213         { .start = 0x00a02440, .end = 0x00a02460 },
2214         { .start = 0x00a02468, .end = 0x00a024b0 },
2215         { .start = 0x00a024c8, .end = 0x00a024cc },
2216         { .start = 0x00a02500, .end = 0x00a02504 },
2217         { .start = 0x00a0250c, .end = 0x00a02510 },
2218         { .start = 0x00a02540, .end = 0x00a02554 },
2219         { .start = 0x00a02580, .end = 0x00a025f4 },
2220         { .start = 0x00a02600, .end = 0x00a0260c },
2221         { .start = 0x00a02648, .end = 0x00a02650 },
2222         { .start = 0x00a02680, .end = 0x00a02680 },
2223         { .start = 0x00a026c0, .end = 0x00a026d0 },
2224         { .start = 0x00a02700, .end = 0x00a0270c },
2225         { .start = 0x00a02804, .end = 0x00a02804 },
2226         { .start = 0x00a02818, .end = 0x00a0281c },
2227         { .start = 0x00a02c00, .end = 0x00a02db4 },
2228         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2229         { .start = 0x00a03000, .end = 0x00a03014 },
2230         { .start = 0x00a0301c, .end = 0x00a0302c },
2231         { .start = 0x00a03034, .end = 0x00a03038 },
2232         { .start = 0x00a03040, .end = 0x00a03048 },
2233         { .start = 0x00a03060, .end = 0x00a03068 },
2234         { .start = 0x00a03070, .end = 0x00a03074 },
2235         { .start = 0x00a0307c, .end = 0x00a0307c },
2236         { .start = 0x00a03080, .end = 0x00a03084 },
2237         { .start = 0x00a0308c, .end = 0x00a03090 },
2238         { .start = 0x00a03098, .end = 0x00a03098 },
2239         { .start = 0x00a030a0, .end = 0x00a030a0 },
2240         { .start = 0x00a030a8, .end = 0x00a030b4 },
2241         { .start = 0x00a030bc, .end = 0x00a030bc },
2242         { .start = 0x00a030c0, .end = 0x00a0312c },
2243         { .start = 0x00a03c00, .end = 0x00a03c5c },
2244         { .start = 0x00a04400, .end = 0x00a04454 },
2245         { .start = 0x00a04460, .end = 0x00a04474 },
2246         { .start = 0x00a044c0, .end = 0x00a044ec },
2247         { .start = 0x00a04500, .end = 0x00a04504 },
2248         { .start = 0x00a04510, .end = 0x00a04538 },
2249         { .start = 0x00a04540, .end = 0x00a04548 },
2250         { .start = 0x00a04560, .end = 0x00a0457c },
2251         { .start = 0x00a04590, .end = 0x00a04598 },
2252         { .start = 0x00a045c0, .end = 0x00a045f4 },
2253 };
2254
2255 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2256                                     struct iwl_fw_error_dump_data **data)
2257 {
2258         struct iwl_fw_error_dump_prph *prph;
2259         unsigned long flags;
2260         u32 prph_len = 0, i;
2261
2262         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2263                 return 0;
2264
2265         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2266                 /* The range includes both boundaries */
2267                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2268                          iwl_prph_dump_addr[i].start + 4;
2269                 int reg;
2270                 __le32 *val;
2271
2272                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2273
2274                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2275                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2276                                         num_bytes_in_chunk);
2277                 prph = (void *)(*data)->data;
2278                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2279                 val = (void *)prph->data;
2280
2281                 for (reg = iwl_prph_dump_addr[i].start;
2282                      reg <= iwl_prph_dump_addr[i].end;
2283                      reg += 4)
2284                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2285                                                                       reg));
2286                 *data = iwl_fw_error_next_data(*data);
2287         }
2288
2289         iwl_trans_release_nic_access(trans, &flags);
2290
2291         return prph_len;
2292 }
2293
2294 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2295                                    struct iwl_fw_error_dump_data **data,
2296                                    int allocated_rb_nums)
2297 {
2298         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2299         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2300         struct iwl_rxq *rxq = &trans_pcie->rxq;
2301         u32 i, r, j, rb_len = 0;
2302
2303         spin_lock(&rxq->lock);
2304
2305         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2306
2307         for (i = rxq->read, j = 0;
2308              i != r && j < allocated_rb_nums;
2309              i = (i + 1) & RX_QUEUE_MASK, j++) {
2310                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2311                 struct iwl_fw_error_dump_rb *rb;
2312
2313                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2314                                DMA_FROM_DEVICE);
2315
2316                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2317
2318                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2319                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2320                 rb = (void *)(*data)->data;
2321                 rb->index = cpu_to_le32(i);
2322                 memcpy(rb->data, page_address(rxb->page), max_len);
2323                 /* remap the page for the free benefit */
2324                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2325                                                      max_len,
2326                                                      DMA_FROM_DEVICE);
2327
2328                 *data = iwl_fw_error_next_data(*data);
2329         }
2330
2331         spin_unlock(&rxq->lock);
2332
2333         return rb_len;
2334 }
2335 #define IWL_CSR_TO_DUMP (0x250)
2336
2337 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2338                                    struct iwl_fw_error_dump_data **data)
2339 {
2340         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2341         __le32 *val;
2342         int i;
2343
2344         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2345         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2346         val = (void *)(*data)->data;
2347
2348         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2349                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2350
2351         *data = iwl_fw_error_next_data(*data);
2352
2353         return csr_len;
2354 }
2355
2356 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2357                                        struct iwl_fw_error_dump_data **data)
2358 {
2359         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2360         unsigned long flags;
2361         __le32 *val;
2362         int i;
2363
2364         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2365                 return 0;
2366
2367         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2368         (*data)->len = cpu_to_le32(fh_regs_len);
2369         val = (void *)(*data)->data;
2370
2371         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2372                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2373
2374         iwl_trans_release_nic_access(trans, &flags);
2375
2376         *data = iwl_fw_error_next_data(*data);
2377
2378         return sizeof(**data) + fh_regs_len;
2379 }
2380
2381 static u32
2382 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2383                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2384                                  u32 monitor_len)
2385 {
2386         u32 buf_size_in_dwords = (monitor_len >> 2);
2387         u32 *buffer = (u32 *)fw_mon_data->data;
2388         unsigned long flags;
2389         u32 i;
2390
2391         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2392                 return 0;
2393
2394         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2395         for (i = 0; i < buf_size_in_dwords; i++)
2396                 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2397         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2398
2399         iwl_trans_release_nic_access(trans, &flags);
2400
2401         return monitor_len;
2402 }
2403
2404 static u32
2405 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2406                             struct iwl_fw_error_dump_data **data,
2407                             u32 monitor_len)
2408 {
2409         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2410         u32 len = 0;
2411
2412         if ((trans_pcie->fw_mon_page &&
2413              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2414             trans->dbg_dest_tlv) {
2415                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2416                 u32 base, write_ptr, wrap_cnt;
2417
2418                 /* If there was a dest TLV - use the values from there */
2419                 if (trans->dbg_dest_tlv) {
2420                         write_ptr =
2421                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2422                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2423                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2424                 } else {
2425                         base = MON_BUFF_BASE_ADDR;
2426                         write_ptr = MON_BUFF_WRPTR;
2427                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2428                 }
2429
2430                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2431                 fw_mon_data = (void *)(*data)->data;
2432                 fw_mon_data->fw_mon_wr_ptr =
2433                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2434                 fw_mon_data->fw_mon_cycle_cnt =
2435                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2436                 fw_mon_data->fw_mon_base_ptr =
2437                         cpu_to_le32(iwl_read_prph(trans, base));
2438
2439                 len += sizeof(**data) + sizeof(*fw_mon_data);
2440                 if (trans_pcie->fw_mon_page) {
2441                         /*
2442                          * The firmware is now asserted, it won't write anything
2443                          * to the buffer. CPU can take ownership to fetch the
2444                          * data. The buffer will be handed back to the device
2445                          * before the firmware will be restarted.
2446                          */
2447                         dma_sync_single_for_cpu(trans->dev,
2448                                                 trans_pcie->fw_mon_phys,
2449                                                 trans_pcie->fw_mon_size,
2450                                                 DMA_FROM_DEVICE);
2451                         memcpy(fw_mon_data->data,
2452                                page_address(trans_pcie->fw_mon_page),
2453                                trans_pcie->fw_mon_size);
2454
2455                         monitor_len = trans_pcie->fw_mon_size;
2456                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2457                         /*
2458                          * Update pointers to reflect actual values after
2459                          * shifting
2460                          */
2461                         base = iwl_read_prph(trans, base) <<
2462                                trans->dbg_dest_tlv->base_shift;
2463                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2464                                            monitor_len / sizeof(u32));
2465                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2466                         monitor_len =
2467                                 iwl_trans_pci_dump_marbh_monitor(trans,
2468                                                                  fw_mon_data,
2469                                                                  monitor_len);
2470                 } else {
2471                         /* Didn't match anything - output no monitor data */
2472                         monitor_len = 0;
2473                 }
2474
2475                 len += monitor_len;
2476                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2477         }
2478
2479         return len;
2480 }
2481
2482 static struct iwl_trans_dump_data
2483 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2484                           struct iwl_fw_dbg_trigger_tlv *trigger)
2485 {
2486         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2487         struct iwl_fw_error_dump_data *data;
2488         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2489         struct iwl_fw_error_dump_txcmd *txcmd;
2490         struct iwl_trans_dump_data *dump_data;
2491         u32 len, num_rbs;
2492         u32 monitor_len;
2493         int i, ptr;
2494         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
2495
2496         /* transport dump header */
2497         len = sizeof(*dump_data);
2498
2499         /* host commands */
2500         len += sizeof(*data) +
2501                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2502
2503         /* FW monitor */
2504         if (trans_pcie->fw_mon_page) {
2505                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2506                        trans_pcie->fw_mon_size;
2507                 monitor_len = trans_pcie->fw_mon_size;
2508         } else if (trans->dbg_dest_tlv) {
2509                 u32 base, end;
2510
2511                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2512                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2513
2514                 base = iwl_read_prph(trans, base) <<
2515                        trans->dbg_dest_tlv->base_shift;
2516                 end = iwl_read_prph(trans, end) <<
2517                       trans->dbg_dest_tlv->end_shift;
2518
2519                 /* Make "end" point to the actual end */
2520                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2521                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2522                         end += (1 << trans->dbg_dest_tlv->end_shift);
2523                 monitor_len = end - base;
2524                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2525                        monitor_len;
2526         } else {
2527                 monitor_len = 0;
2528         }
2529
2530         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2531                 dump_data = vzalloc(len);
2532                 if (!dump_data)
2533                         return NULL;
2534
2535                 data = (void *)dump_data->data;
2536                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2537                 dump_data->len = len;
2538
2539                 return dump_data;
2540         }
2541
2542         /* CSR registers */
2543         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2544
2545         /* PRPH registers */
2546         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2547                 /* The range includes both boundaries */
2548                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2549                         iwl_prph_dump_addr[i].start + 4;
2550
2551                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2552                        num_bytes_in_chunk;
2553         }
2554
2555         /* FH registers */
2556         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2557
2558         if (dump_rbs) {
2559                 /* RBs */
2560                 num_rbs = le16_to_cpu(ACCESS_ONCE(
2561                                       trans_pcie->rxq.rb_stts->closed_rb_num))
2562                                       & 0x0FFF;
2563                 num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK;
2564                 len += num_rbs * (sizeof(*data) +
2565                                   sizeof(struct iwl_fw_error_dump_rb) +
2566                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2567         }
2568
2569         dump_data = vzalloc(len);
2570         if (!dump_data)
2571                 return NULL;
2572
2573         len = 0;
2574         data = (void *)dump_data->data;
2575         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2576         txcmd = (void *)data->data;
2577         spin_lock_bh(&cmdq->lock);
2578         ptr = cmdq->q.write_ptr;
2579         for (i = 0; i < cmdq->q.n_window; i++) {
2580                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2581                 u32 caplen, cmdlen;
2582
2583                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2584                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2585
2586                 if (cmdlen) {
2587                         len += sizeof(*txcmd) + caplen;
2588                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2589                         txcmd->caplen = cpu_to_le32(caplen);
2590                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2591                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2592                 }
2593
2594                 ptr = iwl_queue_dec_wrap(ptr);
2595         }
2596         spin_unlock_bh(&cmdq->lock);
2597
2598         data->len = cpu_to_le32(len);
2599         len += sizeof(*data);
2600         data = iwl_fw_error_next_data(data);
2601
2602         len += iwl_trans_pcie_dump_prph(trans, &data);
2603         len += iwl_trans_pcie_dump_csr(trans, &data);
2604         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2605         if (dump_rbs)
2606                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2607
2608         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2609
2610         dump_data->len = len;
2611
2612         return dump_data;
2613 }
2614
2615 static const struct iwl_trans_ops trans_ops_pcie = {
2616         .start_hw = iwl_trans_pcie_start_hw,
2617         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2618         .fw_alive = iwl_trans_pcie_fw_alive,
2619         .start_fw = iwl_trans_pcie_start_fw,
2620         .stop_device = iwl_trans_pcie_stop_device,
2621
2622         .d3_suspend = iwl_trans_pcie_d3_suspend,
2623         .d3_resume = iwl_trans_pcie_d3_resume,
2624
2625         .send_cmd = iwl_trans_pcie_send_hcmd,
2626
2627         .tx = iwl_trans_pcie_tx,
2628         .reclaim = iwl_trans_pcie_reclaim,
2629
2630         .txq_disable = iwl_trans_pcie_txq_disable,
2631         .txq_enable = iwl_trans_pcie_txq_enable,
2632
2633         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2634
2635         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2636         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2637
2638         .write8 = iwl_trans_pcie_write8,
2639         .write32 = iwl_trans_pcie_write32,
2640         .read32 = iwl_trans_pcie_read32,
2641         .read_prph = iwl_trans_pcie_read_prph,
2642         .write_prph = iwl_trans_pcie_write_prph,
2643         .read_mem = iwl_trans_pcie_read_mem,
2644         .write_mem = iwl_trans_pcie_write_mem,
2645         .configure = iwl_trans_pcie_configure,
2646         .set_pmi = iwl_trans_pcie_set_pmi,
2647         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2648         .release_nic_access = iwl_trans_pcie_release_nic_access,
2649         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2650
2651         .ref = iwl_trans_pcie_ref,
2652         .unref = iwl_trans_pcie_unref,
2653
2654         .dump_data = iwl_trans_pcie_dump_data,
2655 };
2656
2657 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2658                                        const struct pci_device_id *ent,
2659                                        const struct iwl_cfg *cfg)
2660 {
2661         struct iwl_trans_pcie *trans_pcie;
2662         struct iwl_trans *trans;
2663         u16 pci_cmd;
2664         int ret;
2665
2666         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2667                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2668         if (!trans)
2669                 return ERR_PTR(-ENOMEM);
2670
2671         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2672
2673         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2674
2675         trans_pcie->trans = trans;
2676         spin_lock_init(&trans_pcie->irq_lock);
2677         spin_lock_init(&trans_pcie->reg_lock);
2678         spin_lock_init(&trans_pcie->ref_lock);
2679         mutex_init(&trans_pcie->mutex);
2680         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2681
2682         ret = pci_enable_device(pdev);
2683         if (ret)
2684                 goto out_no_pci;
2685
2686         if (!cfg->base_params->pcie_l1_allowed) {
2687                 /*
2688                  * W/A - seems to solve weird behavior. We need to remove this
2689                  * if we don't want to stay in L1 all the time. This wastes a
2690                  * lot of power.
2691                  */
2692                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2693                                        PCIE_LINK_STATE_L1 |
2694                                        PCIE_LINK_STATE_CLKPM);
2695         }
2696
2697         pci_set_master(pdev);
2698
2699         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2700         if (!ret)
2701                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2702         if (ret) {
2703                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2704                 if (!ret)
2705                         ret = pci_set_consistent_dma_mask(pdev,
2706                                                           DMA_BIT_MASK(32));
2707                 /* both attempts failed: */
2708                 if (ret) {
2709                         dev_err(&pdev->dev, "No suitable DMA available\n");
2710                         goto out_pci_disable_device;
2711                 }
2712         }
2713
2714         ret = pci_request_regions(pdev, DRV_NAME);
2715         if (ret) {
2716                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2717                 goto out_pci_disable_device;
2718         }
2719
2720         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2721         if (!trans_pcie->hw_base) {
2722                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2723                 ret = -ENODEV;
2724                 goto out_pci_release_regions;
2725         }
2726
2727         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2728          * PCI Tx retries from interfering with C3 CPU state */
2729         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2730
2731         trans->dev = &pdev->dev;
2732         trans_pcie->pci_dev = pdev;
2733         iwl_disable_interrupts(trans);
2734
2735         ret = pci_enable_msi(pdev);
2736         if (ret) {
2737                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2738                 /* enable rfkill interrupt: hw bug w/a */
2739                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2740                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2741                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2742                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2743                 }
2744         }
2745
2746         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2747         /*
2748          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2749          * changed, and now the revision step also includes bit 0-1 (no more
2750          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2751          * in the old format.
2752          */
2753         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2754                 unsigned long flags;
2755
2756                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2757                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2758
2759                 ret = iwl_pcie_prepare_card_hw(trans);
2760                 if (ret) {
2761                         IWL_WARN(trans, "Exit HW not ready\n");
2762                         goto out_pci_disable_msi;
2763                 }
2764
2765                 /*
2766                  * in-order to recognize C step driver should read chip version
2767                  * id located at the AUX bus MISC address space.
2768                  */
2769                 iwl_set_bit(trans, CSR_GP_CNTRL,
2770                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2771                 udelay(2);
2772
2773                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2774                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2775                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2776                                    25000);
2777                 if (ret < 0) {
2778                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2779                         goto out_pci_disable_msi;
2780                 }
2781
2782                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2783                         u32 hw_step;
2784
2785                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2786                         hw_step |= ENABLE_WFPM;
2787                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2788                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2789                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2790                         if (hw_step == 0x3)
2791                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2792                                                 (SILICON_C_STEP << 2);
2793                         iwl_trans_release_nic_access(trans, &flags);
2794                 }
2795         }
2796
2797         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2798         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2799                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2800
2801         /* Initialize the wait queue for commands */
2802         init_waitqueue_head(&trans_pcie->wait_command_queue);
2803
2804         ret = iwl_pcie_alloc_ict(trans);
2805         if (ret)
2806                 goto out_pci_disable_msi;
2807
2808         ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2809                                    iwl_pcie_irq_handler,
2810                                    IRQF_SHARED, DRV_NAME, trans);
2811         if (ret) {
2812                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2813                 goto out_free_ict;
2814         }
2815
2816         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2817         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2818
2819         return trans;
2820
2821 out_free_ict:
2822         iwl_pcie_free_ict(trans);
2823 out_pci_disable_msi:
2824         pci_disable_msi(pdev);
2825 out_pci_release_regions:
2826         pci_release_regions(pdev);
2827 out_pci_disable_device:
2828         pci_disable_device(pdev);
2829 out_no_pci:
2830         iwl_trans_free(trans);
2831         return ERR_PTR(ret);
2832 }