drivers/net/wireless/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
   5  *
   6  * Portions of this file are derived from the ipw3945 project, as well
   7  * as portions of the ieee80211 subsystem header files.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called LICENSE.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <ilw@linux.intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  *****************************************************************************/
  30 #include <linux/etherdevice.h>
  31 #include <linux/slab.h>
  32 #include <linux/sched.h>
  33
  34 #include "iwl-debug.h"
  35 #include "iwl-csr.h"
  36 #include "iwl-prph.h"
  37 #include "iwl-io.h"
  38 #include "iwl-scd.h"
  39 #include "iwl-op-mode.h"
  40 #include "internal.h"
  41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  42 #include "dvm/commands.h"
  43
  44 #define IWL_TX_CRC_SIZE 4
  45 #define IWL_TX_DELIMITER_SIZE 4
  46
  47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  48  * DMA services
  49  *
  50  * Theory of operation
  51  *
  52  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  53  * of buffer descriptors, each of which points to one or more data buffers for
  54  * the device to read from or fill.  Driver and device exchange status of each
  55  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  56  * entries in each circular buffer, to protect against confusing empty and full
  57  * queue states.
  58  *
  59  * The device reads or writes the data in the queues via the device's several
  60  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  61  *
  62  * For Tx queue, there are low mark and high mark limits. If, after queuing
  63  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  64  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  65  * Tx queue resumed.
  66  *
  67  ***************************************************/
  68 static int iwl_queue_space(const struct iwl_queue *q)
  69 {
  70         unsigned int max;
  71         unsigned int used;
  72
  73         /*
  74          * To avoid ambiguity between empty and completely full queues, there
  75          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  76          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  77          * to reserve any queue entries for this purpose.
  78          */
  79         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  80                 max = q->n_window;
  81         else
  82                 max = TFD_QUEUE_SIZE_MAX - 1;
  83
  84         /*
  85          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  86          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  87          */
  88         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  89
  90         if (WARN_ON(used > max))
  91                 return 0;
  92
  93         return max - used;
  94 }
  95
  96 /*
  97  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
  98  */
  99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
 100 {
 101         q->n_window = slots_num;
 102         q->id = id;
 103
 104         /* slots_num must be power-of-two size, otherwise
 105          * get_cmd_index is broken. */
 106         if (WARN_ON(!is_power_of_2(slots_num)))
 107                 return -EINVAL;
 108
 109         q->low_mark = q->n_window / 4;
 110         if (q->low_mark < 4)
 111                 q->low_mark = 4;
 112
 113         q->high_mark = q->n_window / 8;
 114         if (q->high_mark < 2)
 115                 q->high_mark = 2;
 116
 117         q->write_ptr = 0;
 118         q->read_ptr = 0;
 119
 120         return 0;
 121 }
 122
 123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 124                                   struct iwl_dma_ptr *ptr, size_t size)
 125 {
 126         if (WARN_ON(ptr->addr))
 127                 return -EINVAL;
 128
 129         ptr->addr = dma_alloc_coherent(trans->dev, size,
 130                                        &ptr->dma, GFP_KERNEL);
 131         if (!ptr->addr)
 132                 return -ENOMEM;
 133         ptr->size = size;
 134         return 0;
 135 }
 136
 137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
 138                                   struct iwl_dma_ptr *ptr)
 139 {
 140         if (unlikely(!ptr->addr))
 141                 return;
 142
 143         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 144         memset(ptr, 0, sizeof(*ptr));
 145 }
 146
 147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
 148 {
 149         struct iwl_txq *txq = (void *)data;
 150         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 151         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 152         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 153                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 154         u8 buf[16];
 155         int i;
 156
 157         spin_lock(&txq->lock);
 158         /* check if triggered erroneously */
 159         if (txq->q.read_ptr == txq->q.write_ptr) {
 160                 spin_unlock(&txq->lock);
 161                 return;
 162         }
 163         spin_unlock(&txq->lock);
 164
 165         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 166                 jiffies_to_msecs(txq->wd_timeout));
 167         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 168                 txq->q.read_ptr, txq->q.write_ptr);
 169
 170         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 171
 172         iwl_print_hex_error(trans, buf, sizeof(buf));
 173
 174         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 175                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 176                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 177
 178         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 179                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 180                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 181                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 182                 u32 tbl_dw =
 183                         iwl_trans_read_mem32(trans,
 184                                              trans_pcie->scd_base_addr +
 185                                              SCD_TRANS_TBL_OFFSET_QUEUE(i));
 186
 187                 if (i & 0x1)
 188                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 189                 else
 190                         tbl_dw = tbl_dw & 0x0000FFFF;
 191
 192                 IWL_ERR(trans,
 193                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 194                         i, active ? "" : "in", fifo, tbl_dw,
 195                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
 196                                 (TFD_QUEUE_SIZE_MAX - 1),
 197                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 198         }
 199
 200         iwl_force_nmi(trans);
 201 }
 202
 203 /*
 204  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 205  */
 206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 207                                              struct iwl_txq *txq, u16 byte_cnt)
 208 {
 209         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 211         int write_ptr = txq->q.write_ptr;
 212         int txq_id = txq->q.id;
 213         u8 sec_ctl = 0;
 214         u8 sta_id = 0;
 215         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 216         __le16 bc_ent;
 217         struct iwl_tx_cmd *tx_cmd =
 218                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
 219
 220         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 221
 222         sta_id = tx_cmd->sta_id;
 223         sec_ctl = tx_cmd->sec_ctl;
 224
 225         switch (sec_ctl & TX_CMD_SEC_MSK) {
 226         case TX_CMD_SEC_CCM:
 227                 len += IEEE80211_CCMP_MIC_LEN;
 228                 break;
 229         case TX_CMD_SEC_TKIP:
 230                 len += IEEE80211_TKIP_ICV_LEN;
 231                 break;
 232         case TX_CMD_SEC_WEP:
 233                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 234                 break;
 235         }
 236
 237         if (trans_pcie->bc_table_dword)
 238                 len = DIV_ROUND_UP(len, 4);
 239
 240         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 241                 return;
 242
 243         bc_ent = cpu_to_le16(len | (sta_id << 12));
 244
 245         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 246
 247         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 248                 scd_bc_tbl[txq_id].
 249                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 250 }
 251
 252 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 253                                             struct iwl_txq *txq)
 254 {
 255         struct iwl_trans_pcie *trans_pcie =
 256                 IWL_TRANS_GET_PCIE_TRANS(trans);
 257         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 258         int txq_id = txq->q.id;
 259         int read_ptr = txq->q.read_ptr;
 260         u8 sta_id = 0;
 261         __le16 bc_ent;
 262         struct iwl_tx_cmd *tx_cmd =
 263                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
 264
 265         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 266
 267         if (txq_id != trans_pcie->cmd_queue)
 268                 sta_id = tx_cmd->sta_id;
 269
 270         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 271         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 272
 273         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 274                 scd_bc_tbl[txq_id].
 275                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 276 }
 277
 278 /*
 279  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 280  */
 281 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 282                                     struct iwl_txq *txq)
 283 {
 284         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 285         u32 reg = 0;
 286         int txq_id = txq->q.id;
 287
 288         lockdep_assert_held(&txq->lock);
 289
 290         /*
 291          * explicitly wake up the NIC if:
 292          * 1. shadow registers aren't enabled
 293          * 2. NIC is woken up for CMD regardless of shadow outside this function
 294          * 3. there is a chance that the NIC is asleep
 295          */
 296         if (!trans->cfg->base_params->shadow_reg_enable &&
 297             txq_id != trans_pcie->cmd_queue &&
 298             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 299                 /*
 300                  * wake up nic if it's powered down ...
 301                  * uCode will wake up, and interrupt us again, so next
 302                  * time we'll skip this part.
 303                  */
 304                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 305
 306                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 307                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 308                                        txq_id, reg);
 309                         iwl_set_bit(trans, CSR_GP_CNTRL,
 310                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 311                         txq->need_update = true;
 312                         return;
 313                 }
 314         }
 315
 316         /*
 317          * if not in power-save mode, uCode will never sleep when we're
 318          * trying to tx (during RFKILL, we're not trying to tx).
 319          */
 320         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
 321         iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
 322 }
 323
 324 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 325 {
 326         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 327         int i;
 328
 329         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 330                 struct iwl_txq *txq = &trans_pcie->txq[i];
 331
 332                 spin_lock_bh(&txq->lock);
 333                 if (trans_pcie->txq[i].need_update) {
 334                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 335                         trans_pcie->txq[i].need_update = false;
 336                 }
 337                 spin_unlock_bh(&txq->lock);
 338         }
 339 }
 340
 341 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 342 {
 343         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 344
 345         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 346         if (sizeof(dma_addr_t) > sizeof(u32))
 347                 addr |=
 348                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 349
 350         return addr;
 351 }
 352
 353 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 354                                        dma_addr_t addr, u16 len)
 355 {
 356         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 357         u16 hi_n_len = len << 4;
 358
 359         put_unaligned_le32(addr, &tb->lo);
 360         if (sizeof(dma_addr_t) > sizeof(u32))
 361                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 362
 363         tb->hi_n_len = cpu_to_le16(hi_n_len);
 364
 365         tfd->num_tbs = idx + 1;
 366 }
 367
 368 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
 369 {
 370         return tfd->num_tbs & 0x1f;
 371 }
 372
 373 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 374                                struct iwl_cmd_meta *meta,
 375                                struct iwl_tfd *tfd)
 376 {
 377         int i;
 378         int num_tbs;
 379
 380         /* Sanity check on number of chunks */
 381         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 382
 383         if (num_tbs >= IWL_NUM_OF_TBS) {
 384                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 385                 /* @todo issue fatal error, it is quite serious situation */
 386                 return;
 387         }
 388
 389         /* first TB is never freed - it's the scratchbuf data */
 390
 391         for (i = 1; i < num_tbs; i++)
 392                 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
 393                                  iwl_pcie_tfd_tb_get_len(tfd, i),
 394                                  DMA_TO_DEVICE);
 395
 396         tfd->num_tbs = 0;
 397 }
 398
 399 /*
 400  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 401  * @trans - transport private data
 402  * @txq - tx queue
 403  * @dma_dir - the direction of the DMA mapping
 404  *
 405  * Does NOT advance any TFD circular buffer read/write indexes
 406  * Does NOT free the TFD itself (which is within circular buffer)
 407  */
 408 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 409 {
 410         struct iwl_tfd *tfd_tmp = txq->tfds;
 411
 412         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 413          * idx is bounded by n_window
 414          */
 415         int rd_ptr = txq->q.read_ptr;
 416         int idx = get_cmd_index(&txq->q, rd_ptr);
 417
 418         lockdep_assert_held(&txq->lock);
 419
 420         /* We have only q->n_window txq->entries, but we use
 421          * TFD_QUEUE_SIZE_MAX tfds
 422          */
 423         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
 424
 425         /* free SKB */
 426         if (txq->entries) {
 427                 struct sk_buff *skb;
 428
 429                 skb = txq->entries[idx].skb;
 430
 431                 /* Can be called from irqs-disabled context
 432                  * If skb is not NULL, it means that the whole queue is being
 433                  * freed and that the queue is not empty - free the skb
 434                  */
 435                 if (skb) {
 436                         iwl_op_mode_free_skb(trans->op_mode, skb);
 437                         txq->entries[idx].skb = NULL;
 438                 }
 439         }
 440 }
 441
 442 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 443                                   dma_addr_t addr, u16 len, bool reset)
 444 {
 445         struct iwl_queue *q;
 446         struct iwl_tfd *tfd, *tfd_tmp;
 447         u32 num_tbs;
 448
 449         q = &txq->q;
 450         tfd_tmp = txq->tfds;
 451         tfd = &tfd_tmp[q->write_ptr];
 452
 453         if (reset)
 454                 memset(tfd, 0, sizeof(*tfd));
 455
 456         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 457
 458         /* Each TFD can point to a maximum 20 Tx buffers */
 459         if (num_tbs >= IWL_NUM_OF_TBS) {
 460                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 461                         IWL_NUM_OF_TBS);
 462                 return -EINVAL;
 463         }
 464
 465         if (WARN(addr & ~IWL_TX_DMA_MASK,
 466                  "Unaligned address = %llx\n", (unsigned long long)addr))
 467                 return -EINVAL;
 468
 469         iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
 470
 471         return 0;
 472 }
 473
 474 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
 475                                struct iwl_txq *txq, int slots_num,
 476                                u32 txq_id)
 477 {
 478         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 479         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 480         size_t scratchbuf_sz;
 481         int i;
 482
 483         if (WARN_ON(txq->entries || txq->tfds))
 484                 return -EINVAL;
 485
 486         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
 487                     (unsigned long)txq);
 488         txq->trans_pcie = trans_pcie;
 489
 490         txq->q.n_window = slots_num;
 491
 492         txq->entries = kcalloc(slots_num,
 493                                sizeof(struct iwl_pcie_txq_entry),
 494                                GFP_KERNEL);
 495
 496         if (!txq->entries)
 497                 goto error;
 498
 499         if (txq_id == trans_pcie->cmd_queue)
 500                 for (i = 0; i < slots_num; i++) {
 501                         txq->entries[i].cmd =
 502                                 kmalloc(sizeof(struct iwl_device_cmd),
 503                                         GFP_KERNEL);
 504                         if (!txq->entries[i].cmd)
 505                                 goto error;
 506                 }
 507
 508         /* Circular buffer of transmit frame descriptors (TFDs),
 509          * shared with device */
 510         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 511                                        &txq->q.dma_addr, GFP_KERNEL);
 512         if (!txq->tfds)
 513                 goto error;
 514
 515         BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
 516         BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
 517                         sizeof(struct iwl_cmd_header) +
 518                         offsetof(struct iwl_tx_cmd, scratch));
 519
 520         scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
 521
 522         txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
 523                                               &txq->scratchbufs_dma,
 524                                               GFP_KERNEL);
 525         if (!txq->scratchbufs)
 526                 goto err_free_tfds;
 527
 528         txq->q.id = txq_id;
 529
 530         return 0;
 531 err_free_tfds:
 532         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
 533 error:
 534         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 535                 for (i = 0; i < slots_num; i++)
 536                         kfree(txq->entries[i].cmd);
 537         kfree(txq->entries);
 538         txq->entries = NULL;
 539
 540         return -ENOMEM;
 541
 542 }
 543
 544 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 545                               int slots_num, u32 txq_id)
 546 {
 547         int ret;
 548
 549         txq->need_update = false;
 550
 551         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 552          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 553         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 554
 555         /* Initialize queue's high/low-water marks, and head/tail indexes */
 556         ret = iwl_queue_init(&txq->q, slots_num, txq_id);
 557         if (ret)
 558                 return ret;
 559
 560         spin_lock_init(&txq->lock);
 561
 562         /*
 563          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 564          * given Tx queue, and enable the DMA channel used for that queue.
 565          * Circular buffer (TFD queue in DRAM) physical base address */
 566         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 567                            txq->q.dma_addr >> 8);
 568
 569         return 0;
 570 }
 571
 572 /*
 573  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 574  */
 575 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 576 {
 577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 578         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 579         struct iwl_queue *q = &txq->q;
 580
 581         spin_lock_bh(&txq->lock);
 582         while (q->write_ptr != q->read_ptr) {
 583                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 584                                    txq_id, q->read_ptr);
 585                 iwl_pcie_txq_free_tfd(trans, txq);
 586                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
 587         }
 588         txq->active = false;
 589         spin_unlock_bh(&txq->lock);
 590
 591         /* just in case - this queue may have been stopped */
 592         iwl_wake_queue(trans, txq);
 593 }
 594
 595 /*
 596  * iwl_pcie_txq_free - Deallocate DMA queue.
 597  * @txq: Transmit queue to deallocate.
 598  *
 599  * Empty queue by removing and destroying all BD's.
 600  * Free all buffers.
 601  * 0-fill, but do not free "txq" descriptor structure.
 602  */
 603 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 604 {
 605         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 606         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 607         struct device *dev = trans->dev;
 608         int i;
 609
 610         if (WARN_ON(!txq))
 611                 return;
 612
 613         iwl_pcie_txq_unmap(trans, txq_id);
 614
 615         /* De-alloc array of command/tx buffers */
 616         if (txq_id == trans_pcie->cmd_queue)
 617                 for (i = 0; i < txq->q.n_window; i++) {
 618                         kzfree(txq->entries[i].cmd);
 619                         kzfree(txq->entries[i].free_buf);
 620                 }
 621
 622         /* De-alloc circular buffer of TFDs */
 623         if (txq->tfds) {
 624                 dma_free_coherent(dev,
 625                                   sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
 626                                   txq->tfds, txq->q.dma_addr);
 627                 txq->q.dma_addr = 0;
 628                 txq->tfds = NULL;
 629
 630                 dma_free_coherent(dev,
 631                                   sizeof(*txq->scratchbufs) * txq->q.n_window,
 632                                   txq->scratchbufs, txq->scratchbufs_dma);
 633         }
 634
 635         kfree(txq->entries);
 636         txq->entries = NULL;
 637
 638         del_timer_sync(&txq->stuck_timer);
 639
 640         /* 0-fill queue descriptor structure */
 641         memset(txq, 0, sizeof(*txq));
 642 }
 643
 644 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 645 {
 646         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 647         int nq = trans->cfg->base_params->num_of_queues;
 648         int chan;
 649         u32 reg_val;
 650         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 651                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 652
 653         /* make sure all queue are not stopped/used */
 654         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 655         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 656
 657         trans_pcie->scd_base_addr =
 658                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 659
 660         WARN_ON(scd_base_addr != 0 &&
 661                 scd_base_addr != trans_pcie->scd_base_addr);
 662
 663         /* reset context data, TX status and translation data */
 664         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 665                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 666                             NULL, clear_dwords);
 667
 668         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 669                        trans_pcie->scd_bc_tbls.dma >> 10);
 670
 671         /* The chain extension of the SCD doesn't work well. This feature is
 672          * enabled by default by the HW, so we need to disable it manually.
 673          */
 674         if (trans->cfg->base_params->scd_chain_ext_wa)
 675                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 676
 677         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 678                                 trans_pcie->cmd_fifo,
 679                                 trans_pcie->cmd_q_wdg_timeout);
 680
 681         /* Activate all Tx DMA/FIFO channels */
 682         iwl_scd_activate_fifos(trans);
 683
 684         /* Enable DMA channel */
 685         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 686                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 687                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 688                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 689
 690         /* Update FH chicken bits */
 691         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 692         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 693                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 694
 695         /* Enable L1-Active */
 696         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 697                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 698                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 699 }
 700
 701 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 702 {
 703         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 704         int txq_id;
 705
 706         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 707              txq_id++) {
 708                 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 709
 710                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 711                                    txq->q.dma_addr >> 8);
 712                 iwl_pcie_txq_unmap(trans, txq_id);
 713                 txq->q.read_ptr = 0;
 714                 txq->q.write_ptr = 0;
 715         }
 716
 717         /* Tell NIC where to find the "keep warm" buffer */
 718         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 719                            trans_pcie->kw.dma >> 4);
 720
 721         /*
 722          * Send 0 as the scd_base_addr since the device may have be reset
 723          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 724          * contain garbage.
 725          */
 726         iwl_pcie_tx_start(trans, 0);
 727 }
 728
 729 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 730 {
 731         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 732         unsigned long flags;
 733         int ch, ret;
 734         u32 mask = 0;
 735
 736         spin_lock(&trans_pcie->irq_lock);
 737
 738         if (!iwl_trans_grab_nic_access(trans, false, &flags))
 739                 goto out;
 740
 741         /* Stop each Tx DMA channel */
 742         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 743                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 744                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 745         }
 746
 747         /* Wait for DMA channels to be idle */
 748         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 749         if (ret < 0)
 750                 IWL_ERR(trans,
 751                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 752                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 753
 754         iwl_trans_release_nic_access(trans, &flags);
 755
 756 out:
 757         spin_unlock(&trans_pcie->irq_lock);
 758 }
 759
 760 /*
 761  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 762  */
 763 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 764 {
 765         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 766         int txq_id;
 767
 768         /* Turn off all Tx DMA fifos */
 769         iwl_scd_deactivate_fifos(trans);
 770
 771         /* Turn off all Tx DMA channels */
 772         iwl_pcie_tx_stop_fh(trans);
 773
 774         /*
 775          * This function can be called before the op_mode disabled the
 776          * queues. This happens when we have an rfkill interrupt.
 777          * Since we stop Tx altogether - mark the queues as stopped.
 778          */
 779         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 780         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 781
 782         /* This can happen: start_hw, stop_device */
 783         if (!trans_pcie->txq)
 784                 return 0;
 785
 786         /* Unmap DMA from host system and free skb's */
 787         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 788              txq_id++)
 789                 iwl_pcie_txq_unmap(trans, txq_id);
 790
 791         return 0;
 792 }
 793
 794 /*
 795  * iwl_trans_tx_free - Free TXQ Context
 796  *
 797  * Destroy all TX DMA queues and structures
 798  */
 799 void iwl_pcie_tx_free(struct iwl_trans *trans)
 800 {
 801         int txq_id;
 802         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 803
 804         /* Tx queues */
 805         if (trans_pcie->txq) {
 806                 for (txq_id = 0;
 807                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 808                         iwl_pcie_txq_free(trans, txq_id);
 809         }
 810
 811         kfree(trans_pcie->txq);
 812         trans_pcie->txq = NULL;
 813
 814         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 815
 816         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 817 }
 818
 819 /*
 820  * iwl_pcie_tx_alloc - allocate TX context
 821  * Allocate all Tx DMA structures and initialize them
 822  */
 823 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 824 {
 825         int ret;
 826         int txq_id, slots_num;
 827         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 828
 829         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 830                         sizeof(struct iwlagn_scd_bc_tbl);
 831
 832         /*It is not allowed to alloc twice, so warn when this happens.
 833          * We cannot rely on the previous allocation, so free and fail */
 834         if (WARN_ON(trans_pcie->txq)) {
 835                 ret = -EINVAL;
 836                 goto error;
 837         }
 838
 839         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 840                                    scd_bc_tbls_size);
 841         if (ret) {
 842                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 843                 goto error;
 844         }
 845
 846         /* Alloc keep-warm buffer */
 847         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 848         if (ret) {
 849                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 850                 goto error;
 851         }
 852
 853         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 854                                   sizeof(struct iwl_txq), GFP_KERNEL);
 855         if (!trans_pcie->txq) {
 856                 IWL_ERR(trans, "Not enough memory for txq\n");
 857                 ret = -ENOMEM;
 858                 goto error;
 859         }
 860
 861         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 862         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 863              txq_id++) {
 864                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 865                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 866                 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
 867                                           slots_num, txq_id);
 868                 if (ret) {
 869                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 870                         goto error;
 871                 }
 872         }
 873
 874         return 0;
 875
 876 error:
 877         iwl_pcie_tx_free(trans);
 878
 879         return ret;
 880 }
 881 int iwl_pcie_tx_init(struct iwl_trans *trans)
 882 {
 883         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 884         int ret;
 885         int txq_id, slots_num;
 886         bool alloc = false;
 887
 888         if (!trans_pcie->txq) {
 889                 ret = iwl_pcie_tx_alloc(trans);
 890                 if (ret)
 891                         goto error;
 892                 alloc = true;
 893         }
 894
 895         spin_lock(&trans_pcie->irq_lock);
 896
 897         /* Turn off all Tx DMA fifos */
 898         iwl_scd_deactivate_fifos(trans);
 899
 900         /* Tell NIC where to find the "keep warm" buffer */
 901         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 902                            trans_pcie->kw.dma >> 4);
 903
 904         spin_unlock(&trans_pcie->irq_lock);
 905
 906         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 907         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 908              txq_id++) {
 909                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 910                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 911                 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
 912                                          slots_num, txq_id);
 913                 if (ret) {
 914                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 915                         goto error;
 916                 }
 917         }
 918
 919         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
 920         if (trans->cfg->base_params->num_of_queues > 20)
 921                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
 922                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
 923
 924         return 0;
 925 error:
 926         /*Upon error, free only if we allocated something */
 927         if (alloc)
 928                 iwl_pcie_tx_free(trans);
 929         return ret;
 930 }
 931
 932 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
 933 {
 934         lockdep_assert_held(&txq->lock);
 935
 936         if (!txq->wd_timeout)
 937                 return;
 938
 939         /*
 940          * station is asleep and we send data - that must
 941          * be uAPSD or PS-Poll. Don't rearm the timer.
 942          */
 943         if (txq->frozen)
 944                 return;
 945
 946         /*
 947          * if empty delete timer, otherwise move timer forward
 948          * since we're making progress on this queue
 949          */
 950         if (txq->q.read_ptr == txq->q.write_ptr)
 951                 del_timer(&txq->stuck_timer);
 952         else
 953                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
 954 }
 955
 956 /* Frees buffers until index _not_ inclusive */
 957 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 958                             struct sk_buff_head *skbs)
 959 {
 960         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 961         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 962         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
 963         struct iwl_queue *q = &txq->q;
 964         int last_to_free;
 965
 966         /* This function is not meant to release cmd queue*/
 967         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
 968                 return;
 969
 970         spin_lock_bh(&txq->lock);
 971
 972         if (!txq->active) {
 973                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
 974                                     txq_id, ssn);
 975                 goto out;
 976         }
 977
 978         if (txq->q.read_ptr == tfd_num)
 979                 goto out;
 980
 981         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
 982                            txq_id, txq->q.read_ptr, tfd_num, ssn);
 983
 984         /*Since we free until index _not_ inclusive, the one before index is
 985          * the last we will free. This one must be used */
 986         last_to_free = iwl_queue_dec_wrap(tfd_num);
 987
 988         if (!iwl_queue_used(q, last_to_free)) {
 989                 IWL_ERR(trans,
 990                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
 991                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
 992                         q->write_ptr, q->read_ptr);
 993                 goto out;
 994         }
 995
 996         if (WARN_ON(!skb_queue_empty(skbs)))
 997                 goto out;
 998
 999         for (;
1000              q->read_ptr != tfd_num;
1001              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1002
1003                 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
1004                         continue;
1005
1006                 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
1007
1008                 txq->entries[txq->q.read_ptr].skb = NULL;
1009
1010                 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1011
1012                 iwl_pcie_txq_free_tfd(trans, txq);
1013         }
1014
1015         iwl_pcie_txq_progress(txq);
1016
1017         if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1018                 iwl_wake_queue(trans, txq);
1019
1020         if (q->read_ptr == q->write_ptr) {
1021                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1022                 iwl_trans_pcie_unref(trans);
1023         }
1024
1025 out:
1026         spin_unlock_bh(&txq->lock);
1027 }
1028
1029 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1030                                       const struct iwl_host_cmd *cmd)
1031 {
1032         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1033         int ret;
1034
1035         lockdep_assert_held(&trans_pcie->reg_lock);
1036
1037         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1038             !trans_pcie->ref_cmd_in_flight) {
1039                 trans_pcie->ref_cmd_in_flight = true;
1040                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1041                 iwl_trans_pcie_ref(trans);
1042         }
1043
1044         /*
1045          * wake up the NIC to make sure that the firmware will see the host
1046          * command - we will let the NIC sleep once all the host commands
1047          * returned. This needs to be done only on NICs that have
1048          * apmg_wake_up_wa set.
1049          */
1050         if (trans->cfg->base_params->apmg_wake_up_wa &&
1051             !trans_pcie->cmd_hold_nic_awake) {
1052                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1053                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1054
1055                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1056                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1057                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1058                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1059                                    15000);
1060                 if (ret < 0) {
1061                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1062                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1063                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1064                         return -EIO;
1065                 }
1066                 trans_pcie->cmd_hold_nic_awake = true;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1073 {
1074         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1075
1076         lockdep_assert_held(&trans_pcie->reg_lock);
1077
1078         if (trans_pcie->ref_cmd_in_flight) {
1079                 trans_pcie->ref_cmd_in_flight = false;
1080                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1081                 iwl_trans_pcie_unref(trans);
1082         }
1083
1084         if (trans->cfg->base_params->apmg_wake_up_wa) {
1085                 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
1086                         return 0;
1087
1088                 trans_pcie->cmd_hold_nic_awake = false;
1089                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1090                                            CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1091         }
1092         return 0;
1093 }
1094
1095 /*
1096  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1097  *
1098  * When FW advances 'R' index, all entries between old and new 'R' index
1099  * need to be reclaimed. As result, some free space forms.  If there is
1100  * enough free space (> low mark), wake the stack that feeds us.
1101  */
1102 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1103 {
1104         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1106         struct iwl_queue *q = &txq->q;
1107         unsigned long flags;
1108         int nfreed = 0;
1109
1110         lockdep_assert_held(&txq->lock);
1111
1112         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1113                 IWL_ERR(trans,
1114                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1115                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1116                         q->write_ptr, q->read_ptr);
1117                 return;
1118         }
1119
1120         for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1121              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1122
1123                 if (nfreed++ > 0) {
1124                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1125                                 idx, q->write_ptr, q->read_ptr);
1126                         iwl_force_nmi(trans);
1127                 }
1128         }
1129
1130         if (q->read_ptr == q->write_ptr) {
1131                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1132                 iwl_pcie_clear_cmd_in_flight(trans);
1133                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1134         }
1135
1136         iwl_pcie_txq_progress(txq);
1137 }
1138
1139 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1140                                  u16 txq_id)
1141 {
1142         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1143         u32 tbl_dw_addr;
1144         u32 tbl_dw;
1145         u16 scd_q2ratid;
1146
1147         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1148
1149         tbl_dw_addr = trans_pcie->scd_base_addr +
1150                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1151
1152         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1153
1154         if (txq_id & 0x1)
1155                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1156         else
1157                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1158
1159         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1160
1161         return 0;
1162 }
1163
1164 /* Receiver address (actually, Rx station's index into station table),
1165  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1166 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1167
1168 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1169                                const struct iwl_trans_txq_scd_cfg *cfg,
1170                                unsigned int wdg_timeout)
1171 {
1172         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1173         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1174         int fifo = -1;
1175
1176         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1177                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1178
1179         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1180
1181         if (cfg) {
1182                 fifo = cfg->fifo;
1183
1184                 /* Disable the scheduler prior configuring the cmd queue */
1185                 if (txq_id == trans_pcie->cmd_queue &&
1186                     trans_pcie->scd_set_active)
1187                         iwl_scd_enable_set_active(trans, 0);
1188
1189                 /* Stop this Tx queue before configuring it */
1190                 iwl_scd_txq_set_inactive(trans, txq_id);
1191
1192                 /* Set this queue as a chain-building queue unless it is CMD */
1193                 if (txq_id != trans_pcie->cmd_queue)
1194                         iwl_scd_txq_set_chain(trans, txq_id);
1195
1196                 if (cfg->aggregate) {
1197                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1198
1199                         /* Map receiver-address / traffic-ID to this queue */
1200                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1201
1202                         /* enable aggregations for the queue */
1203                         iwl_scd_txq_enable_agg(trans, txq_id);
1204                         txq->ampdu = true;
1205                 } else {
1206                         /*
1207                          * disable aggregations for the queue, this will also
1208                          * make the ra_tid mapping configuration irrelevant
1209                          * since it is now a non-AGG queue.
1210                          */
1211                         iwl_scd_txq_disable_agg(trans, txq_id);
1212
1213                         ssn = txq->q.read_ptr;
1214                 }
1215         }
1216
1217         /* Place first TFD at index corresponding to start sequence number.
1218          * Assumes that ssn_idx is valid (!= 0xFFF) */
1219         txq->q.read_ptr = (ssn & 0xff);
1220         txq->q.write_ptr = (ssn & 0xff);
1221         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1222                            (ssn & 0xff) | (txq_id << 8));
1223
1224         if (cfg) {
1225                 u8 frame_limit = cfg->frame_limit;
1226
1227                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1228
1229                 /* Set up Tx window size and frame limit for this queue */
1230                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1231                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1232                 iwl_trans_write_mem32(trans,
1233                         trans_pcie->scd_base_addr +
1234                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1235                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1236                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1237                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1238                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1239
1240                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1241                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1242                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1243                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1244                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1245                                SCD_QUEUE_STTS_REG_MSK);
1246
1247                 /* enable the scheduler for this queue (only) */
1248                 if (txq_id == trans_pcie->cmd_queue &&
1249                     trans_pcie->scd_set_active)
1250                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1251
1252                 IWL_DEBUG_TX_QUEUES(trans,
1253                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1254                                     txq_id, fifo, ssn & 0xff);
1255         } else {
1256                 IWL_DEBUG_TX_QUEUES(trans,
1257                                     "Activate queue %d WrPtr: %d\n",
1258                                     txq_id, ssn & 0xff);
1259         }
1260
1261         txq->active = true;
1262 }
1263
1264 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1265                                 bool configure_scd)
1266 {
1267         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268         u32 stts_addr = trans_pcie->scd_base_addr +
1269                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1270         static const u32 zero_val[4] = {};
1271
1272         trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1273         trans_pcie->txq[txq_id].frozen = false;
1274
1275         /*
1276          * Upon HW Rfkill - we stop the device, and then stop the queues
1277          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1278          * allow the op_mode to call txq_disable after it already called
1279          * stop_device.
1280          */
1281         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1282                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1283                           "queue %d not used", txq_id);
1284                 return;
1285         }
1286
1287         if (configure_scd) {
1288                 iwl_scd_txq_set_inactive(trans, txq_id);
1289
1290                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1291                                     ARRAY_SIZE(zero_val));
1292         }
1293
1294         iwl_pcie_txq_unmap(trans, txq_id);
1295         trans_pcie->txq[txq_id].ampdu = false;
1296
1297         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1298 }
1299
1300 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1301
1302 /*
1303  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1304  * @priv: device private data point
1305  * @cmd: a pointer to the ucode command structure
1306  *
1307  * The function returns < 0 values to indicate the operation
1308  * failed. On success, it returns the index (>= 0) of command in the
1309  * command queue.
1310  */
1311 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1312                                  struct iwl_host_cmd *cmd)
1313 {
1314         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1316         struct iwl_queue *q = &txq->q;
1317         struct iwl_device_cmd *out_cmd;
1318         struct iwl_cmd_meta *out_meta;
1319         unsigned long flags;
1320         void *dup_buf = NULL;
1321         dma_addr_t phys_addr;
1322         int idx;
1323         u16 copy_size, cmd_size, scratch_size;
1324         bool had_nocopy = false;
1325         u8 group_id = iwl_cmd_groupid(cmd->id);
1326         int i, ret;
1327         u32 cmd_pos;
1328         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1329         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1330
1331         if (WARN(!trans_pcie->wide_cmd_header && group_id != 0,
1332                  "unsupported wide command %#x\n", cmd->id))
1333                 return -EINVAL;
1334
1335         if (group_id != 0) {
1336                 copy_size = sizeof(struct iwl_cmd_header_wide);
1337                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1338         } else {
1339                 copy_size = sizeof(struct iwl_cmd_header);
1340                 cmd_size = sizeof(struct iwl_cmd_header);
1341         }
1342
1343         /* need one for the header if the first is NOCOPY */
1344         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1345
1346         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1347                 cmddata[i] = cmd->data[i];
1348                 cmdlen[i] = cmd->len[i];
1349
1350                 if (!cmd->len[i])
1351                         continue;
1352
1353                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1354                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1355                         int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1356
1357                         if (copy > cmdlen[i])
1358                                 copy = cmdlen[i];
1359                         cmdlen[i] -= copy;
1360                         cmddata[i] += copy;
1361                         copy_size += copy;
1362                 }
1363
1364                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1365                         had_nocopy = true;
1366                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1367                                 idx = -EINVAL;
1368                                 goto free_dup_buf;
1369                         }
1370                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1371                         /*
1372                          * This is also a chunk that isn't copied
1373                          * to the static buffer so set had_nocopy.
1374                          */
1375                         had_nocopy = true;
1376
1377                         /* only allowed once */
1378                         if (WARN_ON(dup_buf)) {
1379                                 idx = -EINVAL;
1380                                 goto free_dup_buf;
1381                         }
1382
1383                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1384                                           GFP_ATOMIC);
1385                         if (!dup_buf)
1386                                 return -ENOMEM;
1387                 } else {
1388                         /* NOCOPY must not be followed by normal! */
1389                         if (WARN_ON(had_nocopy)) {
1390                                 idx = -EINVAL;
1391                                 goto free_dup_buf;
1392                         }
1393                         copy_size += cmdlen[i];
1394                 }
1395                 cmd_size += cmd->len[i];
1396         }
1397
1398         /*
1399          * If any of the command structures end up being larger than
1400          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1401          * allocated into separate TFDs, then we will need to
1402          * increase the size of the buffers.
1403          */
1404         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1405                  "Command %s (%#x) is too large (%d bytes)\n",
1406                  get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1407                 idx = -EINVAL;
1408                 goto free_dup_buf;
1409         }
1410
1411         spin_lock_bh(&txq->lock);
1412
1413         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1414                 spin_unlock_bh(&txq->lock);
1415
1416                 IWL_ERR(trans, "No space in command queue\n");
1417                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1418                 idx = -ENOSPC;
1419                 goto free_dup_buf;
1420         }
1421
1422         idx = get_cmd_index(q, q->write_ptr);
1423         out_cmd = txq->entries[idx].cmd;
1424         out_meta = &txq->entries[idx].meta;
1425
1426         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1427         if (cmd->flags & CMD_WANT_SKB)
1428                 out_meta->source = cmd;
1429
1430         /* set up the header */
1431         if (group_id != 0) {
1432                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1433                 out_cmd->hdr_wide.group_id = group_id;
1434                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1435                 out_cmd->hdr_wide.length =
1436                         cpu_to_le16(cmd_size -
1437                                     sizeof(struct iwl_cmd_header_wide));
1438                 out_cmd->hdr_wide.reserved = 0;
1439                 out_cmd->hdr_wide.sequence =
1440                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1441                                                  INDEX_TO_SEQ(q->write_ptr));
1442
1443                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1444                 copy_size = sizeof(struct iwl_cmd_header_wide);
1445         } else {
1446                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1447                 out_cmd->hdr.sequence =
1448                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1449                                                  INDEX_TO_SEQ(q->write_ptr));
1450                 out_cmd->hdr.group_id = 0;
1451
1452                 cmd_pos = sizeof(struct iwl_cmd_header);
1453                 copy_size = sizeof(struct iwl_cmd_header);
1454         }
1455
1456         /* and copy the data that needs to be copied */
1457         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1458                 int copy;
1459
1460                 if (!cmd->len[i])
1461                         continue;
1462
1463                 /* copy everything if not nocopy/dup */
1464                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1465                                            IWL_HCMD_DFL_DUP))) {
1466                         copy = cmd->len[i];
1467
1468                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1469                         cmd_pos += copy;
1470                         copy_size += copy;
1471                         continue;
1472                 }
1473
1474                 /*
1475                  * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1476                  * in total (for the scratchbuf handling), but copy up to what
1477                  * we can fit into the payload for debug dump purposes.
1478                  */
1479                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1480
1481                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1482                 cmd_pos += copy;
1483
1484                 /* However, treat copy_size the proper way, we need it below */
1485                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1486                         copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1487
1488                         if (copy > cmd->len[i])
1489                                 copy = cmd->len[i];
1490                         copy_size += copy;
1491                 }
1492         }
1493
1494         IWL_DEBUG_HC(trans,
1495                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1496                      get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1497                      group_id, out_cmd->hdr.cmd,
1498                      le16_to_cpu(out_cmd->hdr.sequence),
1499                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1500
1501         /* start the TFD with the scratchbuf */
1502         scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1503         memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1504         iwl_pcie_txq_build_tfd(trans, txq,
1505                                iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1506                                scratch_size, true);
1507
1508         /* map first command fragment, if any remains */
1509         if (copy_size > scratch_size) {
1510                 phys_addr = dma_map_single(trans->dev,
1511                                            ((u8 *)&out_cmd->hdr) + scratch_size,
1512                                            copy_size - scratch_size,
1513                                            DMA_TO_DEVICE);
1514                 if (dma_mapping_error(trans->dev, phys_addr)) {
1515                         iwl_pcie_tfd_unmap(trans, out_meta,
1516                                            &txq->tfds[q->write_ptr]);
1517                         idx = -ENOMEM;
1518                         goto out;
1519                 }
1520
1521                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1522                                        copy_size - scratch_size, false);
1523         }
1524
1525         /* map the remaining (adjusted) nocopy/dup fragments */
1526         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1527                 const void *data = cmddata[i];
1528
1529                 if (!cmdlen[i])
1530                         continue;
1531                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1532                                            IWL_HCMD_DFL_DUP)))
1533                         continue;
1534                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1535                         data = dup_buf;
1536                 phys_addr = dma_map_single(trans->dev, (void *)data,
1537                                            cmdlen[i], DMA_TO_DEVICE);
1538                 if (dma_mapping_error(trans->dev, phys_addr)) {
1539                         iwl_pcie_tfd_unmap(trans, out_meta,
1540                                            &txq->tfds[q->write_ptr]);
1541                         idx = -ENOMEM;
1542                         goto out;
1543                 }
1544
1545                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1546         }
1547
1548         out_meta->flags = cmd->flags;
1549         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1550                 kzfree(txq->entries[idx].free_buf);
1551         txq->entries[idx].free_buf = dup_buf;
1552
1553         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1554
1555         /* start timer if queue currently empty */
1556         if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1557                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1558
1559         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1560         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1561         if (ret < 0) {
1562                 idx = ret;
1563                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1564                 goto out;
1565         }
1566
1567         /* Increment and update queue's write index */
1568         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1569         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1570
1571         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1572
1573  out:
1574         spin_unlock_bh(&txq->lock);
1575  free_dup_buf:
1576         if (idx < 0)
1577                 kfree(dup_buf);
1578         return idx;
1579 }
1580
1581 /*
1582  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1583  * @rxb: Rx buffer to reclaim
1584  *
1585  * If an Rx buffer has an async callback associated with it the callback
1586  * will be executed.  The attached skb (if present) will only be freed
1587  * if the callback returns 1
1588  */
1589 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1590                             struct iwl_rx_cmd_buffer *rxb)
1591 {
1592         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1593         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1594         int txq_id = SEQ_TO_QUEUE(sequence);
1595         int index = SEQ_TO_INDEX(sequence);
1596         int cmd_index;
1597         struct iwl_device_cmd *cmd;
1598         struct iwl_cmd_meta *meta;
1599         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1600         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1601
1602         /* If a Tx command is being handled and it isn't in the actual
1603          * command queue then there a command routing bug has been introduced
1604          * in the queue management code. */
1605         if (WARN(txq_id != trans_pcie->cmd_queue,
1606                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1607                  txq_id, trans_pcie->cmd_queue, sequence,
1608                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1609                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1610                 iwl_print_hex_error(trans, pkt, 32);
1611                 return;
1612         }
1613
1614         spin_lock_bh(&txq->lock);
1615
1616         cmd_index = get_cmd_index(&txq->q, index);
1617         cmd = txq->entries[cmd_index].cmd;
1618         meta = &txq->entries[cmd_index].meta;
1619
1620         iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1621
1622         /* Input error checking is done when commands are added to queue. */
1623         if (meta->flags & CMD_WANT_SKB) {
1624                 struct page *p = rxb_steal_page(rxb);
1625
1626                 meta->source->resp_pkt = pkt;
1627                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1628                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1629         }
1630
1631         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1632
1633         if (!(meta->flags & CMD_ASYNC)) {
1634                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1635                         IWL_WARN(trans,
1636                                  "HCMD_ACTIVE already clear for command %s\n",
1637                                  get_cmd_string(trans_pcie, cmd->hdr.cmd));
1638                 }
1639                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1640                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1641                                get_cmd_string(trans_pcie, cmd->hdr.cmd));
1642                 wake_up(&trans_pcie->wait_command_queue);
1643         }
1644
1645         meta->flags = 0;
1646
1647         spin_unlock_bh(&txq->lock);
1648 }
1649
1650 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1651
1652 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1653                                     struct iwl_host_cmd *cmd)
1654 {
1655         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1656         int ret;
1657
1658         /* An asynchronous command can not expect an SKB to be set. */
1659         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1660                 return -EINVAL;
1661
1662         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1663         if (ret < 0) {
1664                 IWL_ERR(trans,
1665                         "Error sending %s: enqueue_hcmd failed: %d\n",
1666                         get_cmd_string(trans_pcie, cmd->id), ret);
1667                 return ret;
1668         }
1669         return 0;
1670 }
1671
1672 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1673                                    struct iwl_host_cmd *cmd)
1674 {
1675         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1676         int cmd_idx;
1677         int ret;
1678
1679         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1680                        get_cmd_string(trans_pcie, cmd->id));
1681
1682         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1683                                   &trans->status),
1684                  "Command %s: a command is already active!\n",
1685                  get_cmd_string(trans_pcie, cmd->id)))
1686                 return -EIO;
1687
1688         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1689                        get_cmd_string(trans_pcie, cmd->id));
1690
1691         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1692         if (cmd_idx < 0) {
1693                 ret = cmd_idx;
1694                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1695                 IWL_ERR(trans,
1696                         "Error sending %s: enqueue_hcmd failed: %d\n",
1697                         get_cmd_string(trans_pcie, cmd->id), ret);
1698                 return ret;
1699         }
1700
1701         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1702                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1703                                            &trans->status),
1704                                  HOST_COMPLETE_TIMEOUT);
1705         if (!ret) {
1706                 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1707                 struct iwl_queue *q = &txq->q;
1708
1709                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1710                         get_cmd_string(trans_pcie, cmd->id),
1711                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1712
1713                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1714                         q->read_ptr, q->write_ptr);
1715
1716                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1717                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1718                                get_cmd_string(trans_pcie, cmd->id));
1719                 ret = -ETIMEDOUT;
1720
1721                 iwl_force_nmi(trans);
1722                 iwl_trans_fw_error(trans);
1723
1724                 goto cancel;
1725         }
1726
1727         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1728                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1729                         get_cmd_string(trans_pcie, cmd->id));
1730                 dump_stack();
1731                 ret = -EIO;
1732                 goto cancel;
1733         }
1734
1735         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1736             test_bit(STATUS_RFKILL, &trans->status)) {
1737                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1738                 ret = -ERFKILL;
1739                 goto cancel;
1740         }
1741
1742         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1743                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1744                         get_cmd_string(trans_pcie, cmd->id));
1745                 ret = -EIO;
1746                 goto cancel;
1747         }
1748
1749         return 0;
1750
1751 cancel:
1752         if (cmd->flags & CMD_WANT_SKB) {
1753                 /*
1754                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1755                  * TX cmd queue. Otherwise in case the cmd comes
1756                  * in later, it will possibly set an invalid
1757                  * address (cmd->meta.source).
1758                  */
1759                 trans_pcie->txq[trans_pcie->cmd_queue].
1760                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1761         }
1762
1763         if (cmd->resp_pkt) {
1764                 iwl_free_resp(cmd);
1765                 cmd->resp_pkt = NULL;
1766         }
1767
1768         return ret;
1769 }
1770
1771 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1772 {
1773         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1774             test_bit(STATUS_RFKILL, &trans->status)) {
1775                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1776                                   cmd->id);
1777                 return -ERFKILL;
1778         }
1779
1780         if (cmd->flags & CMD_ASYNC)
1781                 return iwl_pcie_send_hcmd_async(trans, cmd);
1782
1783         /* We still can fail on RFKILL that can be asserted while we wait */
1784         return iwl_pcie_send_hcmd_sync(trans, cmd);
1785 }
1786
1787 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1788                       struct iwl_device_cmd *dev_cmd, int txq_id)
1789 {
1790         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1791         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1792         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1793         struct iwl_cmd_meta *out_meta;
1794         struct iwl_txq *txq;
1795         struct iwl_queue *q;
1796         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1797         void *tb1_addr;
1798         u16 len, tb1_len, tb2_len;
1799         bool wait_write_ptr;
1800         __le16 fc = hdr->frame_control;
1801         u8 hdr_len = ieee80211_hdrlen(fc);
1802         u16 wifi_seq;
1803
1804         txq = &trans_pcie->txq[txq_id];
1805         q = &txq->q;
1806
1807         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1808                       "TX on unused queue %d\n", txq_id))
1809                 return -EINVAL;
1810
1811         spin_lock(&txq->lock);
1812
1813         /* In AGG mode, the index in the ring must correspond to the WiFi
1814          * sequence number. This is a HW requirements to help the SCD to parse
1815          * the BA.
1816          * Check here that the packets are in the right place on the ring.
1817          */
1818         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1819         WARN_ONCE(txq->ampdu &&
1820                   (wifi_seq & 0xff) != q->write_ptr,
1821                   "Q: %d WiFi Seq %d tfdNum %d",
1822                   txq_id, wifi_seq, q->write_ptr);
1823
1824         /* Set up driver data for this TFD */
1825         txq->entries[q->write_ptr].skb = skb;
1826         txq->entries[q->write_ptr].cmd = dev_cmd;
1827
1828         dev_cmd->hdr.sequence =
1829                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1830                             INDEX_TO_SEQ(q->write_ptr)));
1831
1832         tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1833         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1834                        offsetof(struct iwl_tx_cmd, scratch);
1835
1836         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1837         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1838
1839         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1840         out_meta = &txq->entries[q->write_ptr].meta;
1841
1842         /*
1843          * The second TB (tb1) points to the remainder of the TX command
1844          * and the 802.11 header - dword aligned size
1845          * (This calculation modifies the TX command, so do it before the
1846          * setup of the first TB)
1847          */
1848         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1849               hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1850         tb1_len = ALIGN(len, 4);
1851
1852         /* Tell NIC about any 2-byte padding after MAC header */
1853         if (tb1_len != len)
1854                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1855
1856         /* The first TB points to the scratchbuf data - min_copy bytes */
1857         memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1858                IWL_HCMD_SCRATCHBUF_SIZE);
1859         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1860                                IWL_HCMD_SCRATCHBUF_SIZE, true);
1861
1862         /* there must be data left over for TB1 or this code must be changed */
1863         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1864
1865         /* map the data for TB1 */
1866         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1867         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1868         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1869                 goto out_err;
1870         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1871
1872         /*
1873          * Set up TFD's third entry to point directly to remainder
1874          * of skb, if any (802.11 null frames have no payload).
1875          */
1876         tb2_len = skb->len - hdr_len;
1877         if (tb2_len > 0) {
1878                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1879                                                      skb->data + hdr_len,
1880                                                      tb2_len, DMA_TO_DEVICE);
1881                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1882                         iwl_pcie_tfd_unmap(trans, out_meta,
1883                                            &txq->tfds[q->write_ptr]);
1884                         goto out_err;
1885                 }
1886                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1887         }
1888
1889         /* Set up entry for this TFD in Tx byte-count array */
1890         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1891
1892         trace_iwlwifi_dev_tx(trans->dev, skb,
1893                              &txq->tfds[txq->q.write_ptr],
1894                              sizeof(struct iwl_tfd),
1895                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1896                              skb->data + hdr_len, tb2_len);
1897         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1898                                   skb->data + hdr_len, tb2_len);
1899
1900         wait_write_ptr = ieee80211_has_morefrags(fc);
1901
1902         /* start timer if queue currently empty */
1903         if (q->read_ptr == q->write_ptr) {
1904                 if (txq->wd_timeout)
1905                         mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1906                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1907                 iwl_trans_pcie_ref(trans);
1908         }
1909
1910         /* Tell device the write index *just past* this latest filled TFD */
1911         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1912         if (!wait_write_ptr)
1913                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1914
1915         /*
1916          * At this point the frame is "transmitted" successfully
1917          * and we will get a TX status notification eventually.
1918          */
1919         if (iwl_queue_space(q) < q->high_mark) {
1920                 if (wait_write_ptr)
1921                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1922                 else
1923                         iwl_stop_queue(trans, txq);
1924         }
1925         spin_unlock(&txq->lock);
1926         return 0;
1927 out_err:
1928         spin_unlock(&txq->lock);
1929         return -1;
1930 }