1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
34 #include "iwl-debug.h"
39 #include "iwl-op-mode.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
67 ***************************************************/
68 static int iwl_queue_space(const struct iwl_queue *q)
74 * To avoid ambiguity between empty and completely full queues, there
75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
79 if (q->n_window < TFD_QUEUE_SIZE_MAX)
82 max = TFD_QUEUE_SIZE_MAX - 1;
85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
88 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
90 if (WARN_ON(used > max))
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
101 q->n_window = slots_num;
104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num)))
109 q->low_mark = q->n_window / 4;
113 q->high_mark = q->n_window / 8;
114 if (q->high_mark < 2)
123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
124 struct iwl_dma_ptr *ptr, size_t size)
126 if (WARN_ON(ptr->addr))
129 ptr->addr = dma_alloc_coherent(trans->dev, size,
130 &ptr->dma, GFP_KERNEL);
137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
138 struct iwl_dma_ptr *ptr)
140 if (unlikely(!ptr->addr))
143 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
144 memset(ptr, 0, sizeof(*ptr));
147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
149 struct iwl_txq *txq = (void *)data;
150 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
151 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
152 u32 scd_sram_addr = trans_pcie->scd_base_addr +
153 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
157 spin_lock(&txq->lock);
158 /* check if triggered erroneously */
159 if (txq->q.read_ptr == txq->q.write_ptr) {
160 spin_unlock(&txq->lock);
163 spin_unlock(&txq->lock);
165 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
166 jiffies_to_msecs(txq->wd_timeout));
167 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
168 txq->q.read_ptr, txq->q.write_ptr);
170 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
172 iwl_print_hex_error(trans, buf, sizeof(buf));
174 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
175 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
176 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
178 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
179 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
180 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
181 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
183 iwl_trans_read_mem32(trans,
184 trans_pcie->scd_base_addr +
185 SCD_TRANS_TBL_OFFSET_QUEUE(i));
188 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
190 tbl_dw = tbl_dw & 0x0000FFFF;
193 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194 i, active ? "" : "in", fifo, tbl_dw,
195 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
196 (TFD_QUEUE_SIZE_MAX - 1),
197 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
200 iwl_force_nmi(trans);
204 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
207 struct iwl_txq *txq, u16 byte_cnt)
209 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 int write_ptr = txq->q.write_ptr;
212 int txq_id = txq->q.id;
215 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
217 struct iwl_tx_cmd *tx_cmd =
218 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
222 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
224 sta_id = tx_cmd->sta_id;
225 sec_ctl = tx_cmd->sec_ctl;
227 switch (sec_ctl & TX_CMD_SEC_MSK) {
229 len += IEEE80211_CCMP_MIC_LEN;
231 case TX_CMD_SEC_TKIP:
232 len += IEEE80211_TKIP_ICV_LEN;
235 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
239 if (trans_pcie->bc_table_dword)
240 len = DIV_ROUND_UP(len, 4);
242 bc_ent = cpu_to_le16(len | (sta_id << 12));
244 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
246 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
248 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
251 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
254 struct iwl_trans_pcie *trans_pcie =
255 IWL_TRANS_GET_PCIE_TRANS(trans);
256 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
257 int txq_id = txq->q.id;
258 int read_ptr = txq->q.read_ptr;
261 struct iwl_tx_cmd *tx_cmd =
262 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
264 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
266 if (txq_id != trans_pcie->cmd_queue)
267 sta_id = tx_cmd->sta_id;
269 bc_ent = cpu_to_le16(1 | (sta_id << 12));
270 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
272 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
274 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
285 int txq_id = txq->q.id;
287 lockdep_assert_held(&txq->lock);
290 * explicitly wake up the NIC if:
291 * 1. shadow registers aren't enabled
292 * 2. NIC is woken up for CMD regardless of shadow outside this function
293 * 3. there is a chance that the NIC is asleep
295 if (!trans->cfg->base_params->shadow_reg_enable &&
296 txq_id != trans_pcie->cmd_queue &&
297 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
299 * wake up nic if it's powered down ...
300 * uCode will wake up, and interrupt us again, so next
301 * time we'll skip this part.
303 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
305 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
306 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
308 iwl_set_bit(trans, CSR_GP_CNTRL,
309 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
310 txq->need_update = true;
316 * if not in power-save mode, uCode will never sleep when we're
317 * trying to tx (during RFKILL, we're not trying to tx).
319 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
320 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
323 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
328 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329 struct iwl_txq *txq = &trans_pcie->txq[i];
331 spin_lock_bh(&txq->lock);
332 if (trans_pcie->txq[i].need_update) {
333 iwl_pcie_txq_inc_wr_ptr(trans, txq);
334 trans_pcie->txq[i].need_update = false;
336 spin_unlock_bh(&txq->lock);
340 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
342 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
344 dma_addr_t addr = get_unaligned_le32(&tb->lo);
345 if (sizeof(dma_addr_t) > sizeof(u32))
347 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
352 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
353 dma_addr_t addr, u16 len)
355 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
356 u16 hi_n_len = len << 4;
358 put_unaligned_le32(addr, &tb->lo);
359 if (sizeof(dma_addr_t) > sizeof(u32))
360 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
362 tb->hi_n_len = cpu_to_le16(hi_n_len);
364 tfd->num_tbs = idx + 1;
367 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
369 return tfd->num_tbs & 0x1f;
372 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
373 struct iwl_cmd_meta *meta,
379 /* Sanity check on number of chunks */
380 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
382 if (num_tbs >= IWL_NUM_OF_TBS) {
383 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
384 /* @todo issue fatal error, it is quite serious situation */
388 /* first TB is never freed - it's the scratchbuf data */
390 for (i = 1; i < num_tbs; i++)
391 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
392 iwl_pcie_tfd_tb_get_len(tfd, i),
399 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
400 * @trans - transport private data
402 * @dma_dir - the direction of the DMA mapping
404 * Does NOT advance any TFD circular buffer read/write indexes
405 * Does NOT free the TFD itself (which is within circular buffer)
407 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
409 struct iwl_tfd *tfd_tmp = txq->tfds;
411 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
412 * idx is bounded by n_window
414 int rd_ptr = txq->q.read_ptr;
415 int idx = get_cmd_index(&txq->q, rd_ptr);
417 lockdep_assert_held(&txq->lock);
419 /* We have only q->n_window txq->entries, but we use
420 * TFD_QUEUE_SIZE_MAX tfds
422 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
428 skb = txq->entries[idx].skb;
430 /* Can be called from irqs-disabled context
431 * If skb is not NULL, it means that the whole queue is being
432 * freed and that the queue is not empty - free the skb
435 iwl_op_mode_free_skb(trans->op_mode, skb);
436 txq->entries[idx].skb = NULL;
441 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
442 dma_addr_t addr, u16 len, bool reset)
445 struct iwl_tfd *tfd, *tfd_tmp;
450 tfd = &tfd_tmp[q->write_ptr];
453 memset(tfd, 0, sizeof(*tfd));
455 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
457 /* Each TFD can point to a maximum 20 Tx buffers */
458 if (num_tbs >= IWL_NUM_OF_TBS) {
459 IWL_ERR(trans, "Error can not send more than %d chunks\n",
464 if (WARN(addr & ~IWL_TX_DMA_MASK,
465 "Unaligned address = %llx\n", (unsigned long long)addr))
468 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
473 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
474 struct iwl_txq *txq, int slots_num,
477 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
478 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
479 size_t scratchbuf_sz;
482 if (WARN_ON(txq->entries || txq->tfds))
485 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
487 txq->trans_pcie = trans_pcie;
489 txq->q.n_window = slots_num;
491 txq->entries = kcalloc(slots_num,
492 sizeof(struct iwl_pcie_txq_entry),
498 if (txq_id == trans_pcie->cmd_queue)
499 for (i = 0; i < slots_num; i++) {
500 txq->entries[i].cmd =
501 kmalloc(sizeof(struct iwl_device_cmd),
503 if (!txq->entries[i].cmd)
507 /* Circular buffer of transmit frame descriptors (TFDs),
508 * shared with device */
509 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
510 &txq->q.dma_addr, GFP_KERNEL);
514 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
515 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
516 sizeof(struct iwl_cmd_header) +
517 offsetof(struct iwl_tx_cmd, scratch));
519 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
521 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
522 &txq->scratchbufs_dma,
524 if (!txq->scratchbufs)
531 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
533 if (txq->entries && txq_id == trans_pcie->cmd_queue)
534 for (i = 0; i < slots_num; i++)
535 kfree(txq->entries[i].cmd);
543 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
544 int slots_num, u32 txq_id)
548 txq->need_update = false;
550 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
551 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
552 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
554 /* Initialize queue's high/low-water marks, and head/tail indexes */
555 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
559 spin_lock_init(&txq->lock);
562 * Tell nic where to find circular buffer of Tx Frame Descriptors for
563 * given Tx queue, and enable the DMA channel used for that queue.
564 * Circular buffer (TFD queue in DRAM) physical base address */
565 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
566 txq->q.dma_addr >> 8);
572 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
574 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
578 struct iwl_queue *q = &txq->q;
580 spin_lock_bh(&txq->lock);
581 while (q->write_ptr != q->read_ptr) {
582 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
583 txq_id, q->read_ptr);
584 iwl_pcie_txq_free_tfd(trans, txq);
585 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
588 spin_unlock_bh(&txq->lock);
590 /* just in case - this queue may have been stopped */
591 iwl_wake_queue(trans, txq);
595 * iwl_pcie_txq_free - Deallocate DMA queue.
596 * @txq: Transmit queue to deallocate.
598 * Empty queue by removing and destroying all BD's.
600 * 0-fill, but do not free "txq" descriptor structure.
602 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
604 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
605 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
606 struct device *dev = trans->dev;
612 iwl_pcie_txq_unmap(trans, txq_id);
614 /* De-alloc array of command/tx buffers */
615 if (txq_id == trans_pcie->cmd_queue)
616 for (i = 0; i < txq->q.n_window; i++) {
617 kzfree(txq->entries[i].cmd);
618 kzfree(txq->entries[i].free_buf);
621 /* De-alloc circular buffer of TFDs */
623 dma_free_coherent(dev,
624 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
625 txq->tfds, txq->q.dma_addr);
629 dma_free_coherent(dev,
630 sizeof(*txq->scratchbufs) * txq->q.n_window,
631 txq->scratchbufs, txq->scratchbufs_dma);
637 del_timer_sync(&txq->stuck_timer);
639 /* 0-fill queue descriptor structure */
640 memset(txq, 0, sizeof(*txq));
643 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
646 int nq = trans->cfg->base_params->num_of_queues;
649 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
650 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
652 /* make sure all queue are not stopped/used */
653 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
654 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
656 trans_pcie->scd_base_addr =
657 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
659 WARN_ON(scd_base_addr != 0 &&
660 scd_base_addr != trans_pcie->scd_base_addr);
662 /* reset context data, TX status and translation data */
663 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
664 SCD_CONTEXT_MEM_LOWER_BOUND,
667 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
668 trans_pcie->scd_bc_tbls.dma >> 10);
670 /* The chain extension of the SCD doesn't work well. This feature is
671 * enabled by default by the HW, so we need to disable it manually.
673 if (trans->cfg->base_params->scd_chain_ext_wa)
674 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
676 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
677 trans_pcie->cmd_fifo,
678 trans_pcie->cmd_q_wdg_timeout);
680 /* Activate all Tx DMA/FIFO channels */
681 iwl_scd_activate_fifos(trans);
683 /* Enable DMA channel */
684 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
685 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
687 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
689 /* Update FH chicken bits */
690 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
691 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
692 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
694 /* Enable L1-Active */
695 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
696 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
697 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
700 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
702 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
705 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
707 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
709 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
710 txq->q.dma_addr >> 8);
711 iwl_pcie_txq_unmap(trans, txq_id);
713 txq->q.write_ptr = 0;
716 /* Tell NIC where to find the "keep warm" buffer */
717 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
718 trans_pcie->kw.dma >> 4);
721 * Send 0 as the scd_base_addr since the device may have be reset
722 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
725 iwl_pcie_tx_start(trans, 0);
728 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
735 spin_lock(&trans_pcie->irq_lock);
737 if (!iwl_trans_grab_nic_access(trans, false, &flags))
740 /* Stop each Tx DMA channel */
741 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
742 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
743 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
746 /* Wait for DMA channels to be idle */
747 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
750 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
751 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
753 iwl_trans_release_nic_access(trans, &flags);
756 spin_unlock(&trans_pcie->irq_lock);
760 * iwl_pcie_tx_stop - Stop all Tx DMA channels
762 int iwl_pcie_tx_stop(struct iwl_trans *trans)
764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
767 /* Turn off all Tx DMA fifos */
768 iwl_scd_deactivate_fifos(trans);
770 /* Turn off all Tx DMA channels */
771 iwl_pcie_tx_stop_fh(trans);
774 * This function can be called before the op_mode disabled the
775 * queues. This happens when we have an rfkill interrupt.
776 * Since we stop Tx altogether - mark the queues as stopped.
778 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
779 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
781 /* This can happen: start_hw, stop_device */
782 if (!trans_pcie->txq)
785 /* Unmap DMA from host system and free skb's */
786 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
788 iwl_pcie_txq_unmap(trans, txq_id);
794 * iwl_trans_tx_free - Free TXQ Context
796 * Destroy all TX DMA queues and structures
798 void iwl_pcie_tx_free(struct iwl_trans *trans)
801 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
804 if (trans_pcie->txq) {
806 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
807 iwl_pcie_txq_free(trans, txq_id);
810 kfree(trans_pcie->txq);
811 trans_pcie->txq = NULL;
813 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
815 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
819 * iwl_pcie_tx_alloc - allocate TX context
820 * Allocate all Tx DMA structures and initialize them
822 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
825 int txq_id, slots_num;
826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
828 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
829 sizeof(struct iwlagn_scd_bc_tbl);
831 /*It is not allowed to alloc twice, so warn when this happens.
832 * We cannot rely on the previous allocation, so free and fail */
833 if (WARN_ON(trans_pcie->txq)) {
838 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
841 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
845 /* Alloc keep-warm buffer */
846 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
848 IWL_ERR(trans, "Keep Warm allocation failed\n");
852 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
853 sizeof(struct iwl_txq), GFP_KERNEL);
854 if (!trans_pcie->txq) {
855 IWL_ERR(trans, "Not enough memory for txq\n");
860 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
861 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
863 slots_num = (txq_id == trans_pcie->cmd_queue) ?
864 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
865 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
868 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
876 iwl_pcie_tx_free(trans);
880 int iwl_pcie_tx_init(struct iwl_trans *trans)
882 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
884 int txq_id, slots_num;
887 if (!trans_pcie->txq) {
888 ret = iwl_pcie_tx_alloc(trans);
894 spin_lock(&trans_pcie->irq_lock);
896 /* Turn off all Tx DMA fifos */
897 iwl_scd_deactivate_fifos(trans);
899 /* Tell NIC where to find the "keep warm" buffer */
900 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
901 trans_pcie->kw.dma >> 4);
903 spin_unlock(&trans_pcie->irq_lock);
905 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
906 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
908 slots_num = (txq_id == trans_pcie->cmd_queue) ?
909 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
910 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
913 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
918 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
919 if (trans->cfg->base_params->num_of_queues > 20)
920 iwl_set_bits_prph(trans, SCD_GP_CTRL,
921 SCD_GP_CTRL_ENABLE_31_QUEUES);
925 /*Upon error, free only if we allocated something */
927 iwl_pcie_tx_free(trans);
931 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
933 lockdep_assert_held(&txq->lock);
935 if (!txq->wd_timeout)
939 * station is asleep and we send data - that must
940 * be uAPSD or PS-Poll. Don't rearm the timer.
946 * if empty delete timer, otherwise move timer forward
947 * since we're making progress on this queue
949 if (txq->q.read_ptr == txq->q.write_ptr)
950 del_timer(&txq->stuck_timer);
952 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
955 /* Frees buffers until index _not_ inclusive */
956 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
957 struct sk_buff_head *skbs)
959 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
960 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
961 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
962 struct iwl_queue *q = &txq->q;
965 /* This function is not meant to release cmd queue*/
966 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
969 spin_lock_bh(&txq->lock);
972 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
977 if (txq->q.read_ptr == tfd_num)
980 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
981 txq_id, txq->q.read_ptr, tfd_num, ssn);
983 /*Since we free until index _not_ inclusive, the one before index is
984 * the last we will free. This one must be used */
985 last_to_free = iwl_queue_dec_wrap(tfd_num);
987 if (!iwl_queue_used(q, last_to_free)) {
989 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
990 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
991 q->write_ptr, q->read_ptr);
995 if (WARN_ON(!skb_queue_empty(skbs)))
999 q->read_ptr != tfd_num;
1000 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1002 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
1005 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
1007 txq->entries[txq->q.read_ptr].skb = NULL;
1009 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1011 iwl_pcie_txq_free_tfd(trans, txq);
1014 iwl_pcie_txq_progress(txq);
1016 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1017 iwl_wake_queue(trans, txq);
1019 if (q->read_ptr == q->write_ptr) {
1020 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1021 iwl_trans_pcie_unref(trans);
1025 spin_unlock_bh(&txq->lock);
1028 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1029 const struct iwl_host_cmd *cmd)
1031 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1034 lockdep_assert_held(&trans_pcie->reg_lock);
1036 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1037 !trans_pcie->ref_cmd_in_flight) {
1038 trans_pcie->ref_cmd_in_flight = true;
1039 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1040 iwl_trans_pcie_ref(trans);
1044 * wake up the NIC to make sure that the firmware will see the host
1045 * command - we will let the NIC sleep once all the host commands
1046 * returned. This needs to be done only on NICs that have
1047 * apmg_wake_up_wa set.
1049 if (trans->cfg->base_params->apmg_wake_up_wa &&
1050 !trans_pcie->cmd_hold_nic_awake) {
1051 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1052 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1054 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1055 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1056 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1057 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1060 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1061 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1062 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1065 trans_pcie->cmd_hold_nic_awake = true;
1071 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1073 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1075 lockdep_assert_held(&trans_pcie->reg_lock);
1077 if (trans_pcie->ref_cmd_in_flight) {
1078 trans_pcie->ref_cmd_in_flight = false;
1079 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1080 iwl_trans_pcie_unref(trans);
1083 if (trans->cfg->base_params->apmg_wake_up_wa) {
1084 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
1087 trans_pcie->cmd_hold_nic_awake = false;
1088 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1089 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1095 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1097 * When FW advances 'R' index, all entries between old and new 'R' index
1098 * need to be reclaimed. As result, some free space forms. If there is
1099 * enough free space (> low mark), wake the stack that feeds us.
1101 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1104 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1105 struct iwl_queue *q = &txq->q;
1106 unsigned long flags;
1109 lockdep_assert_held(&txq->lock);
1111 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1113 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1114 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1115 q->write_ptr, q->read_ptr);
1119 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1120 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1123 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1124 idx, q->write_ptr, q->read_ptr);
1125 iwl_force_nmi(trans);
1129 if (q->read_ptr == q->write_ptr) {
1130 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1131 iwl_pcie_clear_cmd_in_flight(trans);
1132 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1135 iwl_pcie_txq_progress(txq);
1138 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1146 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1148 tbl_dw_addr = trans_pcie->scd_base_addr +
1149 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1151 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1154 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1156 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1158 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1163 /* Receiver address (actually, Rx station's index into station table),
1164 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1165 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1167 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1168 const struct iwl_trans_txq_scd_cfg *cfg,
1169 unsigned int wdg_timeout)
1171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1172 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1175 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1176 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1178 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1183 /* Disable the scheduler prior configuring the cmd queue */
1184 if (txq_id == trans_pcie->cmd_queue &&
1185 trans_pcie->scd_set_active)
1186 iwl_scd_enable_set_active(trans, 0);
1188 /* Stop this Tx queue before configuring it */
1189 iwl_scd_txq_set_inactive(trans, txq_id);
1191 /* Set this queue as a chain-building queue unless it is CMD */
1192 if (txq_id != trans_pcie->cmd_queue)
1193 iwl_scd_txq_set_chain(trans, txq_id);
1195 if (cfg->aggregate) {
1196 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1198 /* Map receiver-address / traffic-ID to this queue */
1199 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1201 /* enable aggregations for the queue */
1202 iwl_scd_txq_enable_agg(trans, txq_id);
1206 * disable aggregations for the queue, this will also
1207 * make the ra_tid mapping configuration irrelevant
1208 * since it is now a non-AGG queue.
1210 iwl_scd_txq_disable_agg(trans, txq_id);
1212 ssn = txq->q.read_ptr;
1216 /* Place first TFD at index corresponding to start sequence number.
1217 * Assumes that ssn_idx is valid (!= 0xFFF) */
1218 txq->q.read_ptr = (ssn & 0xff);
1219 txq->q.write_ptr = (ssn & 0xff);
1220 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1221 (ssn & 0xff) | (txq_id << 8));
1224 u8 frame_limit = cfg->frame_limit;
1226 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1228 /* Set up Tx window size and frame limit for this queue */
1229 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1230 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1231 iwl_trans_write_mem32(trans,
1232 trans_pcie->scd_base_addr +
1233 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1234 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1235 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1236 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1237 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1239 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1240 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1241 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1242 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1243 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1244 SCD_QUEUE_STTS_REG_MSK);
1246 /* enable the scheduler for this queue (only) */
1247 if (txq_id == trans_pcie->cmd_queue &&
1248 trans_pcie->scd_set_active)
1249 iwl_scd_enable_set_active(trans, BIT(txq_id));
1251 IWL_DEBUG_TX_QUEUES(trans,
1252 "Activate queue %d on FIFO %d WrPtr: %d\n",
1253 txq_id, fifo, ssn & 0xff);
1255 IWL_DEBUG_TX_QUEUES(trans,
1256 "Activate queue %d WrPtr: %d\n",
1257 txq_id, ssn & 0xff);
1263 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1266 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1267 u32 stts_addr = trans_pcie->scd_base_addr +
1268 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1269 static const u32 zero_val[4] = {};
1271 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1272 trans_pcie->txq[txq_id].frozen = false;
1275 * Upon HW Rfkill - we stop the device, and then stop the queues
1276 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1277 * allow the op_mode to call txq_disable after it already called
1280 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1281 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1282 "queue %d not used", txq_id);
1286 if (configure_scd) {
1287 iwl_scd_txq_set_inactive(trans, txq_id);
1289 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1290 ARRAY_SIZE(zero_val));
1293 iwl_pcie_txq_unmap(trans, txq_id);
1294 trans_pcie->txq[txq_id].ampdu = false;
1296 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1299 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1302 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1303 * @priv: device private data point
1304 * @cmd: a pointer to the ucode command structure
1306 * The function returns < 0 values to indicate the operation
1307 * failed. On success, it returns the index (>= 0) of command in the
1310 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1311 struct iwl_host_cmd *cmd)
1313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1314 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1315 struct iwl_queue *q = &txq->q;
1316 struct iwl_device_cmd *out_cmd;
1317 struct iwl_cmd_meta *out_meta;
1318 unsigned long flags;
1319 void *dup_buf = NULL;
1320 dma_addr_t phys_addr;
1322 u16 copy_size, cmd_size, scratch_size;
1323 bool had_nocopy = false;
1326 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1327 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1329 copy_size = sizeof(out_cmd->hdr);
1330 cmd_size = sizeof(out_cmd->hdr);
1332 /* need one for the header if the first is NOCOPY */
1333 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1335 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1336 cmddata[i] = cmd->data[i];
1337 cmdlen[i] = cmd->len[i];
1342 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1343 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1344 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1346 if (copy > cmdlen[i])
1353 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1355 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1359 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1361 * This is also a chunk that isn't copied
1362 * to the static buffer so set had_nocopy.
1366 /* only allowed once */
1367 if (WARN_ON(dup_buf)) {
1372 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1377 /* NOCOPY must not be followed by normal! */
1378 if (WARN_ON(had_nocopy)) {
1382 copy_size += cmdlen[i];
1384 cmd_size += cmd->len[i];
1388 * If any of the command structures end up being larger than
1389 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1390 * allocated into separate TFDs, then we will need to
1391 * increase the size of the buffers.
1393 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1394 "Command %s (%#x) is too large (%d bytes)\n",
1395 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1400 spin_lock_bh(&txq->lock);
1402 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1403 spin_unlock_bh(&txq->lock);
1405 IWL_ERR(trans, "No space in command queue\n");
1406 iwl_op_mode_cmd_queue_full(trans->op_mode);
1411 idx = get_cmd_index(q, q->write_ptr);
1412 out_cmd = txq->entries[idx].cmd;
1413 out_meta = &txq->entries[idx].meta;
1415 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1416 if (cmd->flags & CMD_WANT_SKB)
1417 out_meta->source = cmd;
1419 /* set up the header */
1421 out_cmd->hdr.cmd = cmd->id;
1422 out_cmd->hdr.flags = 0;
1423 out_cmd->hdr.sequence =
1424 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1425 INDEX_TO_SEQ(q->write_ptr));
1427 /* and copy the data that needs to be copied */
1428 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1429 copy_size = sizeof(out_cmd->hdr);
1430 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1436 /* copy everything if not nocopy/dup */
1437 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1438 IWL_HCMD_DFL_DUP))) {
1441 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1448 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1449 * in total (for the scratchbuf handling), but copy up to what
1450 * we can fit into the payload for debug dump purposes.
1452 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1454 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1457 /* However, treat copy_size the proper way, we need it below */
1458 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1459 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1461 if (copy > cmd->len[i])
1468 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1469 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1470 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1471 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1473 /* start the TFD with the scratchbuf */
1474 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1475 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1476 iwl_pcie_txq_build_tfd(trans, txq,
1477 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1478 scratch_size, true);
1480 /* map first command fragment, if any remains */
1481 if (copy_size > scratch_size) {
1482 phys_addr = dma_map_single(trans->dev,
1483 ((u8 *)&out_cmd->hdr) + scratch_size,
1484 copy_size - scratch_size,
1486 if (dma_mapping_error(trans->dev, phys_addr)) {
1487 iwl_pcie_tfd_unmap(trans, out_meta,
1488 &txq->tfds[q->write_ptr]);
1493 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1494 copy_size - scratch_size, false);
1497 /* map the remaining (adjusted) nocopy/dup fragments */
1498 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1499 const void *data = cmddata[i];
1503 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1506 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1508 phys_addr = dma_map_single(trans->dev, (void *)data,
1509 cmdlen[i], DMA_TO_DEVICE);
1510 if (dma_mapping_error(trans->dev, phys_addr)) {
1511 iwl_pcie_tfd_unmap(trans, out_meta,
1512 &txq->tfds[q->write_ptr]);
1517 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1520 out_meta->flags = cmd->flags;
1521 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1522 kzfree(txq->entries[idx].free_buf);
1523 txq->entries[idx].free_buf = dup_buf;
1525 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1527 /* start timer if queue currently empty */
1528 if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1529 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1531 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1532 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1535 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1539 /* Increment and update queue's write index */
1540 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1541 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1543 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1546 spin_unlock_bh(&txq->lock);
1554 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1555 * @rxb: Rx buffer to reclaim
1557 * If an Rx buffer has an async callback associated with it the callback
1558 * will be executed. The attached skb (if present) will only be freed
1559 * if the callback returns 1
1561 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1562 struct iwl_rx_cmd_buffer *rxb)
1564 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1565 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1566 int txq_id = SEQ_TO_QUEUE(sequence);
1567 int index = SEQ_TO_INDEX(sequence);
1569 struct iwl_device_cmd *cmd;
1570 struct iwl_cmd_meta *meta;
1571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1572 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1574 /* If a Tx command is being handled and it isn't in the actual
1575 * command queue then there a command routing bug has been introduced
1576 * in the queue management code. */
1577 if (WARN(txq_id != trans_pcie->cmd_queue,
1578 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1579 txq_id, trans_pcie->cmd_queue, sequence,
1580 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1581 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1582 iwl_print_hex_error(trans, pkt, 32);
1586 spin_lock_bh(&txq->lock);
1588 cmd_index = get_cmd_index(&txq->q, index);
1589 cmd = txq->entries[cmd_index].cmd;
1590 meta = &txq->entries[cmd_index].meta;
1592 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1594 /* Input error checking is done when commands are added to queue. */
1595 if (meta->flags & CMD_WANT_SKB) {
1596 struct page *p = rxb_steal_page(rxb);
1598 meta->source->resp_pkt = pkt;
1599 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1600 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1603 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1605 if (!(meta->flags & CMD_ASYNC)) {
1606 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1608 "HCMD_ACTIVE already clear for command %s\n",
1609 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1611 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1612 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1613 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1614 wake_up(&trans_pcie->wait_command_queue);
1619 spin_unlock_bh(&txq->lock);
1622 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1624 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1625 struct iwl_host_cmd *cmd)
1627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1630 /* An asynchronous command can not expect an SKB to be set. */
1631 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1634 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1637 "Error sending %s: enqueue_hcmd failed: %d\n",
1638 get_cmd_string(trans_pcie, cmd->id), ret);
1644 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1645 struct iwl_host_cmd *cmd)
1647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1651 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1652 get_cmd_string(trans_pcie, cmd->id));
1654 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1656 "Command %s: a command is already active!\n",
1657 get_cmd_string(trans_pcie, cmd->id)))
1660 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1661 get_cmd_string(trans_pcie, cmd->id));
1663 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1666 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1668 "Error sending %s: enqueue_hcmd failed: %d\n",
1669 get_cmd_string(trans_pcie, cmd->id), ret);
1673 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1674 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1676 HOST_COMPLETE_TIMEOUT);
1678 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1679 struct iwl_queue *q = &txq->q;
1681 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1682 get_cmd_string(trans_pcie, cmd->id),
1683 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1685 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1686 q->read_ptr, q->write_ptr);
1688 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1689 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1690 get_cmd_string(trans_pcie, cmd->id));
1693 iwl_force_nmi(trans);
1694 iwl_trans_fw_error(trans);
1699 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1700 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1701 get_cmd_string(trans_pcie, cmd->id));
1707 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1708 test_bit(STATUS_RFKILL, &trans->status)) {
1709 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1714 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1715 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1716 get_cmd_string(trans_pcie, cmd->id));
1724 if (cmd->flags & CMD_WANT_SKB) {
1726 * Cancel the CMD_WANT_SKB flag for the cmd in the
1727 * TX cmd queue. Otherwise in case the cmd comes
1728 * in later, it will possibly set an invalid
1729 * address (cmd->meta.source).
1731 trans_pcie->txq[trans_pcie->cmd_queue].
1732 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1735 if (cmd->resp_pkt) {
1737 cmd->resp_pkt = NULL;
1743 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1745 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1746 test_bit(STATUS_RFKILL, &trans->status)) {
1747 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1752 if (cmd->flags & CMD_ASYNC)
1753 return iwl_pcie_send_hcmd_async(trans, cmd);
1755 /* We still can fail on RFKILL that can be asserted while we wait */
1756 return iwl_pcie_send_hcmd_sync(trans, cmd);
1759 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1760 struct iwl_device_cmd *dev_cmd, int txq_id)
1762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1763 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1764 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1765 struct iwl_cmd_meta *out_meta;
1766 struct iwl_txq *txq;
1767 struct iwl_queue *q;
1768 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1770 u16 len, tb1_len, tb2_len;
1771 bool wait_write_ptr;
1772 __le16 fc = hdr->frame_control;
1773 u8 hdr_len = ieee80211_hdrlen(fc);
1776 txq = &trans_pcie->txq[txq_id];
1779 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1780 "TX on unused queue %d\n", txq_id))
1783 spin_lock(&txq->lock);
1785 /* In AGG mode, the index in the ring must correspond to the WiFi
1786 * sequence number. This is a HW requirements to help the SCD to parse
1788 * Check here that the packets are in the right place on the ring.
1790 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1791 WARN_ONCE(txq->ampdu &&
1792 (wifi_seq & 0xff) != q->write_ptr,
1793 "Q: %d WiFi Seq %d tfdNum %d",
1794 txq_id, wifi_seq, q->write_ptr);
1796 /* Set up driver data for this TFD */
1797 txq->entries[q->write_ptr].skb = skb;
1798 txq->entries[q->write_ptr].cmd = dev_cmd;
1800 dev_cmd->hdr.sequence =
1801 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1802 INDEX_TO_SEQ(q->write_ptr)));
1804 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1805 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1806 offsetof(struct iwl_tx_cmd, scratch);
1808 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1809 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1811 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1812 out_meta = &txq->entries[q->write_ptr].meta;
1815 * The second TB (tb1) points to the remainder of the TX command
1816 * and the 802.11 header - dword aligned size
1817 * (This calculation modifies the TX command, so do it before the
1818 * setup of the first TB)
1820 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1821 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1822 tb1_len = ALIGN(len, 4);
1824 /* Tell NIC about any 2-byte padding after MAC header */
1826 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1828 /* The first TB points to the scratchbuf data - min_copy bytes */
1829 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1830 IWL_HCMD_SCRATCHBUF_SIZE);
1831 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1832 IWL_HCMD_SCRATCHBUF_SIZE, true);
1834 /* there must be data left over for TB1 or this code must be changed */
1835 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1837 /* map the data for TB1 */
1838 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1839 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1840 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1842 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1845 * Set up TFD's third entry to point directly to remainder
1846 * of skb, if any (802.11 null frames have no payload).
1848 tb2_len = skb->len - hdr_len;
1850 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1851 skb->data + hdr_len,
1852 tb2_len, DMA_TO_DEVICE);
1853 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1854 iwl_pcie_tfd_unmap(trans, out_meta,
1855 &txq->tfds[q->write_ptr]);
1858 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1861 /* Set up entry for this TFD in Tx byte-count array */
1862 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1864 trace_iwlwifi_dev_tx(trans->dev, skb,
1865 &txq->tfds[txq->q.write_ptr],
1866 sizeof(struct iwl_tfd),
1867 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1868 skb->data + hdr_len, tb2_len);
1869 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1870 skb->data + hdr_len, tb2_len);
1872 wait_write_ptr = ieee80211_has_morefrags(fc);
1874 /* start timer if queue currently empty */
1875 if (q->read_ptr == q->write_ptr) {
1876 if (txq->wd_timeout)
1877 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1878 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1879 iwl_trans_pcie_ref(trans);
1882 /* Tell device the write index *just past* this latest filled TFD */
1883 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1884 if (!wait_write_ptr)
1885 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1888 * At this point the frame is "transmitted" successfully
1889 * and we will get a TX status notification eventually.
1891 if (iwl_queue_space(q) < q->high_mark) {
1893 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1895 iwl_stop_queue(trans, txq);
1897 spin_unlock(&txq->lock);
1900 spin_unlock(&txq->lock);