2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Register definitions taken from original Realtek rtl8723au driver
16 #include <asm/byteorder.h>
18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01
19 #define RTL8XXXU_DEBUG_REG_READ 0x02
20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08
22 #define RTL8XXXU_DEBUG_CHANNEL 0x10
23 #define RTL8XXXU_DEBUG_TX 0x20
24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40
25 #define RTL8XXXU_DEBUG_RX 0x80
26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100
27 #define RTL8XXXU_DEBUG_USB 0x200
28 #define RTL8XXXU_DEBUG_KEY 0x400
29 #define RTL8XXXU_DEBUG_H2C 0x800
30 #define RTL8XXXU_DEBUG_ACTION 0x1000
31 #define RTL8XXXU_DEBUG_EFUSE 0x2000
33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500
34 #define RTL8XXXU_MAX_REG_POLL 500
35 #define USB_INTR_CONTENT_LENGTH 56
37 #define RTL8XXXU_OUT_ENDPOINTS 3
39 #define REALTEK_USB_READ 0xc0
40 #define REALTEK_USB_WRITE 0x40
41 #define REALTEK_USB_CMD_REQ 0x05
42 #define REALTEK_USB_CMD_IDX 0x00
44 #define TX_TOTAL_PAGE_NUM 0xf8
45 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
46 #define TX_PAGE_NUM_PUBQ 0xe7
47 #define TX_PAGE_NUM_HI_PQ 0x0c
48 #define TX_PAGE_NUM_LO_PQ 0x02
49 #define TX_PAGE_NUM_NORM_PQ 0x02
51 #define RTL_FW_PAGE_SIZE 4096
52 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000
54 #define RTL8723A_CHANNEL_GROUPS 3
55 #define RTL8723A_MAX_RF_PATHS 2
56 #define RF6052_MAX_TX_PWR 0x3f
58 #define EFUSE_MAP_LEN_8723A 256
59 #define EFUSE_MAX_SECTION_8723A 32
60 #define EFUSE_REAL_CONTENT_LEN_8723A 512
61 #define EFUSE_BT_MAP_LEN_8723A 1024
62 #define EFUSE_MAX_WORD_UNIT 4
64 struct rtl8xxxu_rx_desc {
65 #ifdef __LITTLE_ENDIAN
200 struct rtl8xxxu_tx_desc {
214 /* CCK Rates, TxHT = 0 */
215 #define DESC_RATE_1M 0x00
216 #define DESC_RATE_2M 0x01
217 #define DESC_RATE_5_5M 0x02
218 #define DESC_RATE_11M 0x03
220 /* OFDM Rates, TxHT = 0 */
221 #define DESC_RATE_6M 0x04
222 #define DESC_RATE_9M 0x05
223 #define DESC_RATE_12M 0x06
224 #define DESC_RATE_18M 0x07
225 #define DESC_RATE_24M 0x08
226 #define DESC_RATE_36M 0x09
227 #define DESC_RATE_48M 0x0a
228 #define DESC_RATE_54M 0x0b
230 /* MCS Rates, TxHT = 1 */
231 #define DESC_RATE_MCS0 0x0c
232 #define DESC_RATE_MCS1 0x0d
233 #define DESC_RATE_MCS2 0x0e
234 #define DESC_RATE_MCS3 0x0f
235 #define DESC_RATE_MCS4 0x10
236 #define DESC_RATE_MCS5 0x11
237 #define DESC_RATE_MCS6 0x12
238 #define DESC_RATE_MCS7 0x13
239 #define DESC_RATE_MCS8 0x14
240 #define DESC_RATE_MCS9 0x15
241 #define DESC_RATE_MCS10 0x16
242 #define DESC_RATE_MCS11 0x17
243 #define DESC_RATE_MCS12 0x18
244 #define DESC_RATE_MCS13 0x19
245 #define DESC_RATE_MCS14 0x1a
246 #define DESC_RATE_MCS15 0x1b
247 #define DESC_RATE_MCS15_SG 0x1c
248 #define DESC_RATE_MCS32 0x20
250 #define TXDESC_OFFSET_SZ 0
251 #define TXDESC_OFFSET_SHT 16
253 #define TXDESC_BMC BIT(24)
254 #define TXDESC_LSG BIT(26)
255 #define TXDESC_FSG BIT(27)
256 #define TXDESC_OWN BIT(31)
258 #define TXDESC_BROADMULTICAST BIT(0)
259 #define TXDESC_LAST_SEGMENT BIT(2)
260 #define TXDESC_FIRST_SEGMENT BIT(3)
261 #define TXDESC_OWN BIT(7)
265 #define TXDESC_PKT_OFFSET_SZ 0
266 #define TXDESC_AGG_ENABLE BIT(5)
267 #define TXDESC_BK BIT(6)
268 #define TXDESC_QUEUE_SHIFT 8
269 #define TXDESC_QUEUE_MASK 0x1f00
270 #define TXDESC_QUEUE_BK 0x2
271 #define TXDESC_QUEUE_BE 0x0
272 #define TXDESC_QUEUE_VI 0x5
273 #define TXDESC_QUEUE_VO 0x7
274 #define TXDESC_QUEUE_BEACON 0x10
275 #define TXDESC_QUEUE_HIGH 0x11
276 #define TXDESC_QUEUE_MGNT 0x12
277 #define TXDESC_QUEUE_CMD 0x13
278 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
280 #define DESC_RATE_ID_SHIFT 16
281 #define DESC_RATE_ID_MASK 0xf
282 #define TXDESC_NAVUSEHDR BIT(20)
283 #define TXDESC_SEC_RC4 0x00400000
284 #define TXDESC_SEC_AES 0x00c00000
285 #define TXDESC_PKT_OFFSET_SHIFT 26
286 #define TXDESC_AGG_EN BIT(29)
287 #define TXDESC_HWPC BIT(31)
290 #define TXDESC_ACK_REPORT BIT(19)
291 #define TXDESC_AMPDU_DENSITY_SHIFT 20
294 #define TXDESC_SEQ_SHIFT 16
295 #define TXDESC_SEQ_MASK 0x0fff0000
298 #define TXDESC_QOS BIT(6)
299 #define TXDESC_HW_SEQ_ENABLE BIT(7)
300 #define TXDESC_USE_DRIVER_RATE BIT(8)
301 #define TXDESC_DISABLE_DATA_FB BIT(10)
302 #define TXDESC_CTS_SELF_ENABLE BIT(11)
303 #define TXDESC_RTS_CTS_ENABLE BIT(12)
304 #define TXDESC_HW_RTS_ENABLE BIT(13)
305 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
306 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
307 #define TXDESC_SHORT_PREAMBLE BIT(24)
308 #define TXDESC_DATA_BW BIT(25)
309 #define TXDESC_RTS_DATA_BW BIT(27)
310 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
311 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
314 #define TXDESC_RTS_RATE_SHIFT 0
315 #define TXDESC_RTS_RATE_MASK 0x3f
316 #define TXDESC_SHORT_GI BIT(6)
317 #define TXDESC_CCX_TAG BIT(7)
318 #define TXDESC_RETRY_LIMIT_ENABLE BIT(17)
319 #define TXDESC_RETRY_LIMIT_SHIFT 18
320 #define TXDESC_RETRY_LIMIT_MASK 0x00fc0000
323 #define TXDESC_MAX_AGG_SHIFT 11
325 struct phy_rx_agc_info {
326 #ifdef __LITTLE_ENDIAN
333 struct rtl8723au_phy_stats {
334 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
335 u8 ch_corr[RTL8723A_MAX_RF_PATHS];
336 u8 cck_sig_qual_ofdm_pwdb_all;
337 u8 cck_agc_rpt_ofdm_cfosho_a;
338 u8 cck_rpt_b_ofdm_cfosho_b;
340 u8 noise_power_db_msb;
341 u8 path_cfotail[RTL8723A_MAX_RF_PATHS];
342 u8 pcts_mask[RTL8723A_MAX_RF_PATHS];
343 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS];
344 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS];
345 u8 noise_power_db_lsb;
347 u8 stream_csi[RTL8723A_MAX_RF_PATHS];
348 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS];
352 #ifdef __LITTLE_ENDIAN
353 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
358 u8 antenna_select_b:1;
360 #else /* _BIG_ENDIAN_ */
362 u8 antenna_select_b:1;
367 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
374 #define RTL8XXXU_ADDA_REGS 16
375 #define RTL8XXXU_MAC_REGS 4
376 #define RTL8XXXU_BB_REGS 9
378 struct rtl8xxxu_firmware_header {
379 __le16 signature; /* 92C0: test chip; 92C,
383 u8 category; /* AP/NIC and USB/PCI */
386 __le16 major_version; /* FW Version */
387 u8 minor_version; /* FW Subversion, default 0x00 */
390 u8 month; /* Release time Month field */
391 u8 date; /* Release time Date field */
392 u8 hour; /* Release time Hour field */
393 u8 minute; /* Release time Minute field */
395 __le16 ramcodesize; /* Size of RAM code */
398 __le32 svn_idx; /* SVN entry index */
408 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
410 struct rtl8723au_idx {
411 #ifdef __LITTLE_ENDIAN
418 } __attribute__((packed));
420 struct rtl8723au_efuse {
423 u8 cck_tx_power_index_A[3]; /* 0x10 */
424 u8 cck_tx_power_index_B[3];
425 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
426 u8 ht40_1s_tx_power_index_B[3];
428 * The following entries are half-bytes split as:
429 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
431 struct rtl8723au_idx ht20_tx_power_index_diff[3];
432 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
433 struct rtl8723au_idx ht40_max_power_offset[3];
434 struct rtl8723au_idx ht20_max_power_offset[3];
435 u8 channel_plan; /* 0x28 */
443 u8 version /* 0x30 */;
444 u8 customer_id_major;
445 u8 customer_id_minor;
447 u8 chipset; /* 0x34 */
453 u8 mac_addr[ETH_ALEN]; /* 0xc6 */
457 u8 device_name[0x29]; /* 0xd7 */
460 struct rtl8192cu_efuse {
469 __le16 smid; /* 0x10 */
471 u8 mac_addr[ETH_ALEN]; /* 0x16 */
475 u8 device_name[0x14]; /* 0x28 */
476 u8 res4[0x1e]; /* 0x3c */
477 u8 cck_tx_power_index_A[3]; /* 0x5a */
478 u8 cck_tx_power_index_B[3];
479 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */
480 u8 ht40_1s_tx_power_index_B[3];
482 * The following entries are half-bytes split as:
483 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
485 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
486 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */
487 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
488 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */
489 struct rtl8723au_idx ht20_max_power_offset[3];
490 u8 channel_plan; /* 0x75 */
493 u8 thermal_meter; /* xtal_k */ /* 0x78 */
498 u8 res5[1]; /* 0x7d */
503 struct rtl8xxxu_reg8val {
508 struct rtl8xxxu_reg32val {
513 struct rtl8xxxu_rfregval {
518 enum rtl8xxxu_rfpath {
523 struct rtl8xxxu_rfregs {
532 #define H2C_MAX_MBOX 4
533 #define H2C_EXT BIT(7)
534 #define H2C_SET_POWER_MODE 1
535 #define H2C_JOIN_BSS_REPORT 2
536 #define H2C_JOIN_BSS_DISCONNECT 0
537 #define H2C_JOIN_BSS_CONNECT 1
538 #define H2C_SET_RSSI 5
539 #define H2C_SET_RATE_MASK (6 | H2C_EXT)
565 struct rtl8xxxu_fileops;
567 struct rtl8xxxu_priv {
568 struct ieee80211_hw *hw;
569 struct usb_device *udev;
570 struct rtl8xxxu_fileops *fops;
572 spinlock_t tx_urb_lock;
573 struct list_head tx_urb_free_list;
574 int tx_urb_free_count;
577 spinlock_t rx_urb_lock;
578 struct list_head rx_urb_pending_list;
579 int rx_urb_pending_count;
581 struct work_struct rx_urb_wq;
583 u8 mac_addr[ETH_ALEN];
585 u8 cck_tx_power_index_A[3]; /* 0x10 */
586 u8 cck_tx_power_index_B[3];
587 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
588 u8 ht40_1s_tx_power_index_B[3];
590 * The following entries are half-bytes split as:
591 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
593 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
594 struct rtl8723au_idx ht20_tx_power_index_diff[3];
595 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
596 struct rtl8723au_idx ht40_max_power_offset[3];
597 struct rtl8723au_idx ht20_max_power_offset[3];
602 u32 enable_bluetooth:1;
606 u32 has_polarity_ctrl:1;
609 u32 ep_tx_high_queue:1;
610 u32 ep_tx_normal_queue:1;
611 u32 ep_tx_low_queue:1;
612 u32 path_a_hi_power:1;
613 u32 path_a_rf_paths:4;
614 unsigned int pipe_interrupt;
615 unsigned int pipe_in;
616 unsigned int pipe_out[TXDESC_QUEUE_MAX];
617 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
631 struct mutex h2c_mutex;
633 struct usb_anchor rx_anchor;
634 struct usb_anchor tx_anchor;
635 struct usb_anchor int_anchor;
636 struct rtl8xxxu_firmware_header *fw_data;
638 struct mutex usb_buf_mutex;
645 u8 raw[EFUSE_MAP_LEN_8723A];
646 struct rtl8723au_efuse efuse8723;
647 struct rtl8192cu_efuse efuse8192;
649 u32 adda_backup[RTL8XXXU_ADDA_REGS];
650 u32 mac_backup[RTL8XXXU_MAC_REGS];
651 u32 bb_backup[RTL8XXXU_BB_REGS];
652 u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
655 u8 iqk_initialized:1;
656 u8 int_buf[USB_INTR_CONTENT_LENGTH];
659 struct rtl8xxxu_rx_urb {
661 struct ieee80211_hw *hw;
662 struct list_head list;
665 struct rtl8xxxu_tx_urb {
667 struct ieee80211_hw *hw;
668 struct list_head list;
671 struct rtl8xxxu_fileops {
672 int (*parse_efuse) (struct rtl8xxxu_priv *priv);
673 int (*load_firmware) (struct rtl8xxxu_priv *priv);
674 int (*power_on) (struct rtl8xxxu_priv *priv);
675 int writeN_block_size;