1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
29 #ifndef __REALTEK_FIRMWARE92S_H__
30 #define __REALTEK_FIRMWARE92S_H__
32 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
33 #define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE 90000
34 #define RTL8190_CPU_START_OFFSET 0x80
35 /* Firmware Local buffer size. 64k */
36 #define MAX_FIRMWARE_CODE_SIZE 0xFF00
38 #define RT_8192S_FIRMWARE_HDR_SIZE 80
39 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
41 /* support till 64 bit bus width OS */
42 #define MAX_DEV_ADDR_SIZE 8
43 #define MAX_FIRMWARE_INFORMATION_SIZE 32
44 #define MAX_802_11_HEADER_LENGTH (40 + \
45 MAX_FIRMWARE_INFORMATION_SIZE)
46 #define ENCRYPTION_MAX_OVERHEAD 128
47 #define MAX_FRAGMENT_COUNT 8
48 #define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
49 (MAX_802_11_HEADER_LENGTH + \
50 ENCRYPTION_MAX_OVERHEAD) *\
53 #define H2C_TX_CMD_HDR_LEN 8
55 /* The following DM control code are for Reg0x364, */
56 #define FW_DIG_ENABLE_CTL BIT(0)
57 #define FW_HIGH_PWR_ENABLE_CTL BIT(1)
58 #define FW_SS_CTL BIT(2)
59 #define FW_RA_INIT_CTL BIT(3)
60 #define FW_RA_BG_CTL BIT(4)
61 #define FW_RA_N_CTL BIT(5)
62 #define FW_PWR_TRK_CTL BIT(6)
63 #define FW_IQK_CTL BIT(7)
64 #define FW_FA_CTL BIT(8)
65 #define FW_DRIVER_CTRL_DM_CTL BIT(9)
66 #define FW_PAPE_CTL_BY_SW_HW BIT(10)
67 #define FW_DISABLE_ALL_DM 0
68 #define FW_PWR_TRK_PARAM_CLR 0x0000ffff
69 #define FW_RA_PARAM_CLR 0xffff0000
71 enum desc_packet_type {
72 DESC_PACKET_TYPE_INIT = 0,
73 DESC_PACKET_TYPE_NORMAL = 1,
76 /* 8-bytes alignment required */
78 /* --- long word 0 ---- */
79 /* 0x12: CE product, 0x92: IT product */
81 /* 0x87: CE product, 0x81: IT product */
83 /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
84 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
86 /* the same value as reigster value */
88 /* customer ID low byte */
90 /* customer ID high byte */
92 /* 0x11: 1T1R, 0x12: 1T2R,
93 * 0x92: 1T2R turbo, 0x22: 2T2R */
95 /* 4: 4EP, 6: 6EP, 11: 11EP */
98 /* --- long word 1 ---- */
99 /* regulatory class bit map 0 */
100 u8 regulatory_class_0;
101 /* regulatory class bit map 1 */
102 u8 regulatory_class_1;
103 /* regulatory class bit map 2 */
104 u8 regulatory_class_2;
105 /* regulatory class bit map 3 */
106 u8 regulatory_class_3;
107 /* 0:SWSI, 1:HWSI, 2:HWPI */
113 /* --- long word 2 ---- */
114 /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
116 /* 1: for MP use, 0: for normal
117 * driver (to be discussed) */
126 /* --- long word 3 ---- */
129 /* 40MHz BW enable */
130 /* 4181 convert AMSDU to AMPDU, 0: disable */
133 /* 11n AMPDU enable */
135 /* FW offloads, 0: driver handles */
136 u8 rate_control_offload;
137 /* FW offloads, 0: driver handles */
138 u8 aggregation_offload;
142 /* --- long word 4 ---- */
143 /* 1. FW offloads, 0: driver handles */
145 /* 2. FW offloads, 0: driver handles */
147 /* 3. FW offloads, 0: driver handles */
149 /* 4. FW offloads, 0: driver handles */
150 u8 tcp_checksum_offload;
151 /* 5. FW offloads, 0: driver handles */
153 /* 6. FW offloads, 0: driver handles */
154 u8 ps_control_offload;
155 /* 7. FW offloads, 0: driver handles */
159 /* --- long word 5 ---- */
160 /* tcp tx packet length low byte */
161 u8 tcp_tx_frame_len_L;
162 /* tcp tx packet length high byte */
163 u8 tcp_tx_frame_len_H;
164 /* tcp rx packet length low byte */
165 u8 tcp_rx_frame_len_L;
166 /* tcp rx packet length high byte */
167 u8 tcp_rx_frame_len_H;
174 /* 8-byte alinment required */
177 /* --- LONG WORD 0 ---- */
179 /* 0x8000 ~ 0x8FFF for FPGA version,
180 * 0x0000 ~ 0x7FFF for ASIC version, */
182 /* define the size of boot loader */
186 /* --- LONG WORD 1 ---- */
187 /* define the size of FW in IMEM */
189 /* define the size of FW in SRAM */
192 /* --- LONG WORD 2 ---- */
193 /* define the size of DMEM variable */
197 /* --- LONG WORD 3 ---- */
201 struct fw_priv fwpriv;
207 FW_STATUS_LOAD_IMEM = 1,
208 FW_STATUS_LOAD_EMEM = 2,
209 FW_STATUS_LOAD_DMEM = 3,
214 struct fw_hdr *pfwheader;
215 enum fw_status fwstatus;
217 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
218 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
221 u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE];
222 u32 sz_fw_tmpbufferlen;
223 u16 cmdpacket_fragthresold;
226 struct h2c_set_pwrmode_parm {
228 u8 flag_low_traffic_en;
230 u8 flag_rf_low_snr_en;
235 /* beacon TO (ms). ¡§=0¡¨ no limit. */
238 /* only for VOIP mode. */
246 struct h2c_joinbss_rpt_parm {
255 /* EAPOL-Key Key Confirmation Key (KCK) */
257 /* EAPOL-Key Key Encryption Key (KEK) */
259 /* Temporal Key 1 (TK1) */
262 /* Temporal Key 2 (TK2) */
271 struct h2c_wpa_two_way_parm {
272 /* algorithm TKIP or AES */
275 struct h2c_wpa_ptk wpa_ptk_value;
279 FW_H2C_SETPWRMODE = 0,
280 FW_H2C_JOINBSSRPT = 1,
281 FW_H2C_WOWLAN_UPDATE_GTK = 2,
282 FW_H2C_WOWLAN_UPDATE_IV = 3,
283 FW_H2C_WOWLAN_OFFLOAD = 4,
287 H2C_READ_MACREG_CMD, /*0*/
288 H2C_WRITE_MACREG_CMD,
292 H2C_WRITERF_CMD, /*5*/
294 H2C_WRITE_EEPROM_CMD,
297 H2C_READ_CAM_CMD, /*10*/
302 H2C_DISCONNECT_CMD, /*15*/
307 H2C_SETKEY_CMD, /*20*/
311 H2C_SETSTAPWRSTATE_CMD,
312 H2C_SETBASICRATE_CMD, /*25*/
313 H2C_GETBASICRATE_CMD,
317 H2C_GETPHYINFO_CMD, /*30*/
322 H2C_SETATIM_CMD, /*35*/
327 H2C_GETCCXREPORT_CMD, /*40*/
328 H2C_GETDTMREPORT_CMD,
329 H2C_GETTXRATESTATICS_CMD,
330 H2C_SETUSBSUSPEND_CMD,
333 H2C_WOWLAN_UPDATE_GTK_CMD,
334 H2C_WOWLAN_FW_OFFLOAD,
337 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
341 /* The following macros are used for FW
342 * CMD map and parameter updated. */
343 #define FW_CMD_IO_CLR(rtlpriv, _Bit) \
346 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
349 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \
350 rtlpriv->rtlhal.fwcmd_iomap = _val;
352 #define FW_CMD_IO_SET(rtlpriv, _val) \
354 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
355 FW_CMD_IO_UPDATE(rtlpriv, _val); \
358 #define FW_CMD_PARA_SET(rtlpriv, _val) \
360 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
361 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
364 #define FW_CMD_IO_QUERY(rtlpriv) \
365 (u16)(rtlpriv->rtlhal.fwcmd_iomap)
366 #define FW_CMD_IO_PARA_QUERY(rtlpriv) \
367 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
369 int rtl92s_download_fw(struct ieee80211_hw *hw);
370 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
371 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
372 u8 mstatus, u8 ps_qosinfo);