2 * Linux DHD Bus Module for PCIE
4 * $Copyright Open Broadcom Corporation$
6 * $Id: dhd_pcie.h 506084 2014-10-02 15:34:59Z $
15 #ifdef SUPPORT_LINKDOWN_RECOVERY
16 #ifdef CONFIG_ARCH_MSM
17 #ifdef CONFIG_ARCH_MSM8994
18 #include <linux/msm_pcie.h>
20 #include <mach/msm_pcie.h>
22 #endif /* CONFIG_ARCH_MSM */
23 #endif /* SUPPORT_LINKDOWN_RECOVERY */
27 #define PCMSGBUF_HDRLEN 0
28 #define DONGLE_REG_MAP_SIZE (32 * 1024)
29 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
30 #define DONGLE_MIN_MEMSIZE (128 *1024)
32 #define DHD_PCIE_SUCCESS 0
33 #define DHD_PCIE_FAILURE 1
34 #endif /* DHD_DEBUG */
35 #define REMAP_ENAB(bus) ((bus)->remap)
36 #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
38 #define MAX_DHD_TX_FLOWS 256
40 /* user defined data structures */
42 /* Device console log buffer state */
43 #define CONSOLE_LINE_MAX 192
44 #define CONSOLE_BUFFER_MAX 2024
47 typedef struct dhd_console {
48 uint count; /* Poll interval msec counter */
49 uint log_addr; /* Log struct address (fixed) */
50 hnd_log_t log; /* Log struct (host copy) */
51 uint bufsize; /* Size of log buffer */
52 uint8 *buf; /* Log buffer (host copy) */
53 uint last; /* Last buffer read index */
55 #endif /* DHD_DEBUG */
56 typedef struct ring_sh_info {
62 typedef struct dhd_bus {
64 struct pci_dev *dev; /* pci device handle */
65 dll_t const_flowring; /* constructed list of tx flowring queues */
67 si_t *sih; /* Handle for SI calls */
68 char *vars; /* Variables (from CIS and/or other) */
69 uint varsz; /* Size of variables buffer */
70 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
71 sbpcieregs_t *reg; /* Registers for PCIE core */
73 uint armrev; /* CPU core revision */
74 uint ramrev; /* SOCRAM core revision */
75 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
76 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
77 uint32 srmemsize; /* Size of SRMEM */
79 uint32 bus; /* gSPI or SDIO bus */
80 uint32 intstatus; /* Intstatus bits (events) pending */
81 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
82 bool fcstate; /* State of dongle flow-control */
84 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
85 char *fw_path; /* module_param: path to firmware image */
86 char *nv_path; /* module_param: path to nvram vars file */
87 char *nvram_params; /* user specified nvram params. */
90 struct pktq txq; /* Queue length used for flow-control */
92 uint rxlen; /* Length of valid data in buffer */
95 bool intr; /* Use interrupts */
96 bool ipend; /* Device interrupt is pending */
97 bool intdis; /* Interrupts disabled by isr */
98 uint intrcount; /* Count of device interrupt callbacks */
99 uint lastintrs; /* Count as of last watchdog timer */
102 dhd_console_t console; /* Console output polling support */
103 uint console_addr; /* Console address from shared struct */
104 #endif /* DHD_DEBUG */
106 bool alp_only; /* Don't use HT clock (ALP only) */
108 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
109 * Available with socram rev 16
110 * Remap region not DMA-able
113 uint32 dongle_ram_base;
116 pciedev_shared_t *pcie_sh;
118 ioctl_comp_resp_msg_t ioct_resp;
120 volatile char *regs; /* pci device memory va */
121 volatile char *tcm; /* pci device memory va */
123 #ifdef CONFIG_ARCH_MSM8994
124 uint32 bar1_win_base;
125 uint32 bar1_win_mask;
128 uint32 nvram_csm; /* Nvram checksum */
132 uint32 *pcie_mb_intr_addr;
133 void *pcie_mb_intr_osh;
136 /* version 3 shared struct related info start */
137 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
138 uint8 h2d_ring_count;
139 uint8 d2h_ring_count;
141 uint32 ring_state_ptr;
143 uint32 d2h_dma_scratch_buffer_mem_addr;
145 uint32 h2d_mb_data_ptr_addr;
146 uint32 d2h_mb_data_ptr_addr;
147 /* version 3 shared struct related info end */
150 bool ltrsleep_on_unload;
151 uint wait_for_d3_ack;
153 uint32 max_sub_queues;
156 #ifdef SUPPORT_LINKDOWN_RECOVERY
157 #ifdef CONFIG_ARCH_MSM
158 struct msm_pcie_register_event pcie_event;
160 #endif /* CONFIG_ARCH_MSM */
161 #endif /* SUPPORT_LINKDOWN_RECOVERY */
162 #ifdef PCIE_TX_DEFERRAL
163 struct workqueue_struct *tx_wq;
164 struct work_struct create_flow_work;
165 struct work_struct delete_flow_work;
166 unsigned long *delete_flow_map;
167 struct sk_buff_head orphan_list;
168 #endif /* PCIE_TX_DEFERRAL */
172 /* function declarations */
174 extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
175 extern int dhdpcie_bus_register(void);
176 extern void dhdpcie_bus_unregister(void);
177 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
179 extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh, volatile char* regs,
180 volatile char* tcm, uint32 tcm_size);
181 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
182 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
183 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
184 extern void dhdpcie_bus_remove_prep(struct dhd_bus *bus);
185 extern void dhdpcie_bus_release(struct dhd_bus *bus);
186 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
187 extern void dhdpcie_free_irq(dhd_bus_t *bus);
188 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
189 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
190 #ifndef BCMPCIE_OOB_HOST_WAKE
191 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
192 #endif /* !BCMPCIE_OOB_HOST_WAKE */
193 extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
194 extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
195 extern int dhdpcie_disable_device(dhd_bus_t *bus);
196 extern int dhdpcie_enable_device(dhd_bus_t *bus);
197 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
198 extern void dhdpcie_free_resource(dhd_bus_t *bus);
199 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
200 #ifdef BCMPCIE_OOB_HOST_WAKE
201 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
202 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
203 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
204 #endif /* BCMPCIE_OOB_HOST_WAKE */
206 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
207 #endif /* dhd_pcie_h */