drivers/net/wireless/rockchip_wlan/rtl8723au/hal/rtl8723a/rtl8723a_mp.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8723A_MP_C_\r
  21 #ifdef CONFIG_MP_INCLUDED\r
  22 \r
  23 #include <drv_types.h>\r
  24 #include <rtw_mp.h>\r
  25 #include <rtl8723a_hal.h>\r
  26 \r
  27 \r
  28 /*-----------------------------------------------------------------------------\r
  29  * Function:    mpt_SwitchRfSetting\r
  30  *\r
  31  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.\r
  32  *\r
  33  * Input:               IN      PADAPTER                                pAdapter\r
  34  *\r
  35  * Output:              NONE\r
  36  *\r
  37  * Return:              NONE\r
  38  *\r
  39  * Revised History:\r
  40  * When                 Who     Remark\r
  41  * 01/08/2009   MHC     Suggestion from SD3 Willis for 92S series.\r
  42  * 01/09/2009   MHC     Add CCK modification for 40MHZ. Suggestion from SD3.\r
  43  *\r
  44  *---------------------------------------------------------------------------*/\r
  45  static void phy_SwitchRfSetting8723A(PADAPTER   pAdapter,u8 channel )\r
  46 {\r
  47 \r
  48         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
  49     u32                                 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;\r
  50     \r
  51                 DBG_8192C("phy_SwitchRfSetting8723A channel=%d\n",channel);\r
  52 \r
  53 \r
  54         if(channel >= 1 && channel <= 9)\r
  55         {\r
  56                                 DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF0FFFF83\n");\r
  57                                 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);\r
  58         }\r
  59         else if (channel >= 10 && channel <= 14)\r
  60         {\r
  61                                 DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF2FFFF83\n");\r
  62                                 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);\r
  63         }       \r
  64                 \r
  65                 \r
  66 #if     DEV_BUS_TYPE==RT_PCI_INTERFACE\r
  67                 u4Byte                          u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;\r
  68                 //default value\r
  69                 {\r
  70                         u4RF_IPA[0] = 0x4F424;                  //CCK\r
  71                         u4RF_IPA[1] = 0xCF424;                  //OFDM\r
  72                         u4RF_IPA[2] = 0x8F424;                  //MCS   \r
  73                         u4RF_TXBIAS = 0xC0356;                                                  \r
  74                         u4RF_SYN_G2 = 0x4F200;                                                                                                                          \r
  75                 }\r
  76         \r
  77                 switch(channel)\r
  78                 {\r
  79                         case 1:\r
  80                                 u4RF_IPA[0] = 0x4F40C;                  \r
  81                                 u4RF_IPA[1] = 0xCF466;  \r
  82                                 u4RF_TXBIAS = 0xC0350;                                          \r
  83                                 u4RF_SYN_G2 = 0x0F400;                                                                                                                                                  \r
  84                                 break;\r
  85         \r
  86                         case 2:\r
  87                                 u4RF_IPA[0] =  0x4F407;                 \r
  88                                 u4RF_TXBIAS =  0xC0350;                                                                 \r
  89                                 u4RF_SYN_G2 = 0x0F400;                                                                                                                                                                          \r
  90                                 break;\r
  91         \r
  92                         case 3:\r
  93                                 u4RF_IPA[0] =  0x4F407;                 \r
  94                                 u4RF_IPA[2] =  0x8F466;                         \r
  95                                 u4RF_TXBIAS =  0xC0350;                                                                 \r
  96                                 u4RF_SYN_G2 = 0x0F400;                                                                                                                                                                          \r
  97                                 break;\r
  98         \r
  99                         case 5:\r
 100                         case 8: \r
 101                                 u4RF_SYN_G2 =  0x0F400;                                                                                         \r
 102                                 break;\r
 103         \r
 104                         case 6:\r
 105                         case 13:        \r
 106                                 u4RF_IPA[0] =  0x4F40C;                 \r
 107                                 break;\r
 108         \r
 109                         case 7: \r
 110                                 u4RF_IPA[0] =  0x4F40C;                 \r
 111                                 u4RF_SYN_G2 =  0x0F400;                                                                                                                 \r
 112                                 break;                  \r
 113         \r
 114                         case 9:\r
 115                                 u4RF_IPA[2] =  0x8F454;                 \r
 116                                 u4RF_SYN_G2 =  0x0F400;                                                                                                                 \r
 117                                 break;\r
 118         \r
 119                         case 11:        \r
 120                                 u4RF_IPA[0] =  0x4F40C;                 \r
 121                                 u4RF_IPA[1] =  0xCF454; \r
 122                                 u4RF_SYN_G2 =  0x0F400;                                                                                                                 \r
 123                                 break;\r
 124         \r
 125                         default:\r
 126                                 u4RF_IPA[0] =  0x4F424;                 \r
 127                                 u4RF_IPA[1] =  0x8F424;                         \r
 128                                 u4RF_IPA[2] =  0xCF424;                                 \r
 129                                 u4RF_TXBIAS =  0xC0356;                                                 \r
 130                                 u4RF_SYN_G2 =  0x4F200;                                                                                                                                 \r
 131                                 break;\r
 132                 }\r
 133         \r
 134                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);\r
 135                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);\r
 136                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);\r
 137                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);        \r
 138                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);\r
 139         \r
 140                 if((channel >= 1 && channel <= 5) || (channel >= 8 && channel <= 9))\r
 141                 {\r
 142                         PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);\r
 143                 }\r
 144                 else \r
 145                 {\r
 146                         PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);\r
 147                 }               \r
 148         \r
 149 #endif\r
 150         \r
 151 \r
 152 }       \r
 153 \r
 154 \r
 155 \r
 156 \r
 157 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)\r
 158 {\r
 159         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);\r
 160         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 161         u8                              ChannelToSw ;\r
 162         \r
 163         pMptCtx->MptChannelToSw=pAdapter->mppriv.channel;\r
 164         ChannelToSw =pMptCtx->MptChannelToSw;\r
 165         \r
 166         phy_SwitchRfSetting8723A(pAdapter, ChannelToSw);\r
 167 }       \r
 168 \r
 169 \r
 170 \r
 171 \r
 172 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)\r
 173 {\r
 174         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 175         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 176 \r
 177 \r
 178         if (!netif_running(padapter->pnetdev)) {\r
 179                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));\r
 180                 return _FAIL;\r
 181         }\r
 182 \r
 183         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 184                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));\r
 185                 return _FAIL;\r
 186         }\r
 187 \r
 188         if (enable)\r
 189                 pdmpriv->TxPowerTrackControl = _TRUE;\r
 190         else\r
 191                 pdmpriv->TxPowerTrackControl = _FALSE;\r
 192 \r
 193         return _SUCCESS;\r
 194 }\r
 195 \r
 196 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)\r
 197 {\r
 198         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 199         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 200 \r
 201 \r
 202         *enable = pdmpriv->TxPowerTrackControl;\r
 203 }\r
 204 \r
 205 static void Hal_disable_dm(PADAPTER padapter)\r
 206 {\r
 207         u8 v8;\r
 208         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 209         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 210 \r
 211 \r
 212         //3 1. disable firmware dynamic mechanism\r
 213         // disable Power Training, Rate Adaptive\r
 214         v8 = rtw_read8(padapter, REG_BCN_CTRL);\r
 215         v8 &= ~EN_BCN_FUNCTION;\r
 216         rtw_write8(padapter, REG_BCN_CTRL, v8);\r
 217 \r
 218         //3 2. disable driver dynamic mechanism\r
 219         // disable Dynamic Initial Gain\r
 220         // disable High Power\r
 221         // disable Power Tracking\r
 222         Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);\r
 223 \r
 224         // enable APK, LCK and IQK but disable power tracking\r
 225         pdmpriv->TxPowerTrackControl = _FALSE;\r
 226         Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE);\r
 227 }\r
 228 \r
 229 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\r
 230 {\r
 231         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;\r
 232         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;\r
 233         u8              i;\r
 234         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 235 \r
 236 \r
 237         // get current cck swing value and check 0xa22 & 0xa23 later to match the table.\r
 238         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\r
 239 \r
 240         if (!bInCH14)\r
 241         {\r
 242                 // Readback the current bb cck swing value and compare with the table to\r
 243                 // get the current swing index\r
 244                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 245                 {\r
 246                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&\r
 247                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))\r
 248                         {\r
 249                                 CCKSwingIndex = i;\r
 250 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 251 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 252                                 break;\r
 253                         }\r
 254                 }\r
 255 \r
 256                 //Write 0xa22 0xa23\r
 257                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +\r
 258                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;\r
 259 \r
 260 \r
 261                 //Write 0xa24 ~ 0xa27\r
 262                 TempVal2 = 0;\r
 263                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +\r
 264                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +\r
 265                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+\r
 266                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);\r
 267 \r
 268                 //Write 0xa28  0xa29\r
 269                 TempVal3 = 0;\r
 270                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +\r
 271                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;\r
 272         }\r
 273         else\r
 274         {\r
 275                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 276                 {\r
 277                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&\r
 278                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))\r
 279                         {\r
 280                                 CCKSwingIndex = i;\r
 281 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 282 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 283                                 break;\r
 284                         }\r
 285                 }\r
 286 \r
 287                 //Write 0xa22 0xa23\r
 288                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +\r
 289                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;\r
 290 \r
 291                 //Write 0xa24 ~ 0xa27\r
 292                 TempVal2 = 0;\r
 293                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +\r
 294                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +\r
 295                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+\r
 296                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);\r
 297 \r
 298                 //Write 0xa28  0xa29\r
 299                 TempVal3 = 0;\r
 300                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +\r
 301                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;\r
 302         }\r
 303 \r
 304         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\r
 305         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\r
 306         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\r
 307 }\r
 308 \r
 309 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)\r
 310 {\r
 311         s32             TempCCk;\r
 312         u8              CCK_index, CCK_index_old;\r
 313         u8              Action = 0;     //0: no action, 1: even->odd, 2:odd->even\r
 314         u8              TimeOut = 100;\r
 315         s32             i = 0;\r
 316         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 317         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 318 \r
 319 \r
 320         if (!IS_92C_SERIAL(pHalData->VersionID))\r
 321                 return;\r
 322 #if 0\r
 323         while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)\r
 324         {\r
 325                 PlatformSleepUs(100);\r
 326                 TimeOut--;\r
 327                 if(TimeOut <= 0)\r
 328                 {\r
 329                         RTPRINT(FINIT, INIT_TxPower,\r
 330                          ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));\r
 331                         break;\r
 332                 }\r
 333         }\r
 334 #endif\r
 335         if (beven && !pMptCtx->bMptIndexEven)   //odd->even\r
 336         {\r
 337                 Action = 2;\r
 338                 pMptCtx->bMptIndexEven = _TRUE;\r
 339         }\r
 340         else if (!beven && pMptCtx->bMptIndexEven)      //even->odd\r
 341         {\r
 342                 Action = 1;\r
 343                 pMptCtx->bMptIndexEven = _FALSE;\r
 344         }\r
 345 \r
 346         if (Action != 0)\r
 347         {\r
 348                 //Query CCK default setting From 0xa24\r
 349                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;\r
 350                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 351                 {\r
 352                         if (pHalData->dmpriv.bCCKinCH14)\r
 353                         {\r
 354                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)\r
 355                                 {\r
 356                                         CCK_index_old = (u8) i;\r
 357 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",\r
 358 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 359                                         break;\r
 360                                 }\r
 361                         }\r
 362                         else\r
 363                         {\r
 364                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)\r
 365                                 {\r
 366                                         CCK_index_old = (u8) i;\r
 367 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",\r
 368 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 369                                         break;\r
 370                                 }\r
 371                         }\r
 372                 }\r
 373 \r
 374                 if (Action == 1)\r
 375                         CCK_index = CCK_index_old - 1;\r
 376                 else\r
 377                         CCK_index = CCK_index_old + 1;\r
 378 \r
 379 //              RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",\r
 380 //                       CCK_index));\r
 381 \r
 382                 //Adjust CCK according to gain index\r
 383                 if (!pHalData->dmpriv.bCCKinCH14) {\r
 384                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);\r
 385                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);\r
 386                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);\r
 387                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);\r
 388                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);\r
 389                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);\r
 390                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);\r
 391                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);\r
 392                 } else {\r
 393                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);\r
 394                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);\r
 395                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);\r
 396                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);\r
 397                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);\r
 398                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);\r
 399                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);\r
 400                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);\r
 401                 }\r
 402         }\r
 403 #if 0\r
 404         RTPRINT(FINIT, INIT_TxPower,\r
 405         ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));\r
 406 \r
 407         PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);\r
 408 #endif\r
 409 }\r
 410 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/\r
 411 \r
 412 /*\r
 413  * SetChannel\r
 414  * Description\r
 415  *      Use H2C command to change channel,\r
 416  *      not only modify rf register, but also other setting need to be done.\r
 417  */\r
 418 void Hal_SetChannel(PADAPTER pAdapter)\r
 419 {\r
 420 #if 0\r
 421         struct mp_priv *pmp = &pAdapter->mppriv;\r
 422 \r
 423 //      SelectChannel(pAdapter, pmp->channel);\r
 424         set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);\r
 425 #else\r
 426         u8              eRFPath;\r
 427 \r
 428         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 429         struct mp_priv  *pmp = &pAdapter->mppriv;\r
 430         u8              channel = pmp->channel;\r
 431         u8              bandwidth = pmp->bandwidth;\r
 432         u8              rate = pmp->rateidx;\r
 433 \r
 434 \r
 435         // set RF channel register\r
 436         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)\r
 437         {\r
 438       if(IS_HARDWARE_TYPE_8192D(pAdapter))\r
 439                         _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel);\r
 440                 else\r
 441                 _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);\r
 442         }\r
 443         Hal_mpt_SwitchRfSetting(pAdapter);\r
 444 \r
 445         SelectChannel(pAdapter, channel);\r
 446         \r
 447         if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {\r
 448                 pHalData->dmpriv.bCCKinCH14 = _TRUE;\r
 449                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);\r
 450         }\r
 451         else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {\r
 452                 pHalData->dmpriv.bCCKinCH14 = _FALSE;\r
 453                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);\r
 454         }\r
 455 \r
 456 #endif\r
 457 }\r
 458 \r
 459 /*\r
 460  * Notice\r
 461  *      Switch bandwitdth may change center frequency(channel)\r
 462  */\r
 463 void Hal_SetBandwidth(PADAPTER pAdapter)\r
 464 {\r
 465         struct mp_priv *pmp = &pAdapter->mppriv;\r
 466 \r
 467 \r
 468         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);\r
 469         Hal_mpt_SwitchRfSetting(pAdapter);\r
 470 }\r
 471 \r
 472 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 473 {\r
 474         u32 tmpval = 0;\r
 475 \r
 476 \r
 477         // rf-A cck tx power\r
 478         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);\r
 479         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];\r
 480         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);\r
 481 \r
 482         // rf-B cck tx power\r
 483         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);\r
 484         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];\r
 485         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);\r
 486 \r
 487         RT_TRACE(_module_mp_, _drv_notice_,\r
 488                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",\r
 489                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 490 }\r
 491 \r
 492 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 493 {\r
 494         u32 TxAGC = 0;\r
 495         u8 tmpval = 0;\r
 496         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 497         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 498 \r
 499 \r
 500         // HT Tx-rf(A)\r
 501         tmpval = TxPower[RF_PATH_A];\r
 502         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 503 \r
 504         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 505         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 506         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 507         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 508         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 509         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 510 \r
 511         if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))\r
 512         {\r
 513                 if (tmpval > pMptCtx->APK_bound[RF_PATH_A])\r
 514                         write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][0]);\r
 515                 else\r
 516                         write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][1]);\r
 517         }\r
 518 \r
 519         // HT Tx-rf(B)\r
 520         tmpval = TxPower[RF_PATH_B];\r
 521         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 522 \r
 523         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 524         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 525         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 526         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 527         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 528         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 529 \r
 530         if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))\r
 531         {\r
 532                 if (tmpval > pMptCtx->APK_bound[RF_PATH_B])\r
 533                         write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][0]);\r
 534                 else\r
 535                         write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][1]);\r
 536         }\r
 537 \r
 538         RT_TRACE(_module_mp_, _drv_notice_,\r
 539                  ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",\r
 540                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 541 }\r
 542 \r
 543 void Hal_SetAntennaPathPower(PADAPTER pAdapter)\r
 544 {\r
 545         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 546         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 547         u8 rfPath;\r
 548 \r
 549         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;\r
 550         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;\r
 551 \r
 552         switch (pAdapter->mppriv.antenna_tx)\r
 553         {\r
 554                 case ANTENNA_A:\r
 555                 default:\r
 556                         rfPath = RF_PATH_A;\r
 557                         break;\r
 558                 case ANTENNA_B:\r
 559                         rfPath = RF_PATH_B;\r
 560                         break;\r
 561                 case ANTENNA_C:\r
 562                         rfPath = RF_PATH_C;\r
 563                         break;\r
 564         }\r
 565 \r
 566         switch (pHalData->rf_chip)\r
 567         {\r
 568                 case RF_8225:\r
 569                 case RF_8256:\r
 570                 case RF_6052:\r
 571                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 572                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 573                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 574                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 575                         break;\r
 576 \r
 577                 default:\r
 578                         break;\r
 579         }\r
 580 }\r
 581 \r
 582 void Hal_SetTxPower(PADAPTER pAdapter)\r
 583 {\r
 584         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 585         u8 TxPower = pAdapter->mppriv.txpoweridx;\r
 586         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 587         u8 rf, rfPath;\r
 588 \r
 589         for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {\r
 590                 TxPowerLevel[rf] = TxPower;\r
 591         }\r
 592 \r
 593         switch (pAdapter->mppriv.antenna_tx)\r
 594         {\r
 595                 case ANTENNA_A:\r
 596                 default:\r
 597                         rfPath = RF_PATH_A;\r
 598                         break;\r
 599                 case ANTENNA_B:\r
 600                         rfPath = RF_PATH_B;\r
 601                         break;\r
 602                 case ANTENNA_C:\r
 603                         rfPath = RF_PATH_C;\r
 604                         break;\r
 605         }\r
 606 \r
 607         switch (pHalData->rf_chip)\r
 608         {\r
 609                 // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!\r
 610                 // We should call normal driver API later!!\r
 611                 case RF_8225:\r
 612                 case RF_8256:\r
 613                 case RF_6052:\r
 614                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 615                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 616                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 617                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 618                         break;\r
 619 \r
 620                 default:\r
 621                         break;\r
 622         }\r
 623 \r
 624 //      SetCCKTxPower(pAdapter, TxPower);\r
 625 //      SetOFDMTxPower(pAdapter, TxPower);\r
 626 }\r
 627 \r
 628 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)\r
 629 {\r
 630         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;\r
 631         \r
 632         return ;\r
 633 \r
 634         TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);\r
 635         TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);\r
 636         TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);\r
 637 \r
 638         tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);\r
 639         write_bbreg(pAdapter, rFPGA0_TxGainStage,\r
 640                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);\r
 641 }\r
 642 \r
 643 void Hal_SetDataRate(PADAPTER pAdapter)\r
 644 {\r
 645                 if(!IS_HARDWARE_TYPE_8723A(pAdapter))\r
 646                 Hal_mpt_SwitchRfSetting(pAdapter);\r
 647 }\r
 648 \r
 649 \r
 650 void Hal_SetAntenna(PADAPTER pAdapter)\r
 651 {\r
 652         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 653 \r
 654         R_ANTENNA_SELECT_OFDM *p_ofdm_tx;       /* OFDM Tx register */\r
 655         R_ANTENNA_SELECT_CCK *p_cck_txrx;\r
 656 \r
 657         u8      r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;\r
 658         u8      chgTx = 0, chgRx = 0;\r
 659         u32     r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;\r
 660 \r
 661 \r
 662         p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;\r
 663         p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;\r
 664 \r
 665         p_ofdm_tx->r_ant_ht1    = 0x1;\r
 666         p_ofdm_tx->r_ant_ht2    = 0x2;  // Second TX RF path is A\r
 667         p_ofdm_tx->r_ant_non_ht = 0x3;  // 0x1+0x2=0x3\r
 668 \r
 669         switch (pAdapter->mppriv.antenna_tx)\r
 670         {\r
 671                 case ANTENNA_A:\r
 672                         p_ofdm_tx->r_tx_antenna         = 0x1;\r
 673                         r_ofdm_tx_en_val                = 0x1;\r
 674                         p_ofdm_tx->r_ant_l              = 0x1;\r
 675                         p_ofdm_tx->r_ant_ht_s1          = 0x1;\r
 676                         p_ofdm_tx->r_ant_non_ht_s1      = 0x1;\r
 677                         p_cck_txrx->r_ccktx_enable      = 0x8;\r
 678                         chgTx = 1;\r
 679 \r
 680                         // From SD3 Willis suggestion !!! Set RF A=TX and B as standby\r
 681 //                      if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 682                         {\r
 683                         write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
 684                         write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);\r
 685                         r_ofdm_tx_en_val                = 0x3;\r
 686 \r
 687                         // Power save\r
 688                         //cosa r_ant_select_ofdm_val = 0x11111111;\r
 689 \r
 690                         // We need to close RFB by SW control\r
 691                         if (pHalData->rf_type == RF_2T2R)\r
 692                         {\r
 693                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
 694                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);\r
 695                                 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 696                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
 697                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);\r
 698                         }\r
 699                         }\r
 700                         break;\r
 701 \r
 702                 case ANTENNA_B:\r
 703                         p_ofdm_tx->r_tx_antenna         = 0x2;\r
 704                         r_ofdm_tx_en_val                = 0x2;\r
 705                         p_ofdm_tx->r_ant_l              = 0x2;\r
 706                         p_ofdm_tx->r_ant_ht_s1          = 0x2;\r
 707                         p_ofdm_tx->r_ant_non_ht_s1      = 0x2;\r
 708                         p_cck_txrx->r_ccktx_enable      = 0x4;\r
 709                         chgTx = 1;\r
 710 \r
 711                         // From SD3 Willis suggestion !!! Set RF A as standby\r
 712                         //if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 713                         {\r
 714                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);\r
 715                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
 716 //                      r_ofdm_tx_en_val                = 0x3;\r
 717 \r
 718                         // Power save\r
 719                         //cosa r_ant_select_ofdm_val = 0x22222222;\r
 720 \r
 721                         // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.\r
 722                         // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control\r
 723                         if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)\r
 724                         {\r
 725                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);\r
 726                                 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);\r
 727                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
 728 //                              PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 729                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);\r
 730                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
 731                         }\r
 732                         }\r
 733                 break;\r
 734 \r
 735                 case ANTENNA_AB:        // For 8192S\r
 736                         p_ofdm_tx->r_tx_antenna         = 0x3;\r
 737                         r_ofdm_tx_en_val                = 0x3;\r
 738                         p_ofdm_tx->r_ant_l              = 0x3;\r
 739                         p_ofdm_tx->r_ant_ht_s1          = 0x3;\r
 740                         p_ofdm_tx->r_ant_non_ht_s1      = 0x3;\r
 741                         p_cck_txrx->r_ccktx_enable      = 0xC;\r
 742                         chgTx = 1;\r
 743 \r
 744                         // From SD3 Willis suggestion !!! Set RF B as standby\r
 745                         //if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 746                         {\r
 747                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
 748                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
 749 \r
 750                         // Disable Power save\r
 751                         //cosa r_ant_select_ofdm_val = 0x3321333;\r
 752 #if 0\r
 753                         // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.\r
 754                         if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.\r
 755                         {\r
 756                                 mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);\r
 757                         }\r
 758 #endif\r
 759                         // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control\r
 760                         if (pHalData->rf_type == RF_2T2R)\r
 761                         {\r
 762                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
 763                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
 764 //                              PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 765                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
 766                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
 767                         }\r
 768                         }\r
 769                         break;\r
 770 \r
 771                 default:\r
 772                         break;\r
 773         }\r
 774 \r
 775         //\r
 776         // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D\r
 777         // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D\r
 778         // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D\r
 779         //\r
 780         switch (pAdapter->mppriv.antenna_rx)\r
 781         {\r
 782                 case ANTENNA_A:\r
 783                         r_rx_antenna_ofdm               = 0x1;  // A\r
 784                         p_cck_txrx->r_cckrx_enable      = 0x0;  // default: A\r
 785                         p_cck_txrx->r_cckrx_enable_2    = 0x0;  // option: A\r
 786                         chgRx = 1;\r
 787                         break;\r
 788 \r
 789                 case ANTENNA_B:\r
 790                         r_rx_antenna_ofdm               = 0x2;  // B\r
 791                         p_cck_txrx->r_cckrx_enable      = 0x1;  // default: B\r
 792                         p_cck_txrx->r_cckrx_enable_2    = 0x1;  // option: B\r
 793                         chgRx = 1;\r
 794                         break;\r
 795 \r
 796                 case ANTENNA_AB:\r
 797                         r_rx_antenna_ofdm               = 0x3;  // AB\r
 798                         p_cck_txrx->r_cckrx_enable      = 0x0;  // default:A\r
 799                         p_cck_txrx->r_cckrx_enable_2    = 0x1;  // option:B\r
 800                         chgRx = 1;\r
 801                         break;\r
 802 \r
 803                 default:\r
 804                         break;\r
 805         }\r
 806 \r
 807         if (chgTx && chgRx)\r
 808         {\r
 809                 switch(pHalData->rf_chip)\r
 810                 {\r
 811                         case RF_8225:\r
 812                         case RF_8256:\r
 813                         case RF_6052:\r
 814                                 //r_ant_sel_cck_val = r_ant_select_cck_val;\r
 815                                 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);       //OFDM Tx\r
 816                                 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);            //OFDM Tx\r
 817                                 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    //OFDM Rx\r
 818                                 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    //OFDM Rx\r
 819                                 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val);                //CCK TxRx\r
 820 \r
 821                                 break;\r
 822 \r
 823                         default:\r
 824                                 break;\r
 825                 }\r
 826         }\r
 827 \r
 828         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
 829 }\r
 830 \r
 831 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\r
 832 {\r
 833         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 834 \r
 835 \r
 836         if (!netif_running(pAdapter->pnetdev)) {\r
 837                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));\r
 838                 return _FAIL;\r
 839         }\r
 840 \r
 841         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 842                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));\r
 843                 return _FAIL;\r
 844         }\r
 845 \r
 846         target_ther &= 0xff;\r
 847         if (target_ther < 0x07)\r
 848                 target_ther = 0x07;\r
 849         else if (target_ther > 0x1d)\r
 850                 target_ther = 0x1d;\r
 851 \r
 852         pHalData->EEPROMThermalMeter = target_ther;\r
 853 \r
 854         return _SUCCESS;\r
 855 }\r
 856 \r
 857 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)\r
 858 {\r
 859   \r
 860         write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60);     // 0x24: RF Reg[6:5]\r
 861 \r
 862 //      RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));\r
 863 }\r
 864 \r
 865 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)\r
 866 {\r
 867         u32 ThermalValue = 0;\r
 868 \r
 869         ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);      // 0x24: RF Reg[4:0]\r
 870 //      RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));\r
 871         return (u8)ThermalValue;\r
 872 }\r
 873 \r
 874 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)\r
 875 {\r
 876 #if 0\r
 877         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\r
 878         rtw_msleep_os(1000);\r
 879         fw_cmd_data(pAdapter, value, 1);\r
 880         *value &= 0xFF;\r
 881 #else\r
 882 \r
 883         Hal_TriggerRFThermalMeter(pAdapter);\r
 884         rtw_msleep_os(1000);\r
 885         *value = Hal_ReadRFThermalMeter(pAdapter);\r
 886 #endif\r
 887 }\r
 888 \r
 889 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\r
 890 {\r
 891     HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 892         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;\r
 893         if (bStart)// Start Single Carrier.\r
 894         {\r
 895                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));\r
 896                 // 1. if OFDM block on?\r
 897                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
 898                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
 899 \r
 900                 {\r
 901                 // 2. set CCK test mode off, set to CCK normal mode\r
 902                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
 903                 // 3. turn on scramble setting\r
 904                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
 905          }\r
 906                 // 4. Turn On Single Carrier Tx and turn off the other test modes.\r
 907                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
 908                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);\r
 909                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
 910 #ifdef CONFIG_RTL8192C\r
 911                 // 5. Disable TX power saving at STF & LLTF\r
 912                 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);\r
 913 #endif\r
 914         }\r
 915         else// Stop Single Carrier.\r
 916         {\r
 917                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));\r
 918 \r
 919                 // Turn off all test modes.\r
 920                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
 921                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
 922                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
 923 #ifdef CONFIG_RTL8192C\r
 924                 // Cancel disable TX power saving at STF&LLTF\r
 925                 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);\r
 926 #endif\r
 927                 //Delay 10 ms //delay_ms(10);\r
 928                 rtw_msleep_os(10);\r
 929 \r
 930                 //BB Reset\r
 931                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
 932                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
 933         }\r
 934 }\r
 935 \r
 936 \r
 937 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\r
 938 {\r
 939         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 940         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);\r
 941 \r
 942         u8 rfPath;\r
 943 \r
 944         switch (pAdapter->mppriv.antenna_tx)\r
 945         {\r
 946                 case ANTENNA_A:\r
 947                 default:\r
 948                         rfPath = RF_PATH_A;\r
 949                         break;\r
 950                 case ANTENNA_B:\r
 951                         rfPath = RF_PATH_B;\r
 952                         break;\r
 953                 case ANTENNA_C:\r
 954                         rfPath = RF_PATH_C;\r
 955                         break;\r
 956         }\r
 957 \r
 958         pAdapter->mppriv.MptCtx.bSingleTone = bStart;\r
 959         if (bStart)// Start Single Tone.\r
 960         {\r
 961                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));\r
 962                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\r
 963                 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\r
 964 \r
 965                 if (is92C)\r
 966                  {\r
 967                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);\r
 968                         rtw_usleep_os(100);\r
 969                         if (rfPath == RF_PATH_A)\r
 970                                 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.\r
 971                         else if (rfPath == RF_PATH_B)\r
 972                                 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.\r
 973                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.\r
 974                         rtw_usleep_os(100);\r
 975                 } \r
 976                 else\r
 977                 {\r
 978                         write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);\r
 979                         rtw_usleep_os(100);\r
 980                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.\r
 981                         rtw_usleep_os(100);\r
 982                 }                               \r
 983 \r
 984                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
 985                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
 986                 \r
 987         }\r
 988         else// Stop Single Tone.\r
 989         {\r
 990                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));\r
 991                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\r
 992                 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\r
 993 \r
 994                 if (is92C) {\r
 995                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);\r
 996                         rtw_usleep_os(100);\r
 997                         write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.\r
 998                         write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.\r
 999                         rtw_usleep_os(100);\r
1000                 } else {\r
1001                         write_rfreg(pAdapter, rfPath, 0x21, 0x54000);\r
1002                         rtw_usleep_os(100);\r
1003                         write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.\r
1004                         rtw_usleep_os(100);\r
1005                 }\r
1006 \r
1007                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1008                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1009                 \r
1010         }\r
1011         \r
1012 }\r
1013 \r
1014 \r
1015 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\r
1016 {\r
1017         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;\r
1018         if (bStart) // Start Carrier Suppression.\r
1019         {\r
1020                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));\r
1021                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1022                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1023                   {\r
1024                         // 1. if CCK block on?\r
1025                         if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1026                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1027 \r
1028                         //Turn Off All Test Mode\r
1029                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1030                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1031                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1032 \r
1033                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    //transmit mode\r
1034                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  //turn off scramble setting\r
1035 \r
1036                         //Set CCK Tx Test Rate\r
1037                         //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);\r
1038                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    //Set FTxRate to 1Mbps\r
1039                 }\r
1040 \r
1041                  //Set for dynamic set Power index\r
1042                  write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1043                  write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1044                  \r
1045         }\r
1046         else// Stop Carrier Suppression.\r
1047         {\r
1048                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));\r
1049                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1050                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {\r
1051                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    //normal mode\r
1052                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  //turn on scramble setting\r
1053 \r
1054                         //BB Reset\r
1055                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1056                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1057                 }\r
1058                 //Stop for dynamic set Power index\r
1059                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1060                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1061         }\r
1062         //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");\r
1063 }\r
1064 \r
1065 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1066 {\r
1067         u32 cckrate;\r
1068 \r
1069         if (bStart)\r
1070         {\r
1071                 RT_TRACE(_module_mp_, _drv_alert_,\r
1072                          ("SetCCKContinuousTx: test start\n"));\r
1073 \r
1074                 // 1. if CCK block on?\r
1075                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1076                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1077 \r
1078                 //Turn Off All Test Mode\r
1079                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1080                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1081                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1082                 //Set CCK Tx Test Rate\r
1083                 #if 0\r
1084                 switch(pAdapter->mppriv.rateidx)\r
1085                 {\r
1086                         case 2:\r
1087                                 cckrate = 0;\r
1088                                 break;\r
1089                         case 4:\r
1090                                 cckrate = 1;\r
1091                                 break;\r
1092                         case 11:\r
1093                                 cckrate = 2;\r
1094                                 break;\r
1095                         case 22:\r
1096                                 cckrate = 3;\r
1097                                 break;\r
1098                         default:\r
1099                                 cckrate = 0;\r
1100                                 break;\r
1101                 }\r
1102                 #else\r
1103                 cckrate  = pAdapter->mppriv.rateidx;\r
1104                 #endif\r
1105                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
1106                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   //transmit mode\r
1107                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1108 \r
1109                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1110                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1111 \r
1112                 // Patch for CCK 11M waveform\r
1113                 if (cckrate == MPT_RATE_1M)\r
1114                         write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);\r
1115                 else\r
1116                         write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);\r
1117 \r
1118 \r
1119         }\r
1120         else {\r
1121                 RT_TRACE(_module_mp_, _drv_info_,\r
1122                          ("SetCCKContinuousTx: test stop\n"));\r
1123 \r
1124                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   //normal mode\r
1125                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1126 \r
1127                 //BB Reset\r
1128                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1129                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1130                 \r
1131                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1132                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);        \r
1133         }\r
1134 \r
1135         pAdapter->mppriv.MptCtx.bCckContTx = bStart;\r
1136         pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;\r
1137 }/* mpt_StartCckContTx */\r
1138 \r
1139 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1140 {\r
1141     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(pAdapter);\r
1142 \r
1143         if (bStart) {\r
1144                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));\r
1145                 // 1. if OFDM block on?\r
1146                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
1147                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
1148         {\r
1149 \r
1150                 // 2. set CCK test mode off, set to CCK normal mode\r
1151                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
1152 \r
1153                 // 3. turn on scramble setting\r
1154                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
1155         }\r
1156                 // 4. Turn On Continue Tx and turn off the other test modes.\r
1157                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);\r
1158                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1159                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1160 \r
1161                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1162                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1163                 \r
1164         } else {\r
1165                 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));\r
1166                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1167                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1168                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1169                 //Delay 10 ms\r
1170                 rtw_msleep_os(10);\r
1171                 //BB Reset\r
1172                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1173                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1174 \r
1175                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1176                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);        \r
1177         }\r
1178 \r
1179         pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;\r
1180         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;\r
1181 }/* mpt_StartOfdmContTx */\r
1182 \r
1183 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1184 {\r
1185 #if 0\r
1186         // ADC turn off [bit24-21] adc port0 ~ port1\r
1187         if (bStart) {\r
1188                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);\r
1189                 rtw_usleep_os(100);\r
1190         }\r
1191 #endif\r
1192         RT_TRACE(_module_mp_, _drv_info_,\r
1193                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));\r
1194 \r
1195         pAdapter->mppriv.MptCtx.bStartContTx = bStart;\r
1196         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1197         {\r
1198                 Hal_SetCCKContinuousTx(pAdapter, bStart);\r
1199         }\r
1200         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&\r
1201                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))\r
1202         {\r
1203                 Hal_SetOFDMContinuousTx(pAdapter, bStart);\r
1204         }\r
1205 #if 0\r
1206         // ADC turn on [bit24-21] adc port0 ~ port1\r
1207         if (!bStart) {\r
1208                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);\r
1209         }\r
1210 #endif\r
1211 }\r
1212 \r
1213 #endif // CONFIG_MP_INCLUDE\r
1214 \r