1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #define _RTL8723A_MP_C_
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21 #ifdef CONFIG_MP_INCLUDED
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23 #include <drv_types.h>
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25 #include <rtl8723a_hal.h>
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28 /*-----------------------------------------------------------------------------
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29 * Function: mpt_SwitchRfSetting
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31 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
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33 * Input: IN PADAPTER pAdapter
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41 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
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42 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
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44 *---------------------------------------------------------------------------*/
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45 static void phy_SwitchRfSetting8723A(PADAPTER pAdapter,u8 channel )
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48 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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49 u32 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;
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51 DBG_8192C("phy_SwitchRfSetting8723A channel=%d\n",channel);
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54 if(channel >= 1 && channel <= 9)
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56 DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF0FFFF83\n");
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57 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
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59 else if (channel >= 10 && channel <= 14)
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61 DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF2FFFF83\n");
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62 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
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66 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
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67 u4Byte u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;
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70 u4RF_IPA[0] = 0x4F424; //CCK
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71 u4RF_IPA[1] = 0xCF424; //OFDM
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72 u4RF_IPA[2] = 0x8F424; //MCS
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73 u4RF_TXBIAS = 0xC0356;
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74 u4RF_SYN_G2 = 0x4F200;
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80 u4RF_IPA[0] = 0x4F40C;
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81 u4RF_IPA[1] = 0xCF466;
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82 u4RF_TXBIAS = 0xC0350;
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83 u4RF_SYN_G2 = 0x0F400;
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87 u4RF_IPA[0] = 0x4F407;
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88 u4RF_TXBIAS = 0xC0350;
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89 u4RF_SYN_G2 = 0x0F400;
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93 u4RF_IPA[0] = 0x4F407;
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94 u4RF_IPA[2] = 0x8F466;
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95 u4RF_TXBIAS = 0xC0350;
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96 u4RF_SYN_G2 = 0x0F400;
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101 u4RF_SYN_G2 = 0x0F400;
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106 u4RF_IPA[0] = 0x4F40C;
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110 u4RF_IPA[0] = 0x4F40C;
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111 u4RF_SYN_G2 = 0x0F400;
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115 u4RF_IPA[2] = 0x8F454;
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116 u4RF_SYN_G2 = 0x0F400;
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120 u4RF_IPA[0] = 0x4F40C;
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121 u4RF_IPA[1] = 0xCF454;
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122 u4RF_SYN_G2 = 0x0F400;
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126 u4RF_IPA[0] = 0x4F424;
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127 u4RF_IPA[1] = 0x8F424;
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128 u4RF_IPA[2] = 0xCF424;
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129 u4RF_TXBIAS = 0xC0356;
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130 u4RF_SYN_G2 = 0x4F200;
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134 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);
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135 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);
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136 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);
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137 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);
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138 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);
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140 if((channel >= 1 && channel <= 5) || (channel >= 8 && channel <= 9))
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142 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
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146 PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
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157 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
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159 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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160 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
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163 pMptCtx->MptChannelToSw=pAdapter->mppriv.channel;
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164 ChannelToSw =pMptCtx->MptChannelToSw;
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166 phy_SwitchRfSetting8723A(pAdapter, ChannelToSw);
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172 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)
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174 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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175 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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178 if (!netif_running(padapter->pnetdev)) {
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179 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
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183 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
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184 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
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189 pdmpriv->TxPowerTrackControl = _TRUE;
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191 pdmpriv->TxPowerTrackControl = _FALSE;
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196 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)
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198 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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199 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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202 *enable = pdmpriv->TxPowerTrackControl;
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205 static void Hal_disable_dm(PADAPTER padapter)
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208 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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209 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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212 //3 1. disable firmware dynamic mechanism
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213 // disable Power Training, Rate Adaptive
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214 v8 = rtw_read8(padapter, REG_BCN_CTRL);
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215 v8 &= ~EN_BCN_FUNCTION;
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216 rtw_write8(padapter, REG_BCN_CTRL, v8);
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218 //3 2. disable driver dynamic mechanism
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219 // disable Dynamic Initial Gain
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220 // disable High Power
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221 // disable Power Tracking
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222 Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
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224 // enable APK, LCK and IQK but disable power tracking
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225 pdmpriv->TxPowerTrackControl = _FALSE;
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226 Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE);
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229 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
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231 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
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232 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
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234 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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237 // get current cck swing value and check 0xa22 & 0xa23 later to match the table.
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238 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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242 // Readback the current bb cck swing value and compare with the table to
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243 // get the current swing index
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244 for (i = 0; i < CCK_TABLE_SIZE; i++)
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246 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
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247 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
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250 // RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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251 // (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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256 //Write 0xa22 0xa23
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257 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
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258 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
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261 //Write 0xa24 ~ 0xa27
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263 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
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264 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
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265 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
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266 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
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268 //Write 0xa28 0xa29
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270 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
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271 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
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275 for (i = 0; i < CCK_TABLE_SIZE; i++)
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277 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
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278 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
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281 // RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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282 // (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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287 //Write 0xa22 0xa23
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288 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
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289 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
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291 //Write 0xa24 ~ 0xa27
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293 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
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294 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
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295 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
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296 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
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298 //Write 0xa28 0xa29
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300 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
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301 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
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304 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
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305 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
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306 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
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309 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
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312 u8 CCK_index, CCK_index_old;
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313 u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
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316 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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317 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
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320 if (!IS_92C_SERIAL(pHalData->VersionID))
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323 while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
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325 PlatformSleepUs(100);
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329 RTPRINT(FINIT, INIT_TxPower,
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330 ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
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335 if (beven && !pMptCtx->bMptIndexEven) //odd->even
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338 pMptCtx->bMptIndexEven = _TRUE;
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340 else if (!beven && pMptCtx->bMptIndexEven) //even->odd
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343 pMptCtx->bMptIndexEven = _FALSE;
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348 //Query CCK default setting From 0xa24
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349 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
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350 for (i = 0; i < CCK_TABLE_SIZE; i++)
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352 if (pHalData->dmpriv.bCCKinCH14)
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354 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)
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356 CCK_index_old = (u8) i;
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357 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
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358 // rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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364 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)
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366 CCK_index_old = (u8) i;
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367 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
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368 // rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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375 CCK_index = CCK_index_old - 1;
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377 CCK_index = CCK_index_old + 1;
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379 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
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382 //Adjust CCK according to gain index
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383 if (!pHalData->dmpriv.bCCKinCH14) {
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384 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
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385 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
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386 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
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387 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
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388 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
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389 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
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390 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
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391 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
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393 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
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394 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
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395 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
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396 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
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397 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
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398 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
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399 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
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400 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
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404 RTPRINT(FINIT, INIT_TxPower,
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405 ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
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407 PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
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410 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
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415 * Use H2C command to change channel,
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416 * not only modify rf register, but also other setting need to be done.
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418 void Hal_SetChannel(PADAPTER pAdapter)
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421 struct mp_priv *pmp = &pAdapter->mppriv;
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423 // SelectChannel(pAdapter, pmp->channel);
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424 set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
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428 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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429 struct mp_priv *pmp = &pAdapter->mppriv;
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430 u8 channel = pmp->channel;
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431 u8 bandwidth = pmp->bandwidth;
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432 u8 rate = pmp->rateidx;
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435 // set RF channel register
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436 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
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438 if(IS_HARDWARE_TYPE_8192D(pAdapter))
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439 _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel);
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441 _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);
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443 Hal_mpt_SwitchRfSetting(pAdapter);
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445 SelectChannel(pAdapter, channel);
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447 if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {
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448 pHalData->dmpriv.bCCKinCH14 = _TRUE;
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449 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
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451 else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {
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452 pHalData->dmpriv.bCCKinCH14 = _FALSE;
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453 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
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461 * Switch bandwitdth may change center frequency(channel)
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463 void Hal_SetBandwidth(PADAPTER pAdapter)
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465 struct mp_priv *pmp = &pAdapter->mppriv;
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468 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
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469 Hal_mpt_SwitchRfSetting(pAdapter);
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472 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
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477 // rf-A cck tx power
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478 write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
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479 tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
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480 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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482 // rf-B cck tx power
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483 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
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484 tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
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485 write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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487 RT_TRACE(_module_mp_, _drv_notice_,
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488 ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
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489 TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
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492 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
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496 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
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497 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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501 tmpval = TxPower[RF_PATH_A];
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502 TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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504 write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
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505 write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
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506 write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
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507 write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
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508 write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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509 write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
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511 if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))
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513 if (tmpval > pMptCtx->APK_bound[RF_PATH_A])
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514 write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][0]);
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516 write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][1]);
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520 tmpval = TxPower[RF_PATH_B];
\r
521 TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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523 write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
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524 write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
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525 write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
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526 write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
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527 write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
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528 write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
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530 if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))
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532 if (tmpval > pMptCtx->APK_bound[RF_PATH_B])
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533 write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][0]);
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535 write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][1]);
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538 RT_TRACE(_module_mp_, _drv_notice_,
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539 ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",
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540 TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
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543 void Hal_SetAntennaPathPower(PADAPTER pAdapter)
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545 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
546 u8 TxPowerLevel[MAX_RF_PATH_NUMS];
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549 TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
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550 TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
\r
552 switch (pAdapter->mppriv.antenna_tx)
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556 rfPath = RF_PATH_A;
\r
559 rfPath = RF_PATH_B;
\r
562 rfPath = RF_PATH_C;
\r
566 switch (pHalData->rf_chip)
\r
571 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
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572 if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
\r
573 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
\r
574 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
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582 void Hal_SetTxPower(PADAPTER pAdapter)
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584 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
585 u8 TxPower = pAdapter->mppriv.txpoweridx;
\r
586 u8 TxPowerLevel[MAX_RF_PATH_NUMS];
\r
589 for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {
\r
590 TxPowerLevel[rf] = TxPower;
\r
593 switch (pAdapter->mppriv.antenna_tx)
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597 rfPath = RF_PATH_A;
\r
600 rfPath = RF_PATH_B;
\r
603 rfPath = RF_PATH_C;
\r
607 switch (pHalData->rf_chip)
\r
609 // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!
\r
610 // We should call normal driver API later!!
\r
614 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
\r
615 if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
\r
616 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
\r
617 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
\r
624 // SetCCKTxPower(pAdapter, TxPower);
\r
625 // SetOFDMTxPower(pAdapter, TxPower);
\r
628 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
\r
630 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
\r
634 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
\r
635 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
\r
636 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
\r
638 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
\r
639 write_bbreg(pAdapter, rFPGA0_TxGainStage,
\r
640 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
\r
643 void Hal_SetDataRate(PADAPTER pAdapter)
\r
645 if(!IS_HARDWARE_TYPE_8723A(pAdapter))
\r
646 Hal_mpt_SwitchRfSetting(pAdapter);
\r
650 void Hal_SetAntenna(PADAPTER pAdapter)
\r
652 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
654 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
\r
655 R_ANTENNA_SELECT_CCK *p_cck_txrx;
\r
657 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
\r
658 u8 chgTx = 0, chgRx = 0;
\r
659 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
\r
662 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
\r
663 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
\r
665 p_ofdm_tx->r_ant_ht1 = 0x1;
\r
666 p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A
\r
667 p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3
\r
669 switch (pAdapter->mppriv.antenna_tx)
\r
672 p_ofdm_tx->r_tx_antenna = 0x1;
\r
673 r_ofdm_tx_en_val = 0x1;
\r
674 p_ofdm_tx->r_ant_l = 0x1;
\r
675 p_ofdm_tx->r_ant_ht_s1 = 0x1;
\r
676 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
\r
677 p_cck_txrx->r_ccktx_enable = 0x8;
\r
680 // From SD3 Willis suggestion !!! Set RF A=TX and B as standby
\r
681 // if (IS_HARDWARE_TYPE_8192S(pAdapter))
\r
683 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
\r
684 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
\r
685 r_ofdm_tx_en_val = 0x3;
\r
688 //cosa r_ant_select_ofdm_val = 0x11111111;
\r
690 // We need to close RFB by SW control
\r
691 if (pHalData->rf_type == RF_2T2R)
\r
693 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
\r
694 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
\r
695 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
\r
696 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
\r
697 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
\r
703 p_ofdm_tx->r_tx_antenna = 0x2;
\r
704 r_ofdm_tx_en_val = 0x2;
\r
705 p_ofdm_tx->r_ant_l = 0x2;
\r
706 p_ofdm_tx->r_ant_ht_s1 = 0x2;
\r
707 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
\r
708 p_cck_txrx->r_ccktx_enable = 0x4;
\r
711 // From SD3 Willis suggestion !!! Set RF A as standby
\r
712 //if (IS_HARDWARE_TYPE_8192S(pAdapter))
\r
714 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
\r
715 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
\r
716 // r_ofdm_tx_en_val = 0x3;
\r
719 //cosa r_ant_select_ofdm_val = 0x22222222;
\r
721 // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.
\r
722 // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control
\r
723 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
\r
725 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
\r
726 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
\r
727 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
\r
728 // PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
\r
729 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
\r
730 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
\r
735 case ANTENNA_AB: // For 8192S
\r
736 p_ofdm_tx->r_tx_antenna = 0x3;
\r
737 r_ofdm_tx_en_val = 0x3;
\r
738 p_ofdm_tx->r_ant_l = 0x3;
\r
739 p_ofdm_tx->r_ant_ht_s1 = 0x3;
\r
740 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
\r
741 p_cck_txrx->r_ccktx_enable = 0xC;
\r
744 // From SD3 Willis suggestion !!! Set RF B as standby
\r
745 //if (IS_HARDWARE_TYPE_8192S(pAdapter))
\r
747 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
\r
748 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
\r
750 // Disable Power save
\r
751 //cosa r_ant_select_ofdm_val = 0x3321333;
\r
753 // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.
\r
754 if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.
\r
756 mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);
\r
759 // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
\r
760 if (pHalData->rf_type == RF_2T2R)
\r
762 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
\r
763 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
\r
764 // PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
\r
765 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
\r
766 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
\r
776 // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
\r
777 // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
\r
778 // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D
\r
780 switch (pAdapter->mppriv.antenna_rx)
\r
783 r_rx_antenna_ofdm = 0x1; // A
\r
784 p_cck_txrx->r_cckrx_enable = 0x0; // default: A
\r
785 p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
\r
790 r_rx_antenna_ofdm = 0x2; // B
\r
791 p_cck_txrx->r_cckrx_enable = 0x1; // default: B
\r
792 p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
\r
797 r_rx_antenna_ofdm = 0x3; // AB
\r
798 p_cck_txrx->r_cckrx_enable = 0x0; // default:A
\r
799 p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
\r
807 if (chgTx && chgRx)
\r
809 switch(pHalData->rf_chip)
\r
814 //r_ant_sel_cck_val = r_ant_select_cck_val;
\r
815 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx
\r
816 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx
\r
817 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
\r
818 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
\r
819 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx
\r
828 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
\r
831 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
\r
833 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
836 if (!netif_running(pAdapter->pnetdev)) {
\r
837 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
\r
841 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
\r
842 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
\r
846 target_ther &= 0xff;
\r
847 if (target_ther < 0x07)
\r
848 target_ther = 0x07;
\r
849 else if (target_ther > 0x1d)
\r
850 target_ther = 0x1d;
\r
852 pHalData->EEPROMThermalMeter = target_ther;
\r
857 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
\r
860 write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60); // 0x24: RF Reg[6:5]
\r
862 // RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
\r
865 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
\r
867 u32 ThermalValue = 0;
\r
869 ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
\r
870 // RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
\r
871 return (u8)ThermalValue;
\r
874 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
\r
877 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
\r
878 rtw_msleep_os(1000);
\r
879 fw_cmd_data(pAdapter, value, 1);
\r
883 Hal_TriggerRFThermalMeter(pAdapter);
\r
884 rtw_msleep_os(1000);
\r
885 *value = Hal_ReadRFThermalMeter(pAdapter);
\r
889 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
\r
891 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
892 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
\r
893 if (bStart)// Start Single Carrier.
\r
895 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
\r
896 // 1. if OFDM block on?
\r
897 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
\r
898 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
\r
901 // 2. set CCK test mode off, set to CCK normal mode
\r
902 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
\r
903 // 3. turn on scramble setting
\r
904 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
\r
906 // 4. Turn On Single Carrier Tx and turn off the other test modes.
\r
907 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
908 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
\r
909 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
910 #ifdef CONFIG_RTL8192C
\r
911 // 5. Disable TX power saving at STF & LLTF
\r
912 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);
\r
915 else// Stop Single Carrier.
\r
917 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
\r
919 // Turn off all test modes.
\r
920 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
921 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
922 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
923 #ifdef CONFIG_RTL8192C
\r
924 // Cancel disable TX power saving at STF&LLTF
\r
925 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);
\r
927 //Delay 10 ms //delay_ms(10);
\r
931 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
932 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
937 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
\r
939 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
940 BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
\r
944 switch (pAdapter->mppriv.antenna_tx)
\r
948 rfPath = RF_PATH_A;
\r
951 rfPath = RF_PATH_B;
\r
954 rfPath = RF_PATH_C;
\r
958 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
\r
959 if (bStart)// Start Single Tone.
\r
961 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
\r
962 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
\r
963 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
\r
967 _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
\r
968 rtw_usleep_os(100);
\r
969 if (rfPath == RF_PATH_A)
\r
970 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.
\r
971 else if (rfPath == RF_PATH_B)
\r
972 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.
\r
973 write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
\r
974 rtw_usleep_os(100);
\r
978 write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
\r
979 rtw_usleep_os(100);
\r
980 write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
\r
981 rtw_usleep_os(100);
\r
984 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
985 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
988 else// Stop Single Tone.
\r
990 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
\r
991 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
\r
992 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
\r
995 _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
\r
996 rtw_usleep_os(100);
\r
997 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.
\r
998 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.
\r
999 rtw_usleep_os(100);
\r
1001 write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
\r
1002 rtw_usleep_os(100);
\r
1003 write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.
\r
1004 rtw_usleep_os(100);
\r
1007 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1008 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1015 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
\r
1017 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
\r
1018 if (bStart) // Start Carrier Suppression.
\r
1020 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
\r
1021 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
\r
1022 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
\r
1024 // 1. if CCK block on?
\r
1025 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
\r
1026 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
\r
1028 //Turn Off All Test Mode
\r
1029 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
1030 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1031 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1033 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
\r
1034 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
\r
1036 //Set CCK Tx Test Rate
\r
1037 //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
\r
1038 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
\r
1041 //Set for dynamic set Power index
\r
1042 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1043 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1046 else// Stop Carrier Suppression.
\r
1048 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
\r
1049 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
\r
1050 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
\r
1051 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
\r
1052 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
\r
1055 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
1056 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
1058 //Stop for dynamic set Power index
\r
1059 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1060 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1062 //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");
\r
1065 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
\r
1071 RT_TRACE(_module_mp_, _drv_alert_,
\r
1072 ("SetCCKContinuousTx: test start\n"));
\r
1074 // 1. if CCK block on?
\r
1075 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
\r
1076 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
\r
1078 //Turn Off All Test Mode
\r
1079 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
1080 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1081 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1082 //Set CCK Tx Test Rate
\r
1084 switch(pAdapter->mppriv.rateidx)
\r
1103 cckrate = pAdapter->mppriv.rateidx;
\r
1105 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
\r
1106 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
\r
1107 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
\r
1109 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1110 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1112 // Patch for CCK 11M waveform
\r
1113 if (cckrate == MPT_RATE_1M)
\r
1114 write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
\r
1116 write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
\r
1121 RT_TRACE(_module_mp_, _drv_info_,
\r
1122 ("SetCCKContinuousTx: test stop\n"));
\r
1124 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
\r
1125 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
\r
1128 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
1129 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
1131 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1132 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1135 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
\r
1136 pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
\r
1137 }/* mpt_StartCckContTx */
\r
1139 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
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1141 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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1144 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
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1145 // 1. if OFDM block on?
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1146 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
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1147 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
\r
1150 // 2. set CCK test mode off, set to CCK normal mode
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1151 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
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1153 // 3. turn on scramble setting
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1154 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
\r
1156 // 4. Turn On Continue Tx and turn off the other test modes.
\r
1157 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
\r
1158 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
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1159 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
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1161 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
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1162 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1165 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));
\r
1166 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
1167 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1168 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1170 rtw_msleep_os(10);
\r
1172 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
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1173 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
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1175 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1176 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1179 pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
\r
1180 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
\r
1181 }/* mpt_StartOfdmContTx */
\r
1183 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
\r
1186 // ADC turn off [bit24-21] adc port0 ~ port1
\r
1188 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
\r
1189 rtw_usleep_os(100);
\r
1192 RT_TRACE(_module_mp_, _drv_info_,
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1193 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
\r
1195 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
\r
1196 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
\r
1198 Hal_SetCCKContinuousTx(pAdapter, bStart);
\r
1200 else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
\r
1201 (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
\r
1203 Hal_SetOFDMContinuousTx(pAdapter, bStart);
\r
1206 // ADC turn on [bit24-21] adc port0 ~ port1
\r
1208 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
\r
1213 #endif // CONFIG_MP_INCLUDE
\r