1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
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27 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
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29 Major Change History:
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31 ---------- --------------- -------------------------------
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32 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
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33 2011-07-07 Roger Create.
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36 #include <HalPwrSeqCmd.h>
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41 // This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
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44 // We should follow specific format which was released from HW SD.
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46 // 2011.07.07, added by Roger.
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48 u8 HalPwrSeqCmdParsing(
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53 WLAN_PWR_CFG PwrSeqCmd[])
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55 WLAN_PWR_CFG PwrCfgCmd = {0};
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56 u8 bPollingBit = _FALSE;
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60 u32 pollingCount = 0; // polling autoload done.
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61 u32 maxPollingCnt = 5000;
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64 PwrCfgCmd = PwrSeqCmd[AryIdx];
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66 RT_TRACE(_module_hal_init_c_ , _drv_info_,
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67 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
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68 GET_PWR_CFG_OFFSET(PwrCfgCmd),
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69 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
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70 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
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71 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
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72 GET_PWR_CFG_BASE(PwrCfgCmd),
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73 GET_PWR_CFG_CMD(PwrCfgCmd),
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74 GET_PWR_CFG_MASK(PwrCfgCmd),
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75 GET_PWR_CFG_VALUE(PwrCfgCmd)));
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77 //2 Only Handle the command whose FAB, CUT, and Interface are matched
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78 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
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79 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
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80 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
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82 switch (GET_PWR_CFG_CMD(PwrCfgCmd))
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85 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
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89 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
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90 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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92 #ifdef CONFIG_SDIO_HCI
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94 // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
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97 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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99 // Read Back SDIO Local value
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100 value = SdioLocalCmd52Read1Byte(padapter, offset);
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102 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
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103 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
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105 // Write Back SDIO Local value
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106 SdioLocalCmd52Write1Byte(padapter, offset, value);
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111 #ifdef CONFIG_GSPI_HCI
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112 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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113 offset = SPI_LOCAL_OFFSET | offset;
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115 // Read the value from system register
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116 value = rtw_read8(padapter, offset);
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118 value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
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119 value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
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121 // Write the value back to sytem register
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122 rtw_write8(padapter, offset, value);
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126 case PWR_CMD_POLLING:
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127 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
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129 bPollingBit = _FALSE;
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130 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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131 #ifdef CONFIG_GSPI_HCI
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132 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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133 offset = SPI_LOCAL_OFFSET | offset;
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136 #ifdef CONFIG_SDIO_HCI
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137 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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138 value = SdioLocalCmd52Read1Byte(padapter, offset);
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141 value = rtw_read8(padapter, offset);
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143 value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
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144 if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
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145 bPollingBit = _TRUE;
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149 if (pollingCount++ > maxPollingCnt) {
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150 DBG_871X_LEVEL(_drv_always_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
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153 } while (!bPollingBit);
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157 case PWR_CMD_DELAY:
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158 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
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159 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
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160 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
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162 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
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166 // When this command is parsed, end the process
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167 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
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172 RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
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177 AryIdx++;//Add Array Index
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