drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/PhyDM_Adaptivity.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 #include "Mp_Precomp.h"\r
  25 #include "phydm_precomp.h"\r
  26 \r
  27 \r
  28 VOID\r
  29 Phydm_CheckAdaptivity(\r
  30         IN              PVOID                   pDM_VOID\r
  31         )\r
  32 {\r
  33         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  34         if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)\r
  35         {\r
  36                 if(pDM_Odm->bAdaOn == TRUE)\r
  37                 {\r
  38                         if(pDM_Odm->DynamicLinkAdaptivity == TRUE)\r
  39                         {\r
  40                                 if(pDM_Odm->bLinked && pDM_Odm->bCheck == FALSE)\r
  41                                 {\r
  42                                         Phydm_NHMCounterStatistics(pDM_Odm);\r
  43                                         Phydm_CheckEnvironment(pDM_Odm);\r
  44                                 }\r
  45                                 else if(!pDM_Odm->bLinked)\r
  46                                 {\r
  47                                 pDM_Odm->bCheck = FALSE;\r
  48                                 }\r
  49                         }\r
  50                         else\r
  51                         {\r
  52                                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
  53                                 pDM_Odm->adaptivity_flag = TRUE;\r
  54                         }\r
  55                 }\r
  56                 else\r
  57                 {\r
  58                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
  59                         pDM_Odm->adaptivity_flag = FALSE;\r
  60                 }\r
  61         }       \r
  62 }\r
  63 \r
  64 VOID\r
  65 Phydm_NHMCounterStatisticsInit(\r
  66         IN              PVOID                   pDM_VOID\r
  67         )\r
  68 {\r
  69         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  70 \r
  71         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
  72         {\r
  73                 //PHY parameters initialize for ac series\r
  74                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350);      //0x990[31:16]=0xC350   Time duration for NHM unit: us, 0xc350=200ms\r
  75                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff);   //0x994[31:16]=0xffff   th_9, th_10\r
  76                 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c);     //0x998=0xffffff5c              th_3, th_2, th_1, th_0\r
  77                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);       //0x998=0xffffff52              th_3, th_2, th_1, th_0\r
  78                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);       //0x99c=0xffffffff              th_7, th_6, th_5, th_4\r
  79                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff);          //0x9a0[7:0]=0xff               th_8\r
  80                 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7);       //0x994[9:8]=3                  enable CCX\r
  81                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON        enable CCX\r
  82                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1);         //0x9e8[7]=1                    max power among all RX ants     \r
  83                                 \r
  84         }\r
  85         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
  86         {\r
  87                 //PHY parameters initialize for n series\r
  88                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350);       //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms\r
  89                 //ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20);     //0x894[31:16]=0x4e20   Time duration for NHM unit: 4us, 0x4e20=80ms\r
  90                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff);    //0x890[31:16]=0xffff   th_9, th_10\r
  91                 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c);      //0x898=0xffffff5c              th_3, th_2, th_1, th_0\r
  92                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);        //0x898=0xffffff52              th_3, th_2, th_1, th_0\r
  93                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);        //0x89c=0xffffffff              th_7, th_6, th_5, th_4\r
  94                 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff);         //0xe28[7:0]=0xff               th_8\r
  95                 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7);        //0x890[9:8]=3                  enable CCX\r
  96                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1);  //0x890[10:8]=1         ignoreCCA ignore PHYTXON        enable CCX\r
  97                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1);             //0xc0c[7]=1                    max power among all RX ants                             \r
  98         }\r
  99 }\r
 100 \r
 101 VOID\r
 102 Phydm_NHMCounterStatistics(\r
 103         IN              PVOID                   pDM_VOID\r
 104         )\r
 105 {\r
 106         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 107 \r
 108         if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))\r
 109                 return;\r
 110 \r
 111         // Get NHM report\r
 112         Phydm_GetNHMCounterStatistics(pDM_Odm);\r
 113 \r
 114         // Reset NHM counter\r
 115         Phydm_NHMCounterStatisticsReset(pDM_Odm);\r
 116 }\r
 117 \r
 118 VOID\r
 119 Phydm_GetNHMCounterStatistics(\r
 120         IN              PVOID                   pDM_VOID\r
 121         )\r
 122 {\r
 123         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 124         u4Byte          value32 = 0;\r
 125 \r
 126         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 127                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);\r
 128         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 129                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);\r
 130 \r
 131         pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);\r
 132         pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1)>>8);\r
 133 \r
 134 }\r
 135 \r
 136 VOID\r
 137 Phydm_NHMCounterStatisticsReset(\r
 138         IN              PVOID                   pDM_VOID\r
 139         )\r
 140 {\r
 141         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 142         \r
 143         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 144         {                       \r
 145                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);\r
 146                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);\r
 147         }\r
 148         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 149         {\r
 150                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);\r
 151                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);\r
 152         }\r
 153 }\r
 154 \r
 155 VOID\r
 156 Phydm_NHMBBInit(\r
 157         IN              PVOID                   pDM_VOID\r
 158 )\r
 159 {\r
 160         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 161 \r
 162         pDM_Odm->adaptivity_flag = FALSE;\r
 163         pDM_Odm->tolerance_cnt = 3;\r
 164         pDM_Odm->NHMLastTxOkcnt = 0;\r
 165         pDM_Odm->NHMLastRxOkcnt = 0;\r
 166         pDM_Odm->NHMCurTxOkcnt = 0;\r
 167         pDM_Odm->NHMCurRxOkcnt = 0;\r
 168 }\r
 169 \r
 170 VOID\r
 171 Phydm_SetEDCCAThreshold(\r
 172         IN      PVOID   pDM_VOID,\r
 173         IN      s1Byte  H2L,\r
 174         IN      s1Byte  L2H\r
 175 )\r
 176 {\r
 177         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 178         \r
 179         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 180                 {\r
 181                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);\r
 182                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);\r
 183                 }\r
 184         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 185                 {\r
 186                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);\r
 187                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);\r
 188                 }\r
 189 }\r
 190 \r
 191 VOID\r
 192 Phydm_SetTRxMux(\r
 193         IN      PVOID                           pDM_VOID,\r
 194         IN      PhyDM_Trx_MUX_Type      txMode,\r
 195         IN      PhyDM_Trx_MUX_Type      rxMode\r
 196 )\r
 197 {\r
 198         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 199 \r
 200         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 201         {\r
 202                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode);      // set TXmod to standby mode to remove outside noise affect\r
 203                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode);   // set RXmod to standby mode to remove outside noise affect\r
 204                 if(pDM_Odm->RFType > ODM_1T1R)\r
 205                 {\r
 206                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode);    // set TXmod to standby mode to remove outside noise affect\r
 207                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect\r
 208                 }\r
 209         }\r
 210         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 211         {\r
 212                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode);       // set TXmod to standby mode to remove outside noise affect\r
 213                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect\r
 214                 if(pDM_Odm->RFType > ODM_1T1R)\r
 215                 {\r
 216                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode);     // set TXmod to standby mode to remove outside noise affect\r
 217                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode);       // set RXmod to standby mode to remove outside noise affect\r
 218                 }\r
 219         }\r
 220 \r
 221 }\r
 222 \r
 223 VOID\r
 224 Phydm_MACEDCCAState(\r
 225         IN      PVOID                                   pDM_VOID,\r
 226         IN      PhyDM_MACEDCCA_Type             State\r
 227 )\r
 228 {\r
 229         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 230         if(State == PhyDM_IGNORE_EDCCA)\r
 231         {\r
 232                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1);     //ignore EDCCA  reg520[15]=1\r
 233                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0);          //reg524[11]=0\r
 234         }\r
 235         else            // don't set MAC ignore EDCCA signal\r
 236         {\r
 237                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0);     //don't ignore EDCCA     reg520[15]=0\14\r
 238                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);  //reg524[11]=1  \r
 239         }\r
 240 \r
 241         pDM_Odm->EDCCA_enable_state = State;\r
 242         \r
 243         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d \n", State));\r
 244 \r
 245 }\r
 246 \r
 247 BOOLEAN\r
 248 Phydm_CalNHMcnt(\r
 249         IN              PVOID           pDM_VOID\r
 250 )\r
 251 {\r
 252         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 253         u2Byte                  Base = 0;\r
 254 \r
 255         Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;\r
 256 \r
 257         if(Base != 0)\r
 258         {\r
 259                 pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;\r
 260                 pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;\r
 261         }\r
 262         if((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)\r
 263                 return TRUE;                    // clean environment\r
 264         else\r
 265                 return FALSE;           //noisy environment\r
 266 \r
 267 }\r
 268 \r
 269 \r
 270 VOID\r
 271 Phydm_CheckEnvironment(\r
 272         IN      PVOID   pDM_VOID\r
 273 )\r
 274 {\r
 275         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 276         BOOLEAN         isCleanEnvironment = FALSE;\r
 277         u1Byte          i, clean = 0;\r
 278 \r
 279         if(pDM_Odm->bFirstLink == TRUE)\r
 280         {\r
 281                 pDM_Odm->adaptivity_flag = TRUE;\r
 282                 pDM_Odm->bFirstLink = FALSE;\r
 283                 return;\r
 284         }\r
 285         else\r
 286         {\r
 287                 if(pDM_Odm->NHMWait < 3)                        // Start enter NHM after 4 NHMWait\r
 288                 {\r
 289                         pDM_Odm->NHMWait ++;\r
 290                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 291                         return;\r
 292                 }\r
 293                 else\r
 294                 {\r
 295                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 296                         isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
 297                         if(isCleanEnvironment == TRUE)\r
 298                         {\r
 299                                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 300 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 301                                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;                       //mode 1\r
 302                                 pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_backup;\r
 303 #endif\r
 304                                 pDM_Odm->adaptivity_flag = TRUE;\r
 305                         }\r
 306                         else\r
 307                         {\r
 308 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
 309                                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 310 #else\r
 311                                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 312                                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;                        // for AP mode 2\r
 313                                 pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
 314 #endif\r
 315                                 pDM_Odm->adaptivity_flag = FALSE;\r
 316                         }\r
 317 \r
 318                         pDM_Odm->bFirstLink = TRUE;\r
 319                         pDM_Odm->bCheck = TRUE;\r
 320                 }\r
 321                 \r
 322         }\r
 323 \r
 324 \r
 325 }\r
 326 \r
 327 \r
 328 VOID\r
 329 Phydm_NHMBB(\r
 330         IN              PVOID                   pDM_VOID\r
 331 )\r
 332 {\r
 333         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 334         BOOLEAN         bCleanEnvironment;\r
 335 \r
 336         bCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
 337 \r
 338         pDM_Odm->NHMCurTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->NHMLastTxOkcnt;\r
 339         pDM_Odm->NHMCurRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->NHMLastRxOkcnt;\r
 340         pDM_Odm->NHMLastTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast);\r
 341         pDM_Odm->NHMLastRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast);       \r
 342         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("cnt_0=%d, cnt_1=%d, bCleanEnvironment = %d, NHMCurTxOkcnt = %llu, NHMCurRxOkcnt = %llu\n", \r
 343                 pDM_Odm->NHM_cnt_0, pDM_Odm->NHM_cnt_1, bCleanEnvironment, pDM_Odm->NHMCurTxOkcnt, pDM_Odm->NHMCurRxOkcnt));\r
 344 \r
 345         if(pDM_Odm->NHMWait < 4)                        // Start enter NHM after 4 NHMWait\r
 346         {\r
 347                 pDM_Odm->NHMWait ++;\r
 348                 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 349         }\r
 350         else if ( ((pDM_Odm->NHMCurTxOkcnt>>10) > 2) && ((pDM_Odm->NHMCurTxOkcnt) + 1 > (u8Byte)(pDM_Odm->NHMCurRxOkcnt<<2) + 1))               //Tx > 4*Rx and Tx > 2Mb possible for adaptivity test\r
 351         {\r
 352                 if(bCleanEnvironment == TRUE || pDM_Odm->adaptivity_flag == TRUE)\r
 353                 {\r
 354                         //Enable EDCCA since it is possible running Adaptivity testing\r
 355                         pDM_Odm->adaptivity_flag = TRUE;\r
 356                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 357                         pDM_Odm->tolerance_cnt = 0;\r
 358 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 359                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;\r
 360                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;\r
 361 #endif\r
 362                 }\r
 363                 else\r
 364                 {\r
 365                         if(pDM_Odm->tolerance_cnt < 3)\r
 366                                 pDM_Odm->tolerance_cnt ++;\r
 367                         else\r
 368                         {\r
 369 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 370                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
 371                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;\r
 372 #else                           \r
 373                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 374 #endif\r
 375                         pDM_Odm->adaptivity_flag = FALSE;\r
 376                         }\r
 377                 }\r
 378         }\r
 379         else    // TX<RX \r
 380         {\r
 381                 if(pDM_Odm->adaptivity_flag == TRUE && bCleanEnvironment == FALSE)\r
 382                 {\r
 383                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 384                         pDM_Odm->tolerance_cnt = 0;\r
 385 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 386                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;\r
 387                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;\r
 388 #endif\r
 389                 }\r
 390 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)               // for repeater mode add by YuChen 2014.06.23\r
 391 #ifdef UNIVERSAL_REPEATER\r
 392                 else if((bCleanEnvironment == TRUE) && (pDM_Odm->VXD_bLinked) && ((pDM_Odm->NHMCurTxOkcnt>>10) > 1))            // clean environment and VXD linked and Tx TP>1Mb\r
 393                 {\r
 394                         pDM_Odm->adaptivity_flag = TRUE;\r
 395                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 396                         pDM_Odm->tolerance_cnt = 0;\r
 397                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;\r
 398                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;\r
 399                 }\r
 400 #endif \r
 401 #endif                                                                  // for repeater mode add by YuChen 2014.06.23\r
 402                 else\r
 403                 {\r
 404                         if(pDM_Odm->tolerance_cnt < 3)\r
 405                                 pDM_Odm->tolerance_cnt ++;\r
 406                         else\r
 407                         {\r
 408 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 409                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
 410                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;\r
 411 #else\r
 412                         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 413 #endif\r
 414                         pDM_Odm->adaptivity_flag = FALSE;\r
 415                         }\r
 416                 }\r
 417         }\r
 418          \r
 419         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_flag = %d\n ", pDM_Odm->adaptivity_flag));\r
 420 }\r
 421 \r
 422 VOID\r
 423 Phydm_SearchPwdBLowerBound(\r
 424         IN              PVOID           pDM_VOID\r
 425 )\r
 426 {\r
 427         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 428         u4Byte                  value32 =0;\r
 429         u1Byte                  cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50;   //IGI = 0x50 for cal EDCCA lower bound\r
 430         u1Byte                  txEdcca1 = 0, txEdcca0 = 0;\r
 431         BOOLEAN                 bAdjust=TRUE;\r
 432         s1Byte                  TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;\r
 433         s1Byte                  Diff;\r
 434 \r
 435         Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 436         ODM_Write_DIG(pDM_Odm, IGI_Pause);\r
 437         \r
 438         Diff = IGI_target -(s1Byte)IGI;\r
 439         TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 440                 if(TH_L2H_dmc > 10)     \r
 441                         TH_L2H_dmc = 10;\r
 442         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 443 \r
 444         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);                       \r
 445         ODM_delay_ms(5);\r
 446                 \r
 447                 while(bAdjust)\r
 448                         {\r
 449                         for(cnt=0; cnt<20; cnt ++)\r
 450                                 {\r
 451                                 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 452                                         value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);\r
 453                                 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 454                                         value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);\r
 455                         \r
 456                                 if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))\r
 457                                         txEdcca1 = txEdcca1 + 1;\r
 458                                 else if(value32 & BIT29)\r
 459                                         txEdcca1 = txEdcca1 + 1;\r
 460                                 else\r
 461                                         txEdcca0 = txEdcca0 + 1;\r
 462                                 }\r
 463                         \r
 464                                 if(txEdcca1 > 9 )\r
 465                                 {\r
 466                                         IGI = IGI -1;\r
 467                                         TH_L2H_dmc = TH_L2H_dmc + 1;\r
 468                                                 if(TH_L2H_dmc > 10)\r
 469                                                         TH_L2H_dmc = 10;\r
 470                                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 471 \r
 472                                         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 473 \r
 474                                         txEdcca1 = 0;\r
 475                                         txEdcca0 = 0;\r
 476 \r
 477                                         if(TH_L2H_dmc == 10)\r
 478                                                 {\r
 479                                                 bAdjust = FALSE;\r
 480                                                 pDM_Odm->H2L_lb = TH_H2L_dmc;\r
 481                                                 pDM_Odm->L2H_lb = TH_L2H_dmc;\r
 482                                                 pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 483                                                 }\r
 484                                 }\r
 485                                 else\r
 486                                 {\r
 487                                         bAdjust = FALSE;\r
 488                                         pDM_Odm->H2L_lb = TH_H2L_dmc;\r
 489                                         pDM_Odm->L2H_lb = TH_L2H_dmc;   \r
 490                                         pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 491                                 }\r
 492                         }\r
 493                                                         \r
 494         Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
 495         ODM_Write_DIG(pDM_Odm, IGI_Resume);\r
 496         Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); // resume to no link state\r
 497 }\r
 498 \r
 499 VOID\r
 500 Phydm_AdaptivityInit(\r
 501         IN      PVOID           pDM_VOID\r
 502 )\r
 503 {\r
 504         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 505 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 506         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 507         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
 508         pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;\r
 509         pDM_Odm->NHM_enable = (BOOLEAN)pMgntInfo->RegNHMEnable;\r
 510         pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;\r
 511 #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 512         pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE;\r
 513         pDM_Odm->NHM_enable = (BOOLEAN)pDM_Odm->Adapter->registrypriv.nhm_en;\r
 514         pDM_Odm->DynamicLinkAdaptivity = FALSE; // Jeff please add this\r
 515 #endif\r
 516 \r
 517 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 518 \r
 519         if(pDM_Odm->Carrier_Sense_enable == FALSE)\r
 520         {\r
 521 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 522                 if( pMgntInfo->RegL2HForAdaptivity != 0 )\r
 523                         pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
 524                 else\r
 525 #endif\r
 526                         pDM_Odm->TH_L2H_ini = 0xf5; // -7\r
 527         }\r
 528         else\r
 529         {\r
 530 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 531                 if( pMgntInfo->RegL2HForAdaptivity != 0 )\r
 532                         pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
 533                 else\r
 534 #endif\r
 535                 pDM_Odm->TH_L2H_ini = 0xa; \r
 536         }\r
 537 \r
 538         pDM_Odm->AdapEn_RSSI = 20;\r
 539 \r
 540 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 541         if( pMgntInfo->RegHLDiffForAdaptivity != 0 )\r
 542                 pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;\r
 543         else\r
 544 #endif\r
 545         pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 546 \r
 547         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
 548 \r
 549 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 550         prtl8192cd_priv                         priv = pDM_Odm->priv;\r
 551 \r
 552         if(pDM_Odm->Carrier_Sense_enable){\r
 553                 pDM_Odm->TH_L2H_ini = 10;\r
 554                 pDM_Odm->TH_EDCCA_HL_diff = 7;          \r
 555                 pDM_Odm->AdapEn_RSSI = 30;\r
 556         }\r
 557         else\r
 558         {\r
 559                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;       //set by mib\r
 560                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 561                 pDM_Odm->AdapEn_RSSI = 20;\r
 562         }\r
 563 \r
 564         pDM_Odm->TH_L2H_ini_mode2 = 20;\r
 565         pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;\r
 566         //pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;\r
 567         pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;\r
 568         if(priv->pshare->rf_ft_var.adaptivity_enable == 2)\r
 569                 pDM_Odm->DynamicLinkAdaptivity = TRUE;\r
 570         else\r
 571                 pDM_Odm->DynamicLinkAdaptivity = FALSE;\r
 572 //      pDM_Odm->NHM_enable = FALSE;\r
 573 #endif\r
 574 \r
 575         pDM_Odm->IGI_Base = 0x32;       \r
 576         pDM_Odm->IGI_target = 0x1c;\r
 577         pDM_Odm->ForceEDCCA = 0;\r
 578         pDM_Odm->H2L_lb= 0;\r
 579         pDM_Odm->L2H_lb= 0;\r
 580         pDM_Odm->Adaptivity_IGI_upper = 0;\r
 581         pDM_Odm->NHMWait = 0;\r
 582         Phydm_NHMBBInit(pDM_Odm);\r
 583         pDM_Odm->bCheck = FALSE;\r
 584         pDM_Odm->bFirstLink = TRUE;\r
 585         pDM_Odm->bAdaOn = TRUE;\r
 586 \r
 587         ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted\r
 588 \r
 589         //Search pwdB lower bound\r
 590         {\r
 591         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 592                 ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);\r
 593         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 594                 ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);\r
 595         Phydm_SearchPwdBLowerBound(pDM_Odm);\r
 596         }\r
 597         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 598 }\r
 599 \r
 600 \r
 601 BOOLEAN\r
 602 Phydm_Adaptivity(\r
 603         IN              PVOID                   pDM_VOID,\r
 604         IN              u1Byte                  IGI\r
 605 )\r
 606 {\r
 607         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 608         s1Byte TH_L2H_dmc, TH_H2L_dmc, L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;\r
 609         s1Byte Diff, IGI_target;\r
 610         BOOLEAN EDCCA_State = FALSE;\r
 611 \r
 612 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 613         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 614         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 615         BOOLEAN         bFwCurrentInPSMode=FALSE;       \r
 616         PMGNT_INFO                              pMgntInfo = &(pAdapter->MgntInfo);\r
 617         \r
 618         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));   \r
 619 \r
 620         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.\r
 621         if(bFwCurrentInPSMode)\r
 622                 return FALSE;\r
 623 #endif\r
 624 \r
 625         if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))\r
 626         {\r
 627                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));\r
 628                 // Add by Neil Chen to enable edcca to MP Platform \r
 629 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 630                 // Adjust EDCCA.\r
 631                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 632                         Phydm_DynamicEDCCA(pDM_Odm);\r
 633 #endif\r
 634                 return FALSE;\r
 635         }\r
 636 \r
 637 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
 638 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 639         if(pMgntInfo->RegEnableAdaptivity== 2)\r
 640 #else\r
 641         if (pDM_Odm->Adapter->registrypriv.adaptivity_en == 2)\r
 642 #endif\r
 643         {\r
 644                 if(pDM_Odm->Carrier_Sense_enable == FALSE)              // check domain Code for Adaptivity or CarrierSense\r
 645                 {\r
 646                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) && \r
 647                                 !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))\r
 648                         {\r
 649                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d \n", pDM_Odm->odm_Regulation5G));\r
 650                                 return FALSE;\r
 651                         }\r
 652 \r
 653                         else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
 654                                 !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))\r
 655                         {\r
 656                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d \n", pDM_Odm->odm_Regulation2_4G));\r
 657                                 return FALSE;\r
 658                         \r
 659                         }\r
 660                         else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))\r
 661                         {\r
 662                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));\r
 663                                 return FALSE;\r
 664                         }\r
 665                 }\r
 666                 else\r
 667                 {\r
 668                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) && \r
 669                                 !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))\r
 670                         {\r
 671                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
 672                                 return FALSE;\r
 673                         }\r
 674 \r
 675                         else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
 676                                 !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))\r
 677                         {\r
 678                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
 679                                 return FALSE;\r
 680                         \r
 681                         }\r
 682                         else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))\r
 683                         {\r
 684                                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));\r
 685                                 return FALSE;\r
 686                         }\r
 687                 }\r
 688         }\r
 689 #endif\r
 690 \r
 691         \r
 692         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));\r
 693         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n", \r
 694                 pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));\r
 695 \r
 696         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 697                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable\r
 698 \r
 699         if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20\r
 700                 IGI_target = pDM_Odm->IGI_Base;\r
 701         else if(*pDM_Odm->pBandWidth == ODM_BW40M)\r
 702                 IGI_target = pDM_Odm->IGI_Base + 2;\r
 703         else if(*pDM_Odm->pBandWidth == ODM_BW80M)\r
 704                 IGI_target = pDM_Odm->IGI_Base + 2;\r
 705         else\r
 706                 IGI_target = pDM_Odm->IGI_Base;\r
 707         pDM_Odm->IGI_target = (u1Byte) IGI_target;\r
 708         \r
 709         if(*pDM_Odm->pChannel >= 149)           // Band4 -> for AP : mode2, for sd4 and sd7 : turnoff adaptivity\r
 710         {\r
 711 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 712                 if(pDM_Odm->bLinked)\r
 713                 {\r
 714                 Diff = IGI_target -(s1Byte)IGI;\r
 715                 L2H_nolink_Band4 = pDM_Odm->TH_L2H_ini_mode2 + Diff;\r
 716                 if(L2H_nolink_Band4 > 10)       \r
 717                         L2H_nolink_Band4 = 10;          \r
 718                 H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
 719                 }\r
 720 #endif\r
 721                 Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);\r
 722                 return FALSE;\r
 723         }\r
 724 \r
 725         if(!pDM_Odm->ForceEDCCA)\r
 726         {\r
 727                 if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)\r
 728                         EDCCA_State = 1;\r
 729                 else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))\r
 730                         EDCCA_State = 0;\r
 731         }\r
 732         else\r
 733                 EDCCA_State = 1;\r
 734 \r
 735         if(pDM_Odm->Carrier_Sense_enable == FALSE && pDM_Odm->NHM_enable == TRUE)\r
 736                 Phydm_NHMBB(pDM_Odm);\r
 737         \r
 738         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d, EDCCA_enable_state = %d\n",\r
 739                 (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State, pDM_Odm->EDCCA_enable_state));\r
 740         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x %x\n", pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper));\r
 741 \r
 742 \r
 743         if(EDCCA_State == 1)\r
 744         {\r
 745                 Diff = IGI_target -(s1Byte)IGI;\r
 746                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 747                 if(TH_L2H_dmc > 10)     \r
 748                         TH_L2H_dmc = 10;\r
 749                                 \r
 750                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 751 \r
 752                 //replace lower bound to prevent EDCCA always equal 1\r
 753                         if(TH_H2L_dmc < pDM_Odm->H2L_lb)                                \r
 754                                 TH_H2L_dmc = pDM_Odm->H2L_lb;\r
 755                         if(TH_L2H_dmc < pDM_Odm->L2H_lb)\r
 756                                 TH_L2H_dmc = pDM_Odm->L2H_lb;\r
 757         }\r
 758         else\r
 759         {\r
 760                 TH_L2H_dmc = 0x7f;\r
 761                 TH_H2L_dmc = 0x7f;\r
 762         }\r
 763         ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d, adaptivity_flg = %d, bAdaOn = %d, DynamicLinkAdaptivity = %d, NHM_enable = %d\n", \r
 764                 IGI, TH_L2H_dmc, TH_H2L_dmc, pDM_Odm->adaptivity_flag, pDM_Odm->bAdaOn, pDM_Odm->DynamicLinkAdaptivity, pDM_Odm->NHM_enable));\r
 765         \r
 766         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 767         return TRUE;\r
 768 }\r
 769 \r
 770 \r
 771 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 772 VOID\r
 773 Phydm_EnableEDCCA(\r
 774         IN              PVOID                                   pDM_VOID\r
 775 )\r
 776 {\r
 777 \r
 778         // This should be moved out of OUTSRC\r
 779         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 780         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 781         // Enable EDCCA. The value is suggested by SD3 Wilson.\r
 782 \r
 783         //\r
 784         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.\r
 785         //\r
 786         if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))\r
 787         {\r
 788                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);\r
 789                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);\r
 790                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);\r
 791                 \r
 792         }       \r
 793         else\r
 794         {\r
 795                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);\r
 796                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);\r
 797                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);\r
 798         }       \r
 799         \r
 800         //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);\r
 801 }\r
 802 \r
 803 VOID\r
 804 Phydm_DisableEDCCA(\r
 805         IN              PVOID                                   pDM_VOID\r
 806 )\r
 807 {       \r
 808         // Disable EDCCA..\r
 809         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 810         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);\r
 811         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);\r
 812 }\r
 813 \r
 814 //\r
 815 // Description: According to initial gain value to determine to enable or disable EDCCA.\r
 816 //\r
 817 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.\r
 818 //\r
 819 VOID\r
 820 Phydm_DynamicEDCCA(\r
 821         IN              PVOID                                   pDM_VOID\r
 822 )\r
 823 {\r
 824         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 825         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 826         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 827         u1Byte                  RegC50, RegC58;\r
 828         BOOLEAN                 bEDCCAenable = FALSE;\r
 829         \r
 830 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))   \r
 831         BOOLEAN                 bFwCurrentInPSMode=FALSE;       \r
 832 \r
 833         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));   \r
 834 \r
 835         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.\r
 836         if(bFwCurrentInPSMode)\r
 837                 return;\r
 838 #endif\r
 839         //\r
 840         // 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.\r
 841         // 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop\r
 842         // to send beacon in noisy environment or platform.\r
 843         //\r
 844         if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))\r
 845         //if(ACTING_AS_AP(pAdapter))\r
 846         {\r
 847                 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));\r
 848                 Phydm_DisableEDCCA(pDM_Odm);\r
 849                 if(pHalData->bPreEdccaEnable)\r
 850                         Phydm_DisableEDCCA(pDM_Odm);\r
 851                 pHalData->bPreEdccaEnable = FALSE;\r
 852                 return;\r
 853         }\r
 854         \r
 855         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
 856         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);\r
 857 \r
 858 \r
 859         if((RegC50 > 0x28 && RegC58 > 0x28) ||\r
 860                 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||\r
 861                 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))\r
 862         {\r
 863                 if(!pHalData->bPreEdccaEnable)\r
 864                 {\r
 865                         Phydm_EnableEDCCA(pDM_Odm);\r
 866                         pHalData->bPreEdccaEnable = TRUE;\r
 867                 }\r
 868                 \r
 869         }\r
 870         else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))\r
 871         {\r
 872                 if(pHalData->bPreEdccaEnable)\r
 873                 {\r
 874                         Phydm_DisableEDCCA(pDM_Odm);\r
 875                         pHalData->bPreEdccaEnable = FALSE;\r
 876                 }\r
 877         }\r
 878 }\r
 879 \r
 880 #endif\r