drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_AntDiv.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 \r
  25 #include "odm_precomp.h"\r
  26 \r
  27 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
  28 VOID\r
  29 odm_AntDiv_on_off( IN PDM_ODM_T pDM_Odm ,IN u1Byte swch)\r
  30 {\r
  31         if(pDM_Odm->AntDivType==S0S1_SW_ANTDIV || pDM_Odm->AntDivType==CGCS_RX_SW_ANTDIV) \r
  32                 return;\r
  33 \r
  34         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
  35         {\r
  36                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
  37                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
  38                 ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
  39         }\r
  40         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
  41         {\r
  42                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
  43                 if(pDM_Odm->SupportICType == ODM_RTL8812)\r
  44                 {\r
  45                         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
  46                         ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
  47                 }\r
  48                 else\r
  49                 {\r
  50                 ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable\r
  51                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); //CCK AntDiv function block enable\r
  52                 }\r
  53          }\r
  54 }\r
  55 \r
  56 VOID\r
  57 ODM_UpdateRxIdleAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)\r
  58 {\r
  59         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
  60         u4Byte  DefaultAnt, OptionalAnt,value32;\r
  61 \r
  62         #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
  63         PADAPTER                pAdapter = pDM_Odm->Adapter;\r
  64         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
  65         #endif\r
  66 \r
  67         if(pDM_FatTable->RxIdleAnt != Ant)\r
  68         {\r
  69                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
  70                 pDM_FatTable->RxIdleAnt = Ant;\r
  71 \r
  72                 if(Ant == MAIN_ANT)\r
  73                 {\r
  74                         DefaultAnt   =  ANT1_2G; \r
  75                         OptionalAnt =  ANT2_2G; \r
  76                 }\r
  77                 else\r
  78                 {\r
  79                         DefaultAnt  =   ANT2_2G;\r
  80                         OptionalAnt =  ANT1_2G;\r
  81                 }\r
  82         \r
  83                 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
  84                 {\r
  85                         if(pDM_Odm->SupportICType==ODM_RTL8192E)\r
  86                         {\r
  87                                 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX\r
  88                                 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX\r
  89                         }\r
  90                         else\r
  91                         {\r
  92                                 ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt);      //Default RX\r
  93                                 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt);     //Optional RX\r
  94 \r
  95                                 if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
  96                                 {\r
  97                                         value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF);\r
  98                                 \r
  99                                         if (value32 !=0x280)\r
 100                                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt);\r
 101 \r
 102                                         rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);\r
 103                                 }\r
 104                                 \r
 105                         }\r
 106                         ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);            //Default TX    \r
 107                 }\r
 108                 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
 109                 {\r
 110                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT21|BIT20|BIT19, DefaultAnt);    //Default RX\r
 111                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX\r
 112                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT27|BIT26|BIT25, DefaultAnt);    //Default TX\r
 113                 }\r
 114                 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt);    //\14PathA Resp Tx\r
 115         }\r
 116         else// pDM_FatTable->RxIdleAnt == Ant\r
 117         {\r
 118                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ]  RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 119                 pDM_FatTable->RxIdleAnt = Ant;\r
 120         }\r
 121 }\r
 122 \r
 123 \r
 124 VOID\r
 125 odm_UpdateTxAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)\r
 126 {\r
 127         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 128         u1Byte  TxAnt;\r
 129 \r
 130         if(Ant == MAIN_ANT)\r
 131                 TxAnt = ANT1_2G;\r
 132         else\r
 133                 TxAnt = ANT2_2G;\r
 134         \r
 135         pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0;\r
 136         pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1;\r
 137         pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2;\r
 138         #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 139         if (pDM_Odm->antdiv_rssi)\r
 140         {\r
 141                 //panic_printk("[Tx from TxInfo]: MacID:(( %d )),  TxAnt = (( %s ))\n",MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
 142                 //panic_printk("antsel_tr_mux=(( 3'b%d%d%d ))\n",       pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] );\r
 143         }\r
 144         #endif\r
 145         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )),  TxAnt = (( %s ))\n", \r
 146         //                                      MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 147         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",\r
 148                                                         //pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));\r
 149         \r
 150 }\r
 151 \r
 152 \r
 153 \r
 154 #if (RTL8188E_SUPPORT == 1)\r
 155 \r
 156 \r
 157 VOID\r
 158 odm_RX_HWAntDiv_Init_88E(\r
 159         IN              PDM_ODM_T               pDM_Odm\r
 160 )\r
 161 {\r
 162         u4Byte  value32;\r
 163 \r
 164         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 165 \r
 166         #if (MP_DRIVER == 1)\r
 167                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 168                 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
 169                 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);  // 1:CG, 0:CS\r
 170                 return;\r
 171         #endif\r
 172         \r
 173         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
 174         \r
 175         //MAC Setting\r
 176         value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);\r
 177         ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 178         //Pin Settings\r
 179         ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0             //antsel antselb by HW\r
 180         ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0);      //Reg864[10]=1'b0       //antsel2 by HW\r
 181         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1);       //Regb2c[22]=1'b0       //disable CS/CG switch\r
 182         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);       //Regb2c[31]=1'b1       //output at CG only\r
 183         //OFDM Settings\r
 184         ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);\r
 185         //CCK Settings\r
 186         ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue\r
 187         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples       \r
 188         \r
 189         ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0102);       //antenna mapping table\r
 190 \r
 191 }\r
 192 \r
 193 VOID\r
 194 odm_TRX_HWAntDiv_Init_88E(\r
 195         IN              PDM_ODM_T               pDM_Odm\r
 196 )\r
 197 {\r
 198         u4Byte  value32;\r
 199         \r
 200         #if (MP_DRIVER == 1)\r
 201                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 202                 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
 203                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX   (0/1)\r
 204                 return;\r
 205         #endif\r
 206 \r
 207         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));\r
 208         \r
 209         //MAC Setting\r
 210         value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);\r
 211         ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 212         //Pin Settings\r
 213         ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0             //antsel antselb by HW\r
 214         ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0);      //Reg864[10]=1'b0       //antsel2 by HW\r
 215         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0);       //Regb2c[22]=1'b0       //disable CS/CG switch\r
 216         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);       //Regb2c[31]=1'b1       //output at CG only\r
 217         //OFDM Settings\r
 218         ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);\r
 219         //CCK Settings\r
 220         ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue\r
 221         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples\r
 222 \r
 223         //antenna mapping table\r
 224         if(!pDM_Odm->bIsMPChip) //testchip\r
 225         {\r
 226                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1);   //Reg858[10:8]=3'b001\r
 227                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010\r
 228         }\r
 229         else //MPchip\r
 230                 ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201);   //Reg914=3'b010, Reg915=3'b001\r
 231 }\r
 232 \r
 233 VOID\r
 234 odm_Smart_HWAntDiv_Init_88E(\r
 235         IN              PDM_ODM_T               pDM_Odm\r
 236 )\r
 237 {\r
 238         u4Byte  value32, i;\r
 239         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 240         u4Byte  AntCombination = 2;\r
 241 \r
 242     ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
 243     \r
 244 #if (MP_DRIVER == 1)\r
 245     ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));\r
 246     return;\r
 247 #endif\r
 248 \r
 249         for(i=0; i<6; i++)\r
 250         {\r
 251                 pDM_FatTable->Bssid[i] = 0;\r
 252                 pDM_FatTable->antSumRSSI[i] = 0;\r
 253                 pDM_FatTable->antRSSIcnt[i] = 0;\r
 254                 pDM_FatTable->antAveRSSI[i] = 0;\r
 255         }\r
 256         pDM_FatTable->TrainIdx = 0;\r
 257         pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
 258 \r
 259         //MAC Setting\r
 260         value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);\r
 261         ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 262         value32 = ODM_GetMACReg(pDM_Odm,  0x7B4, bMaskDWord);\r
 263         ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match\r
 264         //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);\r
 265         //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18);        //append MACID in reponse packet\r
 266 \r
 267         //Match MAC ADDR\r
 268         ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);\r
 269         ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);\r
 270         \r
 271         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0            //antsel antselb by HW\r
 272         ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0);        //Reg864[10]=1'b0       //antsel2 by HW\r
 273         ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0);        //Regb2c[22]=1'b0       //disable CS/CG switch\r
 274         ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1);        //Regb2c[31]=1'b1       //output at CG only\r
 275         ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);\r
 276         \r
 277         //antenna mapping table\r
 278         if(AntCombination == 2)\r
 279         {\r
 280                 if(!pDM_Odm->bIsMPChip) //testchip\r
 281                 {\r
 282                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1);      //Reg858[10:8]=3'b001\r
 283                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2);    //Reg858[13:11]=3'b010\r
 284                 }\r
 285                 else //MPchip\r
 286                 {\r
 287                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);\r
 288                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);\r
 289                 }\r
 290         }\r
 291         else if(AntCombination == 7)\r
 292         {\r
 293                 if(!pDM_Odm->bIsMPChip) //testchip\r
 294                 {\r
 295                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0);      //Reg858[10:8]=3'b000\r
 296                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1);    //Reg858[13:11]=3'b001\r
 297                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);\r
 298                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2);  //(Reg878[0],Reg858[14:15])=3'b010\r
 299                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011\r
 300                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100\r
 301                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 \r
 302                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 \r
 303                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111\r
 304                 }\r
 305                 else //MPchip\r
 306                 {\r
 307                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 308                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);   \r
 309                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);\r
 310                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);\r
 311                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);\r
 312                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);\r
 313                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);\r
 314                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);\r
 315                 }\r
 316         }\r
 317 \r
 318         //Default Ant Setting when no fast training\r
 319         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1              //from TX Info\r
 320         ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0);       //Default RX\r
 321         ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1);       //Optional RX\r
 322         //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1);  //Default TX\r
 323 \r
 324         //Enter Traing state\r
 325         ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1));      //Reg864[2:0]=3'd6      //ant combination=reg864[2:0]+1\r
 326         //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0              //disable HW AntDiv\r
 327         //ODM_SetBBReg(pDM_Odm,  0xe08 , BIT16, 0); //RegE08[16]=1'b0           //disable fast training\r
 328         //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1);      //RegE08[16]=1'b1               //enable fast training\r
 329         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1                //enable HW AntDiv\r
 330 \r
 331         //SW Control\r
 332         //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);\r
 333         //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);\r
 334         //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);\r
 335         //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);\r
 336         //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);\r
 337         //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);\r
 338 }\r
 339 #endif //#if (RTL8188E_SUPPORT == 1)\r
 340 \r
 341 \r
 342 #if (RTL8192E_SUPPORT == 1)\r
 343 VOID\r
 344 odm_RX_HWAntDiv_Init_92E(\r
 345         IN              PDM_ODM_T               pDM_Odm\r
 346 )\r
 347 {\r
 348         \r
 349 #if (MP_DRIVER == 1)\r
 350         //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 351         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 352         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta  Regc50[8]=1'b0  0: control by c50[9]\r
 353         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1);  // 1:CG, 0:CS\r
 354         return;\r
 355 #endif\r
 356 \r
 357          ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init =>  AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
 358         \r
 359          //Pin Settings\r
 360          ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0,    // "antsel" is controled by HWs\r
 361          ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1  //" CS/CG switching" is controled by HWs\r
 362 \r
 363          //Mapping table\r
 364          ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table\r
 365           \r
 366          //OFDM Settings\r
 367          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold\r
 368          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias\r
 369          \r
 370          //CCK Settings\r
 371          ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
 372          ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
 373          ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
 374          ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples      \r
 375 }\r
 376 \r
 377 VOID\r
 378 odm_TRX_HWAntDiv_Init_92E(\r
 379         IN              PDM_ODM_T               pDM_Odm\r
 380 )\r
 381 {\r
 382         \r
 383 #if (MP_DRIVER == 1)\r
 384         //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 385         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 386         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta  Regc50[8]=1'b0  0: control by c50[9]\r
 387         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1);  // 1:CG, 0:CS\r
 388         return;\r
 389 #endif\r
 390 \r
 391 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 392          pDM_Odm->antdiv_rssi=0;\r
 393 #endif\r
 394 \r
 395          ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV]\n"));\r
 396         \r
 397         //3 --RFE pin setting---------\r
 398         //[MAC]\r
 399         ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1);            //DBG PAD Driving control (GPIO 8)\r
 400         ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0);            //path-A , RFE_CTRL_3 & RFE_CTRL_4\r
 401         //[BB]\r
 402         ODM_SetBBReg(pDM_Odm, 0x944 , BIT4|BIT3, 0x3);     //RFE_buffer\r
 403         ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_   (RFE_CTRL_3)\r
 404         ODM_SetBBReg(pDM_Odm, 0x940 , BIT9|BIT8, 0x0); // r_rfe_path_sel_   (RFE_CTRL_4)\r
 405         ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0);     //RFE_buffer\r
 406         ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0);     //rfe_inv  (RFE_CTRL_3)\r
 407         ODM_SetBBReg(pDM_Odm, 0x92C , BIT4, 1);     //rfe_inv  (RFE_CTRL_4)\r
 408         ODM_SetBBReg(pDM_Odm, 0x930 , 0xFF000, 0x88);           //path-A , RFE_CTRL_3 & 4=> ANTSEL[0]\r
 409         //3 -------------------------\r
 410         \r
 411          //Pin Settings\r
 412         ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0);    //path-A     //disable CS/CG switch\r
 413         ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);    //path-A     //output at CG only\r
 414         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);  //path-A          //antsel antselb by HW\r
 415         ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0);           //path-A     //antsel2 by HW \r
 416  \r
 417         //Mapping table\r
 418          ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table\r
 419           \r
 420          //OFDM Settings\r
 421          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold\r
 422          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias\r
 423          \r
 424          //CCK Settings\r
 425          ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
 426          ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
 427          ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
 428          ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples \r
 429 \r
 430          //Timming issue\r
 431          ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 432 }\r
 433 \r
 434 VOID\r
 435 odm_Smart_HWAntDiv_Init_92E(\r
 436         IN              PDM_ODM_T               pDM_Odm\r
 437 )\r
 438 {\r
 439     ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
 440 }\r
 441 #endif //#if (RTL8192E_SUPPORT == 1)\r
 442 \r
 443 \r
 444 #if (RTL8723B_SUPPORT == 1)\r
 445 VOID\r
 446 odm_TRX_HWAntDiv_Init_8723B(\r
 447         IN              PDM_ODM_T               pDM_Odm\r
 448 )\r
 449 {\r
 450         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n"));\r
 451       \r
 452         //Mapping Table\r
 453         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 454         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);\r
 455         \r
 456         //OFDM HW AntDiv Parameters\r
 457         ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold\r
 458         ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias\r
 459                 \r
 460         //CCK HW AntDiv Parameters\r
 461         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 462         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 463         \r
 464         //BT Coexistence\r
 465         ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1\r
 466         ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 467 \r
 468         //Output Pin Settings\r
 469         ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); //\r
 470                 \r
 471         ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)\r
 472         ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0);\r
 473                 \r
 474         ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1);\r
 475         ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1);\r
 476         ODM_SetMACReg(pDM_Odm, 0x4C ,  BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin\r
 477                 \r
 478         ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out\r
 479         ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //\r
 480 \r
 481         ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse\r
 482         ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse\r
 483 \r
 484         ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]\r
 485         ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]\r
 486 \r
 487         //Timming issue\r
 488         ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 489 \r
 490         //2 [--For HW Bug Setting]\r
 491         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 492                 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable\r
 493 \r
 494         //ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant  by Reg\r
 495 \r
 496 \r
 497 }\r
 498 \r
 499         \r
 500 \r
 501 VOID\r
 502 odm_S0S1_SWAntDiv_Init_8723B(\r
 503         IN              PDM_ODM_T               pDM_Odm\r
 504 )\r
 505 {\r
 506         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 507         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 508 \r
 509         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));\r
 510 \r
 511         //Mapping Table\r
 512         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 513         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);\r
 514         \r
 515         //Output Pin Settings\r
 516         //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); \r
 517         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); \r
 518 \r
 519         pDM_FatTable->bBecomeLinked  =FALSE;\r
 520         pDM_SWAT_Table->try_flag = 0xff;        \r
 521         pDM_SWAT_Table->Double_chk_flag = 0;\r
 522         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
 523 \r
 524         //Timming issue\r
 525         ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 526         \r
 527         //2 [--For HW Bug Setting]\r
 528         ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant  by Reg\r
 529 \r
 530 }\r
 531 #endif //#if (RTL8723B_SUPPORT == 1)\r
 532 \r
 533 \r
 534 #if (RTL8821A_SUPPORT == 1)\r
 535 VOID\r
 536 odm_TRX_HWAntDiv_Init_8821A(\r
 537         IN              PDM_ODM_T               pDM_Odm\r
 538 )\r
 539 {\r
 540         \r
 541 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 542 \r
 543         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 544         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 545 #else\r
 546         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 547 #endif\r
 548         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 549 \r
 550         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));\r
 551 \r
 552         //Output Pin Settings\r
 553         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 554 \r
 555         ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control\r
 556         ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control\r
 557 \r
 558         ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);\r
 559         ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);\r
 560         \r
 561         ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin\r
 562         ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control\r
 563         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]\r
 564         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]\r
 565         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse\r
 566         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse\r
 567 \r
 568         //Mapping Table\r
 569         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 570         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 571 \r
 572         //Set ANT1_8821A as MAIN_ANT\r
 573         if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
 574                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 575         else\r
 576                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 577 \r
 578         //OFDM HW AntDiv Parameters\r
 579         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 580         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
 581                 \r
 582         //CCK HW AntDiv Parameters\r
 583         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 584         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 585 \r
 586         ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 587 \r
 588         //BT Coexistence\r
 589         ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1\r
 590         ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 591 \r
 592         //Timming issue\r
 593         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 594         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 595 \r
 596         //response TX ant by RX ant\r
 597         ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
 598         \r
 599         //2 [--For HW Bug Setting]\r
 600         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 601                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 602                         \r
 603 }\r
 604 \r
 605 VOID\r
 606 odm_S0S1_SWAntDiv_Init_8821A(\r
 607         IN              PDM_ODM_T               pDM_Odm\r
 608 )\r
 609 {\r
 610         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 611         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 612 \r
 613 \r
 614 \r
 615 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 616 \r
 617         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 618         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 619 #else\r
 620         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 621 #endif\r
 622 \r
 623         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));\r
 624 \r
 625         //Output Pin Settings\r
 626         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 627 \r
 628         ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control\r
 629         ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control\r
 630 \r
 631         ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);\r
 632         ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);\r
 633         \r
 634         ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin\r
 635         ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control\r
 636         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]\r
 637         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]\r
 638         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse\r
 639         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse\r
 640 \r
 641         //Mapping Table\r
 642         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 643         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 644 \r
 645         //Set ANT1_8821A as MAIN_ANT\r
 646         if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
 647                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 648         else\r
 649                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 650 \r
 651         //OFDM HW AntDiv Parameters\r
 652         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 653         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
 654                 \r
 655         //CCK HW AntDiv Parameters\r
 656         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 657         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 658 \r
 659         ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 660 \r
 661         //BT Coexistence\r
 662         ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1\r
 663         ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 664 \r
 665         //Timming issue\r
 666         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 667         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 668 \r
 669         //response TX ant by RX ant\r
 670         ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
 671         \r
 672         //2 [--For HW Bug Setting]\r
 673         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 674                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 675 \r
 676                 \r
 677         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
 678         \r
 679         pDM_SWAT_Table->try_flag = 0xff;        \r
 680         pDM_SWAT_Table->Double_chk_flag = 0;\r
 681         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
 682         pDM_SWAT_Table->CurAntenna = MAIN_ANT;\r
 683         pDM_SWAT_Table->PreAntenna = MAIN_ANT;\r
 684         pDM_SWAT_Table->SWAS_NoLink_State = 0;\r
 685 \r
 686 }\r
 687 #endif //#if (RTL8821A_SUPPORT == 1)\r
 688 \r
 689 #if (RTL8881A_SUPPORT == 1)\r
 690 VOID\r
 691 odm_RX_HWAntDiv_Init_8881A(\r
 692         IN              PDM_ODM_T               pDM_Odm\r
 693 )\r
 694 {\r
 695         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CGCS_RX_HW_ANTDIV] \n"));\r
 696 \r
 697 }\r
 698 \r
 699 VOID\r
 700 odm_TRX_HWAntDiv_Init_8881A(\r
 701         IN              PDM_ODM_T               pDM_Odm\r
 702 )\r
 703 {\r
 704 \r
 705         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
 706 \r
 707         //Output Pin Settings\r
 708         // [SPDT related]\r
 709         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 710         ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0);\r
 711         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer\r
 712         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); \r
 713         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1);\r
 714         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0]\r
 715         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0]        \r
 716         \r
 717         //Mapping Table\r
 718         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 719         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 720 \r
 721         //OFDM HW AntDiv Parameters\r
 722         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 723         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias\r
 724         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 725         \r
 726         //CCK HW AntDiv Parameters\r
 727         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 728         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 729 \r
 730         //Timming issue\r
 731         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 732 \r
 733         //2 [--For HW Bug Setting]\r
 734 \r
 735         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant  by Reg //  A-cut bug\r
 736 }\r
 737 \r
 738 #endif //#if (RTL8881A_SUPPORT == 1)\r
 739 \r
 740 \r
 741 #if (RTL8812A_SUPPORT == 1)\r
 742 VOID\r
 743 odm_TRX_HWAntDiv_Init_8812A(\r
 744         IN              PDM_ODM_T               pDM_Odm\r
 745 )\r
 746 {\r
 747          ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
 748 \r
 749         //3 //3 --RFE pin setting---------\r
 750         //[BB]\r
 751         ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0);      //disable SW switch\r
 752         ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0);         \r
 753         ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3);     // in/out\r
 754         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer\r
 755         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); \r
 756         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1);\r
 757         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0]\r
 758         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0]\r
 759         //3 -------------------------\r
 760 \r
 761         //Mapping Table\r
 762         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 763         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 764 \r
 765         //OFDM HW AntDiv Parameters\r
 766         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 767         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias\r
 768         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 769         \r
 770         //CCK HW AntDiv Parameters\r
 771         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 772         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 773 \r
 774         //Timming issue\r
 775         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 776 \r
 777         //2 [--For HW Bug Setting]\r
 778 \r
 779         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant  by Reg //  A-cut bug\r
 780         \r
 781 }\r
 782 \r
 783 #endif //#if (RTL8812A_SUPPORT == 1)\r
 784 \r
 785 VOID\r
 786 odm_HW_AntDiv(\r
 787         IN              PDM_ODM_T               pDM_Odm\r
 788 )\r
 789 {\r
 790         u4Byte  i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI;\r
 791         u4Byte  Main_RSSI, Aux_RSSI, pkt_ratio_m=0, pkt_ratio_a=0,pkt_threshold=10;\r
 792         u1Byte  RxIdleAnt=0, TargetAnt=7;\r
 793         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 794         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;\r
 795         PSTA_INFO_T     pEntry;\r
 796 \r
 797         if(!pDM_Odm->bLinked) //bLinked==False\r
 798         {\r
 799                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
 800         \r
 801                 #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 802                         if (pDM_Odm->antdiv_rssi)\r
 803                                 panic_printk("[No Link!!!]\n");\r
 804                 #endif\r
 805         \r
 806                 if(pDM_FatTable->bBecomeLinked == TRUE)\r
 807                 {\r
 808                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 809                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 810 \r
 811                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 812                 }\r
 813                 return;\r
 814         }       \r
 815         else\r
 816         {\r
 817                 if(pDM_FatTable->bBecomeLinked ==FALSE)\r
 818                 {\r
 819                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));\r
 820                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
 821                         if(pDM_Odm->SupportICType == ODM_RTL8821 )\r
 822                                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
 823                                 \r
 824                         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 825                         else if(pDM_Odm->SupportICType == ODM_RTL8881 )\r
 826                                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
 827                         #endif\r
 828                         \r
 829                         else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812)\r
 830                                 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable\r
 831                         \r
 832                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 833 \r
 834                         if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
 835                         {\r
 836                                 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]   // for 8723B AntDiv function patch.  BB  Dino  130412   \r
 837                                 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]\r
 838                         }\r
 839                 }       \r
 840         }       \r
 841 \r
 842         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[HW AntDiv] Start =>\n"));\r
 843            \r
 844         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
 845         {\r
 846                 pEntry = pDM_Odm->pODM_StaInfo[i];\r
 847                 if(IS_STA_VALID(pEntry))\r
 848                 {\r
 849                         //2 Caculate RSSI per Antenna\r
 850                         Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
 851                         Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
 852                         TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
 853                         /*\r
 854                         if( pDM_FatTable->MainAnt_Cnt[i]!=0 && pDM_FatTable->AuxAnt_Cnt[i]!=0 )\r
 855                         {\r
 856                         pkt_ratio_m=( pDM_FatTable->MainAnt_Cnt[i] / pDM_FatTable->AuxAnt_Cnt[i] );\r
 857                         pkt_ratio_a=( pDM_FatTable->AuxAnt_Cnt[i] / pDM_FatTable->MainAnt_Cnt[i] );\r
 858                                 \r
 859                                 if (pkt_ratio_m >= pkt_threshold)\r
 860                                         TargetAnt=MAIN_ANT;\r
 861                                 \r
 862                                 else if(pkt_ratio_a >= pkt_threshold)\r
 863                                         TargetAnt=AUX_ANT;\r
 864                         }\r
 865                         */                      \r
 866                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%u] \n",pDM_Odm->SupportICType));\r
 867                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Main_Cnt = (( %u ))  , Main_RSSI= ((  %u )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
 868                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Aux_Cnt   = (( %u ))  , Aux_RSSI = ((  %u )) \n", pDM_FatTable->AuxAnt_Cnt[i]  , Aux_RSSI ));\r
 869                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %u ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 870 \r
 871                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
 872                                                                                                               ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0)));\r
 873                         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 874                         if (pDM_Odm->antdiv_rssi)\r
 875                         {\r
 876                                 panic_printk("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType);\r
 877                                 //panic_printk("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
 878                                 //      ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0));\r
 879                                 //panic_printk("*** Phy_AntSel_B=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT2)>>2,\r
 880                                 //      ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT0))\r
 881                                 panic_printk("*** Client[ %lu ] , Main_Cnt = (( %lu ))  , Main_RSSI= ((  %lu )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI);\r
 882                                 panic_printk("*** Client[ %lu ] , Aux_Cnt   = (( %lu ))  , Aux_RSSI = ((  %lu )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI);\r
 883                         }\r
 884                         #endif\r
 885 \r
 886 \r
 887                         LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;\r
 888                         //2 Select MaxRSSI for DIG\r
 889                         if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))\r
 890                                 AntDivMaxRSSI = LocalMaxRSSI;\r
 891                         if(LocalMaxRSSI > MaxRSSI)\r
 892                                 MaxRSSI = LocalMaxRSSI;\r
 893 \r
 894                         //2 Select RX Idle Antenna\r
 895                         if ( (LocalMaxRSSI != 0) &&  (LocalMaxRSSI < MinMaxRSSI) )\r
 896                         {\r
 897                                 RxIdleAnt = TargetAnt;\r
 898                                 MinMaxRSSI = LocalMaxRSSI;\r
 899                         }\r
 900                         /*\r
 901                         if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))\r
 902                                 Main_RSSI = Aux_RSSI;\r
 903                         else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))\r
 904                                 Aux_RSSI = Main_RSSI;\r
 905                 \r
 906                         LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;\r
 907                         if(LocalMinRSSI < MinRSSI)\r
 908                         {\r
 909                                 MinRSSI = LocalMinRSSI;\r
 910                                 RxIdleAnt = TargetAnt;\r
 911                         }       \r
 912                         */\r
 913                         //2 Select TX Antenna\r
 914 \r
 915                         #if TX_BY_REG\r
 916                         \r
 917                         #else\r
 918                                 if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
 919                                         odm_UpdateTxAnt(pDM_Odm, TargetAnt, i);\r
 920                         #endif\r
 921 \r
 922                 }\r
 923                 pDM_FatTable->MainAnt_Sum[i] = 0;\r
 924                 pDM_FatTable->AuxAnt_Sum[i] = 0;\r
 925                 pDM_FatTable->MainAnt_Cnt[i] = 0;\r
 926                 pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
 927         }\r
 928        \r
 929         //2 Set RX Idle Antenna\r
 930         ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
 931 \r
 932         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 933                 if (pDM_Odm->antdiv_rssi)\r
 934                         panic_printk("*** RxIdleAnt = (( %s )) \n \n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
 935         #endif\r
 936         \r
 937         pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;\r
 938         pDM_DigTable->RSSI_max = MaxRSSI;\r
 939 }\r
 940 \r
 941 \r
 942 \r
 943 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
 944 VOID\r
 945 odm_S0S1_SwAntDiv(\r
 946         IN              PDM_ODM_T               pDM_Odm,\r
 947         IN              u1Byte                  Step\r
 948         )\r
 949 {\r
 950         u4Byte                  i,MinMaxRSSI=0xFF, LocalMaxRSSI,LocalMinRSSI;\r
 951         u4Byte                  Main_RSSI, Aux_RSSI;\r
 952         u1Byte                  reset_period=10, SWAntDiv_threshold=35;\r
 953         u1Byte                  HighTraffic_TrainTime_U=0x32,HighTraffic_TrainTime_L,Train_time_temp;\r
 954         u1Byte                  LowTraffic_TrainTime_U=200,LowTraffic_TrainTime_L;\r
 955         u1Byte                  RxIdleAnt, TargetAnt, nextAnt;\r
 956         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 957         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;   \r
 958         PSTA_INFO_T             pEntry=NULL;\r
 959         //static u1Byte         reset_idx;\r
 960         u4Byte                  value32;\r
 961         PADAPTER                Adapter  =  pDM_Odm->Adapter;\r
 962         u8Byte                  curTxOkCnt=0, curRxOkCnt=0,TxCntOffset, RxCntOffset;\r
 963         \r
 964         if(!pDM_Odm->bLinked) //bLinked==False\r
 965         {\r
 966                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
 967                 if(pDM_FatTable->bBecomeLinked == TRUE)\r
 968                 {\r
 969                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0 \n"));\r
 970                         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
 971                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); \r
 972                         \r
 973                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 974                 }\r
 975                 return;\r
 976         }\r
 977         else\r
 978         {\r
 979                 if(pDM_FatTable->bBecomeLinked ==FALSE)\r
 980                 {\r
 981                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));\r
 982                         \r
 983                         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
 984                         {\r
 985                                 value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3);\r
 986                                 \r
 987                                 if (value32==0x0)\r
 988                                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 989                                 else if (value32==0x1)\r
 990                                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 991                                 \r
 992                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);\r
 993                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[6]=0x1 , Set REG 864[5:3]=0x%x \n",value32 ));\r
 994                         }\r
 995 \r
 996                         pDM_SWAT_Table->lastTxOkCnt = 0; \r
 997                         pDM_SWAT_Table->lastRxOkCnt =0; \r
 998                         TxCntOffset = Adapter->TxStats.NumTxBytesUnicast;\r
 999                         RxCntOffset = Adapter->RxStats.NumRxBytesUnicast;\r
1000                         \r
1001                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
1002                 }\r
1003                 else\r
1004                 {\r
1005                         TxCntOffset = 0;\r
1006                         RxCntOffset = 0;\r
1007                 }\r
1008         }\r
1009         \r
1010         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n",\r
1011                 __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag));\r
1012 \r
1013         // Handling step mismatch condition.\r
1014         // Peak step is not finished at last time. Recover the variable and check again.\r
1015         if(     Step != pDM_SWAT_Table->try_flag        )\r
1016         {\r
1017                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag]    Need to Reset After Link\n"));\r
1018                 ODM_SwAntDivRestAfterLink(pDM_Odm);\r
1019         }\r
1020 \r
1021         if(pDM_SWAT_Table->try_flag == 0xff) \r
1022         {       \r
1023                 pDM_SWAT_Table->try_flag = 0;\r
1024                 pDM_SWAT_Table->Train_time_flag=0;\r
1025                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag = 0]  Prepare for peak!\n\n"));\r
1026                 return;\r
1027         }       \r
1028         else//if( try_flag != 0xff ) \r
1029         {\r
1030                 //1 Normal State (Begin Trying)\r
1031                 if(pDM_SWAT_Table->try_flag == 0) \r
1032                 {\r
1033                 \r
1034                         //---trafic decision---\r
1035                         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt - TxCntOffset;\r
1036                         curRxOkCnt =Adapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt - RxCntOffset;\r
1037                         pDM_SWAT_Table->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;\r
1038                         pDM_SWAT_Table->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;\r
1039                         \r
1040                         if (curTxOkCnt > 1875000 || curRxOkCnt > 1875000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)  ( 1.875M * 8bit ) / 2= 7.5M bits /sec )\r
1041                         {\r
1042                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;\r
1043                                 Train_time_temp=pDM_SWAT_Table->Train_time ;\r
1044                                 \r
1045                                 if(pDM_SWAT_Table->Train_time_flag==3)\r
1046                                 {\r
1047                                         HighTraffic_TrainTime_L=0xa;\r
1048                                         \r
1049                                         if(Train_time_temp<=16)\r
1050                                                 Train_time_temp=HighTraffic_TrainTime_L;\r
1051                                         else\r
1052                                                 Train_time_temp-=16;\r
1053                                         \r
1054                                 }                               \r
1055                                 else if(pDM_SWAT_Table->Train_time_flag==2)\r
1056                                 {\r
1057                                         Train_time_temp-=8;\r
1058                                         HighTraffic_TrainTime_L=0xf;\r
1059                                 }       \r
1060                                 else if(pDM_SWAT_Table->Train_time_flag==1)\r
1061                                 {\r
1062                                         Train_time_temp-=4;\r
1063                                         HighTraffic_TrainTime_L=0x1e;\r
1064                                 }\r
1065                                 else if(pDM_SWAT_Table->Train_time_flag==0)\r
1066                                 {\r
1067                                         Train_time_temp+=8;\r
1068                                         HighTraffic_TrainTime_L=0x28;\r
1069                                 }\r
1070 \r
1071                                 \r
1072                                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp));\r
1073 \r
1074                                 //--\r
1075                                 if(Train_time_temp > HighTraffic_TrainTime_U)\r
1076                                         Train_time_temp=HighTraffic_TrainTime_U;\r
1077                                 \r
1078                                 else if(Train_time_temp < HighTraffic_TrainTime_L)\r
1079                                         Train_time_temp=HighTraffic_TrainTime_L;\r
1080 \r
1081                                 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~10ms\r
1082                                 \r
1083                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("  Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));\r
1084                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [HIGH Traffic]  \n" ));\r
1085                         }\r
1086                         else if (curTxOkCnt > 125000 || curRxOkCnt > 125000) // ( 0.125M * 8bit ) / 2 =  0.5M bits /sec )\r
1087                         {\r
1088                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
1089                                 Train_time_temp=pDM_SWAT_Table->Train_time ;\r
1090 \r
1091                                 if(pDM_SWAT_Table->Train_time_flag==3)\r
1092                                 {\r
1093                                         LowTraffic_TrainTime_L=10;\r
1094                                         if(Train_time_temp<50)\r
1095                                                 Train_time_temp=LowTraffic_TrainTime_L;\r
1096                                         else\r
1097                                                 Train_time_temp-=50;\r
1098                                 }                               \r
1099                                 else if(pDM_SWAT_Table->Train_time_flag==2)\r
1100                                 {\r
1101                                         Train_time_temp-=30;\r
1102                                         LowTraffic_TrainTime_L=36;\r
1103                                 }       \r
1104                                 else if(pDM_SWAT_Table->Train_time_flag==1)\r
1105                                 {\r
1106                                         Train_time_temp-=10;\r
1107                                         LowTraffic_TrainTime_L=40;\r
1108                                 }\r
1109                                 else\r
1110                                         Train_time_temp+=10;    \r
1111 \r
1112                                 //--\r
1113                                 if(Train_time_temp >= LowTraffic_TrainTime_U)\r
1114                                         Train_time_temp=LowTraffic_TrainTime_U;\r
1115                                 \r
1116                                 else if(Train_time_temp <= LowTraffic_TrainTime_L)\r
1117                                         Train_time_temp=LowTraffic_TrainTime_L;\r
1118 \r
1119                                 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~20ms\r
1120 \r
1121                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("  Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));\r
1122                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [Low Traffic]  \n" ));\r
1123                         }\r
1124                         else\r
1125                         {\r
1126                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_UltraLOW;\r
1127                                 pDM_SWAT_Table->Train_time = 0xc8; //200ms\r
1128                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [Ultra-Low Traffic]  \n" ));\r
1129                         }\r
1130                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )) \n", \r
1131                                 curTxOkCnt ,curRxOkCnt ));\r
1132                                 \r
1133                         //-----------------\r
1134                 \r
1135                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Current MinMaxRSSI is ((%d)) \n",pDM_FatTable->MinMaxRSSI));\r
1136 \r
1137                         //---reset index---\r
1138                         if(pDM_SWAT_Table->reset_idx>=reset_period)\r
1139                         {\r
1140                                 pDM_FatTable->MinMaxRSSI=0; //\r
1141                                 pDM_SWAT_Table->reset_idx=0;\r
1142                         }\r
1143                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d )) \n",pDM_SWAT_Table->reset_idx ));\r
1144                         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("reset_idx=%d\n",pDM_SWAT_Table->reset_idx));\r
1145                         pDM_SWAT_Table->reset_idx++;\r
1146 \r
1147                         //---double check flag---\r
1148                         if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold && pDM_SWAT_Table->Double_chk_flag== 0)\r
1149                         {                       \r
1150                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" MinMaxRSSI is ((%d)), and > %d \n",\r
1151                                         pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1152 \r
1153                                 pDM_SWAT_Table->Double_chk_flag =1;\r
1154                                 pDM_SWAT_Table->try_flag = 1; \r
1155                                 pDM_SWAT_Table->RSSI_Trying = 0;\r
1156 \r
1157                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test the current Ant for (( %d )) ms again \n", pDM_SWAT_Table->Train_time));\r
1158                                 ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt);  \r
1159                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms    \r
1160                                 return;\r
1161                         }\r
1162                         \r
1163                         nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT;\r
1164 \r
1165                         pDM_SWAT_Table->try_flag = 1;\r
1166                         \r
1167                         if(pDM_SWAT_Table->reset_idx<=1)\r
1168                                 pDM_SWAT_Table->RSSI_Trying = 2;\r
1169                         else\r
1170                                 pDM_SWAT_Table->RSSI_Trying = 1;\r
1171                         \r
1172                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=1]  Normal State:  Begin Trying!! \n"));\r
1173                                                                         \r
1174                 }\r
1175         \r
1176                 else if(pDM_SWAT_Table->try_flag == 1 && pDM_SWAT_Table->Double_chk_flag== 0)\r
1177                 {       \r
1178                         nextAnt = (pDM_FatTable->RxIdleAnt  == MAIN_ANT)? AUX_ANT : MAIN_ANT;           \r
1179                         pDM_SWAT_Table->RSSI_Trying--;\r
1180                 }\r
1181                 \r
1182                 //1 Decision State\r
1183                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0) )\r
1184                 {\r
1185                         \r
1186                         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
1187                         {\r
1188                                 pEntry = pDM_Odm->pODM_StaInfo[i];\r
1189                                 if(IS_STA_VALID(pEntry))\r
1190                                 {\r
1191                                         //2 Caculate RSSI per Antenna\r
1192                                         Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
1193                                         Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
1194                                         \r
1195                                         if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1)\r
1196                                                 Main_RSSI=0;    \r
1197                                         \r
1198                                         if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1)\r
1199                                                 Aux_RSSI=0;\r
1200 \r
1201                                         TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
1202                                         LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI;\r
1203                                         LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI;\r
1204                                         \r
1205                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux));\r
1206                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux));\r
1207                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Main_Cnt = (( %d ))  , Main_RSSI= ((  %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
1208                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Aux_Cnt   = (( %d ))  , Aux_RSSI = ((  %d )) \n", pDM_FatTable->AuxAnt_Cnt[i]  , Aux_RSSI ));\r
1209                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
1210                                         \r
1211                                         //2 Select RX Idle Antenna\r
1212                                         \r
1213                                         if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI)\r
1214                                         {\r
1215                                                         RxIdleAnt = TargetAnt;\r
1216                                                         MinMaxRSSI = LocalMaxRSSI;\r
1217                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI)));\r
1218                                         \r
1219                                                         if((LocalMaxRSSI-LocalMinRSSI)>8)\r
1220                                                         {\r
1221                                                                 if(LocalMinRSSI != 0)\r
1222                                                                         pDM_SWAT_Table->Train_time_flag=3;\r
1223                                                                 else\r
1224                                                                 {\r
1225                                                                         if(MinMaxRSSI > SWAntDiv_threshold)\r
1226                                                                                 pDM_SWAT_Table->Train_time_flag=0;\r
1227                                                                         else\r
1228                                                                                 pDM_SWAT_Table->Train_time_flag=3;\r
1229                                                                 }\r
1230                                                         }\r
1231                                                         else if((LocalMaxRSSI-LocalMinRSSI)>5)\r
1232                                                                 pDM_SWAT_Table->Train_time_flag=2;\r
1233                                                         else if((LocalMaxRSSI-LocalMinRSSI)>2)\r
1234                                                                 pDM_SWAT_Table->Train_time_flag=1;\r
1235                                                         else\r
1236                                                                 pDM_SWAT_Table->Train_time_flag=0;\r
1237                                                         \r
1238                                         }\r
1239                                         \r
1240                                         //2 Select TX Antenna\r
1241                                         if(TargetAnt == MAIN_ANT)\r
1242                                                 pDM_FatTable->antsel_a[i] = ANT1_2G;\r
1243                                         else\r
1244                                                 pDM_FatTable->antsel_a[i] = ANT2_2G;\r
1245                         \r
1246                                 }\r
1247                                         pDM_FatTable->MainAnt_Sum[i] = 0;\r
1248                                         pDM_FatTable->AuxAnt_Sum[i] = 0;\r
1249                                         pDM_FatTable->MainAnt_Cnt[i] = 0;\r
1250                                         pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
1251                                         pDM_FatTable->CCK_counter_main=0;\r
1252                                         pDM_FatTable->CCK_counter_aux=0;\r
1253                                         pDM_FatTable->OFDM_counter_main=0;\r
1254                                         pDM_FatTable->OFDM_counter_aux=0;\r
1255 \r
1256                         }\r
1257                 \r
1258                         \r
1259                         pDM_FatTable->MinMaxRSSI=MinMaxRSSI;\r
1260                         pDM_SWAT_Table->try_flag = 0;\r
1261                                                 \r
1262                         if( pDM_SWAT_Table->Double_chk_flag==1)\r
1263                         {\r
1264                                 pDM_SWAT_Table->Double_chk_flag=0;\r
1265                                 if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold)\r
1266                                 {\r
1267                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) > %d again!! \n",\r
1268                                                 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1269                                         \r
1270                                         ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);        \r
1271                                         \r
1272                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));\r
1273                                         return;\r
1274                                 }\r
1275                                 else\r
1276                                 {\r
1277                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) <= %d !! \n",\r
1278                                                 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1279 \r
1280                                         nextAnt = (pDM_FatTable->RxIdleAnt  == MAIN_ANT)? AUX_ANT : MAIN_ANT;\r
1281                                         pDM_SWAT_Table->try_flag = 0; \r
1282                                         pDM_SWAT_Table->reset_idx=reset_period;\r
1283                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=0]  Normal State:  Need to tryg again!! \n\n\n"));\r
1284                                         return;\r
1285                                 }\r
1286                         }\r
1287                         else\r
1288                         {\r
1289                                 pDM_SWAT_Table->PreAntenna =RxIdleAnt;\r
1290                                 ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt );\r
1291                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));\r
1292                                 return;\r
1293                         }\r
1294                         \r
1295                 }\r
1296 \r
1297         }\r
1298 \r
1299         //1 4.Change TRX antenna\r
1300 \r
1301         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )),    Ant: (( %s )) >>> (( %s )) \n",\r
1302                 pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt  == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX")));\r
1303                 \r
1304         ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt);\r
1305 \r
1306         //1 5.Reset Statistics\r
1307 \r
1308         pDM_FatTable->RxIdleAnt  = nextAnt;\r
1309 \r
1310         //1 6.Set next timer   (Trying State)\r
1311         \r
1312         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms \n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time));\r
1313         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms\r
1314 }\r
1315 \r
1316 \r
1317 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1318 VOID\r
1319 ODM_SW_AntDiv_Callback(\r
1320         PRT_TIMER               pTimer\r
1321 )\r
1322 {\r
1323         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;\r
1324         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1325         pSWAT_T                 pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;\r
1326 \r
1327         #if DEV_BUS_TYPE==RT_PCI_INTERFACE\r
1328                 #if USE_WORKITEM\r
1329                         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);\r
1330                 #else\r
1331                         {\r
1332                         //DbgPrint("SW_antdiv_Callback");\r
1333                         odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);\r
1334                         }\r
1335                 #endif\r
1336         #else\r
1337         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);\r
1338         #endif\r
1339 }\r
1340 VOID\r
1341 ODM_SW_AntDiv_WorkitemCallback(\r
1342     IN PVOID            pContext\r
1343     )\r
1344 {\r
1345         PADAPTER                pAdapter = (PADAPTER)pContext;\r
1346         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1347         \r
1348         //DbgPrint("SW_antdiv_Workitem_Callback");\r
1349         odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);\r
1350 }\r
1351 #endif  //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1352 \r
1353 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1354 VOID\r
1355 ODM_SW_AntDiv_Callback(void *FunctionContext)\r
1356 {\r
1357         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;\r
1358         PADAPTER        padapter = pDM_Odm->Adapter;\r
1359         if(padapter->net_closed == _TRUE)\r
1360             return;\r
1361         //odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE);      \r
1362 }\r
1363 #endif  //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1364 \r
1365 #endif //#if (RTL8723B_SUPPORT == 1)\r
1366 \r
1367 \r
1368 #if(RTL8188E_SUPPORT == 1  || RTL8192E_SUPPORT == 1)\r
1369 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
1370 VOID\r
1371 odm_SetNextMACAddrTarget(\r
1372         IN              PDM_ODM_T               pDM_Odm\r
1373 )\r
1374 {\r
1375         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1376         PSTA_INFO_T     pEntry;\r
1377         //u1Byte        Bssid[6];\r
1378         u4Byte  value32, i;\r
1379 \r
1380         //\r
1381         //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn\r
1382         //\r
1383         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n"));\r
1384         if(pDM_Odm->bLinked)\r
1385         {\r
1386                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
1387                 {\r
1388                         if((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM)\r
1389                                 pDM_FatTable->TrainIdx = 0;\r
1390                         else\r
1391                                 pDM_FatTable->TrainIdx++;\r
1392                         \r
1393                         pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1394                         if(IS_STA_VALID(pEntry))\r
1395                         {\r
1396                                 //Match MAC ADDR\r
1397 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1398                                 value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4];\r
1399 #else\r
1400                                 value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4];\r
1401 #endif\r
1402                                 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);\r
1403 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1404                                 value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0];\r
1405 #else\r
1406                                 value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0];\r
1407 #endif\r
1408                                 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);\r
1409 \r
1410                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%lu\n",pDM_FatTable->TrainIdx));\r
1411 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1412                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",\r
1413                                         pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0]));\r
1414 #else\r
1415                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",\r
1416                                         pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0]));\r
1417 #endif\r
1418 \r
1419                                 break;\r
1420                         }\r
1421                 }\r
1422                 \r
1423         }\r
1424 \r
1425 #if 0\r
1426         //\r
1427         //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn\r
1428         //\r
1429         #if( DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1430         {               \r
1431                 PADAPTER        Adapter =  pDM_Odm->Adapter;\r
1432                 PMGNT_INFO      pMgntInfo = &Adapter->MgntInfo;\r
1433 \r
1434                 for (i=0; i<6; i++)\r
1435                 {\r
1436                         Bssid[i] = pMgntInfo->Bssid[i];\r
1437                         //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);\r
1438                 }\r
1439         }\r
1440         #endif\r
1441 \r
1442         //odm_SetNextMACAddrTarget(pDM_Odm);\r
1443         \r
1444         //1 Select MAC Address Filter\r
1445         for (i=0; i<6; i++)\r
1446         {\r
1447                 if(Bssid[i] != pDM_FatTable->Bssid[i])\r
1448                 {\r
1449                         bMatchBSSID = FALSE;\r
1450                         break;\r
1451                 }\r
1452         }\r
1453         if(bMatchBSSID == FALSE)\r
1454         {\r
1455                 //Match MAC ADDR\r
1456                 value32 = (Bssid[5]<<8)|Bssid[4];\r
1457                 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);\r
1458                 value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];\r
1459                 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);\r
1460         }\r
1461 \r
1462         return bMatchBSSID;\r
1463 #endif\r
1464                                 \r
1465 }\r
1466 \r
1467 VOID\r
1468 odm_FastAntTraining(\r
1469         IN              PDM_ODM_T               pDM_Odm\r
1470 )\r
1471 {\r
1472         u4Byte  i, MaxRSSI=0;\r
1473         u1Byte  TargetAnt=2;\r
1474         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1475         BOOLEAN bPktFilterMacth = FALSE;\r
1476 \r
1477         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));\r
1478 \r
1479         //1 TRAINING STATE\r
1480         if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)\r
1481         {\r
1482                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));\r
1483                 //2 Caculate RSSI per Antenna\r
1484                 for (i=0; i<7; i++)\r
1485                 {\r
1486                         if(pDM_FatTable->antRSSIcnt[i] == 0)\r
1487                                 pDM_FatTable->antAveRSSI[i] = 0;\r
1488                         else\r
1489                         {\r
1490                         pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i];\r
1491                                 bPktFilterMacth = TRUE;\r
1492                         }\r
1493                         if(pDM_FatTable->antAveRSSI[i] > MaxRSSI)\r
1494                         {\r
1495                                 MaxRSSI = pDM_FatTable->antAveRSSI[i];\r
1496                                 TargetAnt = (u1Byte) i;\r
1497                         }\r
1498 \r
1499                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%lu] = %lu, pDM_FatTable->antRSSIcnt[%lu] = %lu\n",\r
1500                                 i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));\r
1501                 }\r
1502 \r
1503                 //2 Select TRX Antenna\r
1504                 if(bPktFilterMacth == FALSE)\r
1505                 {\r
1506                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));\r
1507 \r
1508                         ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0);        //RegE08[16]=1'b0               //disable fast training\r
1509                         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);         //RegC50[7]=1'b0                //disable HW AntDiv\r
1510                 }\r
1511                 else\r
1512                 {\r
1513                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%lu\n",TargetAnt,MaxRSSI));\r
1514 \r
1515                         ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0);        //RegE08[16]=1'b0               //disable fast training\r
1516                         //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);               //RegC50[7]=1'b0                //disable HW AntDiv\r
1517                         ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt);       //Default RX is Omni, Optional RX is the best decision by FAT\r
1518                         //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt);  //Default TX\r
1519                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1              //from TX Info\r
1520 \r
1521 #if 0\r
1522                         pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1523 \r
1524                         if(IS_STA_VALID(pEntry))\r
1525                         {\r
1526                                 pEntry->antsel_a = TargetAnt&BIT0;\r
1527                                 pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
1528                                 pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
1529                         }\r
1530 #else\r
1531                         pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;\r
1532                         pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;\r
1533                         pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;\r
1534 #endif\r
1535 \r
1536 \r
1537                         if(TargetAnt == 0)\r
1538                                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);         //RegC50[7]=1'b0                //disable HW AntDiv\r
1539 \r
1540                 }\r
1541 \r
1542                 //2 Reset Counter\r
1543                 for(i=0; i<7; i++)\r
1544                 {\r
1545                         pDM_FatTable->antSumRSSI[i] = 0;\r
1546                         pDM_FatTable->antRSSIcnt[i] = 0;\r
1547                 }\r
1548                 \r
1549                 pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
1550                 return;\r
1551         }\r
1552 \r
1553         //1 NORMAL STATE\r
1554         if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE)\r
1555         {\r
1556                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));\r
1557 \r
1558                 odm_SetNextMACAddrTarget(pDM_Odm);\r
1559 \r
1560 #if 0\r
1561                                 pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1562                                 if(IS_STA_VALID(pEntry))\r
1563                                 {\r
1564                                         pEntry->antsel_a = TargetAnt&BIT0;\r
1565                                         pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
1566                                         pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
1567                                 }\r
1568 #endif\r
1569 \r
1570                 //2 Prepare Training\r
1571                 pDM_FatTable->FAT_State = FAT_TRAINING_STATE;\r
1572                 ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1);        //RegE08[16]=1'b1               //enable fast training\r
1573                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1                //enable HW AntDiv\r
1574                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));\r
1575                 ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms\r
1576                 \r
1577         }\r
1578                 \r
1579 }\r
1580 \r
1581 VOID\r
1582 odm_FastAntTrainingCallback(\r
1583         IN              PDM_ODM_T               pDM_Odm\r
1584 )\r
1585 {\r
1586 \r
1587 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1588         PADAPTER        padapter = pDM_Odm->Adapter;\r
1589         if(padapter->net_closed == _TRUE)\r
1590             return;\r
1591         //if(*pDM_Odm->pbNet_closed == TRUE)\r
1592            // return;\r
1593 #endif\r
1594 \r
1595 #if USE_WORKITEM\r
1596         ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem);\r
1597 #else\r
1598         odm_FastAntTraining(pDM_Odm);\r
1599 #endif\r
1600 }\r
1601 \r
1602 VOID\r
1603 odm_FastAntTrainingWorkItemCallback(\r
1604         IN              PDM_ODM_T               pDM_Odm\r
1605 )\r
1606 {\r
1607         odm_FastAntTraining(pDM_Odm);\r
1608 }\r
1609 #endif\r
1610 \r
1611 #endif\r
1612 \r
1613 \r
1614 VOID\r
1615 ODM_AntDivInit(\r
1616         IN PDM_ODM_T    pDM_Odm \r
1617         )\r
1618 {\r
1619         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1620         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
1621 \r
1622 \r
1623         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
1624         {\r
1625                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]   Not Support Antenna Diversity Function\n"));\r
1626                 return;\r
1627         }\r
1628         //---\r
1629 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
1630         if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)\r
1631         {\r
1632                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"));\r
1633                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))\r
1634                         return;\r
1635         }\r
1636         else    if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)\r
1637         {\r
1638                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"));\r
1639                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))\r
1640                         return;\r
1641         }\r
1642         else    if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
1643         {\r
1644                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"));\r
1645         }\r
1646 \r
1647          pDM_Odm->antdiv_rssi=0;\r
1648 \r
1649 #endif  \r
1650         //---\r
1651         \r
1652         //2 [--General---]\r
1653         pDM_Odm->antdiv_period=0;\r
1654         pDM_Odm->antdiv_select=0;\r
1655         pDM_SWAT_Table->Ant5G = MAIN_ANT;\r
1656         pDM_SWAT_Table->Ant2G = MAIN_ANT;\r
1657         pDM_FatTable->CCK_counter_main=0;\r
1658         pDM_FatTable->CCK_counter_aux=0;\r
1659         pDM_FatTable->OFDM_counter_main=0;\r
1660         pDM_FatTable->OFDM_counter_aux=0;\r
1661         \r
1662         //3 [Set MAIN_ANT as default antenna if Auto-Ant enable]\r
1663         if (pDM_Odm->antdiv_select==1)\r
1664                 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
1665         else if (pDM_Odm->antdiv_select==2)\r
1666                 pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
1667         else if(pDM_Odm->antdiv_select==0)\r
1668                 pDM_Odm->AntType = ODM_AUTO_ANT;\r
1669         \r
1670         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
1671         {\r
1672                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1673                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1674         }\r
1675         else\r
1676         {\r
1677                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1678                 \r
1679                 if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
1680                 {\r
1681                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1682                         return;\r
1683                 }\r
1684                 else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)\r
1685                 {\r
1686                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
1687                         return;\r
1688                 }\r
1689         }\r
1690         //---\r
1691         if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
1692         {\r
1693                 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1694                 {\r
1695                         #if TX_BY_REG\r
1696                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0); //Reg80c[21]=1'b0              //from Reg\r
1697                         #else\r
1698                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
1699                         #endif\r
1700                 }       \r
1701                 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1702                 {\r
1703                         #if TX_BY_REG\r
1704                         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
1705                         #else\r
1706                         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
1707                         #endif\r
1708                 }\r
1709         }\r
1710                 \r
1711         //2 [--88E---]\r
1712         if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
1713         {\r
1714         #if (RTL8188E_SUPPORT == 1)\r
1715                 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1716                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1717                 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;\r
1718 \r
1719                 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)  && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))\r
1720                 {\r
1721                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]  88E Not Supprrt This AntDiv Type\n"));\r
1722                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1723                         return;\r
1724                 }\r
1725                 \r
1726                 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1727                         odm_RX_HWAntDiv_Init_88E(pDM_Odm);\r
1728                 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1729                         odm_TRX_HWAntDiv_Init_88E(pDM_Odm);\r
1730                 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
1731                         odm_Smart_HWAntDiv_Init_88E(pDM_Odm);\r
1732         #endif  \r
1733         }\r
1734         \r
1735         //2 [--92E---]\r
1736         #if (RTL8192E_SUPPORT == 1)\r
1737         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
1738         {       \r
1739                 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1740                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1741                 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;\r
1742 \r
1743                 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)   && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))\r
1744                 {\r
1745                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]  8192E Not Supprrt This AntDiv Type\n"));\r
1746                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1747                         return;\r
1748                 }\r
1749                 \r
1750                 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1751                         odm_RX_HWAntDiv_Init_92E(pDM_Odm);\r
1752                 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1753                         odm_TRX_HWAntDiv_Init_92E(pDM_Odm);\r
1754                 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
1755                         odm_Smart_HWAntDiv_Init_92E(pDM_Odm);\r
1756         \r
1757         }\r
1758         #endif  \r
1759         \r
1760         //2 [--8723B---]\r
1761         #if (RTL8723B_SUPPORT == 1)\r
1762         else if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
1763         {               \r
1764                 //pDM_Odm->AntDivType = S0S1_SW_ANTDIV;\r
1765                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1766 \r
1767                 if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1768                 {\r
1769                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B  Not Supprrt This AntDiv Type\n"));\r
1770                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1771                         return;\r
1772                 }\r
1773                         \r
1774                 if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
1775                         odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm);\r
1776                 else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
1777                         odm_TRX_HWAntDiv_Init_8723B(pDM_Odm);           \r
1778         }\r
1779         #endif\r
1780         \r
1781         //2 [--8811A 8821A---]\r
1782         #if (RTL8821A_SUPPORT == 1)\r
1783         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
1784         {\r
1785                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1786                 pDM_Odm->AntDivType = S0S1_SW_ANTDIV;\r
1787                         \r
1788                 if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV)\r
1789                 {\r
1790                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv Type\n"));\r
1791                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1792                         return;\r
1793                 }\r
1794                 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)       \r
1795                         odm_TRX_HWAntDiv_Init_8821A(pDM_Odm);\r
1796                 else if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
1797                         odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm);\r
1798         }\r
1799         #endif\r
1800         \r
1801         //2 [--8881A---]\r
1802         #if (RTL8881A_SUPPORT == 1)\r
1803         else if(pDM_Odm->SupportICType == ODM_RTL8881A)\r
1804         {\r
1805                         //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1806                         //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1807                         \r
1808                         if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1809                         {\r
1810                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A  Not Supprrt This AntDiv Type\n"));\r
1811                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1812                                 return;\r
1813                         }\r
1814                         if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1815                                 odm_RX_HWAntDiv_Init_8881A(pDM_Odm);\r
1816                         else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1817                                 odm_TRX_HWAntDiv_Init_8881A(pDM_Odm);   \r
1818         }\r
1819         #endif\r
1820         \r
1821         //2 [--8812---]\r
1822         #if (RTL8812A_SUPPORT == 1)\r
1823         else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
1824         {       \r
1825                         //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1826                         \r
1827                         if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1828                         {\r
1829                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A  Not Supprrt This AntDiv Type\n"));\r
1830                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1831                                 return;\r
1832                         }\r
1833                         odm_TRX_HWAntDiv_Init_8812A(pDM_Odm);\r
1834         }\r
1835         #endif\r
1836         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType));\r
1837         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv SupportAbility=[%lu] \n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6));\r
1838         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv Type=[%d] \n",pDM_Odm->AntDivType));\r
1839 \r
1840 }\r
1841 \r
1842 VOID\r
1843 ODM_AntDiv(\r
1844         IN              PDM_ODM_T               pDM_Odm\r
1845 )\r
1846 {       \r
1847         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
1848         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1849 \r
1850 //#if (DM_ODM_SUPPORT_TYPE == ODM_AP)   \r
1851         if(*pDM_Odm->pBandType == ODM_BAND_5G )\r
1852         {\r
1853                 if(pDM_FatTable->idx_AntDiv_counter_5G <  pDM_Odm->antdiv_period )\r
1854                 {\r
1855                         pDM_FatTable->idx_AntDiv_counter_5G++;\r
1856                         return;\r
1857                 }\r
1858                 else\r
1859                         pDM_FatTable->idx_AntDiv_counter_5G=0;\r
1860         }\r
1861         else    if(*pDM_Odm->pBandType == ODM_BAND_2_4G )\r
1862         {\r
1863                 if(pDM_FatTable->idx_AntDiv_counter_2G <  pDM_Odm->antdiv_period )\r
1864                 {\r
1865                         pDM_FatTable->idx_AntDiv_counter_2G++;\r
1866                         return;\r
1867                 }\r
1868                 else\r
1869                         pDM_FatTable->idx_AntDiv_counter_2G=0;\r
1870         }\r
1871 //#endif        \r
1872         //----------\r
1873         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
1874         {\r
1875                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]   Not Support Antenna Diversity Function\n"));\r
1876                 return;\r
1877         }\r
1878 \r
1879         //----------\r
1880 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1881         if(pAdapter->MgntInfo.AntennaTest)\r
1882                 return;\r
1883         \r
1884         {\r
1885         #if (BEAMFORMING_SUPPORT == 1)                  \r
1886                 BEAMFORMING_CAP         BeamformCap = (pAdapter->MgntInfo.BeamformingInfo.BeamformCap);\r
1887 \r
1888                 if( BeamformCap & BEAMFORMEE_CAP ) //  BFmee On  &&   Div On ->  Div Off\r
1889                 {       \r
1890                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ]   BFmee ==1 \n"));\r
1891                         if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)\r
1892                         {\r
1893                                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1894                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1895                                 return;\r
1896                         }\r
1897                 }\r
1898                 else // BFmee Off   &&   Div Off ->  Div On\r
1899         #endif\r
1900                 {\r
1901                         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)  &&  pDM_Odm->bLinked) \r
1902                         {\r
1903                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : ON ]   BFmee ==0 \n"));\r
1904                                 if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) )\r
1905                                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
1906                                 \r
1907                                 pDM_Odm->SupportAbility |= (ODM_BB_ANT_DIV);\r
1908                         }\r
1909                 }\r
1910         }\r
1911 #endif\r
1912 \r
1913         //----------\r
1914 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
1915         if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)\r
1916         {\r
1917                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n"));\r
1918                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))\r
1919                         return;\r
1920         }\r
1921         else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)\r
1922         {\r
1923                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n"));\r
1924                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))\r
1925                 return;\r
1926         }\r
1927         else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
1928         {\r
1929                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n"));\r
1930         }\r
1931 #endif\r
1932 \r
1933         //----------\r
1934 \r
1935         if (pDM_Odm->antdiv_select==1)\r
1936                 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
1937         else if (pDM_Odm->antdiv_select==2)\r
1938                 pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
1939         else  if (pDM_Odm->antdiv_select==0)\r
1940                 pDM_Odm->AntType = ODM_AUTO_ANT;\r
1941 \r
1942         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d ))  \n",pDM_Odm->AntType,pDM_Odm->pre_AntType));\r
1943         \r
1944         if(pDM_Odm->AntType != ODM_AUTO_ANT)\r
1945         {\r
1946                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX"));\r
1947                         \r
1948                 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
1949                 {\r
1950                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1951 \r
1952                         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1953                                 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0);\r
1954                         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1955                                 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
1956                                                 \r
1957                         if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
1958                                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1959                         else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)\r
1960                                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
1961                 }\r
1962                 pDM_Odm->pre_AntType=pDM_Odm->AntType; \r
1963                 return;\r
1964         }\r
1965         else\r
1966         {\r
1967                 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
1968                 {\r
1969                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
1970                          if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1971                                 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
1972                         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1973                                 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
1974                 }\r
1975                 pDM_Odm->pre_AntType=pDM_Odm->AntType;\r
1976         }\r
1977          \r
1978         \r
1979         //3 -----------------------------------------------------------------------------------------------------------\r
1980         //2 [--88E---]\r
1981         if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
1982         {\r
1983                 #if (RTL8188E_SUPPORT == 1)\r
1984                 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
1985                         odm_HW_AntDiv(pDM_Odm);\r
1986                 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
1987                 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
1988                         odm_FastAntTraining(pDM_Odm);   \r
1989                 #endif\r
1990                 #endif\r
1991         }\r
1992         //2 [--92E---]  \r
1993         #if (RTL8192E_SUPPORT == 1)\r
1994         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
1995         {\r
1996                 if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
1997                         odm_HW_AntDiv(pDM_Odm);\r
1998                 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
1999                 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
2000                         odm_FastAntTraining(pDM_Odm);   \r
2001                 #endif\r
2002         }\r
2003         #endif\r
2004 \r
2005         #if (RTL8723B_SUPPORT == 1)     \r
2006         //2 [--8723B---]\r
2007         else if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
2008         {\r
2009                 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
2010                         odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);\r
2011                 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
2012                         odm_HW_AntDiv(pDM_Odm);\r
2013         }\r
2014         #endif\r
2015         \r
2016         //2 [--8821A---]\r
2017         #if (RTL8821A_SUPPORT == 1)\r
2018         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
2019         {\r
2020                 if(pDM_Odm->bBtDisabled)  //BT disabled\r
2021                 {\r
2022                         if(pDM_Odm->AntDivType == S0S1_SW_ANTDIV)\r
2023                         {\r
2024                         pDM_Odm->AntDivType=CG_TRX_HW_ANTDIV;\r
2025                         ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); \r
2026                         }\r
2027                 }       \r
2028                 else //BT enabled\r
2029                 {\r
2030                         if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
2031                         {\r
2032                         pDM_Odm->AntDivType=S0S1_SW_ANTDIV;\r
2033                         ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0); \r
2034                         }       \r
2035                 }       \r
2036         \r
2037                 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
2038                         odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);\r
2039                 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
2040                 odm_HW_AntDiv(pDM_Odm);\r
2041         }\r
2042         #endif\r
2043         //2 [--8881A---]\r
2044         #if (RTL8881A_SUPPORT == 1)\r
2045         else if(pDM_Odm->SupportICType == ODM_RTL8881A)         \r
2046                 odm_HW_AntDiv(pDM_Odm);\r
2047         #endif\r
2048         //2 [--8812A---]\r
2049         #if (RTL8812A_SUPPORT == 1)\r
2050         else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
2051                 odm_HW_AntDiv(pDM_Odm);\r
2052         #endif\r
2053 }\r
2054 \r
2055 \r
2056 VOID\r
2057 odm_AntselStatistics(\r
2058         IN              PDM_ODM_T               pDM_Odm,\r
2059         IN              u1Byte                  antsel_tr_mux,\r
2060         IN              u4Byte                  MacId,\r
2061         IN              u4Byte                  RxPWDBAll\r
2062 )\r
2063 {\r
2064         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2065 \r
2066         if(antsel_tr_mux == ANT1_2G)\r
2067         {\r
2068                 pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;\r
2069                 pDM_FatTable->MainAnt_Cnt[MacId]++;\r
2070         }\r
2071         else\r
2072         {\r
2073                 pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;\r
2074                 pDM_FatTable->AuxAnt_Cnt[MacId]++;\r
2075         }\r
2076 }\r
2077 \r
2078 \r
2079 VOID\r
2080 ODM_Process_RSSIForAntDiv(      \r
2081         IN OUT  PDM_ODM_T                                       pDM_Odm,\r
2082         IN              PODM_PHY_INFO_T                         pPhyInfo,\r
2083         IN              PODM_PACKET_INFO_T                      pPktinfo\r
2084         )\r
2085 {\r
2086 u1Byte                  isCCKrate=0,CCKMaxRate=DESC_RATE11M;\r
2087 pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2088 \r
2089 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))\r
2090         u4Byte                  RxPower_Ant0, RxPower_Ant1;     \r
2091 #else\r
2092         u1Byte                  RxPower_Ant0, RxPower_Ant1;     \r
2093 #endif\r
2094 \r
2095         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
2096                 CCKMaxRate=DESC_RATE11M;\r
2097         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
2098                 CCKMaxRate=DESC_RATE11M;\r
2099         isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE;\r
2100 \r
2101 #if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))\r
2102                 if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D)\r
2103                 {\r
2104                                 if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)\r
2105                                 {\r
2106                                         //if(pPktinfo->bPacketBeacon)\r
2107                                         //{\r
2108                                         //      DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);\r
2109                                         //}\r
2110                                         ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID,  pPhyInfo->RxPWDBAll, isCCKrate);\r
2111                                 }\r
2112                 }\r
2113 #endif\r
2114                 \r
2115         if(  (pDM_Odm->SupportICType == ODM_RTL8192E||pDM_Odm->SupportICType == ODM_RTL8812)   && (pPktinfo->DataRate > CCKMaxRate) )\r
2116         {\r
2117                 RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0];\r
2118                 RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1];\r
2119         }\r
2120         else\r
2121                 RxPower_Ant0=pPhyInfo->RxPWDBAll;\r
2122         \r
2123         if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
2124         {\r
2125                 if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) &&  pPktinfo->bPacketToSelf   && pDM_FatTable->FAT_State == FAT_TRAINING_STATE )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))\r
2126                 {\r
2127                         u1Byte  antsel_tr_mux;\r
2128                         antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;\r
2129                         pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0;\r
2130                         pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;\r
2131                 }\r
2132         }\r
2133         else //AntDivType != CG_TRX_SMART_ANTDIV \r
2134         {\r
2135                 if(  ( pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT ) &&  (pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID)  )\r
2136                 {\r
2137                          if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E)\r
2138                                 odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0);\r
2139                         else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812)\r
2140                         {\r
2141                                 if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV))\r
2142                                 {\r
2143                                         pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G;\r
2144 \r
2145 \r
2146                                                 if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
2147                                                         pDM_FatTable->CCK_counter_main++;\r
2148                                                 else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
2149                                                         pDM_FatTable->CCK_counter_aux++;\r
2150 \r
2151                                         odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
2152                                 }\r
2153                                 else\r
2154                                 {\r
2155 \r
2156                                         if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
2157                                                 pDM_FatTable->OFDM_counter_main++;\r
2158                                         else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
2159                                                 pDM_FatTable->OFDM_counter_aux++;\r
2160                                         odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
2161                         }\r
2162                 }\r
2163         }\r
2164         }\r
2165         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));\r
2166         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));\r
2167 }\r
2168 \r
2169 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
2170 VOID\r
2171 ODM_SetTxAntByTxInfo(\r
2172         IN              PDM_ODM_T               pDM_Odm,\r
2173         IN              pu1Byte                 pDesc,\r
2174         IN              u1Byte                  macId   \r
2175 )\r
2176 {\r
2177         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2178 \r
2179         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
2180                 return;\r
2181 \r
2182         if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
2183                 return;\r
2184 \r
2185 \r
2186         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
2187         {\r
2188 #if (RTL8723B_SUPPORT == 1)\r
2189                 SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]);\r
2190                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2191                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2192 #endif\r
2193         }\r
2194         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
2195         {\r
2196 #if (RTL8821A_SUPPORT == 1)\r
2197                 SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]);\r
2198                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2199                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2200 #endif\r
2201         }\r
2202         else if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
2203         {\r
2204 #if (RTL8188E_SUPPORT == 1)\r
2205                 SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);\r
2206                 SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);\r
2207                 SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);\r
2208                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2209                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2210 #endif\r
2211         }\r
2212         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
2213         {\r
2214 \r
2215         \r
2216         }\r
2217 }\r
2218 #else// (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
2219 \r
2220 VOID\r
2221 ODM_SetTxAntByTxInfo(\r
2222         //IN            PDM_ODM_T               pDM_Odm,\r
2223         struct  rtl8192cd_priv          *priv,\r
2224         struct  tx_desc                 *pdesc,\r
2225         struct  tx_insn                 *txcfg,\r
2226         unsigned short                  aid     \r
2227 )\r
2228 {\r
2229         pFAT_T          pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable;\r
2230         u4Byte          SupportICType=priv->pshare->_dmODM.SupportICType;\r
2231 \r
2232         if(SupportICType == ODM_RTL8881A)\r
2233         {\r
2234                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******   \n",__FUNCTION__,__LINE__);        \r
2235                 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
2236                 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2237         }\r
2238         else if(SupportICType == ODM_RTL8192E)\r
2239         {\r
2240                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******   \n",__FUNCTION__,__LINE__);        \r
2241                 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
2242                 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2243         }\r
2244         else if(SupportICType == ODM_RTL8812)\r
2245         {\r
2246                 //3 [path-A]\r
2247                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******   \n",__FUNCTION__,__LINE__);\r
2248                         \r
2249                 pdesc->Dword6 &= set_desc(~ BIT(16));\r
2250                 pdesc->Dword6 &= set_desc(~ BIT(17));\r
2251                 pdesc->Dword6 &= set_desc(~ BIT(18));\r
2252                 if(txcfg->pstat)\r
2253                 {\r
2254                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2255                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17);\r
2256                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18);\r
2257                 }\r
2258         }\r
2259 }\r
2260 #endif\r
2261 \r
2262 #else\r
2263 \r
2264 VOID ODM_AntDivInit(    IN PDM_ODM_T    pDM_Odm ){}\r
2265 VOID ODM_AntDiv(        IN PDM_ODM_T            pDM_Odm){}\r
2266 \r
2267 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
2268 \r
2269 \r