drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_AntDiv.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 \r
  25 #include "odm_precomp.h"\r
  26 \r
  27 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
  28 VOID\r
  29 odm_AntDiv_on_off( IN PDM_ODM_T pDM_Odm ,IN u1Byte swch)\r
  30 {\r
  31         if(pDM_Odm->AntDivType==S0S1_SW_ANTDIV || pDM_Odm->AntDivType==CGCS_RX_SW_ANTDIV) \r
  32                 return;\r
  33 \r
  34         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
  35         {\r
  36                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
  37                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
  38                 ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
  39         }\r
  40         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
  41         {\r
  42                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
  43                 if(pDM_Odm->SupportICType == ODM_RTL8812)\r
  44                 {\r
  45                         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
  46                         ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
  47                 }\r
  48                 else\r
  49                 {\r
  50                 ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable\r
  51                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); //CCK AntDiv function block enable\r
  52                 }\r
  53          }\r
  54 }\r
  55 \r
  56 VOID\r
  57 ODM_UpdateRxIdleAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)\r
  58 {\r
  59         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
  60         u4Byte  DefaultAnt, OptionalAnt,value32;\r
  61 \r
  62         #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
  63         PADAPTER                pAdapter = pDM_Odm->Adapter;\r
  64         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
  65         #endif\r
  66 \r
  67         if(pDM_FatTable->RxIdleAnt != Ant)\r
  68         {\r
  69                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
  70                 pDM_FatTable->RxIdleAnt = Ant;\r
  71 \r
  72                 if(Ant == MAIN_ANT)\r
  73                 {\r
  74                         DefaultAnt   =  ANT1_2G; \r
  75                         OptionalAnt =  ANT2_2G; \r
  76                 }\r
  77                 else\r
  78                 {\r
  79                         DefaultAnt  =   ANT2_2G;\r
  80                         OptionalAnt =  ANT1_2G;\r
  81                 }\r
  82         \r
  83                 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
  84                 {\r
  85                         if(pDM_Odm->SupportICType==ODM_RTL8192E)\r
  86                         {\r
  87                                 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX\r
  88                                 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX\r
  89                         }\r
  90                         else\r
  91                         {\r
  92                                 ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt);      //Default RX\r
  93                                 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt);     //Optional RX\r
  94 \r
  95                                 if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
  96                                 {\r
  97                                         value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF);\r
  98                                 \r
  99                                         if (value32 !=0x280)\r
 100                                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt);\r
 101 \r
 102                                         rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);\r
 103                                 }\r
 104                                 \r
 105                         }\r
 106                         ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);            //Default TX    \r
 107                 }\r
 108                 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
 109                 {\r
 110                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT21|BIT20|BIT19, DefaultAnt);    //Default RX\r
 111                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX\r
 112                         ODM_SetBBReg(pDM_Odm, 0xC08 , BIT27|BIT26|BIT25, DefaultAnt);    //Default TX\r
 113                 }\r
 114                 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt);    //\14PathA Resp Tx\r
 115         }\r
 116         else// pDM_FatTable->RxIdleAnt == Ant\r
 117         {\r
 118                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ]  RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 119                 pDM_FatTable->RxIdleAnt = Ant;\r
 120         }\r
 121 }\r
 122 \r
 123 \r
 124 VOID\r
 125 odm_UpdateTxAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)\r
 126 {\r
 127         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 128         u1Byte  TxAnt;\r
 129 \r
 130         if(Ant == MAIN_ANT)\r
 131                 TxAnt = ANT1_2G;\r
 132         else\r
 133                 TxAnt = ANT2_2G;\r
 134         \r
 135         pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0;\r
 136         pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1;\r
 137         pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2;\r
 138         #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 139         if (pDM_Odm->antdiv_rssi)\r
 140         {\r
 141                 //panic_printk("[Tx from TxInfo]: MacID:(( %d )),  TxAnt = (( %s ))\n",MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
 142                 //panic_printk("antsel_tr_mux=(( 3'b%d%d%d ))\n",       pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] );\r
 143         }\r
 144         #endif\r
 145         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )),  TxAnt = (( %s ))\n", \r
 146         //                                      MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 147         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",\r
 148                                                         //pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));\r
 149         \r
 150 }\r
 151 \r
 152 \r
 153 \r
 154 #if (RTL8188E_SUPPORT == 1)\r
 155 \r
 156 \r
 157 VOID\r
 158 odm_RX_HWAntDiv_Init_88E(\r
 159         IN              PDM_ODM_T               pDM_Odm\r
 160 )\r
 161 {\r
 162         u4Byte  value32;\r
 163 \r
 164         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 165 \r
 166 #if (MP_DRIVER == 1)\r
 167                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 168                 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
 169                 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);  // 1:CG, 0:CS\r
 170                 return;\r
 171 #else\r
 172         \r
 173         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
 174         \r
 175         //MAC Setting\r
 176         value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);\r
 177         ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 178         //Pin Settings\r
 179         ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0             //antsel antselb by HW\r
 180         ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0);      //Reg864[10]=1'b0       //antsel2 by HW\r
 181         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1);       //Regb2c[22]=1'b0       //disable CS/CG switch\r
 182         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);       //Regb2c[31]=1'b1       //output at CG only\r
 183         //OFDM Settings\r
 184         ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);\r
 185         //CCK Settings\r
 186         ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue\r
 187         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples       \r
 188         \r
 189         ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0102);       //antenna mapping table\r
 190 \r
 191 #endif\r
 192 }\r
 193 \r
 194 VOID\r
 195 odm_TRX_HWAntDiv_Init_88E(\r
 196         IN              PDM_ODM_T               pDM_Odm\r
 197 )\r
 198 {\r
 199         u4Byte  value32;\r
 200         \r
 201 #if (MP_DRIVER == 1)\r
 202                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 203                 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
 204                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX   (0/1)\r
 205                 return;\r
 206 #else\r
 207 \r
 208         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));\r
 209         \r
 210         //MAC Setting\r
 211         value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);\r
 212         ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 213         //Pin Settings\r
 214         ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0             //antsel antselb by HW\r
 215         ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0);      //Reg864[10]=1'b0       //antsel2 by HW\r
 216         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0);       //Regb2c[22]=1'b0       //disable CS/CG switch\r
 217         ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1);       //Regb2c[31]=1'b1       //output at CG only\r
 218         //OFDM Settings\r
 219         ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);\r
 220         //CCK Settings\r
 221         ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue\r
 222         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples\r
 223 \r
 224         //antenna mapping table\r
 225         if(!pDM_Odm->bIsMPChip) //testchip\r
 226         {\r
 227                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1);   //Reg858[10:8]=3'b001\r
 228                 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010\r
 229         }\r
 230         else //MPchip\r
 231                 ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201);   //Reg914=3'b010, Reg915=3'b001\r
 232 #endif\r
 233 }\r
 234 \r
 235 VOID\r
 236 odm_Smart_HWAntDiv_Init_88E(\r
 237         IN              PDM_ODM_T               pDM_Odm\r
 238 )\r
 239 {\r
 240         u4Byte  value32, i;\r
 241         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 242         u4Byte  AntCombination = 2;\r
 243 \r
 244     ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
 245     \r
 246 #if (MP_DRIVER == 1)\r
 247     ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));\r
 248     return;\r
 249 #else\r
 250 \r
 251         for(i=0; i<6; i++)\r
 252         {\r
 253                 pDM_FatTable->Bssid[i] = 0;\r
 254                 pDM_FatTable->antSumRSSI[i] = 0;\r
 255                 pDM_FatTable->antRSSIcnt[i] = 0;\r
 256                 pDM_FatTable->antAveRSSI[i] = 0;\r
 257         }\r
 258         pDM_FatTable->TrainIdx = 0;\r
 259         pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
 260 \r
 261         //MAC Setting\r
 262         value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);\r
 263         ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output\r
 264         value32 = ODM_GetMACReg(pDM_Odm,  0x7B4, bMaskDWord);\r
 265         ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match\r
 266         //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);\r
 267         //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18);        //append MACID in reponse packet\r
 268 \r
 269         //Match MAC ADDR\r
 270         ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);\r
 271         ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);\r
 272         \r
 273         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0            //antsel antselb by HW\r
 274         ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0);        //Reg864[10]=1'b0       //antsel2 by HW\r
 275         ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0);        //Regb2c[22]=1'b0       //disable CS/CG switch\r
 276         ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1);        //Regb2c[31]=1'b1       //output at CG only\r
 277         ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);\r
 278         \r
 279         //antenna mapping table\r
 280         if(AntCombination == 2)\r
 281         {\r
 282                 if(!pDM_Odm->bIsMPChip) //testchip\r
 283                 {\r
 284                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1);      //Reg858[10:8]=3'b001\r
 285                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2);    //Reg858[13:11]=3'b010\r
 286                 }\r
 287                 else //MPchip\r
 288                 {\r
 289                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);\r
 290                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);\r
 291                 }\r
 292         }\r
 293         else if(AntCombination == 7)\r
 294         {\r
 295                 if(!pDM_Odm->bIsMPChip) //testchip\r
 296                 {\r
 297                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0);      //Reg858[10:8]=3'b000\r
 298                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1);    //Reg858[13:11]=3'b001\r
 299                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);\r
 300                         ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2);  //(Reg878[0],Reg858[14:15])=3'b010\r
 301                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011\r
 302                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100\r
 303                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 \r
 304                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 \r
 305                         ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111\r
 306                 }\r
 307                 else //MPchip\r
 308                 {\r
 309                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 310                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);   \r
 311                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);\r
 312                         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);\r
 313                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);\r
 314                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);\r
 315                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);\r
 316                         ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);\r
 317                 }\r
 318         }\r
 319 \r
 320         //Default Ant Setting when no fast training\r
 321         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1              //from TX Info\r
 322         ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0);       //Default RX\r
 323         ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1);       //Optional RX\r
 324         //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1);  //Default TX\r
 325 \r
 326         //Enter Traing state\r
 327         ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1));      //Reg864[2:0]=3'd6      //ant combination=reg864[2:0]+1\r
 328         //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0              //disable HW AntDiv\r
 329         //ODM_SetBBReg(pDM_Odm,  0xe08 , BIT16, 0); //RegE08[16]=1'b0           //disable fast training\r
 330         //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1);      //RegE08[16]=1'b1               //enable fast training\r
 331         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1                //enable HW AntDiv\r
 332 \r
 333         //SW Control\r
 334         //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);\r
 335         //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);\r
 336         //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);\r
 337         //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);\r
 338         //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);\r
 339         //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);\r
 340 \r
 341 #endif\r
 342 }\r
 343 #endif //#if (RTL8188E_SUPPORT == 1)\r
 344 \r
 345 \r
 346 #if (RTL8192E_SUPPORT == 1)\r
 347 VOID\r
 348 odm_RX_HWAntDiv_Init_92E(\r
 349         IN              PDM_ODM_T               pDM_Odm\r
 350 )\r
 351 {\r
 352         \r
 353 #if (MP_DRIVER == 1)\r
 354         //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 355         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 356         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta  Regc50[8]=1'b0  0: control by c50[9]\r
 357         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1);  // 1:CG, 0:CS\r
 358         return;\r
 359 #endif\r
 360 \r
 361          ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init =>  AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
 362         \r
 363          //Pin Settings\r
 364          ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0,    // "antsel" is controled by HWs\r
 365          ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1  //" CS/CG switching" is controled by HWs\r
 366 \r
 367          //Mapping table\r
 368          ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table\r
 369           \r
 370          //OFDM Settings\r
 371          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold\r
 372          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias\r
 373          \r
 374          //CCK Settings\r
 375          ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
 376          ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
 377          ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
 378          ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples      \r
 379 }\r
 380 \r
 381 VOID\r
 382 odm_TRX_HWAntDiv_Init_92E(\r
 383         IN              PDM_ODM_T               pDM_Odm\r
 384 )\r
 385 {\r
 386         \r
 387 #if (MP_DRIVER == 1)\r
 388         //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
 389         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 390         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta  Regc50[8]=1'b0  0: control by c50[9]\r
 391         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1);  // 1:CG, 0:CS\r
 392         return;\r
 393 #endif\r
 394 \r
 395 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 396          pDM_Odm->antdiv_rssi=0;\r
 397 #endif\r
 398 \r
 399          ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV]\n"));\r
 400         \r
 401         //3 --RFE pin setting---------\r
 402         //[MAC]\r
 403         ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1);            //DBG PAD Driving control (GPIO 8)\r
 404         ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0);            //path-A , RFE_CTRL_3 & RFE_CTRL_4\r
 405         //[BB]\r
 406         ODM_SetBBReg(pDM_Odm, 0x944 , BIT4|BIT3, 0x3);     //RFE_buffer\r
 407         ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_   (RFE_CTRL_3)\r
 408         ODM_SetBBReg(pDM_Odm, 0x940 , BIT9|BIT8, 0x0); // r_rfe_path_sel_   (RFE_CTRL_4)\r
 409         ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0);     //RFE_buffer\r
 410         ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0);     //rfe_inv  (RFE_CTRL_3)\r
 411         ODM_SetBBReg(pDM_Odm, 0x92C , BIT4, 1);     //rfe_inv  (RFE_CTRL_4)\r
 412         ODM_SetBBReg(pDM_Odm, 0x930 , 0xFF000, 0x88);           //path-A , RFE_CTRL_3 & 4=> ANTSEL[0]\r
 413         //3 -------------------------\r
 414         \r
 415          //Pin Settings\r
 416         ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0);    //path-A     //disable CS/CG switch\r
 417         ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);    //path-A     //output at CG only\r
 418         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);  //path-A          //antsel antselb by HW\r
 419         ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0);           //path-A     //antsel2 by HW \r
 420  \r
 421         //Mapping table\r
 422          ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table\r
 423           \r
 424          //OFDM Settings\r
 425          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold\r
 426          ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias\r
 427          \r
 428          //CCK Settings\r
 429          ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
 430          ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
 431          ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
 432          ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples \r
 433 \r
 434          //Timming issue\r
 435          ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 436 }\r
 437 \r
 438 VOID\r
 439 odm_Smart_HWAntDiv_Init_92E(\r
 440         IN              PDM_ODM_T               pDM_Odm\r
 441 )\r
 442 {\r
 443     ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init =>  AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
 444 }\r
 445 #endif //#if (RTL8192E_SUPPORT == 1)\r
 446 \r
 447 \r
 448 #if (RTL8723B_SUPPORT == 1)\r
 449 VOID\r
 450 odm_TRX_HWAntDiv_Init_8723B(\r
 451         IN              PDM_ODM_T               pDM_Odm\r
 452 )\r
 453 {\r
 454         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init =>  AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n"));\r
 455       \r
 456         //Mapping Table\r
 457         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 458         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);\r
 459         \r
 460         //OFDM HW AntDiv Parameters\r
 461         ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold\r
 462         ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias\r
 463                 \r
 464         //CCK HW AntDiv Parameters\r
 465         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 466         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 467         \r
 468         //BT Coexistence\r
 469         ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1\r
 470         ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 471 \r
 472         //Output Pin Settings\r
 473         ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); //\r
 474                 \r
 475         ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)\r
 476         ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0);\r
 477                 \r
 478         ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1);\r
 479         ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1);\r
 480         ODM_SetMACReg(pDM_Odm, 0x4C ,  BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin\r
 481                 \r
 482         ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out\r
 483         ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //\r
 484 \r
 485         ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse\r
 486         ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse\r
 487 \r
 488         ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]\r
 489         ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]\r
 490 \r
 491         //Timming issue\r
 492         ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 493 \r
 494         //2 [--For HW Bug Setting]\r
 495         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 496                 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable\r
 497 \r
 498         //ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant  by Reg\r
 499 \r
 500 \r
 501 }\r
 502 \r
 503         \r
 504 \r
 505 VOID\r
 506 odm_S0S1_SWAntDiv_Init_8723B(\r
 507         IN              PDM_ODM_T               pDM_Odm\r
 508 )\r
 509 {\r
 510         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 511         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 512 \r
 513         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));\r
 514 \r
 515         //Mapping Table\r
 516         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
 517         ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);\r
 518         \r
 519         //Output Pin Settings\r
 520         //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); \r
 521         ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); \r
 522 \r
 523         pDM_FatTable->bBecomeLinked  =FALSE;\r
 524         pDM_SWAT_Table->try_flag = 0xff;        \r
 525         pDM_SWAT_Table->Double_chk_flag = 0;\r
 526         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
 527 \r
 528         //Timming issue\r
 529         ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 530         \r
 531         //2 [--For HW Bug Setting]\r
 532         ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant  by Reg\r
 533 \r
 534 }\r
 535 #endif //#if (RTL8723B_SUPPORT == 1)\r
 536 \r
 537 \r
 538 #if (RTL8821A_SUPPORT == 1)\r
 539 VOID\r
 540 odm_TRX_HWAntDiv_Init_8821A(\r
 541         IN              PDM_ODM_T               pDM_Odm\r
 542 )\r
 543 {\r
 544         \r
 545 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 546 \r
 547         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 548         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 549 #else\r
 550         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 551 #endif\r
 552         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 553 \r
 554         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));\r
 555 \r
 556         //Output Pin Settings\r
 557         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 558 \r
 559         ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control\r
 560         ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control\r
 561 \r
 562         ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);\r
 563         ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);\r
 564         \r
 565         ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin\r
 566         ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control\r
 567         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]\r
 568         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]\r
 569         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse\r
 570         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse\r
 571 \r
 572         //Mapping Table\r
 573         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 574         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 575 \r
 576         //Set ANT1_8821A as MAIN_ANT\r
 577         if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
 578                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 579         else\r
 580                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 581 \r
 582         //OFDM HW AntDiv Parameters\r
 583         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 584         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
 585                 \r
 586         //CCK HW AntDiv Parameters\r
 587         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 588         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 589 \r
 590         ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 591 \r
 592         //BT Coexistence\r
 593         ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1\r
 594         ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 595 \r
 596         //Timming issue\r
 597         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 598         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 599 \r
 600         //response TX ant by RX ant\r
 601         ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
 602         \r
 603         //2 [--For HW Bug Setting]\r
 604         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 605                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 606                         \r
 607 }\r
 608 \r
 609 VOID\r
 610 odm_S0S1_SWAntDiv_Init_8821A(\r
 611         IN              PDM_ODM_T               pDM_Odm\r
 612 )\r
 613 {\r
 614         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 615         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 616 \r
 617 \r
 618 \r
 619 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 620 \r
 621         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 622         pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));   \r
 623 #else\r
 624         pDM_Odm->AntType = ODM_AUTO_ANT;\r
 625 #endif\r
 626 \r
 627         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));\r
 628 \r
 629         //Output Pin Settings\r
 630         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 631 \r
 632         ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control\r
 633         ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control\r
 634 \r
 635         ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);\r
 636         ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);\r
 637         \r
 638         ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin\r
 639         ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control\r
 640         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]\r
 641         ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]\r
 642         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse\r
 643         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse\r
 644 \r
 645         //Mapping Table\r
 646         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 647         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 648 \r
 649         //Set ANT1_8821A as MAIN_ANT\r
 650         if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
 651                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 652         else\r
 653                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 654 \r
 655         //OFDM HW AntDiv Parameters\r
 656         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 657         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
 658                 \r
 659         //CCK HW AntDiv Parameters\r
 660         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 661         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 662 \r
 663         ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 664 \r
 665         //BT Coexistence\r
 666         ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1\r
 667         ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1\r
 668 \r
 669         //Timming issue\r
 670         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 671         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 672 \r
 673         //response TX ant by RX ant\r
 674         ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
 675         \r
 676         //2 [--For HW Bug Setting]\r
 677         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
 678                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable\r
 679 \r
 680                 \r
 681         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
 682         \r
 683         pDM_SWAT_Table->try_flag = 0xff;        \r
 684         pDM_SWAT_Table->Double_chk_flag = 0;\r
 685         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
 686         pDM_SWAT_Table->CurAntenna = MAIN_ANT;\r
 687         pDM_SWAT_Table->PreAntenna = MAIN_ANT;\r
 688         pDM_SWAT_Table->SWAS_NoLink_State = 0;\r
 689 \r
 690 }\r
 691 #endif //#if (RTL8821A_SUPPORT == 1)\r
 692 \r
 693 #if (RTL8881A_SUPPORT == 1)\r
 694 VOID\r
 695 odm_RX_HWAntDiv_Init_8881A(\r
 696         IN              PDM_ODM_T               pDM_Odm\r
 697 )\r
 698 {\r
 699         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CGCS_RX_HW_ANTDIV] \n"));\r
 700 \r
 701 }\r
 702 \r
 703 VOID\r
 704 odm_TRX_HWAntDiv_Init_8881A(\r
 705         IN              PDM_ODM_T               pDM_Odm\r
 706 )\r
 707 {\r
 708 \r
 709         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
 710 \r
 711         //Output Pin Settings\r
 712         // [SPDT related]\r
 713         ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);\r
 714         ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0);\r
 715         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer\r
 716         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); \r
 717         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1);\r
 718         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0]\r
 719         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0]        \r
 720         \r
 721         //Mapping Table\r
 722         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 723         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 724 \r
 725         //OFDM HW AntDiv Parameters\r
 726         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 727         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias\r
 728         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 729         \r
 730         //CCK HW AntDiv Parameters\r
 731         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 732         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 733 \r
 734         //Timming issue\r
 735         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 736 \r
 737         //2 [--For HW Bug Setting]\r
 738 \r
 739         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant  by Reg //  A-cut bug\r
 740 }\r
 741 \r
 742 #endif //#if (RTL8881A_SUPPORT == 1)\r
 743 \r
 744 \r
 745 #if (RTL8812A_SUPPORT == 1)\r
 746 VOID\r
 747 odm_TRX_HWAntDiv_Init_8812A(\r
 748         IN              PDM_ODM_T               pDM_Odm\r
 749 )\r
 750 {\r
 751          ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
 752 \r
 753         //3 //3 --RFE pin setting---------\r
 754         //[BB]\r
 755         ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0);      //disable SW switch\r
 756         ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0);         \r
 757         ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3);     // in/out\r
 758         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer\r
 759         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); \r
 760         ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1);\r
 761         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0]\r
 762         ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0]\r
 763         //3 -------------------------\r
 764 \r
 765         //Mapping Table\r
 766         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
 767         ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
 768 \r
 769         //OFDM HW AntDiv Parameters\r
 770         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
 771         ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias\r
 772         ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns\r
 773         \r
 774         //CCK HW AntDiv Parameters\r
 775         ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M\r
 776         ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples\r
 777 \r
 778         //Timming issue\r
 779         ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
 780 \r
 781         //2 [--For HW Bug Setting]\r
 782 \r
 783         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant  by Reg //  A-cut bug\r
 784         \r
 785 }\r
 786 \r
 787 #endif //#if (RTL8812A_SUPPORT == 1)\r
 788 \r
 789 VOID\r
 790 odm_HW_AntDiv(\r
 791         IN              PDM_ODM_T               pDM_Odm\r
 792 )\r
 793 {\r
 794         u4Byte  i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI;\r
 795         u4Byte  Main_RSSI, Aux_RSSI, pkt_ratio_m=0, pkt_ratio_a=0,pkt_threshold=10;\r
 796         u1Byte  RxIdleAnt=0, TargetAnt=7;\r
 797         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
 798         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;\r
 799         PSTA_INFO_T     pEntry;\r
 800 \r
 801         if(!pDM_Odm->bLinked) //bLinked==False\r
 802         {\r
 803                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
 804         \r
 805                 #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 806                         if (pDM_Odm->antdiv_rssi)\r
 807                                 panic_printk("[No Link!!!]\n");\r
 808                 #endif\r
 809         \r
 810                 if(pDM_FatTable->bBecomeLinked == TRUE)\r
 811                 {\r
 812                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
 813                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 814 \r
 815                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 816                 }\r
 817                 return;\r
 818         }       \r
 819         else\r
 820         {\r
 821                 if(pDM_FatTable->bBecomeLinked ==FALSE)\r
 822                 {\r
 823                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));\r
 824                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
 825                         if(pDM_Odm->SupportICType == ODM_RTL8821 )\r
 826                                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
 827                                 \r
 828                         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 829                         else if(pDM_Odm->SupportICType == ODM_RTL8881 )\r
 830                                 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
 831                         #endif\r
 832                         \r
 833                         else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812)\r
 834                                 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable\r
 835                         \r
 836                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 837 \r
 838                         if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
 839                         {\r
 840                                 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]   // for 8723B AntDiv function patch.  BB  Dino  130412   \r
 841                                 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]\r
 842                         }\r
 843                 }       \r
 844         }       \r
 845 \r
 846         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[HW AntDiv] Start =>\n"));\r
 847            \r
 848         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
 849         {\r
 850                 pEntry = pDM_Odm->pODM_StaInfo[i];\r
 851                 if(IS_STA_VALID(pEntry))\r
 852                 {\r
 853                         //2 Caculate RSSI per Antenna\r
 854                         Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
 855                         Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
 856                         TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
 857                         /*\r
 858                         if( pDM_FatTable->MainAnt_Cnt[i]!=0 && pDM_FatTable->AuxAnt_Cnt[i]!=0 )\r
 859                         {\r
 860                         pkt_ratio_m=( pDM_FatTable->MainAnt_Cnt[i] / pDM_FatTable->AuxAnt_Cnt[i] );\r
 861                         pkt_ratio_a=( pDM_FatTable->AuxAnt_Cnt[i] / pDM_FatTable->MainAnt_Cnt[i] );\r
 862                                 \r
 863                                 if (pkt_ratio_m >= pkt_threshold)\r
 864                                         TargetAnt=MAIN_ANT;\r
 865                                 \r
 866                                 else if(pkt_ratio_a >= pkt_threshold)\r
 867                                         TargetAnt=AUX_ANT;\r
 868                         }\r
 869                         */                      \r
 870                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%u] \n",pDM_Odm->SupportICType));\r
 871                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Main_Cnt = (( %u ))  , Main_RSSI= ((  %u )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
 872                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Aux_Cnt   = (( %u ))  , Aux_RSSI = ((  %u )) \n", pDM_FatTable->AuxAnt_Cnt[i]  , Aux_RSSI ));\r
 873                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %u ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
 874 \r
 875                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
 876                                                                                                               ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0)));\r
 877                         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 878                         if (pDM_Odm->antdiv_rssi)\r
 879                         {\r
 880                                 panic_printk("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType);\r
 881                                 //panic_printk("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
 882                                 //      ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0));\r
 883                                 //panic_printk("*** Phy_AntSel_B=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT2)>>2,\r
 884                                 //      ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT0))\r
 885                                 panic_printk("*** Client[ %lu ] , Main_Cnt = (( %lu ))  , Main_RSSI= ((  %lu )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI);\r
 886                                 panic_printk("*** Client[ %lu ] , Aux_Cnt   = (( %lu ))  , Aux_RSSI = ((  %lu )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI);\r
 887                         }\r
 888                         #endif\r
 889 \r
 890 \r
 891                         LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;\r
 892                         //2 Select MaxRSSI for DIG\r
 893                         if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))\r
 894                                 AntDivMaxRSSI = LocalMaxRSSI;\r
 895                         if(LocalMaxRSSI > MaxRSSI)\r
 896                                 MaxRSSI = LocalMaxRSSI;\r
 897 \r
 898                         //2 Select RX Idle Antenna\r
 899                         if ( (LocalMaxRSSI != 0) &&  (LocalMaxRSSI < MinMaxRSSI) )\r
 900                         {\r
 901                                 RxIdleAnt = TargetAnt;\r
 902                                 MinMaxRSSI = LocalMaxRSSI;\r
 903                         }\r
 904                         /*\r
 905                         if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))\r
 906                                 Main_RSSI = Aux_RSSI;\r
 907                         else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))\r
 908                                 Aux_RSSI = Main_RSSI;\r
 909                 \r
 910                         LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;\r
 911                         if(LocalMinRSSI < MinRSSI)\r
 912                         {\r
 913                                 MinRSSI = LocalMinRSSI;\r
 914                                 RxIdleAnt = TargetAnt;\r
 915                         }       \r
 916                         */\r
 917                         //2 Select TX Antenna\r
 918 \r
 919                         #if TX_BY_REG\r
 920                         \r
 921                         #else\r
 922                                 if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
 923                                         odm_UpdateTxAnt(pDM_Odm, TargetAnt, i);\r
 924                         #endif\r
 925 \r
 926                 }\r
 927                 pDM_FatTable->MainAnt_Sum[i] = 0;\r
 928                 pDM_FatTable->AuxAnt_Sum[i] = 0;\r
 929                 pDM_FatTable->MainAnt_Cnt[i] = 0;\r
 930                 pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
 931         }\r
 932        \r
 933         //2 Set RX Idle Antenna\r
 934         ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
 935 \r
 936         #if(DM_ODM_SUPPORT_TYPE  == ODM_AP)\r
 937                 if (pDM_Odm->antdiv_rssi)\r
 938                         panic_printk("*** RxIdleAnt = (( %s )) \n \n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
 939         #endif\r
 940         \r
 941         pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;\r
 942         pDM_DigTable->RSSI_max = MaxRSSI;\r
 943 }\r
 944 \r
 945 \r
 946 \r
 947 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
 948 VOID\r
 949 odm_S0S1_SwAntDiv(\r
 950         IN              PDM_ODM_T               pDM_Odm,\r
 951         IN              u1Byte                  Step\r
 952         )\r
 953 {\r
 954         u4Byte                  i,MinMaxRSSI=0xFF, LocalMaxRSSI,LocalMinRSSI;\r
 955         u4Byte                  Main_RSSI, Aux_RSSI;\r
 956         u1Byte                  reset_period=10, SWAntDiv_threshold=35;\r
 957         u1Byte                  HighTraffic_TrainTime_U=0x32,HighTraffic_TrainTime_L,Train_time_temp;\r
 958         u1Byte                  LowTraffic_TrainTime_U=200,LowTraffic_TrainTime_L;\r
 959         u1Byte                  RxIdleAnt, TargetAnt, nextAnt;\r
 960         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
 961         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;   \r
 962         PSTA_INFO_T             pEntry=NULL;\r
 963         //static u1Byte         reset_idx;\r
 964         u4Byte                  value32;\r
 965         PADAPTER                Adapter  =  pDM_Odm->Adapter;\r
 966         u8Byte                  curTxOkCnt=0, curRxOkCnt=0,TxCntOffset, RxCntOffset;\r
 967         \r
 968         if(!pDM_Odm->bLinked) //bLinked==False\r
 969         {\r
 970                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
 971                 if(pDM_FatTable->bBecomeLinked == TRUE)\r
 972                 {\r
 973                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0 \n"));\r
 974                         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
 975                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); \r
 976                         \r
 977                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
 978                 }\r
 979                 return;\r
 980         }\r
 981         else\r
 982         {\r
 983                 if(pDM_FatTable->bBecomeLinked ==FALSE)\r
 984                 {\r
 985                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));\r
 986                         \r
 987                         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
 988                         {\r
 989                                 value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3);\r
 990                                 \r
 991                                 if (value32==0x0)\r
 992                                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
 993                                 else if (value32==0x1)\r
 994                                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
 995                                 \r
 996                                 ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);\r
 997                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[6]=0x1 , Set REG 864[5:3]=0x%x \n",value32 ));\r
 998                         }\r
 999 \r
1000                         pDM_SWAT_Table->lastTxOkCnt = 0; \r
1001                         pDM_SWAT_Table->lastRxOkCnt =0; \r
1002                         TxCntOffset = Adapter->TxStats.NumTxBytesUnicast;\r
1003                         RxCntOffset = Adapter->RxStats.NumRxBytesUnicast;\r
1004                         \r
1005                         pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
1006                 }\r
1007                 else\r
1008                 {\r
1009                         TxCntOffset = 0;\r
1010                         RxCntOffset = 0;\r
1011                 }\r
1012         }\r
1013         \r
1014         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n",\r
1015                 __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag));\r
1016 \r
1017         // Handling step mismatch condition.\r
1018         // Peak step is not finished at last time. Recover the variable and check again.\r
1019         if(     Step != pDM_SWAT_Table->try_flag        )\r
1020         {\r
1021                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag]    Need to Reset After Link\n"));\r
1022                 ODM_SwAntDivRestAfterLink(pDM_Odm);\r
1023         }\r
1024 \r
1025         if(pDM_SWAT_Table->try_flag == 0xff) \r
1026         {       \r
1027                 pDM_SWAT_Table->try_flag = 0;\r
1028                 pDM_SWAT_Table->Train_time_flag=0;\r
1029                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag = 0]  Prepare for peak!\n\n"));\r
1030                 return;\r
1031         }       \r
1032         else//if( try_flag != 0xff ) \r
1033         {\r
1034                 //1 Normal State (Begin Trying)\r
1035                 if(pDM_SWAT_Table->try_flag == 0) \r
1036                 {\r
1037                 \r
1038                         //---trafic decision---\r
1039                         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt - TxCntOffset;\r
1040                         curRxOkCnt =Adapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt - RxCntOffset;\r
1041                         pDM_SWAT_Table->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;\r
1042                         pDM_SWAT_Table->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;\r
1043                         \r
1044                         if (curTxOkCnt > 1875000 || curRxOkCnt > 1875000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)  ( 1.875M * 8bit ) / 2= 7.5M bits /sec )\r
1045                         {\r
1046                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;\r
1047                                 Train_time_temp=pDM_SWAT_Table->Train_time ;\r
1048                                 \r
1049                                 if(pDM_SWAT_Table->Train_time_flag==3)\r
1050                                 {\r
1051                                         HighTraffic_TrainTime_L=0xa;\r
1052                                         \r
1053                                         if(Train_time_temp<=16)\r
1054                                                 Train_time_temp=HighTraffic_TrainTime_L;\r
1055                                         else\r
1056                                                 Train_time_temp-=16;\r
1057                                         \r
1058                                 }                               \r
1059                                 else if(pDM_SWAT_Table->Train_time_flag==2)\r
1060                                 {\r
1061                                         Train_time_temp-=8;\r
1062                                         HighTraffic_TrainTime_L=0xf;\r
1063                                 }       \r
1064                                 else if(pDM_SWAT_Table->Train_time_flag==1)\r
1065                                 {\r
1066                                         Train_time_temp-=4;\r
1067                                         HighTraffic_TrainTime_L=0x1e;\r
1068                                 }\r
1069                                 else if(pDM_SWAT_Table->Train_time_flag==0)\r
1070                                 {\r
1071                                         Train_time_temp+=8;\r
1072                                         HighTraffic_TrainTime_L=0x28;\r
1073                                 }\r
1074 \r
1075                                 \r
1076                                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp));\r
1077 \r
1078                                 //--\r
1079                                 if(Train_time_temp > HighTraffic_TrainTime_U)\r
1080                                         Train_time_temp=HighTraffic_TrainTime_U;\r
1081                                 \r
1082                                 else if(Train_time_temp < HighTraffic_TrainTime_L)\r
1083                                         Train_time_temp=HighTraffic_TrainTime_L;\r
1084 \r
1085                                 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~10ms\r
1086                                 \r
1087                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("  Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));\r
1088                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [HIGH Traffic]  \n" ));\r
1089                         }\r
1090                         else if (curTxOkCnt > 125000 || curRxOkCnt > 125000) // ( 0.125M * 8bit ) / 2 =  0.5M bits /sec )\r
1091                         {\r
1092                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
1093                                 Train_time_temp=pDM_SWAT_Table->Train_time ;\r
1094 \r
1095                                 if(pDM_SWAT_Table->Train_time_flag==3)\r
1096                                 {\r
1097                                         LowTraffic_TrainTime_L=10;\r
1098                                         if(Train_time_temp<50)\r
1099                                                 Train_time_temp=LowTraffic_TrainTime_L;\r
1100                                         else\r
1101                                                 Train_time_temp-=50;\r
1102                                 }                               \r
1103                                 else if(pDM_SWAT_Table->Train_time_flag==2)\r
1104                                 {\r
1105                                         Train_time_temp-=30;\r
1106                                         LowTraffic_TrainTime_L=36;\r
1107                                 }       \r
1108                                 else if(pDM_SWAT_Table->Train_time_flag==1)\r
1109                                 {\r
1110                                         Train_time_temp-=10;\r
1111                                         LowTraffic_TrainTime_L=40;\r
1112                                 }\r
1113                                 else\r
1114                                         Train_time_temp+=10;    \r
1115 \r
1116                                 //--\r
1117                                 if(Train_time_temp >= LowTraffic_TrainTime_U)\r
1118                                         Train_time_temp=LowTraffic_TrainTime_U;\r
1119                                 \r
1120                                 else if(Train_time_temp <= LowTraffic_TrainTime_L)\r
1121                                         Train_time_temp=LowTraffic_TrainTime_L;\r
1122 \r
1123                                 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~20ms\r
1124 \r
1125                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("  Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));\r
1126                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [Low Traffic]  \n" ));\r
1127                         }\r
1128                         else\r
1129                         {\r
1130                                 pDM_SWAT_Table->TrafficLoad = TRAFFIC_UltraLOW;\r
1131                                 pDM_SWAT_Table->Train_time = 0xc8; //200ms\r
1132                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("  [Ultra-Low Traffic]  \n" ));\r
1133                         }\r
1134                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )) \n", \r
1135                                 curTxOkCnt ,curRxOkCnt ));\r
1136                                 \r
1137                         //-----------------\r
1138                 \r
1139                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Current MinMaxRSSI is ((%d)) \n",pDM_FatTable->MinMaxRSSI));\r
1140 \r
1141                         //---reset index---\r
1142                         if(pDM_SWAT_Table->reset_idx>=reset_period)\r
1143                         {\r
1144                                 pDM_FatTable->MinMaxRSSI=0; //\r
1145                                 pDM_SWAT_Table->reset_idx=0;\r
1146                         }\r
1147                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d )) \n",pDM_SWAT_Table->reset_idx ));\r
1148                         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("reset_idx=%d\n",pDM_SWAT_Table->reset_idx));\r
1149                         pDM_SWAT_Table->reset_idx++;\r
1150 \r
1151                         //---double check flag---\r
1152                         if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold && pDM_SWAT_Table->Double_chk_flag== 0)\r
1153                         {                       \r
1154                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" MinMaxRSSI is ((%d)), and > %d \n",\r
1155                                         pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1156 \r
1157                                 pDM_SWAT_Table->Double_chk_flag =1;\r
1158                                 pDM_SWAT_Table->try_flag = 1; \r
1159                                 pDM_SWAT_Table->RSSI_Trying = 0;\r
1160 \r
1161                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test the current Ant for (( %d )) ms again \n", pDM_SWAT_Table->Train_time));\r
1162                                 ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt);  \r
1163                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms    \r
1164                                 return;\r
1165                         }\r
1166                         \r
1167                         nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT;\r
1168 \r
1169                         pDM_SWAT_Table->try_flag = 1;\r
1170                         \r
1171                         if(pDM_SWAT_Table->reset_idx<=1)\r
1172                                 pDM_SWAT_Table->RSSI_Trying = 2;\r
1173                         else\r
1174                                 pDM_SWAT_Table->RSSI_Trying = 1;\r
1175                         \r
1176                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=1]  Normal State:  Begin Trying!! \n"));\r
1177                                                                         \r
1178                 }\r
1179         \r
1180                 else if(pDM_SWAT_Table->try_flag == 1 && pDM_SWAT_Table->Double_chk_flag== 0)\r
1181                 {       \r
1182                         nextAnt = (pDM_FatTable->RxIdleAnt  == MAIN_ANT)? AUX_ANT : MAIN_ANT;           \r
1183                         pDM_SWAT_Table->RSSI_Trying--;\r
1184                 }\r
1185                 \r
1186                 //1 Decision State\r
1187                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0) )\r
1188                 {\r
1189                         \r
1190                         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
1191                         {\r
1192                                 pEntry = pDM_Odm->pODM_StaInfo[i];\r
1193                                 if(IS_STA_VALID(pEntry))\r
1194                                 {\r
1195                                         //2 Caculate RSSI per Antenna\r
1196                                         Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
1197                                         Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
1198                                         \r
1199                                         if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1)\r
1200                                                 Main_RSSI=0;    \r
1201                                         \r
1202                                         if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1)\r
1203                                                 Aux_RSSI=0;\r
1204 \r
1205                                         TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
1206                                         LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI;\r
1207                                         LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI;\r
1208                                         \r
1209                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux));\r
1210                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux));\r
1211                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Main_Cnt = (( %d ))  , Main_RSSI= ((  %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
1212                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***  Aux_Cnt   = (( %d ))  , Aux_RSSI = ((  %d )) \n", pDM_FatTable->AuxAnt_Cnt[i]  , Aux_RSSI ));\r
1213                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
1214                                         \r
1215                                         //2 Select RX Idle Antenna\r
1216                                         \r
1217                                         if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI)\r
1218                                         {\r
1219                                                         RxIdleAnt = TargetAnt;\r
1220                                                         MinMaxRSSI = LocalMaxRSSI;\r
1221                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI)));\r
1222                                         \r
1223                                                         if((LocalMaxRSSI-LocalMinRSSI)>8)\r
1224                                                         {\r
1225                                                                 if(LocalMinRSSI != 0)\r
1226                                                                         pDM_SWAT_Table->Train_time_flag=3;\r
1227                                                                 else\r
1228                                                                 {\r
1229                                                                         if(MinMaxRSSI > SWAntDiv_threshold)\r
1230                                                                                 pDM_SWAT_Table->Train_time_flag=0;\r
1231                                                                         else\r
1232                                                                                 pDM_SWAT_Table->Train_time_flag=3;\r
1233                                                                 }\r
1234                                                         }\r
1235                                                         else if((LocalMaxRSSI-LocalMinRSSI)>5)\r
1236                                                                 pDM_SWAT_Table->Train_time_flag=2;\r
1237                                                         else if((LocalMaxRSSI-LocalMinRSSI)>2)\r
1238                                                                 pDM_SWAT_Table->Train_time_flag=1;\r
1239                                                         else\r
1240                                                                 pDM_SWAT_Table->Train_time_flag=0;\r
1241                                                         \r
1242                                         }\r
1243                                         \r
1244                                         //2 Select TX Antenna\r
1245                                         if(TargetAnt == MAIN_ANT)\r
1246                                                 pDM_FatTable->antsel_a[i] = ANT1_2G;\r
1247                                         else\r
1248                                                 pDM_FatTable->antsel_a[i] = ANT2_2G;\r
1249                         \r
1250                                 }\r
1251                                         pDM_FatTable->MainAnt_Sum[i] = 0;\r
1252                                         pDM_FatTable->AuxAnt_Sum[i] = 0;\r
1253                                         pDM_FatTable->MainAnt_Cnt[i] = 0;\r
1254                                         pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
1255                                         pDM_FatTable->CCK_counter_main=0;\r
1256                                         pDM_FatTable->CCK_counter_aux=0;\r
1257                                         pDM_FatTable->OFDM_counter_main=0;\r
1258                                         pDM_FatTable->OFDM_counter_aux=0;\r
1259 \r
1260                         }\r
1261                 \r
1262                         \r
1263                         pDM_FatTable->MinMaxRSSI=MinMaxRSSI;\r
1264                         pDM_SWAT_Table->try_flag = 0;\r
1265                                                 \r
1266                         if( pDM_SWAT_Table->Double_chk_flag==1)\r
1267                         {\r
1268                                 pDM_SWAT_Table->Double_chk_flag=0;\r
1269                                 if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold)\r
1270                                 {\r
1271                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) > %d again!! \n",\r
1272                                                 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1273                                         \r
1274                                         ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);        \r
1275                                         \r
1276                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));\r
1277                                         return;\r
1278                                 }\r
1279                                 else\r
1280                                 {\r
1281                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) <= %d !! \n",\r
1282                                                 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));\r
1283 \r
1284                                         nextAnt = (pDM_FatTable->RxIdleAnt  == MAIN_ANT)? AUX_ANT : MAIN_ANT;\r
1285                                         pDM_SWAT_Table->try_flag = 0; \r
1286                                         pDM_SWAT_Table->reset_idx=reset_period;\r
1287                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=0]  Normal State:  Need to tryg again!! \n\n\n"));\r
1288                                         return;\r
1289                                 }\r
1290                         }\r
1291                         else\r
1292                         {\r
1293                                 pDM_SWAT_Table->PreAntenna =RxIdleAnt;\r
1294                                 ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt );\r
1295                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));\r
1296                                 return;\r
1297                         }\r
1298                         \r
1299                 }\r
1300 \r
1301         }\r
1302 \r
1303         //1 4.Change TRX antenna\r
1304 \r
1305         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )),    Ant: (( %s )) >>> (( %s )) \n",\r
1306                 pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt  == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX")));\r
1307                 \r
1308         ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt);\r
1309 \r
1310         //1 5.Reset Statistics\r
1311 \r
1312         pDM_FatTable->RxIdleAnt  = nextAnt;\r
1313 \r
1314         //1 6.Set next timer   (Trying State)\r
1315         \r
1316         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms \n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time));\r
1317         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms\r
1318 }\r
1319 \r
1320 \r
1321 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1322 VOID\r
1323 ODM_SW_AntDiv_Callback(\r
1324         PRT_TIMER               pTimer\r
1325 )\r
1326 {\r
1327         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;\r
1328         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1329         pSWAT_T                 pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;\r
1330 \r
1331         #if DEV_BUS_TYPE==RT_PCI_INTERFACE\r
1332                 #if USE_WORKITEM\r
1333                         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);\r
1334                 #else\r
1335                         {\r
1336                         //DbgPrint("SW_antdiv_Callback");\r
1337                         odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);\r
1338                         }\r
1339                 #endif\r
1340         #else\r
1341         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);\r
1342         #endif\r
1343 }\r
1344 VOID\r
1345 ODM_SW_AntDiv_WorkitemCallback(\r
1346     IN PVOID            pContext\r
1347     )\r
1348 {\r
1349         PADAPTER                pAdapter = (PADAPTER)pContext;\r
1350         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1351         \r
1352         //DbgPrint("SW_antdiv_Workitem_Callback");\r
1353         odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);\r
1354 }\r
1355 #endif  //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1356 \r
1357 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1358 VOID\r
1359 ODM_SW_AntDiv_Callback(void *FunctionContext)\r
1360 {\r
1361         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;\r
1362         PADAPTER        padapter = pDM_Odm->Adapter;\r
1363         if(padapter->net_closed == _TRUE)\r
1364             return;\r
1365         //odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE);      \r
1366 }\r
1367 #endif  //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1368 \r
1369 #endif //#if (RTL8723B_SUPPORT == 1)\r
1370 \r
1371 \r
1372 #if(RTL8188E_SUPPORT == 1  || RTL8192E_SUPPORT == 1)\r
1373 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
1374 VOID\r
1375 odm_SetNextMACAddrTarget(\r
1376         IN              PDM_ODM_T               pDM_Odm\r
1377 )\r
1378 {\r
1379         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1380         PSTA_INFO_T     pEntry;\r
1381         //u1Byte        Bssid[6];\r
1382         u4Byte  value32, i;\r
1383 \r
1384         //\r
1385         //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn\r
1386         //\r
1387         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n"));\r
1388         if(pDM_Odm->bLinked)\r
1389         {\r
1390                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
1391                 {\r
1392                         if((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM)\r
1393                                 pDM_FatTable->TrainIdx = 0;\r
1394                         else\r
1395                                 pDM_FatTable->TrainIdx++;\r
1396                         \r
1397                         pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1398                         if(IS_STA_VALID(pEntry))\r
1399                         {\r
1400                                 //Match MAC ADDR\r
1401 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1402                                 value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4];\r
1403 #else\r
1404                                 value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4];\r
1405 #endif\r
1406                                 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);\r
1407 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1408                                 value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0];\r
1409 #else\r
1410                                 value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0];\r
1411 #endif\r
1412                                 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);\r
1413 \r
1414                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%lu\n",pDM_FatTable->TrainIdx));\r
1415 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1416                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",\r
1417                                         pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0]));\r
1418 #else\r
1419                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",\r
1420                                         pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0]));\r
1421 #endif\r
1422 \r
1423                                 break;\r
1424                         }\r
1425                 }\r
1426                 \r
1427         }\r
1428 \r
1429 #if 0\r
1430         //\r
1431         //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn\r
1432         //\r
1433         #if( DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1434         {               \r
1435                 PADAPTER        Adapter =  pDM_Odm->Adapter;\r
1436                 PMGNT_INFO      pMgntInfo = &Adapter->MgntInfo;\r
1437 \r
1438                 for (i=0; i<6; i++)\r
1439                 {\r
1440                         Bssid[i] = pMgntInfo->Bssid[i];\r
1441                         //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);\r
1442                 }\r
1443         }\r
1444         #endif\r
1445 \r
1446         //odm_SetNextMACAddrTarget(pDM_Odm);\r
1447         \r
1448         //1 Select MAC Address Filter\r
1449         for (i=0; i<6; i++)\r
1450         {\r
1451                 if(Bssid[i] != pDM_FatTable->Bssid[i])\r
1452                 {\r
1453                         bMatchBSSID = FALSE;\r
1454                         break;\r
1455                 }\r
1456         }\r
1457         if(bMatchBSSID == FALSE)\r
1458         {\r
1459                 //Match MAC ADDR\r
1460                 value32 = (Bssid[5]<<8)|Bssid[4];\r
1461                 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);\r
1462                 value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];\r
1463                 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);\r
1464         }\r
1465 \r
1466         return bMatchBSSID;\r
1467 #endif\r
1468                                 \r
1469 }\r
1470 \r
1471 VOID\r
1472 odm_FastAntTraining(\r
1473         IN              PDM_ODM_T               pDM_Odm\r
1474 )\r
1475 {\r
1476         u4Byte  i, MaxRSSI=0;\r
1477         u1Byte  TargetAnt=2;\r
1478         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1479         BOOLEAN bPktFilterMacth = FALSE;\r
1480 \r
1481         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));\r
1482 \r
1483         //1 TRAINING STATE\r
1484         if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)\r
1485         {\r
1486                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));\r
1487                 //2 Caculate RSSI per Antenna\r
1488                 for (i=0; i<7; i++)\r
1489                 {\r
1490                         if(pDM_FatTable->antRSSIcnt[i] == 0)\r
1491                                 pDM_FatTable->antAveRSSI[i] = 0;\r
1492                         else\r
1493                         {\r
1494                         pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i];\r
1495                                 bPktFilterMacth = TRUE;\r
1496                         }\r
1497                         if(pDM_FatTable->antAveRSSI[i] > MaxRSSI)\r
1498                         {\r
1499                                 MaxRSSI = pDM_FatTable->antAveRSSI[i];\r
1500                                 TargetAnt = (u1Byte) i;\r
1501                         }\r
1502 \r
1503                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%lu] = %lu, pDM_FatTable->antRSSIcnt[%lu] = %lu\n",\r
1504                                 i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));\r
1505                 }\r
1506 \r
1507                 //2 Select TRX Antenna\r
1508                 if(bPktFilterMacth == FALSE)\r
1509                 {\r
1510                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));\r
1511 \r
1512                         ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0);        //RegE08[16]=1'b0               //disable fast training\r
1513                         ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);         //RegC50[7]=1'b0                //disable HW AntDiv\r
1514                 }\r
1515                 else\r
1516                 {\r
1517                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%lu\n",TargetAnt,MaxRSSI));\r
1518 \r
1519                         ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0);        //RegE08[16]=1'b0               //disable fast training\r
1520                         //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);               //RegC50[7]=1'b0                //disable HW AntDiv\r
1521                         ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt);       //Default RX is Omni, Optional RX is the best decision by FAT\r
1522                         //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt);  //Default TX\r
1523                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1              //from TX Info\r
1524 \r
1525 #if 0\r
1526                         pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1527 \r
1528                         if(IS_STA_VALID(pEntry))\r
1529                         {\r
1530                                 pEntry->antsel_a = TargetAnt&BIT0;\r
1531                                 pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
1532                                 pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
1533                         }\r
1534 #else\r
1535                         pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;\r
1536                         pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;\r
1537                         pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;\r
1538 #endif\r
1539 \r
1540 \r
1541                         if(TargetAnt == 0)\r
1542                                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0);         //RegC50[7]=1'b0                //disable HW AntDiv\r
1543 \r
1544                 }\r
1545 \r
1546                 //2 Reset Counter\r
1547                 for(i=0; i<7; i++)\r
1548                 {\r
1549                         pDM_FatTable->antSumRSSI[i] = 0;\r
1550                         pDM_FatTable->antRSSIcnt[i] = 0;\r
1551                 }\r
1552                 \r
1553                 pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
1554                 return;\r
1555         }\r
1556 \r
1557         //1 NORMAL STATE\r
1558         if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE)\r
1559         {\r
1560                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));\r
1561 \r
1562                 odm_SetNextMACAddrTarget(pDM_Odm);\r
1563 \r
1564 #if 0\r
1565                                 pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
1566                                 if(IS_STA_VALID(pEntry))\r
1567                                 {\r
1568                                         pEntry->antsel_a = TargetAnt&BIT0;\r
1569                                         pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
1570                                         pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
1571                                 }\r
1572 #endif\r
1573 \r
1574                 //2 Prepare Training\r
1575                 pDM_FatTable->FAT_State = FAT_TRAINING_STATE;\r
1576                 ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1);        //RegE08[16]=1'b1               //enable fast training\r
1577                 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1                //enable HW AntDiv\r
1578                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));\r
1579                 ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms\r
1580                 \r
1581         }\r
1582                 \r
1583 }\r
1584 \r
1585 VOID\r
1586 odm_FastAntTrainingCallback(\r
1587         IN              PDM_ODM_T               pDM_Odm\r
1588 )\r
1589 {\r
1590 \r
1591 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1592         PADAPTER        padapter = pDM_Odm->Adapter;\r
1593         if(padapter->net_closed == _TRUE)\r
1594             return;\r
1595         //if(*pDM_Odm->pbNet_closed == TRUE)\r
1596            // return;\r
1597 #endif\r
1598 \r
1599 #if USE_WORKITEM\r
1600         ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem);\r
1601 #else\r
1602         odm_FastAntTraining(pDM_Odm);\r
1603 #endif\r
1604 }\r
1605 \r
1606 VOID\r
1607 odm_FastAntTrainingWorkItemCallback(\r
1608         IN              PDM_ODM_T               pDM_Odm\r
1609 )\r
1610 {\r
1611         odm_FastAntTraining(pDM_Odm);\r
1612 }\r
1613 #endif\r
1614 \r
1615 #endif\r
1616 \r
1617 \r
1618 VOID\r
1619 ODM_AntDivInit(\r
1620         IN PDM_ODM_T    pDM_Odm \r
1621         )\r
1622 {\r
1623         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1624         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
1625 \r
1626 \r
1627         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
1628         {\r
1629                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]   Not Support Antenna Diversity Function\n"));\r
1630                 return;\r
1631         }\r
1632         //---\r
1633 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
1634         if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)\r
1635         {\r
1636                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"));\r
1637                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))\r
1638                         return;\r
1639         }\r
1640         else    if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)\r
1641         {\r
1642                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"));\r
1643                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))\r
1644                         return;\r
1645         }\r
1646         else    if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
1647         {\r
1648                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"));\r
1649         }\r
1650 \r
1651          pDM_Odm->antdiv_rssi=0;\r
1652 \r
1653 #endif  \r
1654         //---\r
1655         \r
1656         //2 [--General---]\r
1657         pDM_Odm->antdiv_period=0;\r
1658         pDM_Odm->antdiv_select=0;\r
1659         pDM_SWAT_Table->Ant5G = MAIN_ANT;\r
1660         pDM_SWAT_Table->Ant2G = MAIN_ANT;\r
1661         pDM_FatTable->CCK_counter_main=0;\r
1662         pDM_FatTable->CCK_counter_aux=0;\r
1663         pDM_FatTable->OFDM_counter_main=0;\r
1664         pDM_FatTable->OFDM_counter_aux=0;\r
1665         \r
1666         //3 [Set MAIN_ANT as default antenna if Auto-Ant enable]\r
1667         if (pDM_Odm->antdiv_select==1)\r
1668                 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
1669         else if (pDM_Odm->antdiv_select==2)\r
1670                 pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
1671         else if(pDM_Odm->antdiv_select==0)\r
1672                 pDM_Odm->AntType = ODM_AUTO_ANT;\r
1673         \r
1674         if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
1675         {\r
1676                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1677                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1678         }\r
1679         else\r
1680         {\r
1681                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1682                 \r
1683                 if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
1684                 {\r
1685                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1686                         return;\r
1687                 }\r
1688                 else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)\r
1689                 {\r
1690                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
1691                         return;\r
1692                 }\r
1693         }\r
1694         //---\r
1695         if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
1696         {\r
1697                 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1698                 {\r
1699                         #if TX_BY_REG\r
1700                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0); //Reg80c[21]=1'b0              //from Reg\r
1701                         #else\r
1702                         ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
1703                         #endif\r
1704                 }       \r
1705                 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1706                 {\r
1707                         #if TX_BY_REG\r
1708                         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
1709                         #else\r
1710                         ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
1711                         #endif\r
1712                 }\r
1713         }\r
1714                 \r
1715         //2 [--88E---]\r
1716         if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
1717         {\r
1718         #if (RTL8188E_SUPPORT == 1)\r
1719                 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1720                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1721                 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;\r
1722 \r
1723                 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)  && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))\r
1724                 {\r
1725                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]  88E Not Supprrt This AntDiv Type\n"));\r
1726                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1727                         return;\r
1728                 }\r
1729                 \r
1730                 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1731                         odm_RX_HWAntDiv_Init_88E(pDM_Odm);\r
1732                 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1733                         odm_TRX_HWAntDiv_Init_88E(pDM_Odm);\r
1734                 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
1735                         odm_Smart_HWAntDiv_Init_88E(pDM_Odm);\r
1736         #endif  \r
1737         }\r
1738         \r
1739         //2 [--92E---]\r
1740         #if (RTL8192E_SUPPORT == 1)\r
1741         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
1742         {       \r
1743                 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1744                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1745                 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;\r
1746 \r
1747                 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)   && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))\r
1748                 {\r
1749                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]  8192E Not Supprrt This AntDiv Type\n"));\r
1750                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1751                         return;\r
1752                 }\r
1753                 \r
1754                 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1755                         odm_RX_HWAntDiv_Init_92E(pDM_Odm);\r
1756                 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1757                         odm_TRX_HWAntDiv_Init_92E(pDM_Odm);\r
1758                 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
1759                         odm_Smart_HWAntDiv_Init_92E(pDM_Odm);\r
1760         \r
1761         }\r
1762         #endif  \r
1763         \r
1764         //2 [--8723B---]\r
1765         #if (RTL8723B_SUPPORT == 1)\r
1766         else if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
1767         {               \r
1768                 //pDM_Odm->AntDivType = S0S1_SW_ANTDIV;\r
1769                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1770 \r
1771                 if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1772                 {\r
1773                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B  Not Supprrt This AntDiv Type\n"));\r
1774                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1775                         return;\r
1776                 }\r
1777                         \r
1778                 if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
1779                         odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm);\r
1780                 else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
1781                         odm_TRX_HWAntDiv_Init_8723B(pDM_Odm);           \r
1782         }\r
1783         #endif\r
1784         \r
1785         //2 [--8811A 8821A---]\r
1786         #if (RTL8821A_SUPPORT == 1)\r
1787         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
1788         {\r
1789                 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1790                 pDM_Odm->AntDivType = S0S1_SW_ANTDIV;\r
1791                         \r
1792                 if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV)\r
1793                 {\r
1794                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv Type\n"));\r
1795                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1796                         return;\r
1797                 }\r
1798                 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)       \r
1799                         odm_TRX_HWAntDiv_Init_8821A(pDM_Odm);\r
1800                 else if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
1801                         odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm);\r
1802         }\r
1803         #endif\r
1804         \r
1805         //2 [--8881A---]\r
1806         #if (RTL8881A_SUPPORT == 1)\r
1807         else if(pDM_Odm->SupportICType == ODM_RTL8881A)\r
1808         {\r
1809                         //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
1810                         //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1811                         \r
1812                         if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1813                         {\r
1814                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A  Not Supprrt This AntDiv Type\n"));\r
1815                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1816                                 return;\r
1817                         }\r
1818                         if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
1819                                 odm_RX_HWAntDiv_Init_8881A(pDM_Odm);\r
1820                         else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
1821                                 odm_TRX_HWAntDiv_Init_8881A(pDM_Odm);   \r
1822         }\r
1823         #endif\r
1824         \r
1825         //2 [--8812---]\r
1826         #if (RTL8812A_SUPPORT == 1)\r
1827         else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
1828         {       \r
1829                         //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
1830                         \r
1831                         if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)\r
1832                         {\r
1833                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A  Not Supprrt This AntDiv Type\n"));\r
1834                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1835                                 return;\r
1836                         }\r
1837                         odm_TRX_HWAntDiv_Init_8812A(pDM_Odm);\r
1838         }\r
1839         #endif\r
1840         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType));\r
1841         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv SupportAbility=[%lu] \n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6));\r
1842         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv Type=[%d] \n",pDM_Odm->AntDivType));\r
1843 \r
1844 }\r
1845 \r
1846 VOID\r
1847 ODM_AntDiv(\r
1848         IN              PDM_ODM_T               pDM_Odm\r
1849 )\r
1850 {       \r
1851         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
1852         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
1853 \r
1854 //#if (DM_ODM_SUPPORT_TYPE == ODM_AP)   \r
1855         if(*pDM_Odm->pBandType == ODM_BAND_5G )\r
1856         {\r
1857                 if(pDM_FatTable->idx_AntDiv_counter_5G <  pDM_Odm->antdiv_period )\r
1858                 {\r
1859                         pDM_FatTable->idx_AntDiv_counter_5G++;\r
1860                         return;\r
1861                 }\r
1862                 else\r
1863                         pDM_FatTable->idx_AntDiv_counter_5G=0;\r
1864         }\r
1865         else    if(*pDM_Odm->pBandType == ODM_BAND_2_4G )\r
1866         {\r
1867                 if(pDM_FatTable->idx_AntDiv_counter_2G <  pDM_Odm->antdiv_period )\r
1868                 {\r
1869                         pDM_FatTable->idx_AntDiv_counter_2G++;\r
1870                         return;\r
1871                 }\r
1872                 else\r
1873                         pDM_FatTable->idx_AntDiv_counter_2G=0;\r
1874         }\r
1875 //#endif        \r
1876         //----------\r
1877         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
1878         {\r
1879                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!]   Not Support Antenna Diversity Function\n"));\r
1880                 return;\r
1881         }\r
1882 \r
1883         //----------\r
1884 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1885         if(pAdapter->MgntInfo.AntennaTest)\r
1886                 return;\r
1887         \r
1888         {\r
1889         #if (BEAMFORMING_SUPPORT == 1)                  \r
1890                 BEAMFORMING_CAP         BeamformCap = (pAdapter->MgntInfo.BeamformingInfo.BeamformCap);\r
1891 \r
1892                 if( BeamformCap & BEAMFORMEE_CAP ) //  BFmee On  &&   Div On ->  Div Off\r
1893                 {       \r
1894                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ]   BFmee ==1 \n"));\r
1895                         if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)\r
1896                         {\r
1897                                 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1898                                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
1899                                 return;\r
1900                         }\r
1901                 }\r
1902                 else // BFmee Off   &&   Div Off ->  Div On\r
1903         #endif\r
1904                 {\r
1905                         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)  &&  pDM_Odm->bLinked) \r
1906                         {\r
1907                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : ON ]   BFmee ==0 \n"));\r
1908                                 if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) )\r
1909                                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
1910                                 \r
1911                                 pDM_Odm->SupportAbility |= (ODM_BB_ANT_DIV);\r
1912                         }\r
1913                 }\r
1914         }\r
1915 #endif\r
1916 \r
1917         //----------\r
1918 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
1919         if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)\r
1920         {\r
1921                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n"));\r
1922                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))\r
1923                         return;\r
1924         }\r
1925         else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)\r
1926         {\r
1927                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n"));\r
1928                 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))\r
1929                 return;\r
1930         }\r
1931         else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
1932         {\r
1933                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n"));\r
1934         }\r
1935 #endif\r
1936 \r
1937         //----------\r
1938 \r
1939         if (pDM_Odm->antdiv_select==1)\r
1940                 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
1941         else if (pDM_Odm->antdiv_select==2)\r
1942                 pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
1943         else  if (pDM_Odm->antdiv_select==0)\r
1944                 pDM_Odm->AntType = ODM_AUTO_ANT;\r
1945 \r
1946         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d ))  \n",pDM_Odm->AntType,pDM_Odm->pre_AntType));\r
1947         \r
1948         if(pDM_Odm->AntType != ODM_AUTO_ANT)\r
1949         {\r
1950                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX"));\r
1951                         \r
1952                 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
1953                 {\r
1954                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
1955 \r
1956                         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1957                                 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0);\r
1958                         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1959                                 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
1960                                                 \r
1961                         if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
1962                                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
1963                         else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)\r
1964                                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
1965                 }\r
1966                 pDM_Odm->pre_AntType=pDM_Odm->AntType; \r
1967                 return;\r
1968         }\r
1969         else\r
1970         {\r
1971                 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
1972                 {\r
1973                         odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
1974                          if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
1975                                 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
1976                         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
1977                                 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
1978                 }\r
1979                 pDM_Odm->pre_AntType=pDM_Odm->AntType;\r
1980         }\r
1981          \r
1982         \r
1983         //3 -----------------------------------------------------------------------------------------------------------\r
1984         //2 [--88E---]\r
1985         if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
1986         {\r
1987                 #if (RTL8188E_SUPPORT == 1)\r
1988                 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
1989                         odm_HW_AntDiv(pDM_Odm);\r
1990                 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
1991                 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
1992                         odm_FastAntTraining(pDM_Odm);   \r
1993                 #endif\r
1994                 #endif\r
1995         }\r
1996         //2 [--92E---]  \r
1997         #if (RTL8192E_SUPPORT == 1)\r
1998         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
1999         {\r
2000                 if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
2001                         odm_HW_AntDiv(pDM_Odm);\r
2002                 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
2003                 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
2004                         odm_FastAntTraining(pDM_Odm);   \r
2005                 #endif\r
2006         }\r
2007         #endif\r
2008 \r
2009         #if (RTL8723B_SUPPORT == 1)     \r
2010         //2 [--8723B---]\r
2011         else if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
2012         {\r
2013                 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
2014                         odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);\r
2015                 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
2016                         odm_HW_AntDiv(pDM_Odm);\r
2017         }\r
2018         #endif\r
2019         \r
2020         //2 [--8821A---]\r
2021         #if (RTL8821A_SUPPORT == 1)\r
2022         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
2023         {\r
2024                 if(!pDM_Odm->bBtEnabled)  //BT disabled\r
2025                 {\r
2026                         if(pDM_Odm->AntDivType == S0S1_SW_ANTDIV)\r
2027                         {\r
2028                         pDM_Odm->AntDivType=CG_TRX_HW_ANTDIV;\r
2029                         ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); \r
2030                         }\r
2031                 }       \r
2032                 else //BT enabled\r
2033                 {\r
2034                         if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
2035                         {\r
2036                         pDM_Odm->AntDivType=S0S1_SW_ANTDIV;\r
2037                         ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0); \r
2038                         }       \r
2039                 }       \r
2040         \r
2041                 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
2042                         odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);\r
2043                 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
2044                 odm_HW_AntDiv(pDM_Odm);\r
2045         }\r
2046         #endif\r
2047         //2 [--8881A---]\r
2048         #if (RTL8881A_SUPPORT == 1)\r
2049         else if(pDM_Odm->SupportICType == ODM_RTL8881A)         \r
2050                 odm_HW_AntDiv(pDM_Odm);\r
2051         #endif\r
2052         //2 [--8812A---]\r
2053         #if (RTL8812A_SUPPORT == 1)\r
2054         else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
2055                 odm_HW_AntDiv(pDM_Odm);\r
2056         #endif\r
2057 }\r
2058 \r
2059 \r
2060 VOID\r
2061 odm_AntselStatistics(\r
2062         IN              PDM_ODM_T               pDM_Odm,\r
2063         IN              u1Byte                  antsel_tr_mux,\r
2064         IN              u4Byte                  MacId,\r
2065         IN              u4Byte                  RxPWDBAll\r
2066 )\r
2067 {\r
2068         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2069 \r
2070         if(antsel_tr_mux == ANT1_2G)\r
2071         {\r
2072                 pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;\r
2073                 pDM_FatTable->MainAnt_Cnt[MacId]++;\r
2074         }\r
2075         else\r
2076         {\r
2077                 pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;\r
2078                 pDM_FatTable->AuxAnt_Cnt[MacId]++;\r
2079         }\r
2080 }\r
2081 \r
2082 \r
2083 VOID\r
2084 ODM_Process_RSSIForAntDiv(      \r
2085         IN OUT  PDM_ODM_T                                       pDM_Odm,\r
2086         IN              PODM_PHY_INFO_T                         pPhyInfo,\r
2087         IN              PODM_PACKET_INFO_T                      pPktinfo\r
2088         )\r
2089 {\r
2090 u1Byte                  isCCKrate=0,CCKMaxRate=DESC_RATE11M;\r
2091 pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2092 \r
2093 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))\r
2094         u4Byte                  RxPower_Ant0, RxPower_Ant1;     \r
2095 #else\r
2096         u1Byte                  RxPower_Ant0, RxPower_Ant1;     \r
2097 #endif\r
2098 \r
2099         if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
2100                 CCKMaxRate=DESC_RATE11M;\r
2101         else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
2102                 CCKMaxRate=DESC_RATE11M;\r
2103         isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE;\r
2104 \r
2105 #if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))\r
2106                 if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D)\r
2107                 {\r
2108                                 if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)\r
2109                                 {\r
2110                                         //if(pPktinfo->bPacketBeacon)\r
2111                                         //{\r
2112                                         //      DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);\r
2113                                         //}\r
2114                                         ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID,  pPhyInfo->RxPWDBAll, isCCKrate);\r
2115                                 }\r
2116                 }\r
2117 #endif\r
2118                 \r
2119         if(  (pDM_Odm->SupportICType == ODM_RTL8192E||pDM_Odm->SupportICType == ODM_RTL8812)   && (pPktinfo->DataRate > CCKMaxRate) )\r
2120         {\r
2121                 RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0];\r
2122                 RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1];\r
2123         }\r
2124         else\r
2125                 RxPower_Ant0=pPhyInfo->RxPWDBAll;\r
2126         \r
2127         if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
2128         {\r
2129                 if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) &&  pPktinfo->bPacketToSelf   && pDM_FatTable->FAT_State == FAT_TRAINING_STATE )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))\r
2130                 {\r
2131                         u1Byte  antsel_tr_mux;\r
2132                         antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;\r
2133                         pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0;\r
2134                         pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;\r
2135                 }\r
2136         }\r
2137         else //AntDivType != CG_TRX_SMART_ANTDIV \r
2138         {\r
2139                 if(  ( pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT ) &&  (pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID)  )\r
2140                 {\r
2141                          if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E)\r
2142                                 odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0);\r
2143                         else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812)\r
2144                         {\r
2145                                 if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV))\r
2146                                 {\r
2147                                         pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G;\r
2148 \r
2149 \r
2150                                                 if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
2151                                                         pDM_FatTable->CCK_counter_main++;\r
2152                                                 else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
2153                                                         pDM_FatTable->CCK_counter_aux++;\r
2154 \r
2155                                         odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
2156                                 }\r
2157                                 else\r
2158                                 {\r
2159 \r
2160                                         if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
2161                                                 pDM_FatTable->OFDM_counter_main++;\r
2162                                         else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
2163                                                 pDM_FatTable->OFDM_counter_aux++;\r
2164                                         odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
2165                         }\r
2166                 }\r
2167         }\r
2168         }\r
2169         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));\r
2170         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));\r
2171 }\r
2172 \r
2173 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
2174 VOID\r
2175 ODM_SetTxAntByTxInfo(\r
2176         IN              PDM_ODM_T               pDM_Odm,\r
2177         IN              pu1Byte                 pDesc,\r
2178         IN              u1Byte                  macId   \r
2179 )\r
2180 {\r
2181         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;\r
2182 \r
2183         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
2184                 return;\r
2185 \r
2186         if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
2187                 return;\r
2188 \r
2189 \r
2190         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
2191         {\r
2192 #if (RTL8723B_SUPPORT == 1)\r
2193                 SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]);\r
2194                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2195                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2196 #endif\r
2197         }\r
2198         else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
2199         {\r
2200 #if (RTL8821A_SUPPORT == 1)\r
2201                 SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]);\r
2202                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2203                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2204 #endif\r
2205         }\r
2206         else if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
2207         {\r
2208 #if (RTL8188E_SUPPORT == 1)\r
2209                 SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);\r
2210                 SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);\r
2211                 SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);\r
2212                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
2213                         //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
2214 #endif\r
2215         }\r
2216         else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
2217         {\r
2218 \r
2219         \r
2220         }\r
2221 }\r
2222 #else// (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
2223 \r
2224 VOID\r
2225 ODM_SetTxAntByTxInfo(\r
2226         //IN            PDM_ODM_T               pDM_Odm,\r
2227         struct  rtl8192cd_priv          *priv,\r
2228         struct  tx_desc                 *pdesc,\r
2229         struct  tx_insn                 *txcfg,\r
2230         unsigned short                  aid     \r
2231 )\r
2232 {\r
2233         pFAT_T          pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable;\r
2234         u4Byte          SupportICType=priv->pshare->_dmODM.SupportICType;\r
2235 \r
2236         if(SupportICType == ODM_RTL8881A)\r
2237         {\r
2238                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******   \n",__FUNCTION__,__LINE__);        \r
2239                 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
2240                 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2241         }\r
2242         else if(SupportICType == ODM_RTL8192E)\r
2243         {\r
2244                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******   \n",__FUNCTION__,__LINE__);        \r
2245                 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
2246                 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2247         }\r
2248         else if(SupportICType == ODM_RTL8812)\r
2249         {\r
2250                 //3 [path-A]\r
2251                 //panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******   \n",__FUNCTION__,__LINE__);\r
2252                         \r
2253                 pdesc->Dword6 &= set_desc(~ BIT(16));\r
2254                 pdesc->Dword6 &= set_desc(~ BIT(17));\r
2255                 pdesc->Dword6 &= set_desc(~ BIT(18));\r
2256                 if(txcfg->pstat)\r
2257                 {\r
2258                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
2259                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17);\r
2260                         pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18);\r
2261                 }\r
2262         }\r
2263 }\r
2264 #endif\r
2265 \r
2266 #else\r
2267 \r
2268 VOID ODM_AntDivInit(    IN PDM_ODM_T    pDM_Odm ){}\r
2269 VOID ODM_AntDiv(        IN PDM_ODM_T            pDM_Odm){}\r
2270 \r
2271 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
2272 \r
2273 \r