drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DIG.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 \r
  25 #include "odm_precomp.h"\r
  26 #define ADAPTIVITY_VERSION      "5.0"
  27
  28 \r
  29 VOID\r
  30 ODM_ChangeDynamicInitGainThresh(
  31         IN      PVOID           pDM_VOID,
  32         IN      u4Byte          DM_Type,
  33         IN      u4Byte          DM_Value
  34         )
  35 {
  36         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  37         pDIG_T                  pDM_DigTable = &pDM_Odm->DM_DigTable;
  38
  39         if (DM_Type == DIG_TYPE_THRESH_HIGH)
  40         {
  41                 pDM_DigTable->RssiHighThresh = DM_Value;
  42         }
  43         else if (DM_Type == DIG_TYPE_THRESH_LOW)
  44         {
  45                 pDM_DigTable->RssiLowThresh = DM_Value;
  46         }
  47         else if (DM_Type == DIG_TYPE_ENABLE)
  48         {
  49                 pDM_DigTable->Dig_Enable_Flag   = TRUE;
  50         }
  51         else if (DM_Type == DIG_TYPE_DISABLE)
  52         {
  53                 pDM_DigTable->Dig_Enable_Flag = FALSE;
  54         }
  55         else if (DM_Type == DIG_TYPE_BACKOFF)
  56         {
  57                 if(DM_Value > 30)
  58                         DM_Value = 30;
  59                 pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
  60         }
  61         else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
  62         {
  63                 if(DM_Value == 0)
  64                         DM_Value = 0x1;
  65                 pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
  66         }
  67         else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
  68         {
  69                 if(DM_Value > 0x50)
  70                         DM_Value = 0x50;
  71                 pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
  72         }
  73 }       // DM_ChangeDynamicInitGainThresh //\r
  74
  75 VOID
  76 odm_NHMCounterStatisticsInit(
  77         IN              PVOID                   pDM_VOID
  78         )
  79 {
  80         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;
  81
  82         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
  83         {
  84                 //PHY parameters initialize for ac series
  85                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0x2710);      //0x990[31:16]=0x2710   Time duration for NHM unit: 4us, 0x2710=40ms
  86                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff);   //0x994[31:16]=0xffff   th_9, th_10
  87                 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c);     //0x998=0xffffff5c              th_3, th_2, th_1, th_0
  88                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff52);       //0x998=0xffffff52              th_3, th_2, th_1, th_0
  89                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);       //0x99c=0xffffffff              th_7, th_6, th_5, th_4
  90                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff);          //0x9a0[7:0]=0xff               th_8
  91                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3                  enable CCX
  92                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1);         //0x9e8[7]=1                    max power among all RX ants
  93
  94                 //panic_printk("RTL8812AU phy parameters init %s,%d\n", __FUNCTION__, __LINE__);
  95         }
  96         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
  97         {
  98                 //PHY parameters initialize for n series
  99                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x2710);       //0x894[31:16]=0x2710   Time duration for NHM unit: 4us, 0x2710=40ms
 100                 //ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20);     //0x894[31:16]=0x4e20   Time duration for NHM unit: 4us, 0x4e20=80ms
 101                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff);    //0x890[31:16]=0xffff   th_9, th_10
 102                 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c);      //0x898=0xffffff5c              th_3, th_2, th_1, th_0
 103                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff52);        //0x898=0xffffff52              th_3, th_2, th_1, th_0
 104                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);        //0x89c=0xffffffff              th_7, th_6, th_5, th_4
 105                 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff);         //0xe28[7:0]=0xff               th_8
 106                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7);  //0x890[9:8]=3                  enable CCX
 107                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1);             //0xc0c[7]=1                    max power among all RX ants
 108         }
 109 }
 110
 111 VOID
 112 odm_NHMCounterStatistics(
 113         IN              PVOID                   pDM_VOID
 114         )
 115 {
 116         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 117
 118         // Get NHM report
 119         odm_GetNHMCounterStatistics(pDM_Odm);
 120
 121         // Reset NHM counter
 122         odm_NHMCounterStatisticsReset(pDM_Odm);
 123 }
 124
 125 VOID
 126 odm_GetNHMCounterStatistics(
 127         IN              PVOID                   pDM_VOID
 128         )
 129 {
 130         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 131         u4Byte          value32 = 0;\r
 132
 133         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 134                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
 135         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 136                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
 137
 138         pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
 139 }
 140
 141 VOID
 142 odm_NHMCounterStatisticsReset(
 143         IN              PVOID                   pDM_VOID
 144         )
 145 {
 146         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 147
 148         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 149         {
 150                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
 151                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
 152         }
 153         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 154         {
 155                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
 156                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
 157         }
 158 }
 159
 160 VOID
 161 odm_NHMBBInit(
 162         IN              PVOID                   pDM_VOID
 163 )
 164 {
 165         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 166
 167         pDM_Odm->adaptivity_flag = 0;
 168         pDM_Odm->tolerance_cnt = 3;
 169         pDM_Odm->NHMLastTxOkcnt = 0;
 170         pDM_Odm->NHMLastRxOkcnt = 0;
 171         pDM_Odm->NHMCurTxOkcnt = 0;
 172         pDM_Odm->NHMCurRxOkcnt = 0;
 173 }
 174
 175 //
 176 VOID
 177 odm_NHMBB(
 178         IN              PVOID                   pDM_VOID
 179 )
 180 {
 181         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 182         u4Byte          value32;
 183         //u1Byte        test_status;
 184         //PFALSE_ALARM_STATISTICS pFalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
 185
 186         pDM_Odm->NHMCurTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->NHMLastTxOkcnt;
 187         pDM_Odm->NHMCurRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->NHMLastRxOkcnt;
 188         pDM_Odm->NHMLastTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast);
 189         pDM_Odm->NHMLastRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast);
 190         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NHM_cnt_0=%d, NHMCurTxOkcnt = %llu, NHMCurRxOkcnt = %llu\n",
 191                 pDM_Odm->NHM_cnt_0, pDM_Odm->NHMCurTxOkcnt, pDM_Odm->NHMCurRxOkcnt));
 192
 193
 194         if ( (pDM_Odm->NHMCurTxOkcnt) + 1 > (u8Byte)(pDM_Odm->NHMCurRxOkcnt<<2) + 1)            //Tx > 4*Rx possible for adaptivity test
 195         {
 196                 if(pDM_Odm->NHM_cnt_0 >= 190 || pDM_Odm->adaptivity_flag == TRUE)
 197                 {
 198                         //Enable EDCCA since it is possible running Adaptivity testing
 199                         //test_status = 1;
 200                         pDM_Odm->adaptivity_flag = TRUE;
 201                         ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0);     //don't ignore EDCCA     reg520[15]=0\14
 202                         ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);  //reg524[11]=1
 203                         pDM_Odm->tolerance_cnt = 0;
 204 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 205                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
 206                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
 207 #endif
 208                 }
 209                 else
 210                 {
 211                         if(pDM_Odm->tolerance_cnt<3)
 212                                 pDM_Odm->tolerance_cnt = pDM_Odm->tolerance_cnt + 1;
 213                         else
 214                                 pDM_Odm->tolerance_cnt = 4;
 215                         //test_status = 5;
 216                         if(pDM_Odm->tolerance_cnt > 3)
 217                         {
 218                                 //test_status = 3;
 219 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 220                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
 221                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
 222 #else
 223                                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1);     //ignore EDCCA  reg520[15]=1
 224                                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0);          //reg524[11]=0
 225 #endif
 226                                 pDM_Odm->adaptivity_flag = FALSE;
 227                         }
 228                 }
 229         }
 230         else    // TX<RX
 231         {
 232                 if(pDM_Odm->adaptivity_flag == TRUE && pDM_Odm->NHM_cnt_0 <= 200)
 233                 {
 234                         //test_status = 2;
 235                         ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0);     //don't ignore EDCCA     reg520[15]=0\14
 236                         ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);  //reg524[11]=1
 237                         pDM_Odm->tolerance_cnt = 0;
 238 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 239                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
 240                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
 241 #endif
 242                 }
 243                 else
 244                 {
 245                         if(pDM_Odm->tolerance_cnt<3)
 246                                 pDM_Odm->tolerance_cnt = pDM_Odm->tolerance_cnt + 1;
 247                         else
 248                                 pDM_Odm->tolerance_cnt = 4;
 249                         //test_status = 5;
 250                         if(pDM_Odm->tolerance_cnt >3)
 251                         {
 252                                 //test_status = 4;
 253 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 254                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
 255                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
 256 #else
 257                                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1);     //ignore EDCCA  reg520[15]=1
 258                                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0);          //reg524[11]=0
 259 #endif
 260                                 pDM_Odm->adaptivity_flag = FALSE;
 261                         }
 262                 }
 263         }
 264
 265         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("adaptivity_flag = %d\n ", pDM_Odm->adaptivity_flag));
 266 }
 267
 268 VOID
 269 odm_SearchPwdBLowerBound(
 270         IN              PVOID           pDM_VOID,
 271         IN              u1Byte          IGI_target
 272 )
 273 {
 274         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 275         u4Byte                  value32 =0;
 276         u1Byte                  cnt, IGI;
 277         BOOLEAN                 bAdjust=TRUE;
 278         s1Byte                  TH_L2H_dmc, TH_H2L_dmc;
 279         s1Byte                  TH_L2H, TH_H2L, Diff;
 280
 281         IGI = 0x50; // find H2L, L2H lower bound
 282         ODM_Write_DIG(pDM_Odm, IGI);
 283
 284
 285         Diff = IGI_target -(s1Byte)IGI;
 286         TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
 287                 if(TH_L2H_dmc > 10)
 288                         TH_L2H_dmc = 10;
 289         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
 290         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 291                 {
 292                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
 293                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
 294                 }
 295         else
 296                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
 297
 298         ODM_delay_ms(5);\r
 299
 300                 while(bAdjust)
 301                         {
 302                         for(cnt=0; cnt<20; cnt ++)
 303                                 {
 304                                 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 305                                         value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);
 306                                 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 307                                         value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);
 308
 309                                 if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))
 310                                         pDM_Odm->txEdcca1 = pDM_Odm->txEdcca1 + 1;
 311                                 else if(value32 & BIT29)
 312                                         pDM_Odm->txEdcca1 = pDM_Odm->txEdcca1 + 1;
 313                                 else
 314                                         pDM_Odm->txEdcca0 = pDM_Odm->txEdcca0 + 1;
 315                                 }
 316                         //DbgPrint("txEdcca1 = %d, txEdcca0 = %d\n", pDM_Odm->txEdcca1, pDM_Odm->txEdcca0);
 317
 318                                 if(pDM_Odm->txEdcca1 > 5 )
 319                                 {
 320                                         IGI = IGI -1;
 321                                         TH_L2H_dmc = TH_L2H_dmc + 1;
 322                                                 if(TH_L2H_dmc > 10)
 323                                                         TH_L2H_dmc = 10;
 324                                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
 325                                         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 326                                         {
 327                                                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
 328                                                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
 329                                         }
 330                                         else
 331                                                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
 332
 333                                         pDM_Odm->TxHangFlg = TRUE;
 334                                         pDM_Odm->txEdcca1 = 0;
 335                                         pDM_Odm->txEdcca0 = 0;
 336
 337                                         if(TH_L2H_dmc == 10)
 338                                                 {
 339                                                 bAdjust = FALSE;
 340                                                 pDM_Odm->TxHangFlg = FALSE;
 341                                                 pDM_Odm->txEdcca1 = 0;
 342                                                 pDM_Odm->txEdcca0 = 0;
 343                                                 pDM_Odm->H2L_lb = TH_H2L_dmc;
 344                                                 pDM_Odm->L2H_lb = TH_L2H_dmc;
 345                                                 pDM_Odm->Adaptivity_IGI_upper = IGI;
 346                                                 }
 347                                         }
 348                                 else
 349                                 {
 350                                         bAdjust = FALSE;
 351                                         pDM_Odm->TxHangFlg = FALSE;
 352                                         pDM_Odm->txEdcca1 = 0;
 353                                         pDM_Odm->txEdcca0 = 0;
 354                                         pDM_Odm->H2L_lb = TH_H2L_dmc;
 355                                         pDM_Odm->L2H_lb = TH_L2H_dmc;
 356                                         pDM_Odm->Adaptivity_IGI_upper = IGI;
 357                                 }
 358                         }
 359
 360
 361 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI = 0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", IGI, pDM_Odm->H2L_lb , pDM_Odm->L2H_lb));
 362
 363 }
 364
 365 VOID
 366 odm_AdaptivityInit(
 367         IN      PVOID           pDM_VOID
 368 )
 369 {
 370         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 371 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
 372         PADAPTER                pAdapter        = pDM_Odm->Adapter;
 373         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);
 374         pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;
 375 #endif
 376
 377 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
 378
 379         if(pDM_Odm->Carrier_Sense_enable == FALSE)\r
 380         {
 381                 pDM_Odm->TH_L2H_ini = 0xf7; // -7
 382         }
 383         else
 384                 pDM_Odm->TH_L2H_ini = 0xa; \r
 385
 386         pDM_Odm->AdapEn_RSSI = 20;
 387         pDM_Odm->TH_EDCCA_HL_diff = 7;
 388
 389 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 390
 391         if(pDM_Odm->Carrier_Sense_enable){
 392                 pDM_Odm->TH_L2H_ini = 10;
 393                 pDM_Odm->TH_EDCCA_HL_diff = 3;
 394                 pDM_Odm->AdapEn_RSSI = 30;
 395         }
 396         else
 397         {
 398                 pDM_Odm->TH_L2H_ini = 0xf7;
 399                 pDM_Odm->TH_EDCCA_HL_diff = 7;
 400                 pDM_Odm->AdapEn_RSSI = 20;
 401         }
 402
 403         pDM_Odm->TH_L2H_ini_mode2 = 20;
 404         pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
 405         pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
 406         pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;
 407
 408 #endif
 409
 410         pDM_Odm->IGI_Base = 0x32;
 411         pDM_Odm->IGI_target = 0x1c;
 412         pDM_Odm->ForceEDCCA = 0;
 413         pDM_Odm->NHM_disable = FALSE;
 414         pDM_Odm->TxHangFlg = TRUE;
 415         pDM_Odm->txEdcca0 = 0;
 416         pDM_Odm->txEdcca1 = 0;
 417         pDM_Odm->H2L_lb= 0;
 418         pDM_Odm->L2H_lb= 0;
 419         pDM_Odm->Adaptivity_IGI_upper = 0;
 420         odm_NHMBBInit(pDM_Odm);
 421
 422         ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted
 423 }
 424
 425
 426 VOID
 427 odm_Adaptivity(
 428         IN              PVOID                   pDM_VOID,
 429         IN              u1Byte                  IGI
 430 )
 431 {
 432         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 433         s1Byte TH_L2H_dmc, TH_H2L_dmc;\r
 434         s1Byte Diff, IGI_target;
 435         BOOLEAN EDCCA_State = FALSE;
 436
 437 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 438         PADAPTER                pAdapter        = pDM_Odm->Adapter;
 439         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 440         BOOLEAN         bFwCurrentInPSMode=FALSE;
 441         PMGNT_INFO                              pMgntInfo = &(pAdapter->MgntInfo);
 442
 443         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
 444
 445         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
 446         if(bFwCurrentInPSMode)
 447                 return;
 448 #endif
 449
 450         if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
 451         {
 452                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
 453                 // Add by Neil Chen to enable edcca to MP Platform
 454 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 455                 // Adjust EDCCA.
 456                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 457                         odm_DynamicEDCCA(pDM_Odm);
 458 #endif
 459                 return;
 460         }
 461         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
 462         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
 463                 pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
 464
 465         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 466                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
 467
 468         if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
 469                 IGI_target = pDM_Odm->IGI_Base;
 470         else if(*pDM_Odm->pBandWidth == ODM_BW40M)
 471                 IGI_target = pDM_Odm->IGI_Base + 2;
 472         else if(*pDM_Odm->pBandWidth == ODM_BW80M)
 473                 IGI_target = pDM_Odm->IGI_Base + 2;
 474         else
 475                 IGI_target = pDM_Odm->IGI_Base;
 476         pDM_Odm->IGI_target = (u1Byte) IGI_target;
 477
 478         //Search pwdB lower bound
 479         if(pDM_Odm->TxHangFlg == TRUE)
 480         {
 481                 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 482                         ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
 483                 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 484                         ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
 485                 odm_SearchPwdBLowerBound(pDM_Odm, pDM_Odm->IGI_target );
 486         }
 487
 488         if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) // Band4 doesn't need adaptivity
 489         {
 490                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 491                 {
 492                    ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
 493                    ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
 494                 }
 495                 else
 496                    ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
 497                 return;
 498         }
 499
 500         if(!pDM_Odm->ForceEDCCA)
 501         {
 502                 if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
 503                         EDCCA_State = 1;
 504                 else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
 505                         EDCCA_State = 0;
 506         }
 507         else
 508                 EDCCA_State = 1;
 509 \r
 510         if(pDM_Odm->bLinked && pDM_Odm->Carrier_Sense_enable == FALSE && pDM_Odm->NHM_disable == FALSE &&pDM_Odm->TxHangFlg == FALSE)\r
 511                 odm_NHMBB(pDM_Odm);\r
 512
 513         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
 514                 (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State));
 515
 516         if(EDCCA_State == 1)
 517         {
 518                 Diff = IGI_target -(s1Byte)IGI;
 519                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
 520                 if(TH_L2H_dmc > 10)
 521                         TH_L2H_dmc = 10;
 522
 523                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
 524
 525                 //replace lower bound to prevent EDCCA always equal 1
 526                         if(TH_H2L_dmc < pDM_Odm->H2L_lb)
 527                                 TH_H2L_dmc = pDM_Odm->H2L_lb;
 528                         if(TH_L2H_dmc < pDM_Odm->L2H_lb)
 529                                 TH_L2H_dmc = pDM_Odm->L2H_lb;
 530         }
 531         else
 532         {
 533                 TH_L2H_dmc = 0x7f;
 534                 TH_H2L_dmc = 0x7f;
 535         }
 536         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
 537                 IGI, TH_L2H_dmc, TH_H2L_dmc));
 538         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 539         {
 540                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
 541                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
 542         }
 543         else
 544                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
 545 }
 546 \r
 547 int
 548 getIGIForDiff(int value_IGI)
 549 {
 550         #define ONERCCA_LOW_TH          0x30
 551         #define ONERCCA_LOW_DIFF        8
 552
 553         if (value_IGI < ONERCCA_LOW_TH) {
 554                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
 555                         return ONERCCA_LOW_TH;
 556                 else
 557                         return value_IGI + ONERCCA_LOW_DIFF;
 558         } else {
 559                 return value_IGI;
 560         }
 561 }
 562 \r
 563 VOID
 564 ODM_Write_DIG(
 565         IN      PVOID                   pDM_VOID,
 566         IN      u1Byte                  CurrentIGI
 567         )
 568 {
 569         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 570         pDIG_T                  pDM_DigTable = &pDM_Odm->DM_DigTable;
 571
 572         if(pDM_DigTable->bStopDIG)
 573         {
 574                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Stop Writing IGI\n"));
 575                 return;
 576         }
 577
 578         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n",
 579                 ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
 580
 581         if(pDM_DigTable->CurIGValue != CurrentIGI)
 582         {
 583                 //1 Check initial gain by upper bound
 584                 if(!pDM_DigTable->bPSDInProgress)
 585                 {
 586                         if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
 587                         {
 588                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_TRACE, ("CurrentIGI(0x%02x) is larger than upper bound !!\n",pDM_DigTable->rx_gain_range_max));
 589                                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 590                         }
 591
 592                 }
 593
 594                 //1 Set IGI value
 595                 if(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE))
 596                 {
 597                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 598
 599                         if(pDM_Odm->RFType > ODM_1T1R)
 600                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 601
 602                         if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R))
 603                         {
 604                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 605                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 606                         }
 607                 }
 608                 else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
 609                 {
 610                         switch(*(pDM_Odm->pOnePathCCA))
 611                         {
 612                                 case ODM_CCA_2R:
 613                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 614
 615                                         if(pDM_Odm->RFType > ODM_1T1R)
 616                                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 617
 618                                         if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R))
 619                                         {
 620                                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 621                                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 622                                         }
 623                                         break;
 624                                 case ODM_CCA_1R_A:
 625                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 626                                         if(pDM_Odm->RFType != ODM_1T1R)
 627                                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
 628                                         break;
 629                                 case ODM_CCA_1R_B:
 630                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
 631                                         if(pDM_Odm->RFType != ODM_1T1R)
 632                                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
 633                                         break;
 634                         }
 635                 }
 636                 pDM_DigTable->CurIGValue = CurrentIGI;
 637         }
 638
 639         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_TRACE, ("CurrentIGI(0x%02x). \n",CurrentIGI));
 640
 641 }
 642 \r
 643 VOID
 644 odm_PauseDIG(
 645         IN              PVOID                                   pDM_VOID,\r
 646         IN              ODM_Pause_DIG_TYPE              PauseType,
 647         IN              u1Byte                                  IGIValue
 648 )
 649 {
 650         PDM_ODM_T                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 651         pDIG_T                          pDM_DigTable = &pDM_Odm->DM_DigTable;
 652         static  BOOLEAN         bPaused = FALSE;
 653
 654         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG()=========>\n"));
 655
 656 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 657         if(*pDM_DigTable->pbP2pLinkInProgress)
 658         {
 659                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): P2P in progress !!\n"));
 660                 return;
 661         }
 662 #endif
 663
 664         if((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) && pDM_Odm->TxHangFlg == TRUE)
 665         {
 666                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Dynamic adjust threshold in progress !!\n"));
 667                 return;
 668         }
 669
 670         if(!bPaused && (!(pDM_Odm->SupportAbility & ODM_BB_DIG) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)))
 671         {
 672                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
 673                 return;
 674         }
 675
 676         switch(PauseType)
 677         {
 678                 //1 Pause DIG
 679                 case ODM_PAUSE_DIG:
 680                         //2 Disable DIG
 681                         ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_DIG));
 682                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Pause DIG !!\n"));
 683
 684                         //2 Backup IGI value
 685                         if(!bPaused)
 686                         {
 687                                 pDM_DigTable->IGIBackup = pDM_DigTable->CurIGValue;
 688                                 bPaused = TRUE;
 689                         }
 690                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Backup IGI  = 0x%x\n", pDM_DigTable->IGIBackup));
 691
 692                         //2 Write new IGI value
 693                         ODM_Write_DIG(pDM_Odm, IGIValue);
 694                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write new IGI = 0x%x\n", IGIValue));
 695                         break;
 696
 697                 //1 Resume DIG
 698                 case ODM_RESUME_DIG:
 699                         if(bPaused)
 700                         {
 701                                 //2 Write backup IGI value
 702                                 ODM_Write_DIG(pDM_Odm, pDM_DigTable->IGIBackup);
 703                                 bPaused = FALSE;
 704                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write original IGI = 0x%x\n", pDM_DigTable->IGIBackup));
 705
 706                                 //2 Enable DIG
 707                                 ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_DIG);
 708                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Resume DIG !!\n"));
 709                         }
 710                         break;
 711
 712                 default:
 713                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong  type !!\n"));
 714                         break;
 715         }
 716 }
 717
 718 BOOLEAN
 719 odm_DigAbort(
 720         IN              PVOID                   pDM_VOID
 721         )
 722 {
 723         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 724 \r
 725 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 726         prtl8192cd_priv                         priv = pDM_Odm->priv;\r
 727 #elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 728         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 729         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;\r
 730 #endif\r
 731 \r
 732         //SupportAbility
 733         if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))\r
 734         {\r
 735                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_FA_CNT is disabled\n"));
 736                 return  TRUE;\r
 737         }\r
 738 \r
 739         //SupportAbility\r
 740         if(!(pDM_Odm->SupportAbility & ODM_BB_DIG))\r
 741         {       \r
 742                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_DIG is disabled\n"));
 743                 return  TRUE;\r
 744         }\r
 745 \r
 746         //ScanInProcess\r
 747         if(*(pDM_Odm->pbScanInProcess))\r
 748         {\r
 749                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress \n"));
 750                 return  TRUE;\r
 751         }\r
 752 \r
 753         //add by Neil Chen to avoid PSD is processing\r
 754         if(pDM_Odm->bDMInitialGainEnable == FALSE)\r
 755         {\r
 756                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing \n"));
 757                 return  TRUE;\r
 758         }\r
 759 \r
 760 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 761         #if OS_WIN_FROM_WIN7(OS_VERSION)\r
 762         if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
 763         {
 764                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test \n"));
 765                 return  TRUE;
 766         }
 767         #endif\r
 768 \r
 769         if(pDM_Odm->bBtHsOperation)\r
 770         {\r
 771                 odm_DigForBtHsMode(pDM_Odm);\r
 772         }       \r
 773 \r
 774         if(!(pDM_Odm->SupportICType &(ODM_RTL8723A|ODM_RTL8188E)))\r
 775         {\r
 776                 if(pRX_HP_Table->RXHP_flag == 1)\r
 777                 {\r
 778                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In RXHP Operation \n"));
 779                         return  TRUE;   \r
 780                 }\r
 781         }\r
 782 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 783         #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV      \r
 784         if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
 785         {
 786                 printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min);
 787                 ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi);
 788                 return  TRUE;
 789         }
 790         #endif\r
 791 #else\r
 792         if (!(priv->up_time > 5))\r
 793         {\r
 794                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG Operation Period \n"));
 795                 return  TRUE;\r
 796         }\r
 797 #endif\r
 798 \r
 799         return  FALSE;
 800 }\r
 801 \r
 802 VOID
 803 odm_DIGInit(
 804         IN              PVOID           pDM_VOID
 805         )
 806 {
 807         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 808         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
 809         PFALSE_ALARM_STATISTICS         FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
 810
 811         pDM_DigTable->bStopDIG = FALSE;
 812         pDM_DigTable->bPSDInProgress = FALSE;
 813         pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
 814         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 815         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 816         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 817         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 818         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 819         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 820         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 821         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 822         pDM_DigTable->CurCCK_CCAThres = 0x83;
 823         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 824         pDM_DigTable->LargeFAHit = 0;
 825         pDM_DigTable->Recover_cnt = 0;
 826         pDM_DigTable->bMediaConnect_0 = FALSE;
 827         pDM_DigTable->bMediaConnect_1 = FALSE;
 828
 829         //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error
 830         pDM_Odm->bDMInitialGainEnable = TRUE;
 831
 832 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 833         pDM_DigTable->DIG_Dynamic_MIN_0 = 0x25;
 834         pDM_DigTable->DIG_Dynamic_MIN_1 = 0x25;
 835
 836         // For AP\ ADSL modified DIG
 837         pDM_DigTable->bTpTarget = FALSE;
 838         pDM_DigTable->bNoiseEst = TRUE;
 839         pDM_DigTable->IGIOffset_A = 0;
 840         pDM_DigTable->IGIOffset_B = 0;
 841         pDM_DigTable->TpTrainTH_min = 0;
 842
 843         // For RTL8881A
 844         FalseAlmCnt->Cnt_Ofdm_fail_pre = 0;
 845
 846         //Dyanmic EDCCA
 847         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 848         {
 849                 ODM_SetBBReg(pDM_Odm, 0xC50, 0xFFFF0000, 0xfafd);
 850         }
 851 #else
 852         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 853         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 854
 855         //To Initi BT30 IGI
 856         pDM_DigTable->BT30_CurIGI=0x32;\r
 857 \r
 858         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 859         *pDM_DigTable->pbP2pLinkInProgress= FALSE;\r
 860         #endif\r
 861 #endif
 862
 863         if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA))
 864         {
 865                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 866                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 867         }
 868         else
 869         {
 870                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 871                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 872         }
 873
 874 }
 875 \r
 876
 877 VOID
 878 odm_DIG(
 879         IN              PVOID           pDM_VOID
 880         )
 881 {
 882         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 883 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 884         PADAPTER                                        pAdapter        = pDM_Odm->Adapter;\r
 885         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);\r
 886 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 887         prtl8192cd_priv                         priv = pDM_Odm->priv;\r
 888         PSTA_INFO_T                             pEntry;\r
 889 #endif\r
 890 \r
 891         // Common parameters
 892         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;\r
 893         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 894         BOOLEAN                                         FirstConnect,FirstDisConnect;
 895         u1Byte                                          DIG_MaxOfMin, DIG_Dynamic_MIN, i;
 896         u1Byte                                          dm_dig_max, dm_dig_min;\r
 897         u1Byte                                          CurrentIGI = pDM_DigTable->CurIGValue;\r
 898         u1Byte                                          offset;\r
 899         u4Byte                                          dm_FA_thres[3];\r
 900         u1Byte                                          Adap_IGI_Upper = 0;
 901         u4Byte                                          TxTp = 0, RxTp = 0;\r
 902         BOOLEAN                                         bDFSBand = FALSE;\r
 903         BOOLEAN                                         bPerformance = TRUE, bFirstTpTarget = FALSE, bFirstCoverage = FALSE;\r
 904 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 905         u4Byte                                          TpTrainTH_MIN = DM_DIG_TP_Target_TH0;\r
 906         static          u1Byte                  TimeCnt = 0;\r
 907 #endif\r
 908 \r
 909         if(odm_DigAbort(pDM_Odm) == TRUE)\r
 910                 return;\r
 911 \r
 912         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()===========================>\n\n"));
 913 \r
 914         if(pDM_Odm->adaptivity_flag == TRUE)
 915                 Adap_IGI_Upper = pDM_Odm->Adaptivity_IGI_upper;
 916
 917 \r
 918         //1 Update status
 919         if(pDM_Odm->SupportICType == ODM_RTL8192D)
 920         {
 921                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
 922                 {
 923                         if(*(pDM_Odm->pbMasterOfDMSP))\r
 924                         {
 925                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;\r
 926                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
 927                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
 928                         }
 929                         else\r
 930                         {
 931                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;\r
 932                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
 933                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
 934                         }
 935                 }
 936                 else
 937                 {
 938                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)\r
 939                         {
 940                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;\r
 941                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
 942                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
 943                         }
 944                         else\r
 945                         {
 946                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;\r
 947                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
 948                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
 949                         }
 950                 }
 951         }\r
 952         else
 953         {
 954                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 955                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
 956                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);\r
 957         }
 958
 959 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 960         //1 Noise Floor Estimate
 961         //pDM_DigTable->bNoiseEst = (FirstConnect)?TRUE:pDM_DigTable->bNoiseEst;
 962         //odm_InbandNoiseCalculate (pDM_Odm);
 963
 964         //1 Mode decision
 965         if(pDM_Odm->bLinked)
 966         {
 967                 //2 Calculate total TP
 968                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
 969                 {
 970                         pEntry = pDM_Odm->pODM_StaInfo[i];
 971                         if(IS_STA_VALID(pEntry))
 972                         {
 973                                 RxTp += (u4Byte)(pEntry->rx_byte_cnt_LowMAW>>7);
 974                                 TxTp += (u4Byte)(pEntry->tx_byte_cnt_LowMAW>>7);                        //Kbps
 975                         }
 976                 }
 977                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TX TP = %dkbps, RX TP = %dkbps\n", TxTp, RxTp));
 978         }
 979
 980         switch(pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable)
 981         {
 982                 case 0:
 983                 {
 984                         bPerformance = TRUE;
 985                         break;
 986                 }
 987                 case 1:
 988                 {
 989                         bPerformance = FALSE;
 990                         break;
 991                 }
 992                 case 2:
 993                 {
 994                         if(pDM_Odm->bLinked)
 995                         {
 996                                 if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH0)
 997                                         TpTrainTH_MIN = pDM_DigTable->TpTrainTH_min;
 998
 999                                 if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH1)
1000                                         TpTrainTH_MIN = DM_DIG_TP_Target_TH1;
1001
1002                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TP training mode lower bound = %dkbps\n", TpTrainTH_MIN));
1003
1004                                 //2 Decide DIG mode by total TP
1005                                 if((TxTp + RxTp) > DM_DIG_TP_Target_TH1)                        // change to performance mode
1006                                 {
1007                                         bFirstTpTarget = (!pDM_DigTable->bTpTarget)?TRUE:FALSE;
1008                                         pDM_DigTable->bTpTarget = TRUE;
1009                                         bPerformance = TRUE;
1010                                 }
1011                                 else if((TxTp + RxTp) < TpTrainTH_MIN)  // change to coverage mode
1012                                 {
1013                                         bFirstCoverage = (pDM_DigTable->bTpTarget)?TRUE:FALSE;
1014
1015                                         if(TimeCnt < DM_DIG_TP_Training_Period)
1016                                         {
1017                                                 pDM_DigTable->bTpTarget = FALSE;
1018                                                 bPerformance = FALSE;
1019                                                 TimeCnt++;
1020                                         }
1021                                         else
1022                                         {
1023                                                 pDM_DigTable->bTpTarget = TRUE;
1024                                                 bPerformance = TRUE;
1025                                                 bFirstTpTarget = TRUE;
1026                                                 TimeCnt = 0;
1027                                         }
1028                                 }
1029                                 else                                                                            // remain previous mode
1030                                 {
1031                                         bPerformance = pDM_DigTable->bTpTarget;
1032
1033                                         if(!bPerformance)
1034                                         {
1035                                                 if(TimeCnt < DM_DIG_TP_Training_Period)
1036                                                         TimeCnt++;
1037                                                 else
1038                                                 {
1039                                                         pDM_DigTable->bTpTarget = TRUE;
1040                                                         bPerformance = TRUE;
1041                                                         bFirstTpTarget = TRUE;
1042                                                         TimeCnt = 0;
1043                                                 }
1044                                         }
1045                                 }
1046
1047                                 if(!bPerformance)
1048                                         pDM_DigTable->TpTrainTH_min = RxTp + TxTp;
1049
1050                         }
1051                         else
1052                         {
1053                                 bPerformance = FALSE;
1054                                 pDM_DigTable->TpTrainTH_min = 0;
1055                         }
1056                         break;
1057                 }
1058                 default:
1059                         bPerformance = TRUE;
1060         }
1061
1062         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d  ======\n", pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable));
1063         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== bPerformance = %d ======\n", bPerformance));
1064 #endif
1065
1066         //1 Boundary Decision
1067         if((pDM_Odm->SupportICType & ODM_RTL8192C) && (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)))
1068         {
1069                 //2 High power case
1070                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1071                 {
1072                         dm_dig_max = DM_DIG_MAX_AP_HP;
1073                         dm_dig_min = DM_DIG_MIN_AP_HP;
1074                 }
1075                 else
1076                 {
1077                         dm_dig_max = DM_DIG_MAX_NIC_HP;
1078                         dm_dig_min = DM_DIG_MIN_NIC_HP;
1079                 }
1080                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
1081         }
1082         else
1083         {\r
1084 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1085                 //2 For AP\ADSL\r
1086                 if(!bPerformance)\r
1087                 {\r
1088                         dm_dig_max = DM_DIG_MAX_AP_COVERAGR;\r
1089                         dm_dig_min = DM_DIG_MIN_AP_COVERAGE;\r
1090                         DIG_MaxOfMin = DM_DIG_MAX_OF_MIN_COVERAGE;\r
1091                 }\r
1092                 else\r
1093                 {\r
1094                         dm_dig_max = DM_DIG_MAX_AP;\r
1095                         dm_dig_min = DM_DIG_MIN_AP;\r
1096                         DIG_MaxOfMin = DM_DIG_MAX_OF_MIN;
1097                 }\r
1098 \r
1099                 //4 DFS band\r
1100                 if (((*pDM_Odm->pChannel>= 52) &&(*pDM_Odm->pChannel <= 64)) ||\r
1101                         ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140)))\r
1102                 {\r
1103                         bDFSBand = TRUE;\r
1104                         dm_dig_min = DM_DIG_MIN_AP_DFS;\r
1105                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): ====== In DFS band ======\n"));
1106                 }\r
1107
1108                 //4 TX2path\r
1109                 if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B))\r
1110                                 dm_dig_max = 0x2A;\r
1111
1112 #if RTL8192E_SUPPORT
1113 #ifdef HIGH_POWER_EXT_LNA
1114                 if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA))
1115                         dm_dig_max = 0x42;
1116 #endif
1117 #endif
1118
1119 #else\r
1120                 //2 For WIN\CE\r
1121                 if(pDM_Odm->SupportICType >= ODM_RTL8188E)\r
1122                         dm_dig_max = 0x5A;\r
1123                 else\r
1124                         dm_dig_max = DM_DIG_MAX_NIC;\r
1125                 \r
1126                 if(pDM_Odm->SupportICType != ODM_RTL8821)\r
1127                         dm_dig_min = DM_DIG_MIN_NIC;\r
1128                 else\r
1129                         dm_dig_min = 0x1C;\r
1130
1131                 DIG_MaxOfMin = DM_DIG_MAX_AP;
1132 #endif  \r
1133         }
1134         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min));
1135 \r
1136 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1137         // for P2P case\r
1138         if(0 < *pDM_Odm->pu1ForcedIgiLb)
1139         {
1140                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): P2P case: Force IGI lb to: %u !!!!!!\n", *pDM_Odm->pu1ForcedIgiLb));
1141                 dm_dig_min = *pDM_Odm->pu1ForcedIgiLb;
1142                 dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1);
1143         }
1144 #endif
1145 \r
1146         //1 Adjust boundary by RSSI\r
1147         if(pDM_Odm->bLinked && bPerformance)\r
1148         {\r
1149                 //2 Modify DIG upper bound\r
1150 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1151                 offset = 15;\r
1152 #else\r
1153                 //4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT\r
1154                 if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723A)) && (pDM_Odm->bBtLimitedDig==1))
1155                 {
1156                         offset = 10;\r
1157                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Coex. case: Force upper bound to RSSI + %d !!!!!!\n", offset));
1158                 }
1159                 else\r
1160                         offset = 15;\r
1161 #endif\r
1162
1163                 if((pDM_Odm->RSSI_Min + offset) > dm_dig_max )\r
1164                         pDM_DigTable->rx_gain_range_max = dm_dig_max;\r
1165                 else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min )
1166                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
1167                 else\r
1168                         pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset;\r
1169
1170 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
1171                 //2 Modify DIG lower bound\r
1172                 //if(pDM_Odm->bOneEntryOnly)\r
1173                 {
1174                         if(pDM_Odm->RSSI_Min < dm_dig_min)\r
1175                                 DIG_Dynamic_MIN = dm_dig_min;\r
1176                         else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)\r
1177                                 DIG_Dynamic_MIN = DIG_MaxOfMin;\r
1178                         else\r
1179                                 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;\r
1180                 }\r
1181 #else\r
1182                 {\r
1183                         //4 For AP\r
1184 #ifdef __ECOS\r
1185                         HAL_REORDER_BARRIER();\r
1186 #else\r
1187                         rmb();\r
1188 #endif\r
1189                         if (bDFSBand)\r
1190                         {\r
1191                                 DIG_Dynamic_MIN = dm_dig_min;\r
1192                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force lower bound to 0x%x after link !!!!!!\n", dm_dig_min));
1193                         }\r
1194                         else \r
1195                         {\r
1196                                 if(pDM_Odm->RSSI_Min < dm_dig_min)\r
1197                                         DIG_Dynamic_MIN = dm_dig_min;\r
1198                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)\r
1199                                         DIG_Dynamic_MIN = DIG_MaxOfMin;\r
1200                                 else\r
1201                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;\r
1202                         }\r
1203                 }\r
1204 #endif\r
1205         }
1206         else
1207         {\r
1208 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1209                 if(bPerformance && bDFSBand)\r
1210                 {\r
1211                         pDM_DigTable->rx_gain_range_max = 0x28;\r
1212                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force upper bound to 0x%x before link !!!!!!\n", pDM_DigTable->rx_gain_range_max));
1213                 }\r
1214                 else\r
1215 #endif\r
1216                 {\r
1217                         pDM_DigTable->rx_gain_range_max = dm_dig_max;\r
1218                 }\r
1219                 DIG_Dynamic_MIN = dm_dig_min;\r
1220         }\r
1221
1222         //1 Force Lower Bound for AntDiv
1223         if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly)\r
1224         {\r
1225                 if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
1226                 {\r
1227                         if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV ||pDM_Odm->AntDivType == S0S1_SW_ANTDIV)\r
1228                         {\r
1229                                 if(pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin)\r
1230                                         DIG_Dynamic_MIN = DIG_MaxOfMin;\r
1231                                 else\r
1232                                         DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;\r
1233                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: Force lower bound to 0x%x !!!!!!\n", DIG_Dynamic_MIN));
1234                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: RSSI_max = 0x%x !!!!!!\n", pDM_DigTable->AntDiv_RSSI_max));
1235                         }\r
1236                 }\r
1237         }\r
1238         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n",\r
1239                 pDM_DigTable->rx_gain_range_max, DIG_Dynamic_MIN));\r
1240         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Link status: bLinked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n\n",\r
1241                 pDM_Odm->bLinked, pDM_Odm->RSSI_Min, FirstConnect, FirstDisConnect));
1242 \r
1243         //1 Modify DIG lower bound, deal with abnormal case
1244         //2 Abnormal false alarm case
1245 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1246         if(bDFSBand)\r
1247         {
1248                 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN;\r
1249         }
1250         else\r
1251 #endif\r
1252         {\r
1253                 if(FirstDisConnect)
1254                 {\r
1255                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN;\r
1256                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN;\r
1257                 }\r
1258                 else\r
1259                         pDM_DigTable->rx_gain_range_min = odm_ForbiddenIGICheck(pDM_Odm, DIG_Dynamic_MIN, CurrentIGI);
1260         }
1261 \r
1262         //2 Abnormal # beacon case
1263 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1264                 if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(pAdapter))
1265                         pDM_Odm->bsta_state = TRUE;
1266 #endif\r
1267 \r
1268
1269 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
1270         if(pDM_Odm->bLinked && !FirstConnect)
1271         {\r
1272                 if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pDM_Odm->bsta_state))
1273                 {
1274                         pDM_DigTable->rx_gain_range_min = dm_dig_min;
1275                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x !!!!!!\n\n",
1276                                 pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, pDM_DigTable->rx_gain_range_min));
1277                 }
1278         }\r
1279 #endif\r
1280 \r
1281         //2 Abnormal lower bound case
1282         if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max)
1283         {
1284                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
1285                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal lower bound case: Force lower bound to 0x%x !!!!!!\n\n",pDM_DigTable->rx_gain_range_min));
1286         }
1287 \r
1288
1289         //1 False alarm threshold decision\r
1290         odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres);\r
1291         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2]));
1292 \r
1293         //1 Adjust initial gain by false alarm
1294         if(pDM_Odm->bLinked && bPerformance)
1295         {\r
1296                 //2 After link
1297                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI after link\n"));
1298
1299                 if(bFirstTpTarget || (FirstConnect && bPerformance))
1300                 {       \r
1301                         pDM_DigTable->LargeFAHit = 0;\r
1302                         \r
1303 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1304                         if(bDFSBand)\r
1305                         {\r
1306                                 if(pDM_Odm->RSSI_Min > 0x28)\r
1307                                         CurrentIGI = 0x28;\r
1308                                 else\r
1309                                         CurrentIGI = pDM_Odm->RSSI_Min;\r
1310                                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: One-shot to 0x28 upmost!!!!!!\n"));
1311                         }\r
1312                         else\r
1313 #endif\r
1314                         {\r
1315                                 if(pDM_Odm->RSSI_Min < DIG_MaxOfMin)\r
1316                                 {\r
1317                                         if(CurrentIGI < pDM_Odm->RSSI_Min)\r
1318                                                 CurrentIGI = pDM_Odm->RSSI_Min;\r
1319                                 }\r
1320                                 else\r
1321                                 {\r
1322                                         if(CurrentIGI < DIG_MaxOfMin)\r
1323                                                 CurrentIGI = DIG_MaxOfMin;\r
1324                                 }\r
1325 \r
1326 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
1327                                 if(pDM_Odm->SupportICType == ODM_RTL8812)\r
1328                                         ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF);\r
1329 #endif\r
1330                         }\r
1331
1332                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First connect case: IGI does on-shot to 0x%x\n", CurrentIGI));
1333
1334                 }\r
1335                 else\r
1336                 {\r
1337                         if(pFalseAlmCnt->Cnt_all > dm_FA_thres[2])\r
1338                                 CurrentIGI = CurrentIGI + 4;
1339                         else if (pFalseAlmCnt->Cnt_all > dm_FA_thres[1])\r
1340                                 CurrentIGI = CurrentIGI + 2;
1341                         else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0])\r
1342                                 CurrentIGI = CurrentIGI - 2;
1343
1344                         //4 Abnormal # beacon case
1345 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1346                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(pAdapter)) //STA mode is linked to AP\r
1347                                 pDM_Odm->bsta_state = _TRUE;\r
1348 #endif\r
1349 \r
1350 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
1351                         if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state))\r
1352                         {                                               \r
1353                                 CurrentIGI = pDM_DigTable->rx_gain_range_min;\r
1354                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n",
1355                                         pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, CurrentIGI));
1356                         }\r
1357 #endif\r
1358                 }\r
1359         }
1360         else
1361         {\r
1362                 //2 Before link
1363                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n"));
1364
1365                 if(FirstDisConnect || bFirstCoverage)
1366                 {
1367                         CurrentIGI = dm_dig_min;\r
1368                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First disconnect case: IGI does on-shot to lower bound\n"));
1369                 }
1370                 else\r
1371                 {\r
1372                         if(pFalseAlmCnt->Cnt_all > dm_FA_thres[2])\r
1373                                 CurrentIGI = CurrentIGI + 4;\r
1374                         else if (pFalseAlmCnt->Cnt_all > dm_FA_thres[1])\r
1375                                 CurrentIGI = CurrentIGI + 2;\r
1376                         else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0])\r
1377                                 CurrentIGI = CurrentIGI - 2;\r
1378                 }\r
1379         }
1380 \r
1381         //1 Check initial gain by upper/lower bound
1382         if(CurrentIGI < pDM_DigTable->rx_gain_range_min)
1383                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
1384
1385         if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
1386                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
1387
1388         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x, TotalFA = %d\n\n", CurrentIGI, pFalseAlmCnt->Cnt_all));
1389
1390         //1 Force upper bound and lower bound for adaptivity
1391         if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE)
1392         {
1393                 if(CurrentIGI > Adap_IGI_Upper)
1394                         CurrentIGI = Adap_IGI_Upper;
1395
1396                 if(pDM_Odm->IGI_LowerBound != 0)
1397                 {
1398                         if(CurrentIGI < pDM_Odm->IGI_LowerBound)
1399                                 CurrentIGI = pDM_Odm->IGI_LowerBound;
1400                 }
1401                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", Adap_IGI_Upper));
1402                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adaptivity case: Force lower bound to 0x%x !!!!!!\n\n", pDM_Odm->IGI_LowerBound));
1403         }
1404
1405
1406         //1 High power RSSI threshold
1407 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)     \r
1408         if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD))
1409         {
1410                 // High power IGI lower bound
1411                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
1412                 if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND)
1413                 {
1414                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue));
1415                         //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
1416                         CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
1417                 }
1418         }
1419         if((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter))
1420         {
1421                 if(pHalData->UndecoratedSmoothedPWDB > 0x28)
1422                 {
1423                         if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
1424                         {
1425                                 //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
1426                                 CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
1427                         }
1428                 }
1429         }\r
1430 #endif
1431
1432         //1 Update status
1433 #if (RTL8192D_SUPPORT==1)
1434         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1435         {
1436                 //sherry  delete DualMacSmartConncurrent 20110517
1437                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
1438                 {
1439                         ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
1440                         if(*(pDM_Odm->pbMasterOfDMSP))\r
1441                         {
1442                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1443                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;\r
1444                         }
1445                         else\r
1446                         {
1447                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
1448                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;\r
1449                         }
1450                 }
1451                 else
1452                 {
1453                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1454                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)\r
1455                         {
1456                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1457                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;\r
1458                         }
1459                         else\r
1460                         {
1461                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
1462                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;\r
1463                         }
1464                 }
1465         }
1466         else
1467 #endif
1468         {
1469 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
1470                 if(pDM_Odm->bBtHsOperation)
1471                 {
1472                         if(pDM_Odm->bLinked)
1473                         {
1474                                 if(pDM_DigTable->BT30_CurIGI > (CurrentIGI))
1475                                         ODM_Write_DIG(pDM_Odm, CurrentIGI);
1476                                 else
1477                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);\r
1478
1479                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1480                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
1481                         }
1482                         else
1483                         {
1484                                 if(pDM_Odm->bLinkInProcess)
1485                                         ODM_Write_DIG(pDM_Odm, 0x1c);
1486                                 else if(pDM_Odm->bBtConnectProcess)
1487                                         ODM_Write_DIG(pDM_Odm, 0x28);
1488                                 else
1489                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1490                         }
1491                 }
1492                 else            // BT is not using
1493 #endif
1494                 {
1495                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);\r
1496                         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1497                         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
1498                 }
1499         }
1500 }\r
1501 \r
1502 VOID
1503 odm_DIGbyRSSI_LPS(
1504         IN              PVOID           pDM_VOID
1505         )
1506 {
1507 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
1508         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
1509         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1510
1511 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
1512 #if 0           //and 2.3.5 coding rule
1513         struct mlme_priv        *pmlmepriv = &(pAdapter->mlmepriv);
1514         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1515         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1516 #endif
1517 #endif
1518
1519         u1Byte  RSSI_Lower=DM_DIG_MIN_NIC;   //0x1E or 0x1C
1520         u1Byte  CurrentIGI=pDM_Odm->RSSI_Min;
1521
1522         CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
1523
1524         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS()==>\n"));
1525
1526         // Using FW PS mode to make IGI
1527         //Adjust by  FA in LPS MODE
1528         if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS)
1529                 CurrentIGI = CurrentIGI+4;
1530         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
1531                 CurrentIGI = CurrentIGI+2;
1532         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
1533                 CurrentIGI = CurrentIGI-2;
1534
1535
1536         //Lower bound checking
1537
1538         //RSSI Lower bound check
1539         if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
1540                 RSSI_Lower =(pDM_Odm->RSSI_Min-10);
1541         else
1542                 RSSI_Lower =DM_DIG_MIN_NIC;
1543
1544         //Upper and Lower Bound checking
1545          if(CurrentIGI > DM_DIG_MAX_NIC)
1546                 CurrentIGI=DM_DIG_MAX_NIC;
1547          else if(CurrentIGI < RSSI_Lower)
1548                 CurrentIGI =RSSI_Lower;
1549
1550
1551         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pFalseAlmCnt->Cnt_all = %d\n",pFalseAlmCnt->Cnt_all));
1552         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pDM_Odm->RSSI_Min = %d\n",pDM_Odm->RSSI_Min));
1553         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): CurrentIGI = 0x%x\n",CurrentIGI));
1554
1555         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1556 #endif
1557 }
1558 \r
1559 VOID
1560 odm_DigForBtHsMode(
1561         IN              PVOID           pDM_VOID
1562         )
1563 {\r
1564 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1565         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
1566         pDIG_T                                  pDM_DigTable=&pDM_Odm->DM_DigTable;
1567         u1Byte                                  digForBtHs=0;
1568         u1Byte                                  digUpBound=0x5a;
1569
1570         if(pDM_Odm->bBtConnectProcess)
1571         {
1572                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
1573                         digForBtHs = 0x28;
1574                 else
1575                         digForBtHs = 0x22;
1576         }
1577         else
1578         {
1579                 //
1580                 // Decide DIG value by BT HS RSSI.
1581                 //
1582                 digForBtHs = pDM_Odm->btHsRssi+4;
1583
1584                 //DIG Bound
1585                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
1586                         digUpBound = 0x3e;
1587
1588                 if(digForBtHs > digUpBound)
1589                         digForBtHs = digUpBound;
1590                 if(digForBtHs < 0x1c)
1591                         digForBtHs = 0x1c;
1592
1593                 // update Current IGI
1594                 pDM_DigTable->BT30_CurIGI = digForBtHs;
1595         }
1596         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs));
1597 #endif
1598 }
1599 \r
1600
1601 //3============================================================
1602 //3 FASLE ALARM CHECK
1603 //3============================================================
1604
1605 VOID
1606 odm_FalseAlarmCounterStatistics(
1607         IN              PVOID           pDM_VOID
1608         )
1609 {
1610         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
1611         PFALSE_ALARM_STATISTICS         FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1612         u4Byte                                          ret_value;
1613
1614 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1615 //Mark there, and check this in odm_DMWatchDog
1616 #if 0 //(DM_ODM_SUPPORT_TYPE == ODM_AP)
1617         prtl8192cd_priv priv            = pDM_Odm->priv;
1618         if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )
1619                 return;
1620 #endif
1621 #endif
1622
1623 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1624         if((pDM_Odm->SupportICType == ODM_RTL8192D) &&
1625                 (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&&    ////modify by Guo.Mingzhi 2011-12-29
1626                 (!(*(pDM_Odm->pbMasterOfDMSP))))
1627         {
1628                 odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm);
1629                 return;
1630         }
1631 #endif
1632
1633         if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
1634                 return;
1635
1636         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1637         {
1638
1639                 //hold ofdm counter
1640                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter
1641                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter
1642
1643                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
1644                 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
1645                 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
1646
1647                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
1648                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
1649                 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
1650
1651                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
1652                 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
1653                 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
1654
1655                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
1656                 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
1657
1658                 FalseAlmCnt->Cnt_Ofdm_fail =    FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
1659                                                                 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
1660                                                                 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
1661
1662 #if (RTL8188E_SUPPORT==1)
1663                 if(pDM_Odm->SupportICType == ODM_RTL8188E)
1664                 {
1665                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
1666                         FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
1667                         FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
1668                 }
1669 #endif
1670
1671 #if (RTL8192D_SUPPORT==1)
1672                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
1673                 {
1674                         odm_GetCCKFalseAlarm_92D(pDM_Odm);
1675                 }
1676                 else
1677 #endif
1678                 {
1679                         //hold cck counter
1680                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
1681                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
1682
1683                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
1684                         FalseAlmCnt->Cnt_Cck_fail = ret_value;
1685
1686                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
1687                         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value& 0xff)<<8;
1688
1689                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
1690                         FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
1691                 }
1692
1693                 FalseAlmCnt->Cnt_all = (        FalseAlmCnt->Cnt_Fast_Fsync +
1694                                                         FalseAlmCnt->Cnt_SB_Search_fail +
1695                                                         FalseAlmCnt->Cnt_Parity_Fail +
1696                                                         FalseAlmCnt->Cnt_Rate_Illegal +
1697                                                         FalseAlmCnt->Cnt_Crc8_fail +
1698                                                         FalseAlmCnt->Cnt_Mcs_fail +
1699                                                         FalseAlmCnt->Cnt_Cck_fail);
1700
1701                 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
1702
1703 #if (RTL8192C_SUPPORT==1)
1704                 if(pDM_Odm->SupportICType == ODM_RTL8192C)
1705                         odm_ResetFACounter_92C(pDM_Odm);
1706 #endif
1707
1708 #if (RTL8192D_SUPPORT==1)
1709                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
1710                         odm_ResetFACounter_92D(pDM_Odm);
1711 #endif
1712
1713                 if(pDM_Odm->SupportICType >=ODM_RTL8723A)
1714                 {
1715                         //reset false alarm counter registers
1716                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
1717                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
1718                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
1719                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
1720
1721                         //update ofdm counter
1722                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter
1723                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter
1724
1725                         //reset CCK CCA counter
1726                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
1727                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
1728                         //reset CCK FA counter
1729                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
1730                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
1731                 }
1732
1733                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
1734                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
1735                         FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
1736                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
1737                         FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
1738                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
1739                 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
1740         }
1741         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1742         {
1743                 u4Byte CCKenable;
1744                 u4Byte Cnt_Ofdm_fail_temp = 0;
1745
1746                 //read OFDM FA counter
1747                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
1748                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
1749
1750                 //read CCK/OFDM CCA counter
1751                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11AC, bMaskDWord);\r
1752                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff0000) >> 16;
1753                 FalseAlmCnt->Cnt_CCK_CCA = ret_value & 0xffff;
1754
1755                 // For 8881A
1756                 if(pDM_Odm->SupportICType == ODM_RTL8881A)
1757                 {
1758                         if(FalseAlmCnt->Cnt_Ofdm_fail >= FalseAlmCnt->Cnt_Ofdm_fail_pre)
1759                         {
1760                                 Cnt_Ofdm_fail_temp = FalseAlmCnt->Cnt_Ofdm_fail_pre;
1761                                 FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail;
1762                                 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Ofdm_fail - Cnt_Ofdm_fail_temp;
1763                         }
1764                         else
1765                                 FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail;
1766                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail_pre));
1767                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail_pre=%d\n",  Cnt_Ofdm_fail_temp));
1768
1769                         // Reset FA counter by enable/disable OFDM
1770                         if(FalseAlmCnt->Cnt_Ofdm_fail_pre >= 0x7fff)
1771                         {
1772                                 // reset OFDM
1773                                 ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,0);
1774                                 ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,1);
1775                                 FalseAlmCnt->Cnt_Ofdm_fail_pre = 0;
1776                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Reset false alarm counter\n"));
1777                         }
1778                 }
1779
1780                 // reset OFDM FA coutner
1781                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
1782                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
1783
1784                 // reset CCK FA counter
1785                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
1786                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
1787
1788                 // reset CCA counter
1789                 ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 1);
1790                 ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 0);
1791
1792                 CCKenable =  ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28);
1793                 if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G)
1794                 {
1795                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
1796                         FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_CCK_CCA + FalseAlmCnt->Cnt_OFDM_CCA;
1797                 }
1798                 else
1799                 {
1800                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail;
1801                         FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA;
1802                 }
1803
1804         }
1805
1806         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_OFDM_CCA=%d\n",       FalseAlmCnt->Cnt_OFDM_CCA));
1807         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_CCK_CCA=%d\n",        FalseAlmCnt->Cnt_CCK_CCA));
1808         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_CCA_all=%d\n",        FalseAlmCnt->Cnt_CCA_all));
1809         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
1810         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n",       FalseAlmCnt->Cnt_Cck_fail));
1811         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
1812         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n",  FalseAlmCnt->Cnt_all));
1813 }
1814
1815
1816 VOID
1817 odm_FAThresholdCheck(
1818         IN              PVOID                   pDM_VOID,
1819         IN              BOOLEAN                 bDFSBand,
1820         IN              BOOLEAN                 bPerformance,
1821         IN              u4Byte                  RxTp,
1822         IN              u4Byte                  TxTp,
1823         OUT             u4Byte*                 dm_FA_thres
1824         )
1825 {
1826         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;
1827
1828         if(pDM_Odm->bLinked && (bPerformance||bDFSBand))
1829         {
1830                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
1831                 {
1832                         // 8192D special case
1833                         dm_FA_thres[0] = DM_DIG_FA_TH0_92D;
1834                         dm_FA_thres[1] = DM_DIG_FA_TH1_92D;
1835                         dm_FA_thres[2] = DM_DIG_FA_TH2_92D;
1836                 }
1837 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1838                 else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1839                 {
1840                         // For AP
1841                         if((RxTp>>2) > TxTp && RxTp < 10000 && RxTp > 500)                      // 10Mbps & 0.5Mbps
1842                         {
1843                                 dm_FA_thres[0] = 0x080;
1844                                 dm_FA_thres[1] = 0x100;
1845                                 dm_FA_thres[2] = 0x200;
1846                         }
1847                         else
1848                         {
1849                                 dm_FA_thres[0] = 0x100;
1850                                 dm_FA_thres[1] = 0x200;
1851                                 dm_FA_thres[2] = 0x300;
1852                         }
1853                 }
1854 #else
1855                 else if(pDM_Odm->SupportICType == ODM_RTL8723A && pDM_Odm->bBtLimitedDig)
1856                 {
1857                         // 8723A BT special case
1858                         dm_FA_thres[0] = DM_DIG_FA_TH0;
1859                         dm_FA_thres[1] = 0x250;
1860                         dm_FA_thres[2] = 0x300;
1861                 }
1862 #endif
1863                 else
1864                 {
1865                         // For NIC
1866                         dm_FA_thres[0] = DM_DIG_FA_TH0;
1867                         dm_FA_thres[1] = DM_DIG_FA_TH1;
1868                         dm_FA_thres[2] = DM_DIG_FA_TH2;
1869                 }
1870         }
1871         else
1872         {
1873 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1874                 if(bDFSBand)
1875                 {
1876                         // For DFS band and no link
1877                         dm_FA_thres[0] = 250;
1878                         dm_FA_thres[1] = 1000;
1879                         dm_FA_thres[2] = 2000;
1880                 }
1881                 else
1882 #endif
1883                 {
1884                         dm_FA_thres[0] = 2000;
1885                         dm_FA_thres[1] = 4000;
1886                         dm_FA_thres[2] = 5000;
1887                 }
1888         }
1889         return;
1890 }
1891
1892 u1Byte
1893 odm_ForbiddenIGICheck(
1894         IN              PVOID                   pDM_VOID,
1895         IN              u1Byte                  DIG_Dynamic_MIN,
1896         IN              u1Byte                  CurrentIGI
1897         )
1898 {
1899         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
1900         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1901         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1902         u1Byte                                          rx_gain_range_min = pDM_DigTable->rx_gain_range_min;
1903
1904         if(pFalseAlmCnt->Cnt_all > 10000)
1905         {
1906                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case. \n"));
1907
1908                 if(pDM_DigTable->LargeFAHit != 3)
1909                         pDM_DigTable->LargeFAHit++;
1910
1911                 if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
1912                 {
1913                         pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
1914                         pDM_DigTable->LargeFAHit = 1;
1915                 }
1916
1917                 if(pDM_DigTable->LargeFAHit >= 3)
1918                 {
1919                         if((pDM_DigTable->ForbiddenIGI + 2) > pDM_DigTable->rx_gain_range_max)
1920                                 rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
1921                         else
1922                                 rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2);
1923                         pDM_DigTable->Recover_cnt = 1800;
1924                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: Recover_cnt = %d \n", pDM_DigTable->Recover_cnt));
1925                 }
1926         }
1927         else
1928         {
1929                 if(pDM_DigTable->Recover_cnt != 0)\r
1930                 {\r
1931                         pDM_DigTable->Recover_cnt --;\r
1932                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Recover_cnt = %d \n", pDM_DigTable->Recover_cnt));\r
1933                 }\r
1934                 else
1935                 {
1936                         if(pDM_DigTable->LargeFAHit < 3)
1937                         {
1938                                 if((pDM_DigTable->ForbiddenIGI - 2) < DIG_Dynamic_MIN) //DM_DIG_MIN)
1939                                 {
1940                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN;
1941                                         rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN;
1942                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
1943                                 }
1944                                 else
1945                                 {
1946                                         pDM_DigTable->ForbiddenIGI -= 2;
1947                                         rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2);
1948                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
1949                                 }
1950                         }
1951                         else
1952                         {
1953                                 pDM_DigTable->LargeFAHit = 0;
1954                         }
1955                 }
1956         }
1957
1958         return rx_gain_range_min;
1959
1960 }
1961
1962 VOID
1963 odm_InbandNoiseCalculate (
1964         IN              PVOID           pDM_VOID
1965         )
1966 {
1967 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1968         PDM_ODM_T                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
1969         pDIG_T                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1970         u1Byte                          IGIBackup, TimeCnt = 0, ValidCnt = 0;
1971         BOOLEAN                         bTimeout = TRUE;
1972         s1Byte                          sNoise_A, sNoise_B;
1973         s4Byte                          NoiseRpt_A = 0,NoiseRpt_B = 0;
1974         u4Byte                          tmp = 0;
1975         static  u1Byte          failCnt = 0;
1976
1977         if(!(pDM_Odm->SupportICType & (ODM_RTL8192E)))
1978                 return;
1979
1980         if(pDM_Odm->RFType == ODM_1T1R || *(pDM_Odm->pOnePathCCA) != ODM_CCA_2R)
1981                 return;
1982
1983         if(!pDM_DigTable->bNoiseEst)
1984                 return;
1985
1986         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n"));
1987
1988         //1 Set initial gain.
1989         IGIBackup = pDM_DigTable->CurIGValue;
1990         pDM_DigTable->IGIOffset_A = 0;
1991         pDM_DigTable->IGIOffset_B = 0;
1992         ODM_Write_DIG(pDM_Odm, 0x24);
1993
1994         //1 Update idle time power report
1995         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1996                 ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x0);
1997
1998         delay_ms(2);
1999
2000         //1 Get noise power level
2001         while(1)
2002         {
2003                 //2 Read Noise Floor Report
2004                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2005                         tmp = ODM_GetBBReg(pDM_Odm, 0x8f8, bMaskLWord);
2006
2007                 sNoise_A = (s1Byte)(tmp & 0xff);
2008                 sNoise_B = (s1Byte)((tmp & 0xff00)>>8);
2009
2010                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B));
2011
2012                 if((sNoise_A < 20 && sNoise_A >= -70) && (sNoise_B < 20 && sNoise_B >= -70))
2013                 {
2014                         ValidCnt++;
2015                         NoiseRpt_A += sNoise_A;
2016                         NoiseRpt_B += sNoise_B;
2017                         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B));
2018                 }
2019
2020                 TimeCnt++;
2021                 bTimeout = (TimeCnt >= 150)?TRUE:FALSE;
2022
2023                 if(ValidCnt == 20 || bTimeout)
2024                         break;
2025
2026                 delay_ms(2);
2027
2028         }
2029
2030         //1 Keep idle time power report
2031         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2032                 ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x1);
2033
2034         //1 Recover IGI
2035         ODM_Write_DIG(pDM_Odm, IGIBackup);
2036
2037         //1 Calculate Noise Floor
2038         if(ValidCnt != 0)
2039         {
2040                 NoiseRpt_A  /= (ValidCnt<<1);
2041                 NoiseRpt_B  /= (ValidCnt<<1);
2042         }
2043
2044         if(bTimeout)
2045         {
2046                 NoiseRpt_A = 0;
2047                 NoiseRpt_B = 0;
2048
2049                 failCnt ++;
2050                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", failCnt));
2051
2052                 if(failCnt == 3)
2053                 {
2054                         failCnt = 0;
2055                         pDM_DigTable->bNoiseEst = FALSE;
2056                 }
2057         }
2058         else
2059         {
2060                 NoiseRpt_A = -110 + 0x24 + NoiseRpt_A -6;
2061                 NoiseRpt_B = -110 + 0x24 + NoiseRpt_B -6;
2062                 pDM_DigTable->bNoiseEst = FALSE;
2063                 failCnt = 0;
2064                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NoiseRpt_A = %d, NoiseRpt_B = %d\n", NoiseRpt_A, NoiseRpt_B));
2065         }
2066
2067         //1 Calculate IGI Offset
2068         if(NoiseRpt_A > NoiseRpt_B)
2069         {
2070                 pDM_DigTable->IGIOffset_A = NoiseRpt_A - NoiseRpt_B;
2071                 pDM_DigTable->IGIOffset_B = 0;
2072         }
2073         else
2074         {
2075                 pDM_DigTable->IGIOffset_A = 0;
2076                 pDM_DigTable->IGIOffset_B = NoiseRpt_B - NoiseRpt_A;
2077         }
2078
2079 #endif
2080         return;
2081 }
2082
2083 //3============================================================
2084 //3 CCK Packet Detect Threshold
2085 //3============================================================
2086
2087 VOID
2088 odm_PauseCCKPacketDetection(
2089         IN              PVOID                                   pDM_VOID,
2090         IN              ODM_Pause_CCKPD_TYPE    PauseType,
2091         IN              u1Byte                                  CCKPDThreshold
2092 )
2093 {
2094         PDM_ODM_T                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2095         pDIG_T                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2096         static  BOOLEAN         bPaused = FALSE;
2097
2098         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection()=========>\n"));
2099
2100 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2101         if(*pDM_DigTable->pbP2pLinkInProgress)
2102         {
2103                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("P2P in progress !!\n"));
2104                 return;
2105         }
2106 #endif
2107
2108         if(!bPaused && (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)))
2109         {
2110                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Return: SupportAbility ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n"));
2111                 return;
2112         }
2113
2114         switch(PauseType)
2115         {
2116                 //1 Pause CCK Packet Detection Threshold
2117                 case ODM_PAUSE_CCKPD:
2118                         //2 Disable DIG
2119                         ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_CCK_PD));
2120                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Pause CCK packet detection threshold !!\n"));
2121
2122                         //2 Backup CCK Packet Detection Threshold value
2123                         if(!bPaused)
2124                         {
2125                                 pDM_DigTable->CCKPDBackup = pDM_DigTable->CurCCK_CCAThres;
2126                                 bPaused = TRUE;
2127                         }
2128                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Backup CCK packet detection tgreshold  = %d\n", pDM_DigTable->CCKPDBackup));
2129
2130                         //2 Write new CCK Packet Detection Threshold value
2131                         ODM_Write_CCK_CCA_Thres(pDM_Odm, CCKPDThreshold);
2132                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Write new CCK packet detection tgreshold = %d\n", CCKPDThreshold));
2133                         break;
2134
2135                 //1 Resume CCK Packet Detection Threshold
2136                 case ODM_RESUME_CCKPD:
2137                         if(bPaused)
2138                         {
2139                                 //2 Write backup CCK Packet Detection Threshold value
2140                                 ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->CCKPDBackup);
2141                                 bPaused = FALSE;
2142                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Write original CCK packet detection tgreshold = %d\n", pDM_DigTable->CCKPDBackup));
2143
2144                                 //2 Enable CCK Packet Detection Threshold
2145                                 ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_CCK_PD);
2146                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Resume CCK packet detection threshold  !!\n"));
2147                         }
2148                         break;
2149
2150                 default:
2151                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Wrong  type !!\n"));
2152                         break;
2153         }
2154         return;
2155 }
2156
2157
2158 VOID
2159 odm_CCKPacketDetectionThresh(
2160         IN              PVOID           pDM_VOID
2161         )
2162 {
2163         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2164         PFALSE_ALARM_STATISTICS         FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
2165         u1Byte                                          CurCCK_CCAThres;
2166
2167
2168 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2169 //modify by Guo.Mingzhi 2011-12-29
2170         if (pDM_Odm->bDualMacSmartConcurrent == TRUE)
2171 //      if (pDM_Odm->bDualMacSmartConcurrent == FALSE)
2172                 return;
2173         if(pDM_Odm->bBtHsOperation)
2174         {
2175                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n"));
2176                 ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd);
2177                 return;
2178         }
2179 #endif
2180
2181         if((!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD)) ||(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)))
2182         {
2183                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh()  return==========\n"));
2184                 return;
2185         }
2186
2187 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
2188         if(pDM_Odm->ExtLNA)
2189                 return;
2190 #endif
2191
2192         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh()  ==========>\n"));
2193
2194         if(pDM_Odm->bLinked)
2195         {
2196                 if(pDM_Odm->RSSI_Min > 25)
2197                         CurCCK_CCAThres = 0xcd;
2198                 else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10))
2199                         CurCCK_CCAThres = 0x83;
2200                 else
2201                 {
2202                         if(FalseAlmCnt->Cnt_Cck_fail > 1000)
2203                                 CurCCK_CCAThres = 0x83;
2204                         else
2205                                 CurCCK_CCAThres = 0x40;
2206                 }
2207         }
2208         else
2209         {
2210                 if(FalseAlmCnt->Cnt_Cck_fail > 1000)
2211                         CurCCK_CCAThres = 0x83;
2212                 else
2213                         CurCCK_CCAThres = 0x40;
2214         }
2215
2216 #if (RTL8192D_SUPPORT==1)
2217         if((pDM_Odm->SupportICType == ODM_RTL8192D) && (*pDM_Odm->pBandType == ODM_BAND_2_4G))
2218                 ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres);
2219         else
2220 #endif
2221                 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
2222
2223         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh()  CurCCK_CCAThres = 0x%x\n",CurCCK_CCAThres));
2224 }
2225
2226 VOID
2227 ODM_Write_CCK_CCA_Thres(
2228         IN      PVOID                   pDM_VOID,
2229         IN      u1Byte                  CurCCK_CCAThres
2230         )
2231 {
2232         PDM_ODM_T                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2233         pDIG_T                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2234
2235         if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres)              //modify by Guo.Mingzhi 2012-01-03
2236         {
2237                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres);
2238         }
2239         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
2240         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
2241 }\r
2242 \r
2243 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2244
2245 VOID
2246 odm_EnableEDCCA(
2247         IN              PVOID                                   pDM_VOID\r
2248 )
2249 {
2250
2251         // This should be moved out of OUTSRC
2252         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
2253         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
2254         // Enable EDCCA. The value is suggested by SD3 Wilson.
2255
2256         //
2257         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
2258         //
2259         if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
2260         {
2261                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
2262                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
2263                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
2264
2265         }
2266         else
2267         {
2268                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
2269                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
2270                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
2271         }
2272
2273         //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
2274 }
2275
2276 VOID
2277 odm_DisableEDCCA(
2278         IN              PVOID                                   pDM_VOID\r
2279 )
2280 {
2281         // Disable EDCCA..\r
2282         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
2283         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
2284         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
2285 }
2286
2287 //
2288 // Description: According to initial gain value to determine to enable or disable EDCCA.
2289 //
2290 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
2291 //
2292 VOID
2293 odm_DynamicEDCCA(
2294         IN              PVOID                                   pDM_VOID\r
2295 )
2296 {
2297         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
2298         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
2299         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2300         u1Byte                  RegC50, RegC58;
2301         BOOLEAN                 bEDCCAenable = FALSE;
2302
2303 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2304         BOOLEAN                 bFwCurrentInPSMode=FALSE;
2305
2306         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
2307
2308         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
2309         if(bFwCurrentInPSMode)
2310                 return;
2311 #endif
2312         //
2313         // 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.
2314         // 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop
2315         // to send beacon in noisy environment or platform.
2316         //
2317         if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))
2318         //if(ACTING_AS_AP(pAdapter))
2319         {
2320                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));
2321                 odm_DisableEDCCA(pDM_Odm);
2322                 if(pHalData->bPreEdccaEnable)
2323                         odm_DisableEDCCA(pDM_Odm);
2324                 pHalData->bPreEdccaEnable = FALSE;
2325                 return;
2326         }
2327
2328         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
2329         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
2330
2331
2332         if((RegC50 > 0x28 && RegC58 > 0x28) ||
2333                 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
2334                 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
2335         {
2336                 if(!pHalData->bPreEdccaEnable)
2337                 {
2338                         odm_EnableEDCCA(pDM_Odm);
2339                         pHalData->bPreEdccaEnable = TRUE;
2340                 }
2341
2342         }
2343         else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
2344         {
2345                 if(pHalData->bPreEdccaEnable)
2346                 {
2347                         odm_DisableEDCCA(pDM_Odm);
2348                         pHalData->bPreEdccaEnable = FALSE;
2349                 }
2350         }
2351 }
2352 \r
2353 // <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis)\r
2354 VOID
2355 odm_RFEControl(
2356         IN      PDM_ODM_T       pDM_Odm,
2357         IN  u8Byte              RSSIVal
2358         )
2359 {
2360         PADAPTER                Adapter = (PADAPTER)pDM_Odm->Adapter;
2361     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(Adapter);
2362         static u1Byte   TRSW_HighPwr = 0;
2363
2364         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n",
2365                          RSSIVal, TRSW_HighPwr, pHalData->RFEType ));
2366
2367     if (pHalData->RFEType == 3) {
2368
2369         pDM_Odm->RSSI_TRSW = RSSIVal;
2370
2371         if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H)
2372                 {
2373             TRSW_HighPwr = 1; // Switch to
2374             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
2375             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3);  // Set ANTSW=1/ANTSWB=0  for SW control
2376
2377         }
2378                 else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L)
2379         {
2380             TRSW_HighPwr = 0; // Switched back
2381             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
2382             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0);  // Set ANTSW=1/ANTSWB=0  for SW control
2383
2384         }
2385     }
2386
2387
2388         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L));
2389         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n",
2390                                  RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW));
2391         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr));
2392 }
2393
2394 VOID
2395 odm_MPT_DIGWorkItemCallback(
2396     IN PVOID            pContext
2397     )
2398 {
2399         PADAPTER        Adapter = (PADAPTER)pContext;
2400         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2401         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
2402
2403         ODM_MPT_DIG(pDM_Odm);
2404 }
2405
2406 VOID
2407 odm_MPT_DIGCallback(
2408         PRT_TIMER               pTimer
2409 )
2410 {
2411         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
2412        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
2413           PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
2414
2415
2416         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
2417                 #if USE_WORKITEM
2418                         PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
2419                 #else
2420                         ODM_MPT_DIG(pDM_Odm);
2421                 #endif
2422         #else
2423                 PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
2424         #endif
2425
2426 }
2427
2428 #endif
2429
2430 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
2431 VOID
2432 odm_MPT_DIGCallback(
2433         IN              PVOID                                   pDM_VOID
2434 )
2435 {
2436         PDM_ODM_T                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2437 #if USE_WORKITEM
2438         PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
2439 #else
2440         ODM_MPT_DIG(pDM_Odm);
2441 #endif
2442 }
2443 #endif
2444
2445 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
2446 VOID
2447 odm_MPT_Write_DIG(
2448         IN              PVOID                                   pDM_VOID,
2449         IN              u1Byte                                  CurIGValue
2450 )
2451 {
2452         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2453         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2454
2455         ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), CurIGValue);
2456
2457         if(pDM_Odm->RFType > ODM_1T1R)
2458                 ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), CurIGValue);
2459
2460         if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R))
2461         {
2462                 ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_C,pDM_Odm), CurIGValue);
2463                 ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_D,pDM_Odm), CurIGValue);
2464         }
2465
2466         pDM_DigTable->CurIGValue = CurIGValue;
2467
2468         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurIGValue = 0x%x\n", CurIGValue));
2469         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("pDM_Odm->RFType = 0x%x\n", pDM_Odm->RFType));
2470 }
2471
2472 VOID
2473 ODM_MPT_DIG(
2474         IN              PVOID                                   pDM_VOID
2475         )
2476 {
2477         PDM_ODM_T                                       pDM_Odm = (PDM_ODM_T)pDM_VOID;
2478         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2479         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
2480         u1Byte                                          CurrentIGI = pDM_DigTable->CurIGValue;
2481         u1Byte                                          DIG_Upper = 0x40, DIG_Lower = 0x20;
2482         u4Byte                                          RXOK_cal;
2483         u4Byte                                          RxPWDBAve_final;
2484         u1Byte                                          IGI_A = 0x20, IGI_B = 0x20;
2485
2486 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2487
2488         #if ODM_FIX_2G_DIG
2489         IGI_A = 0x22;
2490         IGI_B = 0x24;
2491         #endif
2492
2493 #else
2494         if (!(pDM_Odm->priv->pshare->rf_ft_var.mp_specific && pDM_Odm->priv->pshare->mp_dig_on))
2495                 return;
2496
2497         if (*pDM_Odm->pBandType == ODM_BAND_5G)
2498                 DIG_Lower = 0x22;
2499 #endif
2500
2501         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType));
2502
2503 #if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)))
2504         if (*pDM_Odm->pBandType == ODM_BAND_5G || (pDM_Odm->SupportICType & ODM_RTL8814A)) // for 5G or 8814
2505 #else
2506         if (1) // for both 2G/5G
2507 #endif
2508                 {
2509                 odm_FalseAlarmCounterStatistics(pDM_Odm);
2510
2511                 RXOK_cal = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM;
2512                 RxPWDBAve_final = (RXOK_cal != 0)?pDM_Odm->RxPWDBAve/RXOK_cal:0;
2513
2514                 pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0;
2515                 pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0;
2516                 pDM_Odm->RxPWDBAve = 0;
2517                 pDM_Odm->MPDIG_2G = FALSE;
2518
2519 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2520                 pDM_Odm->Times_2G = 0;
2521 #endif
2522
2523                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", RXOK_cal));
2524                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", RxPWDBAve_final));
2525
2526                 if (RXOK_cal >= 70 && RxPWDBAve_final <= 40)
2527                 {
2528                         if (CurrentIGI > 0x24)
2529                                 odm_MPT_Write_DIG(pDM_Odm, 0x24);
2530                 }
2531                 else
2532                 {
2533                         if(pFalseAlmCnt->Cnt_all > 1000){
2534                                 CurrentIGI = CurrentIGI + 8;
2535                         }
2536                         else if(pFalseAlmCnt->Cnt_all > 200){
2537                                 CurrentIGI = CurrentIGI + 4;
2538                         }
2539                         else if (pFalseAlmCnt->Cnt_all > 50){
2540                                 CurrentIGI = CurrentIGI + 2;
2541                         }
2542                         else if (pFalseAlmCnt->Cnt_all < 2){
2543                                 CurrentIGI = CurrentIGI - 2;
2544                         }
2545
2546                         if (CurrentIGI < DIG_Lower ){
2547                                 CurrentIGI = DIG_Lower;
2548                         }
2549
2550                         if(CurrentIGI > DIG_Upper){
2551                                 CurrentIGI = DIG_Upper;
2552                         }
2553
2554                         odm_MPT_Write_DIG(pDM_Odm, CurrentIGI);
2555                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n",
2556                                 CurrentIGI, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail));
2557                 }
2558         }
2559         else
2560         {
2561                 if(pDM_Odm->MPDIG_2G == FALSE)
2562                 {
2563                         if((pDM_Odm->SupportPlatform & ODM_WIN) && !(pDM_Odm->SupportICType & ODM_RTL8814A))
2564                         {
2565                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n"));
2566                                 ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), IGI_A);
2567                                 ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), IGI_B);
2568                                 pDM_DigTable->CurIGValue = IGI_B;
2569                         }
2570                         else
2571                                 odm_MPT_Write_DIG(pDM_Odm, IGI_A);
2572                 }
2573
2574 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2575                 pDM_Odm->Times_2G++;
2576
2577                 if (pDM_Odm->Times_2G == 3)
2578 #endif
2579                 {
2580                         pDM_Odm->MPDIG_2G = TRUE;
2581                 }
2582         }
2583
2584 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2585         if (pDM_Odm->SupportICType == ODM_RTL8812)
2586                 odm_RFEControl(pDM_Odm, RxPWDBAve_final);
2587 #endif
2588
2589         ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700);
2590 }\r
2591 #endif\r