1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 #ifndef __ODM_REGDEFINE11N_H__
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22 #define __ODM_REGDEFINE11N_H__
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26 #define ODM_REG_RF_MODE_11N 0x00
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27 #define ODM_REG_RF_0B_11N 0x0B
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28 #define ODM_REG_CHNBW_11N 0x18
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29 #define ODM_REG_T_METER_11N 0x24
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30 #define ODM_REG_RF_25_11N 0x25
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31 #define ODM_REG_RF_26_11N 0x26
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32 #define ODM_REG_RF_27_11N 0x27
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33 #define ODM_REG_RF_2B_11N 0x2B
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34 #define ODM_REG_RF_2C_11N 0x2C
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35 #define ODM_REG_RXRF_A3_11N 0x3C
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36 #define ODM_REG_T_METER_92D_11N 0x42
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37 #define ODM_REG_T_METER_88E_11N 0x42
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43 #define ODM_REG_BB_CTRL_11N 0x800
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44 #define ODM_REG_RF_PIN_11N 0x804
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45 #define ODM_REG_PSD_CTRL_11N 0x808
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46 #define ODM_REG_TX_ANT_CTRL_11N 0x80C
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47 #define ODM_REG_BB_PWR_SAV5_11N 0x818
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48 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824
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49 #define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
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50 #define ODM_REG_RX_DEFUALT_A_11N 0x858
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51 #define ODM_REG_RX_DEFUALT_B_11N 0x85A
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52 #define ODM_REG_BB_PWR_SAV3_11N 0x85C
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53 #define ODM_REG_ANTSEL_CTRL_11N 0x860
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54 #define ODM_REG_RX_ANT_CTRL_11N 0x864
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55 #define ODM_REG_PIN_CTRL_11N 0x870
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56 #define ODM_REG_BB_PWR_SAV1_11N 0x874
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57 #define ODM_REG_ANTSEL_PATH_11N 0x878
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58 #define ODM_REG_BB_3WIRE_11N 0x88C
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59 #define ODM_REG_SC_CNT_11N 0x8C4
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60 #define ODM_REG_PSD_DATA_11N 0x8B4
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61 #define ODM_REG_PSD_DATA_11N 0x8B4
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62 #define ODM_REG_NHM_TIMER_11N 0x894
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63 #define ODM_REG_NHM_TH9_TH10_11N 0x890
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64 #define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
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65 #define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
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66 #define ODM_REG_NHM_CNT_11N 0x8d8
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68 #define ODM_REG_DBG_RPT_11N 0x908
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69 #define ODM_REG_ANT_MAPPING1_11N 0x914
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70 #define ODM_REG_ANT_MAPPING2_11N 0x918
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72 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
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73 #define ODM_REG_CCK_CCA_11N 0xA0A
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74 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
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75 #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
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76 #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
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77 #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
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78 #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
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79 #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
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80 #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
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81 #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
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82 #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
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83 #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
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84 #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
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85 #define ODM_REG_CCK_FA_RST_11N 0xA2C
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86 #define ODM_REG_CCK_FA_MSB_11N 0xA58
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87 #define ODM_REG_CCK_FA_LSB_11N 0xA5C
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88 #define ODM_REG_CCK_CCA_CNT_11N 0xA60
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89 #define ODM_REG_BB_PWR_SAV4_11N 0xA74
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91 #define ODM_REG_LNA_SWITCH_11N 0xB2C
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92 #define ODM_REG_PATH_SWITCH_11N 0xB30
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93 #define ODM_REG_RSSI_CTRL_11N 0xB38
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94 #define ODM_REG_CONFIG_ANTA_11N 0xB68
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95 #define ODM_REG_RSSI_BT_11N 0xB9C
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97 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
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98 #define ODM_REG_BB_RX_PATH_11N 0xC04
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99 #define ODM_REG_TRMUX_11N 0xC08
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100 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
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101 #define ODM_REG_RXIQI_MATRIX_11N 0xC14
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102 #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
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103 #define ODM_REG_IGI_A_11N 0xC50
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104 #define ODM_REG_ANTDIV_PARA2_11N 0xC54
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105 #define ODM_REG_IGI_B_11N 0xC58
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106 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C
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107 #define ODM_REG_L1SBD_PD_CH_11N 0XC6C
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108 #define ODM_REG_BB_PWR_SAV2_11N 0xC70
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109 #define ODM_REG_RX_OFF_11N 0xC7C
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110 #define ODM_REG_TXIQK_MATRIXA_11N 0xC80
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111 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88
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112 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
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113 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
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114 #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
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115 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4
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116 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
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118 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00
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119 #define ODM_REG_BB_ATC_11N 0xD2C
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120 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
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121 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
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122 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
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123 #define ODM_REG_RPT_11N 0xDF4
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125 #define ODM_REG_TXAGC_A_6_18_11N 0xE00
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126 #define ODM_REG_TXAGC_A_24_54_11N 0xE04
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127 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
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128 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
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129 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
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130 #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
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131 #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
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132 #define ODM_REG_FPGA0_IQK_11N 0xE28
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133 #define ODM_REG_TXIQK_TONE_A_11N 0xE30
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134 #define ODM_REG_RXIQK_TONE_A_11N 0xE34
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135 #define ODM_REG_TXIQK_PI_A_11N 0xE38
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136 #define ODM_REG_RXIQK_PI_A_11N 0xE3C
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137 #define ODM_REG_TXIQK_11N 0xE40
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138 #define ODM_REG_RXIQK_11N 0xE44
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139 #define ODM_REG_IQK_AGC_PTS_11N 0xE48
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140 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C
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141 #define ODM_REG_BLUETOOTH_11N 0xE6C
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142 #define ODM_REG_RX_WAIT_CCA_11N 0xE70
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143 #define ODM_REG_TX_CCK_RFON_11N 0xE74
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144 #define ODM_REG_TX_CCK_BBON_11N 0xE78
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145 #define ODM_REG_OFDM_RFON_11N 0xE7C
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146 #define ODM_REG_OFDM_BBON_11N 0xE80
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147 #define ODM_REG_TX2RX_11N 0xE84
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148 #define ODM_REG_TX2TX_11N 0xE88
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149 #define ODM_REG_RX_CCK_11N 0xE8C
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150 #define ODM_REG_RX_OFDM_11N 0xED0
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151 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4
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152 #define ODM_REG_RX2RX_11N 0xED8
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153 #define ODM_REG_STANDBY_11N 0xEDC
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154 #define ODM_REG_SLEEP_11N 0xEE0
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155 #define ODM_REG_PMPD_ANAEN_11N 0xEEC
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156 #define ODM_REG_IGI_C_11N 0xF84
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157 #define ODM_REG_IGI_D_11N 0xF88
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160 #define ODM_REG_BB_RST_11N 0x02
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161 #define ODM_REG_ANTSEL_PIN_11N 0x4C
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162 #define ODM_REG_EARLY_MODE_11N 0x4D0
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163 #define ODM_REG_RSSI_MONITOR_11N 0x4FE
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164 #define ODM_REG_EDCA_VO_11N 0x500
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165 #define ODM_REG_EDCA_VI_11N 0x504
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166 #define ODM_REG_EDCA_BE_11N 0x508
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167 #define ODM_REG_EDCA_BK_11N 0x50C
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168 #define ODM_REG_TXPAUSE_11N 0x522
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169 #define ODM_REG_RESP_TX_11N 0x6D8
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170 #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
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171 #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
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175 #define ODM_BIT_IGI_11N 0x0000007F
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176 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
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177 #define ODM_BIT_BB_RX_PATH_11N 0xF
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178 #define ODM_BIT_BB_ATC_11N BIT11
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