drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_types.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __ODM_TYPES_H__
  21 #define __ODM_TYPES_H__
  22
  23
  24
  25
  26 #define ODM_RATEMCS15_SG                0x1c
  27 #define ODM_RATEMCS32                   0x20
  28
  29
  30 // CCK Rates, TxHT = 0
  31 #define ODM_RATE1M                              0x00
  32 #define ODM_RATE2M                              0x01
  33 #define ODM_RATE5_5M                    0x02
  34 #define ODM_RATE11M                             0x03
  35 // OFDM Rates, TxHT = 0
  36 #define ODM_RATE6M                              0x04
  37 #define ODM_RATE9M                              0x05
  38 #define ODM_RATE12M                             0x06
  39 #define ODM_RATE18M                             0x07
  40 #define ODM_RATE24M                             0x08
  41 #define ODM_RATE36M                             0x09
  42 #define ODM_RATE48M                             0x0A
  43 #define ODM_RATE54M                             0x0B
  44 // MCS Rates, TxHT = 1
  45 #define ODM_RATEMCS0                    0x0C
  46 #define ODM_RATEMCS1                    0x0D
  47 #define ODM_RATEMCS2                    0x0E
  48 #define ODM_RATEMCS3                    0x0F
  49 #define ODM_RATEMCS4                    0x10
  50 #define ODM_RATEMCS5                    0x11
  51 #define ODM_RATEMCS6                    0x12
  52 #define ODM_RATEMCS7                    0x13
  53 #define ODM_RATEMCS8                    0x14
  54 #define ODM_RATEMCS9                    0x15
  55 #define ODM_RATEMCS10                   0x16
  56 #define ODM_RATEMCS11                   0x17
  57 #define ODM_RATEMCS12                   0x18
  58 #define ODM_RATEMCS13                   0x19
  59 #define ODM_RATEMCS14                   0x1A
  60 #define ODM_RATEMCS15                   0x1B
  61 #define ODM_RATEMCS16                   0x1C
  62 #define ODM_RATEMCS17                   0x1D
  63 #define ODM_RATEMCS18                   0x1E
  64 #define ODM_RATEMCS19                   0x1F
  65 #define ODM_RATEMCS20                   0x20
  66 #define ODM_RATEMCS21                   0x21
  67 #define ODM_RATEMCS22                   0x22
  68 #define ODM_RATEMCS23                   0x23
  69 #define ODM_RATEMCS24                   0x24
  70 #define ODM_RATEMCS25                   0x25
  71 #define ODM_RATEMCS26                   0x26
  72 #define ODM_RATEMCS27                   0x27
  73 #define ODM_RATEMCS28                   0x28
  74 #define ODM_RATEMCS29                   0x29
  75 #define ODM_RATEMCS30                   0x2A
  76 #define ODM_RATEMCS31                   0x2B
  77 #define ODM_RATEVHTSS1MCS0              0x2C
  78 #define ODM_RATEVHTSS1MCS1              0x2D
  79 #define ODM_RATEVHTSS1MCS2              0x2E
  80 #define ODM_RATEVHTSS1MCS3              0x2F
  81 #define ODM_RATEVHTSS1MCS4              0x30
  82 #define ODM_RATEVHTSS1MCS5              0x31
  83 #define ODM_RATEVHTSS1MCS6              0x32
  84 #define ODM_RATEVHTSS1MCS7              0x33
  85 #define ODM_RATEVHTSS1MCS8              0x34
  86 #define ODM_RATEVHTSS1MCS9              0x35
  87 #define ODM_RATEVHTSS2MCS0              0x36
  88 #define ODM_RATEVHTSS2MCS1              0x37
  89 #define ODM_RATEVHTSS2MCS2              0x38
  90 #define ODM_RATEVHTSS2MCS3              0x39
  91 #define ODM_RATEVHTSS2MCS4              0x3A
  92 #define ODM_RATEVHTSS2MCS5              0x3B
  93 #define ODM_RATEVHTSS2MCS6              0x3C
  94 #define ODM_RATEVHTSS2MCS7              0x3D
  95 #define ODM_RATEVHTSS2MCS8              0x3E
  96 #define ODM_RATEVHTSS2MCS9              0x3F
  97 #define ODM_RATEVHTSS3MCS0              0x40
  98 #define ODM_RATEVHTSS3MCS1              0x41
  99 #define ODM_RATEVHTSS3MCS2              0x42
 100 #define ODM_RATEVHTSS3MCS3              0x43
 101 #define ODM_RATEVHTSS3MCS4              0x44
 102 #define ODM_RATEVHTSS3MCS5              0x45
 103 #define ODM_RATEVHTSS3MCS6              0x46
 104 #define ODM_RATEVHTSS3MCS7              0x47
 105 #define ODM_RATEVHTSS3MCS8              0x48
 106 #define ODM_RATEVHTSS3MCS9              0x49
 107 #define ODM_RATEVHTSS4MCS0              0x4A
 108 #define ODM_RATEVHTSS4MCS1              0x4B
 109 #define ODM_RATEVHTSS4MCS2              0x4C
 110 #define ODM_RATEVHTSS4MCS3              0x4D
 111 #define ODM_RATEVHTSS4MCS4              0x4E
 112 #define ODM_RATEVHTSS4MCS5              0x4F
 113 #define ODM_RATEVHTSS4MCS6              0x50
 114 #define ODM_RATEVHTSS4MCS7              0x51
 115 #define ODM_RATEVHTSS4MCS8              0x52
 116 #define ODM_RATEVHTSS4MCS9              0x53
 117
 118 //
 119 // Define Different SW team support
 120 //
 121 #define ODM_AP                  0x01    //BIT0
 122 #define ODM_ADSL                0x02    //BIT1
 123 #define ODM_CE                  0x04    //BIT2
 124 #define ODM_WIN                 0x08    //BIT3
 125
 126 #define DM_ODM_SUPPORT_TYPE                     ODM_CE
 127
 128 // Deifne HW endian support
 129 #define ODM_ENDIAN_BIG  0
 130 #define ODM_ENDIAN_LITTLE       1
 131
 132 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 133 #define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
 134 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
 135 #define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
 136 #endif
 137
 138 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
 139 #define         RT_PCI_INTERFACE                                1
 140 #define         RT_USB_INTERFACE                                2
 141 #define         RT_SDIO_INTERFACE                               3
 142 #endif
 143
 144 typedef enum _HAL_STATUS{
 145         HAL_STATUS_SUCCESS,
 146         HAL_STATUS_FAILURE,
 147         /*RT_STATUS_PENDING,
 148         RT_STATUS_RESOURCE,
 149         RT_STATUS_INVALID_CONTEXT,
 150         RT_STATUS_INVALID_PARAMETER,
 151         RT_STATUS_NOT_SUPPORT,
 152         RT_STATUS_OS_API_FAILED,*/
 153 }HAL_STATUS,*PHAL_STATUS;
 154
 155 #if( DM_ODM_SUPPORT_TYPE == ODM_AP)
 156 #define         MP_DRIVER               0
 157 #endif
 158 #if(DM_ODM_SUPPORT_TYPE != ODM_WIN)
 159
 160 #define         VISTA_USB_RX_REVISE                     0
 161
 162 //
 163 // Declare for ODM spin lock defintion temporarily fro compile pass.
 164 //
 165 typedef enum _RT_SPINLOCK_TYPE{
 166         RT_TX_SPINLOCK = 1,
 167         RT_RX_SPINLOCK = 2,
 168         RT_RM_SPINLOCK = 3,
 169         RT_CAM_SPINLOCK = 4,
 170         RT_SCAN_SPINLOCK = 5,
 171         RT_LOG_SPINLOCK = 7,
 172         RT_BW_SPINLOCK = 8,
 173         RT_CHNLOP_SPINLOCK = 9,
 174         RT_RF_OPERATE_SPINLOCK = 10,
 175         RT_INITIAL_SPINLOCK = 11,
 176         RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
 177 #if VISTA_USB_RX_REVISE
 178         RT_USBRX_CONTEXT_SPINLOCK = 13,
 179         RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
 180 #endif
 181         //Shall we define Ndis 6.2 SpinLock Here ?
 182         RT_PORT_SPINLOCK=16,
 183         RT_VNIC_SPINLOCK=17,
 184         RT_HVL_SPINLOCK=18,
 185         RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
 186
 187         RT_BTData_SPINLOCK=25,
 188
 189         RT_WAPI_OPTION_SPINLOCK=26,
 190         RT_WAPI_RX_SPINLOCK=27,
 191
 192       // add for 92D CCK control issue
 193         RT_CCK_PAGEA_SPINLOCK = 28,
 194         RT_BUFFER_SPINLOCK = 29,
 195         RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
 196         RT_GEN_TEMP_BUF_SPINLOCK = 31,
 197         RT_AWB_SPINLOCK = 32,
 198         RT_FW_PS_SPINLOCK = 33,
 199         RT_HW_TIMER_SPIN_LOCK = 34,
 200         RT_MPT_WI_SPINLOCK = 35,
 201         RT_P2P_SPIN_LOCK = 36,  // Protect P2P context
 202         RT_DBG_SPIN_LOCK = 37,
 203         RT_IQK_SPINLOCK = 38,
 204         RT_PENDED_OID_SPINLOCK = 39,
 205         RT_CHNLLIST_SPINLOCK = 40,
 206         RT_INDIC_SPINLOCK = 41, //protect indication
 207         RT_RFD_SPINLOCK = 42,
 208         RT_LAST_SPINLOCK,
 209 }RT_SPINLOCK_TYPE;
 210
 211 #endif
 212
 213
 214 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 215         #define STA_INFO_T                      RT_WLAN_STA
 216         #define PSTA_INFO_T                     PRT_WLAN_STA
 217
 218 //    typedef unsigned long             u4Byte,*pu4Byte;
 219 #define CONFIG_HW_ANTENNA_DIVERSITY
 220 #define CONFIG_SW_ANTENNA_DIVERSITY
 221
 222 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
 223
 224         // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
 225         #define ADSL_AP_BUILD_WORKAROUND
 226         #define AP_BUILD_WORKAROUND
 227
 228         //2 [ Configure Antenna Diversity ]
 229 #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
 230         #define CONFIG_HW_ANTENNA_DIVERSITY
 231         #define ODM_EVM_ENHANCE_ANTDIV
 232
 233         //----------
 234         #if(!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
 235                 #define CONFIG_NO_2G_DIVERSITY
 236         #endif
 237
 238         #ifdef CONFIG_NO_5G_DIVERSITY_8881A
 239                 #define CONFIG_NO_5G_DIVERSITY
 240         #elif  defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
 241                 #define CONFIG_5G_CGCS_RX_DIVERSITY
 242         #elif  defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
 243                 #define CONFIG_5G_CG_TRX_DIVERSITY
 244         #endif
 245
 246         #if(!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
 247                 #define CONFIG_NO_5G_DIVERSITY
 248         #endif
 249         //----------
 250         #if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
 251                 #define CONFIG_NOT_SUPPORT_ANTDIV
 252         #elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
 253                 #define CONFIG_2G_SUPPORT_ANTDIV
 254         #elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
 255                 #define CONFIG_5G_SUPPORT_ANTDIV
 256         #elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
 257                 #define CONFIG_2G5G_SUPPORT_ANTDIV
 258         #endif
 259         //----------
 260 #endif
 261         #ifdef AP_BUILD_WORKAROUND
 262         #include "../typedef.h"
 263         #else
 264         typedef void                                    VOID,*PVOID;
 265         typedef unsigned char                   BOOLEAN,*PBOOLEAN;
 266         typedef unsigned char                   u1Byte,*pu1Byte;
 267         typedef unsigned short                  u2Byte,*pu2Byte;
 268         typedef unsigned int                    u4Byte,*pu4Byte;
 269         typedef unsigned long long              u8Byte,*pu8Byte;
 270 #if 1
 271 /* In ARM platform, system would use the type -- "char" as "unsigned char"
 272  * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
 273     typedef signed char                         s1Byte,*ps1Byte;
 274 #else
 275         typedef char                                    s1Byte,*ps1Byte;
 276 #endif
 277         typedef short                                   s2Byte,*ps2Byte;
 278         typedef long                                    s4Byte,*ps4Byte;
 279         typedef long long                               s8Byte,*ps8Byte;
 280         #endif
 281
 282         typedef struct rtl8192cd_priv   *prtl8192cd_priv;
 283         typedef struct stat_info                STA_INFO_T,*PSTA_INFO_T;
 284         typedef struct timer_list               RT_TIMER, *PRT_TIMER;
 285         typedef  void *                         RT_TIMER_CALL_BACK;
 286
 287 #ifdef CONFIG_PCI_HCI
 288         #define DEV_BUS_TYPE            RT_PCI_INTERFACE
 289 #endif
 290
 291         #define _TRUE                           1
 292         #define _FALSE                          0
 293
 294 #elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
 295
 296         // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
 297         #define ADSL_AP_BUILD_WORKAROUND
 298         #define ADSL_BUILD_WORKAROUND
 299         //
 300
 301         typedef unsigned char                   BOOLEAN,*PBOOLEAN;
 302         typedef unsigned char                   u1Byte,*pu1Byte;
 303         typedef unsigned short                  u2Byte,*pu2Byte;
 304         typedef unsigned int                    u4Byte,*pu4Byte;
 305         typedef unsigned long long              u8Byte,*pu8Byte;
 306 #if 1
 307 /* In ARM platform, system would use the type -- "char" as "unsigned char"
 308  * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
 309     typedef signed char                         s1Byte,*ps1Byte;
 310 #else
 311         typedef char                                    s1Byte,*ps1Byte;
 312 #endif
 313         typedef short                                   s2Byte,*ps2Byte;
 314         typedef long                                    s4Byte,*ps4Byte;
 315         typedef long long                               s8Byte,*ps8Byte;
 316
 317         typedef struct rtl8192cd_priv   *prtl8192cd_priv;
 318         typedef struct stat_info                STA_INFO_T,*PSTA_INFO_T;
 319         typedef struct timer_list               RT_TIMER, *PRT_TIMER;
 320         typedef  void *                         RT_TIMER_CALL_BACK;
 321
 322         #define DEV_BUS_TYPE            RT_PCI_INTERFACE
 323
 324         #define _TRUE                           1
 325         #define _FALSE                          0
 326
 327 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
 328         #include <drv_types.h>
 329
 330 #if 0
 331         typedef u8                                      u1Byte, *pu1Byte;
 332         typedef u16                                     u2Byte,*pu2Byte;
 333         typedef u32                                     u4Byte,*pu4Byte;
 334         typedef u64                                     u8Byte,*pu8Byte;
 335         typedef s8                                      s1Byte,*ps1Byte;
 336         typedef s16                                     s2Byte,*ps2Byte;
 337         typedef s32                                     s4Byte,*ps4Byte;
 338         typedef s64                                     s8Byte,*ps8Byte;
 339 #else
 340         #define u1Byte          u8
 341         #define pu1Byte         u8*
 342
 343         #define u2Byte          u16
 344         #define pu2Byte         u16*
 345
 346         #define u4Byte          u32
 347         #define pu4Byte         u32*
 348
 349         #define u8Byte          u64
 350         #define pu8Byte         u64*
 351
 352         #define s1Byte          s8
 353         #define ps1Byte         s8*
 354
 355         #define s2Byte          s16
 356         #define ps2Byte         s16*
 357
 358         #define s4Byte          s32
 359         #define ps4Byte         s32*
 360
 361         #define s8Byte          s64
 362         #define ps8Byte         s64*
 363
 364 #endif
 365         #ifdef CONFIG_USB_HCI
 366                 #define DEV_BUS_TYPE    RT_USB_INTERFACE
 367         #elif defined(CONFIG_PCI_HCI)
 368                 #define DEV_BUS_TYPE    RT_PCI_INTERFACE
 369         #elif defined(CONFIG_SDIO_HCI)
 370                 #define DEV_BUS_TYPE    RT_SDIO_INTERFACE
 371         #elif defined(CONFIG_GSPI_HCI)
 372                 #define DEV_BUS_TYPE    RT_SDIO_INTERFACE
 373         #endif
 374
 375
 376         #if defined(CONFIG_LITTLE_ENDIAN)
 377                 #define ODM_ENDIAN_TYPE                 ODM_ENDIAN_LITTLE
 378         #elif defined (CONFIG_BIG_ENDIAN)
 379                 #define ODM_ENDIAN_TYPE                 ODM_ENDIAN_BIG
 380         #endif
 381
 382         typedef struct timer_list               RT_TIMER, *PRT_TIMER;
 383         typedef  void *                         RT_TIMER_CALL_BACK;
 384         #define STA_INFO_T                      struct sta_info
 385         #define PSTA_INFO_T             struct sta_info *
 386
 387
 388
 389         #define TRUE    _TRUE
 390         #define FALSE   _FALSE
 391
 392
 393         #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
 394         #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
 395         #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
 396
 397         //define useless flag to avoid compile warning
 398         #define USE_WORKITEM 0
 399         #define         FOR_BRAZIL_PRETEST 0
 400         #define   FPGA_TWO_MAC_VERIFICATION     0
 401         #define RTL8881A_SUPPORT        0
 402 #endif
 403
 404 #define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
 405 #define COND_ELSE  2
 406 #define COND_ENDIF 3
 407
 408 #endif // __ODM_TYPES_H__
 409