drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/rtl8723b/HalPhyRf_8723B.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 #include "Mp_Precomp.h"\r
  22 #include "../phydm_precomp.h"\r
  23 \r
  24 \r
  25 \r
  26 /*---------------------------Define Local Constant---------------------------*/\r
  27 // 2010/04/25 MH Define the max tx power tracking tx agc power.\r
  28 #define         ODM_TXPWRTRACK_MAX_IDX8723B     6\r
  29 \r
  30 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0]\r
  31 #define         PATH_S0                                                 1 // RF_PATH_B\r
  32 #define         IDX_0xC94                                               0\r
  33 #define         IDX_0xC80                                               1\r
  34 #define         IDX_0xC4C                                               2\r
  35 #define         IDX_0xC14                                               0\r
  36 #define         IDX_0xCA0                                               1\r
  37 #define         KEY                                                     0\r
  38 #define         VAL                                                     1\r
  39 \r
  40 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1]\r
  41 #define         PATH_S1                                                 0 // RF_PATH_A\r
  42 #define         IDX_0xC9C                                               0\r
  43 #define         IDX_0xC88                                               1\r
  44 #define         IDX_0xC4C                                               2\r
  45 #define         IDX_0xC1C                                               0\r
  46 #define         IDX_0xC78                                               1\r
  47 \r
  48 \r
  49 /*---------------------------Define Local Constant---------------------------*/\r
  50 \r
  51 \r
  52 //3============================================================\r
  53 //3 Tx Power Tracking\r
  54 //3============================================================\r
  55 \r
  56 \r
  57 void setIqkMatrix_8723B(\r
  58         PDM_ODM_T       pDM_Odm,\r
  59         u1Byte          OFDM_index,\r
  60         u1Byte          RFPath,\r
  61         s4Byte          IqkResult_X,\r
  62         s4Byte          IqkResult_Y\r
  63         )\r
  64 {\r
  65         s4Byte                  ele_A=0, ele_D, ele_C=0, value32;\r
  66 \r
  67         if (OFDM_index >= OFDM_TABLE_SIZE)\r
  68                 OFDM_index = OFDM_TABLE_SIZE-1;\r
  69 \r
  70         ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;              \r
  71         \r
  72         //new element A = element D x X\r
  73         if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))\r
  74         {\r
  75                 if ((IqkResult_X & 0x00000200) != 0)    //consider minus\r
  76                         IqkResult_X = IqkResult_X | 0xFFFFFC00;\r
  77                 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;\r
  78                         \r
  79                 //new element C = element D x Y\r
  80                 if ((IqkResult_Y & 0x00000200) != 0)\r
  81                         IqkResult_Y = IqkResult_Y | 0xFFFFFC00;\r
  82                 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;\r
  83 \r
  84                 //if (RFPath == ODM_RF_PATH_A)\r
  85                 switch (RFPath)\r
  86                 {\r
  87                 case ODM_RF_PATH_A:\r
  88                         //wirte new elements A, C, D to regC80 and regC94, element B is always 0\r
  89                         value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;\r
  90                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);\r
  91 \r
  92                         value32 = (ele_C&0x000003C0)>>6;\r
  93                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);\r
  94 \r
  95                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
  96                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);                    \r
  97                         break;\r
  98                 case ODM_RF_PATH_B:\r
  99                         //wirte new elements A, C, D to regC88 and regC9C, element B is always 0\r
 100                         value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;\r
 101                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);\r
 102 \r
 103                         value32 = (ele_C&0x000003C0)>>6;\r
 104                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);    \r
 105                         \r
 106                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
 107                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);\r
 108                         \r
 109                         break;                  \r
 110                 default:\r
 111                         break;\r
 112                 }       \r
 113         }\r
 114         else\r
 115         {\r
 116                 switch (RFPath)\r
 117                 {\r
 118                 case ODM_RF_PATH_A:\r
 119                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                              \r
 120                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);\r
 121                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);                       \r
 122                         break;\r
 123 \r
 124                 case ODM_RF_PATH_B:\r
 125                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                                                                              \r
 126                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);       \r
 127                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);                               \r
 128                         break;                  \r
 129 \r
 130                 default:\r
 131                         break;\r
 132                 }               \r
 133         }\r
 134 \r
 135         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", \r
 136         (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));                              \r
 137 }\r
 138 \r
 139 \r
 140 VOID\r
 141 setCCKFilterCoefficient(\r
 142         PDM_ODM_T       pDM_Odm,\r
 143         u1Byte          CCKSwingIndex\r
 144 )\r
 145 {\r
 146         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 147         {\r
 148                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);\r
 149                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);\r
 150                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);\r
 151                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);\r
 152                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);\r
 153                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);\r
 154                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);\r
 155                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);           \r
 156         }\r
 157         else\r
 158         {\r
 159                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);\r
 160                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);\r
 161                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);\r
 162                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);\r
 163                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);\r
 164                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);\r
 165                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);\r
 166                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);       \r
 167         }               \r
 168 }\r
 169 \r
 170 void DoIQK_8723B(\r
 171         PDM_ODM_T       pDM_Odm,\r
 172         u1Byte          DeltaThermalIndex,\r
 173         u1Byte          ThermalValue,   \r
 174         u1Byte          Threshold\r
 175         )\r
 176 {\r
 177 #if 0 // mark by Lucas@SD4 20140128, suggested by Allen@SD3\r
 178 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 179         PADAPTER                Adapter = pDM_Odm->Adapter;\r
 180         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 181 #endif\r
 182 \r
 183         ODM_ResetIQKResult(pDM_Odm);            \r
 184 \r
 185 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 186 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 187 #if USE_WORKITEM\r
 188         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 189 #else\r
 190         PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 191 #endif\r
 192 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 193         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 194 #endif\r
 195 #endif                  \r
 196 \r
 197 \r
 198         pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;\r
 199 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 200         PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE);\r
 201 #else\r
 202         PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE);\r
 203 #endif\r
 204         \r
 205 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 206 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 207 #if USE_WORKITEM\r
 208         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 209 #else\r
 210         PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 211 #endif\r
 212 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 213         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 214 #endif\r
 215 #endif\r
 216 #endif // #if 0\r
 217 }\r
 218 \r
 219 /*-----------------------------------------------------------------------------\r
 220  * Function:    odm_TxPwrTrackSetPwr88E()\r
 221  *\r
 222  * Overview:    88E change all channel tx power accordign to flag.\r
 223  *                              OFDM & CCK are all different.\r
 224  *\r
 225  * Input:               NONE\r
 226  *\r
 227  * Output:              NONE\r
 228  *\r
 229  * Return:              NONE\r
 230  *\r
 231  * Revised History:\r
 232  *      When            Who     Remark\r
 233  *      04/23/2012      MHC     Create Version 0.  \r
 234  *\r
 235  *---------------------------------------------------------------------------*/\r
 236 VOID\r
 237 ODM_TxPwrTrackSetPwr_8723B(\r
 238         PDM_ODM_T                       pDM_Odm,\r
 239         PWRTRACK_METHOD         Method,\r
 240         u1Byte                          RFPath,\r
 241         u1Byte                          ChannelMappedIndex\r
 242         )\r
 243 {\r
 244         PADAPTER        Adapter = pDM_Odm->Adapter;\r
 245         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
 246         u1Byte          PwrTrackingLimit_OFDM = 34; //+0dB\r
 247         u1Byte          PwrTrackingLimit_CCK= 28;       //-2dB\r
 248         u1Byte          TxRate = 0xFF;\r
 249         u1Byte          Final_OFDM_Swing_Index = 0; \r
 250         u1Byte          Final_CCK_Swing_Index = 0; \r
 251         u1Byte          i = 0;\r
 252 \r
 253         if (pDM_Odm->mp_mode == TRUE)\r
 254         {\r
 255 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))\r
 256         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
 257                 PMPT_CONTEXT            pMptCtx = &(Adapter->MptCtx);\r
 258         #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 259                 PMPT_CONTEXT            pMptCtx = &(Adapter->mppriv.MptCtx);\r
 260         #endif\r
 261                 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 262 #endif\r
 263         }\r
 264         else\r
 265         {\r
 266                 u2Byte  rate     = *(pDM_Odm->pForcedDataRate);\r
 267         \r
 268                 if(!rate) //auto rate\r
 269                 {\r
 270                         if(pDM_Odm->TxRate != 0xFF)\r
 271                                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
 272                                 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);\r
 273                                 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 274                                 TxRate = HwRateToMRate(pDM_Odm->TxRate);\r
 275                                 #endif\r
 276                 }\r
 277                 else //force rate\r
 278                 {\r
 279                         TxRate = (u1Byte)rate;\r
 280                 }\r
 281         }\r
 282 \r
 283         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));\r
 284 \r
 285         if(TxRate != 0xFF)\r
 286         {\r
 287                 //2 CCK\r
 288                 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))\r
 289                         PwrTrackingLimit_CCK = 28;      //-2dB\r
 290                 //2 OFDM\r
 291                 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))\r
 292                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 293                 else if(TxRate == MGN_54M)\r
 294                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 295 \r
 296                 //2 HT\r
 297                 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK\r
 298                         PwrTrackingLimit_OFDM= 38; //+4dB\r
 299                 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM\r
 300                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 301                 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM\r
 302                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 303 \r
 304                 else\r
 305                         PwrTrackingLimit_OFDM =  pDM_Odm->DefaultOfdmIndex;   //Default OFDM index = 30\r
 306         }\r
 307         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));\r
 308 \r
 309         if (Method == TXAGC) \r
 310         {\r
 311                 u1Byte  rf = 0;\r
 312                 u4Byte  pwr = 0, TxAGC = 0;\r
 313                 PADAPTER Adapter = pDM_Odm->Adapter;\r
 314 \r
 315                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel)));\r
 316 \r
 317                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 318 \r
 319 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))\r
 320                 if (pDM_Odm->mp_mode == TRUE)\r
 321                 {\r
 322                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 323                         pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath];\r
 324                         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);\r
 325                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 326                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);\r
 327                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));\r
 328 \r
 329                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 330                         pwr += (pDM_Odm->BbSwingIdxOfdm[RFPath] - pDM_Odm->BbSwingIdxOfdmBase[RFPath]);\r
 331                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 332                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 333                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 334                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 335                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 336                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 337                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 338                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));\r
 339                 }\r
 340                 else            \r
 341                 {\r
 342                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 343                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 344 \r
 345                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 346                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 347                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 348                 }\r
 349 #endif\r
 350         }\r
 351         else if (Method == BBSWING)\r
 352         {\r
 353                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 354                 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; \r
 355 \r
 356                 // Adjust BB swing by OFDM IQ matrix\r
 357                 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)\r
 358                         Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;\r
 359                 else if (Final_OFDM_Swing_Index <= 0)\r
 360                         Final_OFDM_Swing_Index = 0;\r
 361 \r
 362                 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)\r
 363                         Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;\r
 364                 else if (pDM_Odm->BbSwingIdxCck <= 0)\r
 365                         Final_CCK_Swing_Index = 0;\r
 366 \r
 367                 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, \r
 368                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 369                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);  \r
 370 \r
 371                 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);\r
 372 \r
 373         }\r
 374         else if (Method == MIX_MODE)\r
 375         {\r
 376                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 377                         ("pDM_Odm->DefaultOfdmIndex=%d,  pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",\r
 378                         pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath],RFPath ));\r
 379 \r
 380                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 381                 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 382 \r
 383                 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM )     //BBSwing higher then Limit\r
 384                 {\r
 385                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;\r
 386 \r
 387                         setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, \r
 388                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 389                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 390 \r
 391                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 392                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 393                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 394 \r
 395                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 396                                 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", \r
 397                                 PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));\r
 398                 }\r
 399                 else if (Final_OFDM_Swing_Index <= 0)\r
 400                 {\r
 401                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;\r
 402 \r
 403                         setIqkMatrix_8723B(pDM_Odm, 0, RFPath, \r
 404                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 405                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 406 \r
 407                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 408                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 409                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 410 \r
 411                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 412                                 ("******Path_A Lower then BBSwing lower bound  0 , Remnant TxAGC Value = %d \n", \r
 413                                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));\r
 414                 }\r
 415                 else\r
 416                 {\r
 417                         setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, \r
 418                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 419                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 420 \r
 421                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 422                                 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));\r
 423 \r
 424                         if(pDM_Odm->Modify_TxAGC_Flag_PathA)  //If TxAGC has changed, reset TxAGC again\r
 425                         {\r
 426                                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;\r
 427                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 428                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 429                                 pDM_Odm->Modify_TxAGC_Flag_PathA = FALSE;\r
 430 \r
 431                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 432                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));\r
 433                         }\r
 434                 }\r
 435 \r
 436                 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)\r
 437                 {\r
 438                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;\r
 439                         setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);\r
 440                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 441                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 442 \r
 443                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 444                                 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d \n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx));\r
 445                 }\r
 446                 else if(Final_CCK_Swing_Index <= 0)       // Lowest CCK Index = 0\r
 447                 {\r
 448                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;\r
 449                         setCCKFilterCoefficient(pDM_Odm, 0);\r
 450                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 451                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 452 \r
 453                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 454                                 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d \n", 0, pDM_Odm->Remnant_CCKSwingIdx));\r
 455                 }\r
 456                 else\r
 457                 {\r
 458                         setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);\r
 459 \r
 460                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 461                                 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index));\r
 462 \r
 463                         if(pDM_Odm->Modify_TxAGC_Flag_PathA_CCK)  //If TxAGC has changed, reset TxAGC again\r
 464                         {\r
 465                                 pDM_Odm->Remnant_CCKSwingIdx = 0;\r
 466                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 467                                 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK= FALSE;\r
 468 \r
 469                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 470                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n"));\r
 471                         }\r
 472                 }\r
 473         }\r
 474         else\r
 475         {\r
 476                 return; // This method is not supported.\r
 477         }\r
 478 }\r
 479 \r
 480 VOID\r
 481 GetDeltaSwingTable_8723B(\r
 482         IN      PDM_ODM_T                       pDM_Odm,\r
 483         OUT pu1Byte                     *TemperatureUP_A,\r
 484         OUT pu1Byte                     *TemperatureDOWN_A,\r
 485         OUT pu1Byte                     *TemperatureUP_B,\r
 486         OUT pu1Byte                     *TemperatureDOWN_B      \r
 487         )\r
 488 {\r
 489         PADAPTER                Adapter                  = pDM_Odm->Adapter;\r
 490         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
 491         HAL_DATA_TYPE   *pHalData                = GET_HAL_DATA(Adapter);\r
 492         u2Byte                  rate                     = *(pDM_Odm->pForcedDataRate);\r
 493         u1Byte                  channel                  = pHalData->CurrentChannel;\r
 494 \r
 495         if ( 1 <= channel && channel <= 14) {\r
 496                 if (IS_CCK_RATE(rate)) {\r
 497                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;\r
 498                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;\r
 499                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;\r
 500                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;     \r
 501                 } else {\r
 502                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;\r
 503                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;\r
 504                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;\r
 505                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;                        \r
 506                 }\r
 507         }/*else if ( 36 <= channel && channel <= 64) {\r
 508                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];\r
 509                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];\r
 510                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];\r
 511                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];\r
 512         } else if ( 100 <= channel && channel <= 140) {\r
 513                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];\r
 514                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];\r
 515                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];\r
 516                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];\r
 517         } else if ( 149 <= channel && channel <= 173) {\r
 518                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; \r
 519                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; \r
 520                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; \r
 521                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; \r
 522         }*/else {\r
 523                 *TemperatureUP_A   = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 524                 *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;   \r
 525                 *TemperatureUP_B   = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 526                 *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;           \r
 527         }\r
 528         \r
 529         return;\r
 530 }\r
 531 \r
 532 \r
 533 void ConfigureTxpowerTrack_8723B(\r
 534         PTXPWRTRACK_CFG pConfig\r
 535         )\r
 536 {\r
 537         pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;\r
 538         pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;\r
 539         pConfig->Threshold_IQK = IQK_THRESHOLD;\r
 540         pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;\r
 541         pConfig->RfPathCount = MAX_PATH_NUM_8723B;\r
 542         pConfig->ThermalRegAddr = RF_T_METER_8723B;\r
 543                 \r
 544         pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;\r
 545         pConfig->DoIQK = DoIQK_8723B;\r
 546         pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;\r
 547         pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;\r
 548 }\r
 549 \r
 550 //1 7.  IQK\r
 551 #define MAX_TOLERANCE           5\r
 552 #define IQK_DELAY_TIME          1               //ms\r
 553 \r
 554 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 555 phy_PathA_IQK_8723B(\r
 556 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 557         IN PDM_ODM_T            pDM_Odm,\r
 558 #else\r
 559         IN      PADAPTER        pAdapter,\r
 560 #endif\r
 561         IN      BOOLEAN         configPathB,\r
 562         IN      u1Byte          RF_Path\r
 563         )\r
 564 {\r
 565         u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;\r
 566         u1Byte result = 0x00;\r
 567 \r
 568 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 569         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
 570         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 571         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 572         #endif\r
 573         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 574         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 575         #endif\r
 576 #endif  \r
 577 \r
 578 \r
 579         // Save RF Path \r
 580         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
 581 \r
 582         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));\r
 583 \r
 584         //leave IQK mode\r
 585         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 586 \r
 587         //      enable path A PA in TXIQK mode\r
 588         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
 589         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );\r
 590         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );\r
 591         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );\r
 592         //      disable path B PA in TXIQK mode\r
 593 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 );\r
 594 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 );\r
 595 \r
 596         //1 Tx IQK\r
 597         //IQK setting\r
 598         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 599         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 600         //path-A IQK setting\r
 601 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));\r
 602         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 603         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 604         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 605         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 606 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);\r
 607         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);\r
 608         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);\r
 609         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 610         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 611 \r
 612         //LO calibration setting\r
 613 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 614         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);\r
 615 \r
 616         //enter IQK mode\r
 617         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 618 \r
 619         //Ant switch\r
 620         if (configPathB || (RF_Path == 0))\r
 621                 // wifi switch to S1\r
 622                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 623         else\r
 624                 // wifi switch to S0\r
 625                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 626 \r
 627         //GNT_BT = 0\r
 628         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 629 \r
 630         //One shot, path A LOK & IQK\r
 631 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 632         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 633         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 634         \r
 635         // delay x ms\r
 636 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));\r
 637         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 638         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 639 \r
 640         //restore Ant Path\r
 641         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 642         //GNT_BT = 1\r
 643         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 644 \r
 645         //leave IQK mode\r
 646         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 647 \r
 648 \r
 649         // Check failed\r
 650         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 651         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 652         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 653         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));\r
 654         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
 655         //monitor image power before & after IQK\r
 656         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
 657         ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
 658 \r
 659 \r
 660         if(!(regEAC & BIT28) &&         \r
 661                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 662                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
 663                 result |= 0x01;\r
 664 \r
 665         return result;\r
 666 \r
 667 #if 0\r
 668         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 669                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 670                 (((regEAC & 0x03FF0000)>>16) != 0x36))\r
 671                 result |= 0x02;\r
 672         else\r
 673                 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));\r
 674 #endif  \r
 675         }\r
 676 \r
 677 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 678 phy_PathA_RxIQK8723B(\r
 679 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 680         IN PDM_ODM_T            pDM_Odm,\r
 681 #else\r
 682         IN      PADAPTER        pAdapter,\r
 683 #endif\r
 684         IN      BOOLEAN         configPathB,\r
 685         IN      u1Byte          RF_Path\r
 686         )\r
 687 {\r
 688         u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp, Path_SEL_BB;\r
 689         u1Byte result = 0x00;\r
 690 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 691         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 692         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 693         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 694         #endif\r
 695         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 696         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 697         #endif\r
 698 #endif  \r
 699 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));\r
 700 \r
 701         // Save RF Path \r
 702         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); \r
 703 \r
 704         //leave IQK mode\r
 705         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 706 \r
 707         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n"));\r
 708         //1 Get TXIMR setting\r
 709         //modify RXIQK mode table\r
 710 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));\r
 711         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
 712         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
 713         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);\r
 714         //LNA2 off, PA on for Dcut\r
 715         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);\r
 716 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);  \r
 717         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 718         \r
 719         //IQK setting\r
 720         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 721         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 722 \r
 723         //path-A IQK setting\r
 724         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 725         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 726         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 727         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 728 \r
 729 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);\r
 730         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);\r
 731         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);    \r
 732         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 733         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 734 \r
 735         //LO calibration setting\r
 736 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 737         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
 738 \r
 739         //enter IQK mode\r
 740         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 741 \r
 742         //Ant switch\r
 743         if (configPathB || (RF_Path == 0))\r
 744                 // wifi switch to S1\r
 745                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 746         else\r
 747                 // wifi switch to S0\r
 748                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 749 \r
 750         //GNT_BT = 0\r
 751         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 752 \r
 753         //One shot, path A LOK & IQK\r
 754 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 755         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 756         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 757         \r
 758         // delay x ms\r
 759 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));\r
 760         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 761         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 762 \r
 763         //restore Ant Path\r
 764         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 765         //GNT_BT = 1\r
 766         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 767 \r
 768         //leave IQK mode\r
 769         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 770 \r
 771         // Check failed\r
 772         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 773         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 774         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 775         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));   \r
 776         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
 777         //monitor image power before & after IQK\r
 778         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
 779                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
 780 \r
 781                 if(!(regEAC & BIT28) &&         \r
 782                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 783                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
 784 \r
 785                         result |= 0x01;\r
 786                 else                                                    //if Tx not OK, ignore Rx\r
 787                         return result;  \r
 788 \r
 789 \r
 790         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);  \r
 791         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);\r
 792         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));  \r
 793         \r
 794 \r
 795         //1 RX IQK\r
 796         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n"));\r
 797 \r
 798         //modify RXIQK mode table\r
 799 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));\r
 800         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                      \r
 801         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);                            \r
 802         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
 803         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); \r
 804         //LAN2 on, PA off for Dcut\r
 805         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); \r
 806 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);                             \r
 807         \r
 808         //PA, PAD setting\r
 809         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 );  \r
 810         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f ); \r
 811 \r
 812 \r
 813         //IQK setting\r
 814         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 815 \r
 816         //path-A IQK setting\r
 817         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 818         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 819         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 820         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 821 \r
 822         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);\r
 823 //      ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);\r
 824         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);\r
 825         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 826         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 827 \r
 828         //LO calibration setting\r
 829 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 830         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);\r
 831 \r
 832         //enter IQK mode\r
 833         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 834 \r
 835         //Ant switch\r
 836         if (configPathB || (RF_Path == 0))\r
 837                 // wifi switch to S1\r
 838                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 839         else\r
 840                 // wifi switch to S0\r
 841                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 842 \r
 843         //GNT_BT = 0\r
 844         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 845 \r
 846         //One shot, path A LOK & IQK\r
 847 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 848         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 849         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 850         \r
 851         // delay x ms\r
 852 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 853         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 854         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 855 \r
 856         //restore Ant Path\r
 857         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 858         //GNT_BT = 1\r
 859         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 860 \r
 861     //leave IQK mode\r
 862         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 863 \r
 864         // Check failed\r
 865         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 866         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);\r
 867         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
 868         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));\r
 869         //monitor image power before & after IQK\r
 870         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", \r
 871         ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));\r
 872 \r
 873         //      PA/PAD controlled by 0x0\r
 874         //leave IQK mode\r
 875         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 876         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 );\r
 877 \r
 878         /* Allen 20141201 */\r
 879                 tmp=(regEAC & 0x03FF0000)>>16;\r
 880                 if ((tmp & 0x200)> 0)\r
 881                         tmp = 0x400 - tmp;\r
 882                         \r
 883         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 884                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 885                 (((regEAC & 0x03FF0000)>>16) != 0x36)&&         \r
 886                         (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&\r
 887                         (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&\r
 888                         (tmp < 0x1a))\r
 889                 result |= 0x02;\r
 890         else                                                    //if Tx not OK, ignore Rx\r
 891                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK fail!!\n"));\r
 892         \r
 893 \r
 894         return result;\r
 895 \r
 896 \r
 897 }\r
 898 \r
 899 u1Byte                          //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 900 phy_PathB_IQK_8723B(\r
 901 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 902         IN PDM_ODM_T            pDM_Odm\r
 903 #else\r
 904         IN      PADAPTER        pAdapter\r
 905 #endif\r
 906         )\r
 907 {\r
 908         u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;\r
 909         u1Byte  result = 0x00;\r
 910 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 911         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 912         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 913         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 914         #endif\r
 915         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 916         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 917         #endif\r
 918 #endif  \r
 919         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B IQK!\n"));\r
 920 \r
 921         // Save RF Path\r
 922         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
 923 \r
 924     //leave IQK mode\r
 925         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 926 \r
 927         //      in TXIQK mode\r
 928 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
 929 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );\r
 930 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );\r
 931 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );\r
 932         //      enable path B PA in TXIQK mode\r
 933         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1);\r
 934         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1);\r
 935 \r
 936 \r
 937 \r
 938         //1 Tx IQK\r
 939         //IQK setting\r
 940         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 941         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 942         //path-A IQK setting\r
 943 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n"));\r
 944         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 945         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 946         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 947         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 948         \r
 949 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114);\r
 950         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);\r
 951         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);\r
 952         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 953         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 954 \r
 955         //LO calibration setting\r
 956 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 957         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);\r
 958 \r
 959         //enter IQK mode\r
 960         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);      \r
 961 \r
 962         //switch to path B\r
 963         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 964 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
 965 \r
 966         //GNT_BT = 0\r
 967         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 968 \r
 969         //One shot, path B LOK & IQK\r
 970 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
 971         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 972         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 973 \r
 974         // delay x ms\r
 975 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 976         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 977         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 978 \r
 979         //restore Ant Path\r
 980         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 981         //GNT_BT = 1\r
 982         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 983 \r
 984     //leave IQK mode\r
 985         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 986 \r
 987 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord)));\r
 988         \r
 989         \r
 990         // Check failed\r
 991         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 992         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 993         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 994         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
 995         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
 996         //monitor image power before & after IQK\r
 997         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
 998                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
 999 \r
1000         if(!(regEAC & BIT28) &&         \r
1001                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
1002                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
1003                 result |= 0x01;\r
1004 \r
1005         return result;\r
1006 \r
1007 #if 0\r
1008         if(!(regEAC & BIT30) &&\r
1009                 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&\r
1010                 (((regECC & 0x03FF0000)>>16) != 0x36))\r
1011                 result |= 0x02;\r
1012         else\r
1013                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));\r
1014         \r
1015 #endif\r
1016 }\r
1017 \r
1018 \r
1019 \r
1020 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
1021 phy_PathB_RxIQK8723B(\r
1022 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1023         IN PDM_ODM_T            pDM_Odm,\r
1024 #else\r
1025         IN      PADAPTER        pAdapter,\r
1026 #endif\r
1027         IN      BOOLEAN         configPathB\r
1028         )\r
1029 {\r
1030         u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;\r
1031         u1Byte result = 0x00;\r
1032 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1033         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1034         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1035         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1036         #endif\r
1037         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1038         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1039         #endif\r
1040 #endif  \r
1041 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n"));\r
1042 \r
1043         // Save RF Path\r
1044         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
1045     //leave IQK mode\r
1046         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
1047 \r
1048         //switch to path B\r
1049         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1050 \r
1051         //1 Get TXIMR setting\r
1052         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n"));\r
1053         //modify RXIQK mode table\r
1054 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));\r
1055         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
1056         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
1057         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );\r
1058         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 );\r
1059         //open PA S1 & SMIXER\r
1060         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );\r
1061         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd );\r
1062         \r
1063 \r
1064         //IQK setting\r
1065         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
1066         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
1067 \r
1068 \r
1069         //path-B IQK setting\r
1070         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
1071         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
1072         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1073         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1074 \r
1075 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f );\r
1076         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);\r
1077         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);    \r
1078         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
1079         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
1080 \r
1081         //LO calibration setting\r
1082 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
1083         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
1084 \r
1085     //enter IQK mode\r
1086         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1087 \r
1088         //switch to path B\r
1089         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1090 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
1091 \r
1092         //GNT_BT = 0\r
1093         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
1094 \r
1095         //One shot, path B TXIQK @ RXIQK\r
1096 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
1097         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
1098         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
1099 \r
1100         \r
1101         // delay x ms\r
1102 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
1103         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
1104         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
1105 \r
1106         //restore Ant Path\r
1107         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
1108         //GNT_BT = 1\r
1109         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
1110 \r
1111     //leave IQK mode\r
1112         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1113 \r
1114         // Check failed\r
1115         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
1116         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
1117         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
1118         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
1119         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
1120         //monitor image power before & after IQK\r
1121         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
1122                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
1123 \r
1124 \r
1125                 if(!(regEAC & BIT28) &&         \r
1126                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
1127                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
1128                         result |= 0x01;\r
1129                 else                                                    //if Tx not OK, ignore Rx\r
1130                         return result;  \r
1131 \r
1132 \r
1133 \r
1134         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);  \r
1135         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);\r
1136         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));  \r
1137         \r
1138 \r
1139         //1 RX IQK\r
1140         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n"));\r
1141 \r
1142         //modify RXIQK mode table\r
1143         //<20121009, Kordan> RF Mode = 3\r
1144         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1145         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);                             \r
1146         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
1147         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); \r
1148         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); \r
1149 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);   \r
1150 \r
1151         //open PA S1 & close SMIXER\r
1152         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); \r
1153         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd);\r
1154 \r
1155         //PA, PAD setting\r
1156 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);\r
1157 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); \r
1158 \r
1159 \r
1160 \r
1161         //IQK setting\r
1162         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
1163 \r
1164         //path-B IQK setting\r
1165         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
1166         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
1167         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1168         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1169 \r
1170         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);\r
1171 //      ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);    \r
1172         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);\r
1173         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
1174         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
1175 \r
1176         //LO calibration setting\r
1177 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
1178         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);\r
1179 \r
1180     //enter IQK mode\r
1181         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1182 \r
1183         //switch to path B\r
1184         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1185 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
1186 \r
1187         //GNT_BT = 0\r
1188         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
1189 \r
1190         //One shot, path B LOK & IQK\r
1191 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
1192         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
1193         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
1194         \r
1195         // delay x ms\r
1196 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
1197         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
1198         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
1199 \r
1200         //restore Ant Path\r
1201         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
1202         //GNT_BT = 1\r
1203         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
1204 \r
1205     //leave IQK mode\r
1206         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1207 \r
1208         // Check failed\r
1209         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
1210         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);;\r
1211 \r
1212         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
1213         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));\r
1214         //monitor image power before & after IQK\r
1215         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", \r
1216                 ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));\r
1217 \r
1218         //      PA/PAD controlled by 0x0\r
1219         //leave IQK mode\r
1220 //      ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x00000000);\r
1221 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 );\r
1222 \r
1223 \r
1224 \r
1225 #if 0   \r
1226         if(!(regEAC & BIT31) &&         \r
1227                 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&\r
1228                 (((regEBC & 0x03FF0000)>>16) != 0x42) )\r
1229                 result |= 0x01;\r
1230         else                                                    //if Tx not OK, ignore Rx\r
1231                 return result;\r
1232 #endif  \r
1233 \r
1234 \r
1235         /* Allen 20141201 */\r
1236                 tmp=(regEAC & 0x03FF0000)>>16;\r
1237                 if ((tmp & 0x200)> 0)\r
1238                         tmp = 0x400 - tmp;\r
1239 \r
1240         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
1241                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
1242                 (((regEAC & 0x03FF0000)>>16) != 0x36) &&        \r
1243                         (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&\r
1244                         (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&\r
1245                         (tmp < 0x1a))\r
1246                         \r
1247                 result |= 0x02;\r
1248         else\r
1249                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));\r
1250         \r
1251 \r
1252         return result;\r
1253 \r
1254 \r
1255 }\r
1256 \r
1257 \r
1258 VOID\r
1259 _PHY_PathAFillIQKMatrix8723B(\r
1260 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1261         IN PDM_ODM_T            pDM_Odm,\r
1262 #else\r
1263         IN      PADAPTER        pAdapter,\r
1264 #endif\r
1265         IN      BOOLEAN         bIQKOK,\r
1266         IN      s4Byte          result[][8],\r
1267         IN      u1Byte          final_candidate,\r
1268         IN      BOOLEAN         bTxOnly\r
1269         )\r
1270 {\r
1271         u4Byte  Oldval_0, X, TX0_A, reg;\r
1272         s4Byte  Y, TX0_C;\r
1273 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1274         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1275         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1276         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1277         #endif\r
1278         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1279         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1280         #endif\r
1281 #endif  \r
1282         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1283 \r
1284         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
1285 \r
1286         if(final_candidate == 0xFF)\r
1287                 return;\r
1288 \r
1289         else if(bIQKOK)\r
1290         {\r
1291                 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
1292 \r
1293                 X = result[final_candidate][0];\r
1294                 if ((X & 0x00000200) != 0)\r
1295                         X = X | 0xFFFFFC00;                     \r
1296                 TX0_A = (X * Oldval_0) >> 8;\r
1297                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));\r
1298                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);\r
1299 \r
1300                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));\r
1301          \r
1302                 Y = result[final_candidate][1];\r
1303                 if ((Y & 0x00000200) != 0)\r
1304                         Y = Y | 0xFFFFFC00;     \r
1305 \r
1306                 //2 Tx IQC\r
1307                 TX0_C = (Y * Oldval_0) >> 8;\r
1308                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));\r
1309                 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));\r
1310                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;\r
1311                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord);\r
1312                 \r
1313                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));\r
1314                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;\r
1315                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord);\r
1316 \r
1317                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));\r
1318                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;\r
1319                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);\r
1320 \r
1321                 if(bTxOnly)\r
1322                 {\r
1323                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n"));\r
1324 \r
1325                         // <20130226, Kordan> Saving RxIQC, otherwise not initialized.\r
1326                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1327                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1328                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1329 //                      pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);\r
1330                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;\r
1331                         return;\r
1332                 }\r
1333 \r
1334                 reg = result[final_candidate][2];\r
1335 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)               \r
1336                 if( RTL_ABS(reg ,0x100) >= 16) \r
1337                         reg = 0x100;\r
1338 #endif\r
1339 \r
1340                 //2 Rx IQC\r
1341                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);\r
1342                 reg = result[final_candidate][3] & 0x3F;\r
1343                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);\r
1344                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1345                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);\r
1346 \r
1347                 reg = (result[final_candidate][3] >> 6) & 0xF;\r
1348                 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);\r
1349                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1350                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1351                 \r
1352         }\r
1353 }\r
1354 \r
1355 VOID\r
1356 _PHY_PathBFillIQKMatrix8723B(\r
1357 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1358         IN PDM_ODM_T            pDM_Odm,\r
1359 #else\r
1360         IN      PADAPTER        pAdapter,\r
1361 #endif\r
1362         IN      BOOLEAN         bIQKOK,\r
1363         IN      s4Byte          result[][8],\r
1364         IN      u1Byte          final_candidate,\r
1365         IN      BOOLEAN         bTxOnly                 //do Tx only\r
1366         )\r
1367 {\r
1368         u4Byte  Oldval_1, X, TX1_A, reg;\r
1369         s4Byte  Y, TX1_C;\r
1370 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1371         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1372         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1373         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1374         #endif\r
1375         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1376         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1377         #endif\r
1378 #endif  \r
1379         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1380 \r
1381         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
1382 \r
1383         if(final_candidate == 0xFF)\r
1384                 return;\r
1385 \r
1386         else if(bIQKOK)\r
1387         {\r
1388                 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
1389 \r
1390                 X = result[final_candidate][4];\r
1391                 if ((X & 0x00000200) != 0)\r
1392                         X = X | 0xFFFFFC00;     \r
1393                 TX1_A = (X * Oldval_1) >> 8;\r
1394                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));\r
1395 \r
1396                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);\r
1397                 \r
1398                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));\r
1399 \r
1400                 Y = result[final_candidate][5];\r
1401                 if ((Y & 0x00000200) != 0)\r
1402                         Y = Y | 0xFFFFFC00;     \r
1403 \r
1404                 TX1_C = (Y * Oldval_1) >> 8;\r
1405                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));\r
1406                 \r
1407                 //2 Tx IQC              \r
1408                 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));\r
1409 //              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE;\r
1410 //              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);\r
1411                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;\r
1412                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);\r
1413 \r
1414                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));\r
1415                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;\r
1416                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord);\r
1417 \r
1418                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));\r
1419                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;\r
1420                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);\r
1421                 \r
1422                 if(bTxOnly) {\r
1423                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n"));\r
1424                         \r
1425                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1426 //                      pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);             \r
1427                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;    \r
1428                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1429                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1430                         return;\r
1431                 }\r
1432 \r
1433                 //2 Rx IQC\r
1434                 reg = result[final_candidate][6];\r
1435                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);\r
1436                 reg = result[final_candidate][7] & 0x3F;\r
1437                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);\r
1438                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1439                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord);\r
1440 \r
1441                 reg = (result[final_candidate][7] >> 6) & 0xF;\r
1442 //              ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);\r
1443                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1444                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(ODM_GetBBReg(pDM_Odm,rOFDM0_RxIQExtAnta, bMaskDWord)& 0x0fffffff);                \r
1445         }\r
1446 }\r
1447 \r
1448 //\r
1449 // 2011/07/26 MH Add an API for testing IQK fail case.\r
1450 //\r
1451 // MP Already declare in odm.c \r
1452 \r
1453 VOID\r
1454 ODM_SetIQCbyRFpath(\r
1455         IN PDM_ODM_T            pDM_Odm,\r
1456     IN u4Byte RFpath\r
1457         )\r
1458 {\r
1459 \r
1460   PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1461 \r
1462   if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)&&\r
1463         (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0))\r
1464   {\r
1465         if(RFpath) //S1: RFpath = 0, S0:RFpath = 1\r
1466         {\r
1467           //S0 TX IQC\r
1468       ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);\r
1469           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);\r
1470           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);\r
1471       //S0 RX IQC\r
1472           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);\r
1473           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);\r
1474     }\r
1475     else\r
1476     {\r
1477           //S1 TX IQC\r
1478           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);\r
1479           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);\r
1480           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);\r
1481           //S1 RX IQC\r
1482           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);\r
1483           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);\r
1484     }\r
1485   }     \r
1486 }\r
1487 \r
1488 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) \r
1489 BOOLEAN\r
1490 ODM_CheckPowerStatus(\r
1491         IN      PADAPTER                Adapter)\r
1492 {\r
1493 /*\r
1494         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
1495         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;\r
1496         RT_RF_POWER_STATE       rtState;\r
1497         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);\r
1498 \r
1499         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.\r
1500         if (pMgntInfo->init_adpt_in_progress == TRUE)\r
1501         {\r
1502                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));\r
1503                 return  TRUE;\r
1504         }\r
1505         \r
1506         //\r
1507         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.\r
1508         //\r
1509         Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));        \r
1510         if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)\r
1511         {\r
1512                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", \r
1513                 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));\r
1514                 return  FALSE;\r
1515         }\r
1516 */\r
1517         return  TRUE;\r
1518 }\r
1519 #endif\r
1520 \r
1521 VOID\r
1522 _PHY_SaveADDARegisters8723B(\r
1523 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1524         IN PDM_ODM_T            pDM_Odm,\r
1525 #else\r
1526         IN      PADAPTER        pAdapter,\r
1527 #endif\r
1528         IN      pu4Byte         ADDAReg,\r
1529         IN      pu4Byte         ADDABackup,\r
1530         IN      u4Byte          RegisterNum\r
1531         )\r
1532 {\r
1533         u4Byte  i;\r
1534 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1535         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1536         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1537         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1538         #endif\r
1539         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1540         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1541         #endif\r
1542         \r
1543         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
1544                 return;\r
1545 #endif\r
1546         \r
1547         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));\r
1548         for( i = 0 ; i < RegisterNum ; i++){\r
1549                 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);\r
1550         }\r
1551 }\r
1552 \r
1553 \r
1554 VOID\r
1555 _PHY_SaveMACRegisters8723B(\r
1556 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1557         IN PDM_ODM_T            pDM_Odm,\r
1558 #else\r
1559         IN      PADAPTER        pAdapter,\r
1560 #endif\r
1561         IN      pu4Byte         MACReg,\r
1562         IN      pu4Byte         MACBackup\r
1563         )\r
1564 {\r
1565         u4Byte  i;\r
1566 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1567         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1568         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1569         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1570         #endif\r
1571         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1572         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1573         #endif\r
1574 #endif  \r
1575         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));\r
1576         for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1577                 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);               \r
1578         }\r
1579         MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);               \r
1580 \r
1581 }\r
1582 \r
1583 \r
1584 VOID\r
1585 _PHY_ReloadADDARegisters8723B(\r
1586 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1587         IN PDM_ODM_T            pDM_Odm,\r
1588 #else\r
1589         IN      PADAPTER        pAdapter,\r
1590 #endif\r
1591         IN      pu4Byte         ADDAReg,\r
1592         IN      pu4Byte         ADDABackup,\r
1593         IN      u4Byte          RegiesterNum\r
1594         )\r
1595 {\r
1596         u4Byte  i;\r
1597 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1598         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1599         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1600         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1601         #endif\r
1602         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1603         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1604         #endif\r
1605 #endif\r
1606         \r
1607         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));\r
1608         for(i = 0 ; i < RegiesterNum; i++)\r
1609         {\r
1610                 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);\r
1611         }\r
1612 }\r
1613 \r
1614 VOID\r
1615 _PHY_ReloadMACRegisters8723B(\r
1616 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1617         IN PDM_ODM_T            pDM_Odm,\r
1618 #else\r
1619         IN      PADAPTER        pAdapter,\r
1620 #endif\r
1621         IN      pu4Byte         MACReg,\r
1622         IN      pu4Byte         MACBackup\r
1623         )\r
1624 {\r
1625         u4Byte  i;\r
1626 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1627         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1628         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1629         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1630         #endif\r
1631         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1632         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1633         #endif\r
1634 #endif\r
1635         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Reload MAC parameters !\n"));\r
1636         for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1637                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);\r
1638         }\r
1639         ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);       \r
1640 }\r
1641 \r
1642 \r
1643 VOID\r
1644 _PHY_PathADDAOn8723B(\r
1645 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1646         IN PDM_ODM_T            pDM_Odm,\r
1647 #else\r
1648         IN      PADAPTER        pAdapter,\r
1649 #endif\r
1650         IN      pu4Byte         ADDAReg,\r
1651         IN      BOOLEAN         isPathAOn,\r
1652         IN      BOOLEAN         is2T\r
1653         )\r
1654 {\r
1655         u4Byte  pathOn;\r
1656         u4Byte  i;\r
1657 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1658         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1659         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1660         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1661         #endif\r
1662         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1663         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1664         #endif\r
1665 #endif\r
1666         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));\r
1667 \r
1668         pathOn = isPathAOn ? 0x01c00014 : 0x01c00014;\r
1669         if(FALSE == is2T){\r
1670                 pathOn = 0x01c00014;\r
1671                 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014);\r
1672         }\r
1673         else{\r
1674                 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);\r
1675         }\r
1676         \r
1677         for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){\r
1678                 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);\r
1679         }\r
1680         \r
1681 }\r
1682 \r
1683 VOID\r
1684 _PHY_MACSettingCalibration8723B(\r
1685 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1686         IN PDM_ODM_T            pDM_Odm,\r
1687 #else\r
1688         IN      PADAPTER        pAdapter,\r
1689 #endif\r
1690         IN      pu4Byte         MACReg,\r
1691         IN      pu4Byte         MACBackup       \r
1692         )\r
1693 {\r
1694         u4Byte  i = 0;\r
1695 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1696         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1697         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1698         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1699         #endif\r
1700         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1701         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1702         #endif\r
1703 #endif  \r
1704         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));\r
1705 \r
1706         ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);\r
1707 \r
1708         for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1709                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));\r
1710         }\r
1711         ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); \r
1712 \r
1713 }\r
1714 \r
1715 VOID\r
1716 _PHY_PathAStandBy8723B(\r
1717 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1718         IN PDM_ODM_T            pDM_Odm\r
1719 #else\r
1720         IN PADAPTER pAdapter\r
1721 #endif\r
1722         )\r
1723 {\r
1724 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1725         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1726         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1727         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1728         #endif\r
1729         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1730         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1731         #endif\r
1732 #endif  \r
1733         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path-A standby mode!\n"));\r
1734 \r
1735         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0);\r
1736 //Allen\r
1737         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);\r
1738         //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);\r
1739 //\r
1740         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1741 }\r
1742 \r
1743 VOID\r
1744 _PHY_PIModeSwitch8723B(\r
1745 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1746         IN PDM_ODM_T            pDM_Odm,\r
1747 #else\r
1748         IN      PADAPTER        pAdapter,\r
1749 #endif\r
1750         IN      BOOLEAN         PIMode\r
1751         )\r
1752 {\r
1753         u4Byte  mode;\r
1754 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1755         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1756         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1757         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1758         #endif\r
1759         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1760         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1761         #endif\r
1762 #endif  \r
1763         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));\r
1764 \r
1765         mode = PIMode ? 0x01000100 : 0x01000000;\r
1766         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);\r
1767         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);\r
1768 }\r
1769 \r
1770 BOOLEAN                                                 \r
1771 phy_SimularityCompare_8723B(\r
1772 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1773         IN PDM_ODM_T            pDM_Odm,\r
1774 #else\r
1775         IN      PADAPTER        pAdapter,\r
1776 #endif\r
1777         IN      s4Byte          result[][8],\r
1778         IN      u1Byte           c1,\r
1779         IN      u1Byte           c2\r
1780         )\r
1781 {\r
1782         u4Byte          i, j, diff, SimularityBitMap, bound = 0;\r
1783 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1784         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
1785         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1786         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1787         #endif\r
1788         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1789         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1790         #endif\r
1791 #endif  \r
1792         u1Byte          final_candidate[2] = {0xFF, 0xFF};      //for path A and path B\r
1793         BOOLEAN         bResult = TRUE;\r
1794 //#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1795 //      BOOLEAN         is2T = IS_92C_SERIAL( pHalData->VersionID);\r
1796 //#else\r
1797         BOOLEAN         is2T = TRUE;\r
1798 //#endif\r
1799 \r
1800         s4Byte tmp1 = 0,tmp2 = 0;\r
1801         \r
1802         if(is2T)\r
1803                 bound = 8;\r
1804         else\r
1805                 bound = 4;\r
1806 \r
1807         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2));\r
1808 \r
1809 \r
1810         SimularityBitMap = 0;\r
1811         \r
1812         for( i = 0; i < bound; i++ )\r
1813         {\r
1814                 \r
1815                 if((i==1) || (i==3) || (i==5) || (i==7))\r
1816                 {\r
1817                         if((result[c1][i]& 0x00000200) != 0)\r
1818                                 tmp1 = result[c1][i] | 0xFFFFFC00; \r
1819                         else\r
1820                                 tmp1 = result[c1][i];\r
1821 \r
1822                         if((result[c2][i]& 0x00000200) != 0)\r
1823                                 tmp2 = result[c2][i] | 0xFFFFFC00; \r
1824                         else\r
1825                                 tmp2 = result[c2][i];\r
1826                 }\r
1827                 else\r
1828                 {\r
1829                         tmp1 = result[c1][i];   \r
1830                         tmp2 = result[c2][i];\r
1831                 }\r
1832                 \r
1833                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);\r
1834                 \r
1835                 if (diff > MAX_TOLERANCE)\r
1836                 {\r
1837                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",      diff, i, result[c1][i], result[c2][i]));\r
1838                 \r
1839                         if((i == 2 || i == 6) && !SimularityBitMap)\r
1840                         {\r
1841                                 if(result[c1][i]+result[c1][i+1] == 0)\r
1842                                         final_candidate[(i/4)] = c2;\r
1843                                 else if (result[c2][i]+result[c2][i+1] == 0)\r
1844                                         final_candidate[(i/4)] = c1;\r
1845                                 else\r
1846                                         SimularityBitMap = SimularityBitMap|(1<<i);                             \r
1847                         }\r
1848                         else\r
1849                                 SimularityBitMap = SimularityBitMap|(1<<i);\r
1850                 }\r
1851         }\r
1852         \r
1853         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap   %x !!!\n", SimularityBitMap));\r
1854         \r
1855         if ( SimularityBitMap == 0)\r
1856         {\r
1857                 for( i = 0; i < (bound/4); i++ )\r
1858                 {\r
1859                         if(final_candidate[i] != 0xFF)\r
1860                         {\r
1861                                 for( j = i*4; j < (i+1)*4-2; j++)\r
1862                                         result[3][j] = result[final_candidate[i]][j];\r
1863                                 bResult = FALSE;\r
1864                         }\r
1865                 }\r
1866                 return bResult;\r
1867         }\r
1868         else \r
1869         {\r
1870 \r
1871         if (!(SimularityBitMap & 0x03))                 //path A TX OK\r
1872         {\r
1873                 for(i = 0; i < 2; i++)\r
1874                         result[3][i] = result[c1][i];\r
1875         }\r
1876 \r
1877         if (!(SimularityBitMap & 0x0c))                 //path A RX OK\r
1878         {\r
1879                 for(i = 2; i < 4; i++)\r
1880                         result[3][i] = result[c1][i];\r
1881         }\r
1882 \r
1883         if (!(SimularityBitMap & 0x30)) //path B TX OK\r
1884         {\r
1885                 for(i = 4; i < 6; i++)\r
1886                         result[3][i] = result[c1][i];\r
1887 \r
1888         }\r
1889 \r
1890         if (!(SimularityBitMap & 0xc0)) //path B RX OK\r
1891         {\r
1892                 for(i = 6; i < 8; i++)\r
1893                         result[3][i] = result[c1][i];\r
1894         }\r
1895                         return FALSE;\r
1896         }       \r
1897 }\r
1898 \r
1899 \r
1900 \r
1901 VOID    \r
1902 phy_IQCalibrate_8723B(\r
1903 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1904         IN PDM_ODM_T            pDM_Odm,\r
1905 #else\r
1906         IN      PADAPTER        pAdapter,\r
1907 #endif\r
1908         IN      s4Byte          result[][8],\r
1909         IN      u1Byte          t,\r
1910         IN      BOOLEAN         is2T,\r
1911         IN      u1Byte          RF_Path\r
1912         )\r
1913 {\r
1914 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1915         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
1916         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1917         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1918         #endif\r
1919         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1920         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1921         #endif\r
1922 #endif  \r
1923         u4Byte                  i;\r
1924         u1Byte                  PathAOK, PathBOK;\r
1925         u1Byte                  tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0);\r
1926         u1Byte                  tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0);    \r
1927         u4Byte                  ADDA_REG[IQK_ADDA_REG_NUM] = {  \r
1928                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
1929                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
1930                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
1931                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
1932                                                 rTx_To_Tx,              rRx_CCK,        \r
1933                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
1934                                                 rRx_TO_Rx,              rStandby,       \r
1935                                                 rSleep,                         rPMPD_ANAEN };\r
1936         u4Byte                  IQK_MAC_REG[IQK_MAC_REG_NUM] = {\r
1937                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
1938                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
1939                                         \r
1940         //since 92C & 92D have the different define in IQK_BB_REG       \r
1941         u4Byte  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
1942                                                         rOFDM0_TRxPathEnable,           rOFDM0_TRMuxPar,        \r
1943                                                         rFPGA0_XCD_RFInterfaceSW,       rConfig_AntA,   rConfig_AntB,\r
1944                                                         rFPGA0_XAB_RFInterfaceSW,       rFPGA0_XA_RFInterfaceOE,        \r
1945                                                         rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting       \r
1946                                                         };      \r
1947 \r
1948         u4Byte Path_SEL_BB;\r
1949 //        u4Byte Path_SEL_BB, Path_SEL_RF;\r
1950 \r
1951 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1952         u4Byte  retryCount = 2;\r
1953 #else\r
1954 #if MP_DRIVER\r
1955         const u4Byte    retryCount = 1;\r
1956 #else\r
1957         const u4Byte    retryCount = 2;\r
1958 #endif\r
1959 #endif\r
1960 \r
1961 if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )\r
1962 {\r
1963                 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);\r
1964                 return;\r
1965 }\r
1966 \r
1967         // Note: IQ calibration must be performed after loading \r
1968         //              PHY_REG.txt , and radio_a, radio_b.txt  \r
1969         \r
1970         //u4Byte bbvalue;\r
1971 \r
1972 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1973 #ifdef MP_TEST\r
1974                 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)\r
1975                         retryCount = 9; \r
1976 #endif\r
1977 #endif\r
1978 \r
1979 \r
1980         if(t==0)\r
1981         {\r
1982 //               bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);\r
1983 //                      RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));\r
1984 \r
1985                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
1986         \r
1987                 // Save ADDA parameters, turn Path A ADDA on\r
1988 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1989                 _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1990                 _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1991                 _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);                          \r
1992 #else\r
1993                 _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1994                 _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1995                 _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);           \r
1996 #endif\r
1997         }\r
1998         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
1999         \r
2000 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2001         \r
2002         _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T);\r
2003 #else\r
2004         _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T);\r
2005 #endif\r
2006                 \r
2007 //no serial mode\r
2008 #if 0   \r
2009         if(t==0)\r
2010         {\r
2011                 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));\r
2012         }\r
2013         \r
2014         if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
2015                 // Switch BB to PI mode to do IQ Calibration.\r
2016 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2017                 _PHY_PIModeSwitch8723B(pAdapter, TRUE);\r
2018 #else\r
2019                 _PHY_PIModeSwitch8723B(pDM_Odm, TRUE);\r
2020 #endif\r
2021         }\r
2022 #endif\r
2023 \r
2024         //save RF path for 8723B\r
2025 //      Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
2026 //      Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);\r
2027         \r
2028         //MAC settings\r
2029 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2030         _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2031 #else\r
2032         _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2033 #endif\r
2034         \r
2035         //BB setting\r
2036         //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);     \r
2037         ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);       \r
2038         ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);\r
2039         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);\r
2040         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);\r
2041 \r
2042         \r
2043 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);\r
2044 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);   \r
2045 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);\r
2046 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);    \r
2047         \r
2048 \r
2049 //for 8723B\r
2050 #if 0\r
2051         if(is2T)\r
2052         {\r
2053 \r
2054                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);\r
2055         }\r
2056 #endif\r
2057 \r
2058         \r
2059 //no APK\r
2060 #if 0\r
2061         //Page B init\r
2062         //AP or IQK\r
2063         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);\r
2064         \r
2065         if(is2T)\r
2066         {\r
2067                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);\r
2068         }\r
2069 #endif\r
2070 \r
2071 //RX IQ calibration setting for 8723B D cut large current issue when leaving IPS\r
2072 \r
2073         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);       \r
2074         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
2075     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
2076     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);\r
2077     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);\r
2078     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); \r
2079     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); \r
2080 /*\r
2081 //LOK RF setting\r
2082         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1);\r
2083         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1);\r
2084         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032);\r
2085         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); \r
2086 */\r
2087 \r
2088 \r
2089 //path A TX IQK\r
2090 #if 1\r
2091 \r
2092         for(i = 0 ; i < retryCount ; i++){\r
2093 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2094                 PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path);\r
2095 #else\r
2096                 PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path);\r
2097 #endif\r
2098 //              if(PathAOK == 0x03){\r
2099                 if(PathAOK == 0x01){\r
2100                         // Path A Tx IQK Success\r
2101                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2102                         pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask);\r
2103 \r
2104                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));\r
2105                                 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2106                                 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2107                         break;\r
2108                 }\r
2109 #if 0           \r
2110                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK\r
2111                 {\r
2112                         RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only      Tx Success!!\n"));\r
2113                         \r
2114                         result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2115                         result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;                        \r
2116                 }\r
2117 #endif          \r
2118         }\r
2119 #endif\r
2120 \r
2121 //path A RXIQK\r
2122 #if 1\r
2123 \r
2124         for(i = 0 ; i < retryCount ; i++){\r
2125 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2126                 PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path);\r
2127 #else\r
2128                 PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path);\r
2129 #endif\r
2130                 if(PathAOK == 0x03){\r
2131                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK Success!!\n"));\r
2132 //                              result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2133 //                              result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2134                                 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2135                                 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2136                         break;\r
2137                 }\r
2138                 else\r
2139                 {\r
2140                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));           \r
2141                 }\r
2142         }\r
2143 \r
2144         if(0x00 == PathAOK){            \r
2145                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));            \r
2146         }\r
2147 #endif\r
2148 \r
2149 //path B IQK\r
2150 #if 1\r
2151 \r
2152         if(is2T){\r
2153 \r
2154 /*\r
2155 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2156 //              _PHY_PathAStandBy8723B(pAdapter);\r
2157 \r
2158                 // Turn Path B ADDA on\r
2159                 _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T);\r
2160 #else\r
2161 //              _PHY_PathAStandBy8723B(pDM_Odm);\r
2162 \r
2163                 // Turn Path B ADDA on\r
2164                 _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T);\r
2165 #endif\r
2166 */\r
2167 \r
2168 //path B TX IQK\r
2169 #if 1\r
2170                 for(i = 0 ; i < retryCount ; i++){\r
2171 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2172                         PathBOK = phy_PathB_IQK_8723B(pAdapter);\r
2173 #else\r
2174                         PathBOK = phy_PathB_IQK_8723B(pDM_Odm);\r
2175 #endif\r
2176 //              if(PathBOK == 0x03){\r
2177                 if(PathBOK == 0x01){\r
2178                         // Path B Tx IQK Success\r
2179                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2180                         pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask);\r
2181 \r
2182                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n"));\r
2183                                 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2184                                 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2185                         break;\r
2186                 }\r
2187 #if 0           \r
2188                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK\r
2189                 {\r
2190                         RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only      Tx Success!!\n"));\r
2191                         \r
2192                         result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;\r
2193                         result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;                        \r
2194                 }\r
2195 #endif          \r
2196         }\r
2197 #endif\r
2198 \r
2199 //path B RX IQK\r
2200 #if 1\r
2201 \r
2202 for(i = 0 ; i < retryCount ; i++){\r
2203 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2204                 PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T);\r
2205 #else\r
2206                 PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T);\r
2207 #endif\r
2208                 if(PathBOK == 0x03){\r
2209                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK Success!!\n"));\r
2210 //                              result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2211 //                              result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2212                                 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2213                                 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2214                         break;\r
2215                 }\r
2216                 else\r
2217                 {\r
2218                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n"));           \r
2219                 }\r
2220         }\r
2221 \r
2222 #endif\r
2223 \r
2224 ////////Allen end ///////// \r
2225                 if(0x00 == PathBOK){            \r
2226                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));            \r
2227                 }\r
2228         }\r
2229 #endif  //pathB IQK\r
2230 \r
2231         //Back to BB mode, load original value\r
2232         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));\r
2233         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);\r
2234 \r
2235         if(t!=0)\r
2236         {\r
2237                 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
2238                         // Switch back BB to SI mode after finish IQ Calibration.\r
2239 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2240 //                      _PHY_PIModeSwitch8723B(pAdapter, FALSE);\r
2241 #else\r
2242 //                      _PHY_PIModeSwitch8723B(pDM_Odm, FALSE);\r
2243 #endif\r
2244                 }\r
2245 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2246 \r
2247                 // Reload ADDA power saving parameters\r
2248                 _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2249 \r
2250                 // Reload MAC parameters\r
2251                 _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2252                 \r
2253                 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
2254 #else\r
2255                 // Reload ADDA power saving parameters\r
2256                 _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2257 \r
2258                 // Reload MAC parameters\r
2259                 _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2260                 \r
2261                 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
2262 #endif\r
2263 \r
2264 \r
2265                 //Reload RF path\r
2266 //              ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);\r
2267 //              ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);\r
2268         \r
2269                 //Allen initial gain 0xc50\r
2270                 // Restore RX initial gain\r
2271                 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50);\r
2272                 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50);\r
2273                 if(is2T){\r
2274                         ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50);\r
2275                         ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58);\r
2276                 }\r
2277         \r
2278                 //load 0xe30 IQC default value\r
2279                 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
2280                 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                          \r
2281                 \r
2282         }\r
2283         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n"));\r
2284         \r
2285 }\r
2286 \r
2287 \r
2288 VOID    \r
2289 phy_LCCalibrate_8723B(\r
2290         IN PDM_ODM_T            pDM_Odm,\r
2291         IN      BOOLEAN         is2T\r
2292         )\r
2293 {\r
2294         u1Byte  tmpReg;\r
2295         u4Byte  RF_Amode=0, RF_Bmode=0, LC_Cal;\r
2296 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2297                 PADAPTER pAdapter = pDM_Odm->Adapter;\r
2298 #endif  \r
2299         if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )\r
2300         {\r
2301                 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);\r
2302                 return;\r
2303         }\r
2304 \r
2305         //Check continuous TX and Packet TX\r
2306         tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);\r
2307 \r
2308         if((tmpReg&0x70) != 0)                  //Deal with contisuous TX case\r
2309                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F);    //disable all continuous TX\r
2310         else                                                    // Deal with Packet TX case\r
2311                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);             // block all queues\r
2312 \r
2313         if((tmpReg&0x70) != 0)\r
2314         {\r
2315                 //1. Read original RF mode\r
2316                 //Path-A\r
2317 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2318                 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
2319 \r
2320                 //Path-B\r
2321                 if(is2T)\r
2322                         RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); \r
2323 #else\r
2324                 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
2325 \r
2326                 //Path-B\r
2327                 if(is2T)\r
2328                         RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);    \r
2329 #endif  \r
2330 \r
2331                 //2. Set RF mode = standby mode\r
2332                 //Path-A\r
2333                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);\r
2334 \r
2335                 //Path-B\r
2336                 if(is2T)\r
2337                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);                   \r
2338         }\r
2339         \r
2340         //3. Read RF reg18\r
2341 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2342         LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
2343 #else\r
2344         LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
2345 #endif  \r
2346         \r
2347         //4. Set LC calibration begin   bit15\r
2348         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON\r
2349         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);\r
2350 \r
2351         ODM_delay_ms(100);              \r
2352 \r
2353         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF\r
2354 \r
2355         // Channel 10 LC calibration issue for 8723bs with 26M xtal\r
2356         if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2)\r
2357         {\r
2358                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);\r
2359         }\r
2360 \r
2361         //Restore original situation\r
2362         if((tmpReg&0x70) != 0)  //Deal with contisuous TX case \r
2363         {  \r
2364                 //Path-A\r
2365                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);\r
2366                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);\r
2367                 \r
2368                 //Path-B\r
2369                 if(is2T)\r
2370                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);\r
2371         }\r
2372         else // Deal with Packet TX case\r
2373         {\r
2374                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); \r
2375         }\r
2376 }\r
2377 \r
2378 //Analog Pre-distortion calibration\r
2379 #define         APK_BB_REG_NUM  8\r
2380 #define         APK_CURVE_REG_NUM 4\r
2381 #define         PATH_NUM                2\r
2382 \r
2383 VOID    \r
2384 phy_APCalibrate_8723B(\r
2385 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2386         IN PDM_ODM_T            pDM_Odm,\r
2387 #else\r
2388         IN      PADAPTER        pAdapter,\r
2389 #endif\r
2390         IN      s1Byte          delta,\r
2391         IN      BOOLEAN         is2T\r
2392         )\r
2393 {\r
2394 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2395         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2396         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2397         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
2398         #endif\r
2399         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2400         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
2401         #endif\r
2402 #endif\r
2403         u4Byte                  regD[PATH_NUM];\r
2404         u4Byte                  tmpReg, index, offset,  apkbound;\r
2405         u1Byte                  path, i, pathbound = PATH_NUM;          \r
2406         u4Byte                  BB_backup[APK_BB_REG_NUM];\r
2407         u4Byte                  BB_REG[APK_BB_REG_NUM] = {      \r
2408                                                 rFPGA1_TxBlock,         rOFDM0_TRxPathEnable, \r
2409                                                 rFPGA0_RFMOD,   rOFDM0_TRMuxPar, \r
2410                                                 rFPGA0_XCD_RFInterfaceSW,       rFPGA0_XAB_RFInterfaceSW, \r
2411                                                 rFPGA0_XA_RFInterfaceOE,        rFPGA0_XB_RFInterfaceOE };\r
2412         u4Byte                  BB_AP_MODE[APK_BB_REG_NUM] = {  \r
2413                                                 0x00000020, 0x00a05430, 0x02040000, \r
2414                                                 0x000800e4, 0x00204000 };\r
2415         u4Byte                  BB_normal_AP_MODE[APK_BB_REG_NUM] = {   \r
2416                                                 0x00000020, 0x00a05430, 0x02040000, \r
2417                                                 0x000800e4, 0x22204000 };                                               \r
2418 \r
2419         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
2420         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
2421                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
2422                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
2423                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
2424                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
2425                                                 rTx_To_Tx,              rRx_CCK,        \r
2426                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
2427                                                 rRx_TO_Rx,              rStandby,       \r
2428                                                 rSleep,                         rPMPD_ANAEN };\r
2429 \r
2430         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
2431         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
2432                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
2433                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
2434 \r
2435         u4Byte                  APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
2436                                         {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},\r
2437                                         {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}\r
2438                                         };      \r
2439 \r
2440         u4Byte                  APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
2441                                         {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},  //path settings equal to path b settings\r
2442                                         {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}\r
2443                                         };\r
2444         \r
2445         u4Byte                  APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
2446                                         {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},\r
2447                                         {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}\r
2448                                         };\r
2449 \r
2450         u4Byte                  APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
2451                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},  //path settings equal to path b settings\r
2452                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}\r
2453                                         };\r
2454 \r
2455         u4Byte                  AFE_on_off[PATH_NUM] = {\r
2456                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
2457 \r
2458         u4Byte                  APK_offset[PATH_NUM] = {\r
2459                                         rConfig_AntA, rConfig_AntB};\r
2460 \r
2461         u4Byte                  APK_normal_offset[PATH_NUM] = {\r
2462                                         rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};\r
2463                                         \r
2464         u4Byte                  APK_value[PATH_NUM] = {\r
2465                                         0x92fc0000, 0x12fc0000};                                        \r
2466 \r
2467         u4Byte                  APK_normal_value[PATH_NUM] = {\r
2468                                         0x92680000, 0x12680000};                                        \r
2469 \r
2470         s1Byte                  APK_delta_mapping[APK_BB_REG_NUM][13] = {\r
2471                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2472                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},                                                                                  \r
2473                                         {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2474                                         {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2475                                         {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}\r
2476                                         };\r
2477         \r
2478         u4Byte                  APK_normal_setting_value_1[13] = {\r
2479                                         0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,\r
2480                                         0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,\r
2481                                         0x12680000, 0x00880000, 0x00880000\r
2482                                         };\r
2483 \r
2484         u4Byte                  APK_normal_setting_value_2[16] = {\r
2485                                         0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,\r
2486                                         0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,\r
2487                                         0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,\r
2488                                         0x00050006\r
2489                                         };\r
2490         \r
2491         u4Byte                  APK_result[PATH_NUM][APK_BB_REG_NUM];   //val_1_1a, val_1_2a, val_2a, val_3a, val_4a\r
2492 //      u4Byte                  AP_curve[PATH_NUM][APK_CURVE_REG_NUM];\r
2493 \r
2494         s4Byte                  BB_offset, delta_V, delta_offset;\r
2495 \r
2496 #if MP_DRIVER == 1\r
2497 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2498         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);   \r
2499 #else\r
2500         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2501 #endif\r
2502         pMptCtx->APK_bound[0] = 45;\r
2503         pMptCtx->APK_bound[1] = 52;     \r
2504 \r
2505 #endif\r
2506 \r
2507         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));\r
2508         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));\r
2509         if(!is2T)\r
2510                 pathbound = 1;\r
2511 \r
2512         //2 FOR NORMAL CHIP SETTINGS\r
2513 \r
2514 // Temporarily do not allow normal driver to do the following settings because these offset\r
2515 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal\r
2516 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the\r
2517 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.\r
2518 #if MP_DRIVER != 1\r
2519         return;\r
2520 #endif\r
2521         //settings adjust for normal chip\r
2522         for(index = 0; index < PATH_NUM; index ++)\r
2523         {\r
2524                 APK_offset[index] = APK_normal_offset[index];\r
2525                 APK_value[index] = APK_normal_value[index];\r
2526                 AFE_on_off[index] = 0x6fdb25a4;\r
2527         }\r
2528 \r
2529         for(index = 0; index < APK_BB_REG_NUM; index ++)\r
2530         {\r
2531                 for(path = 0; path < pathbound; path++)\r
2532                 {\r
2533                         APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];\r
2534                         APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];\r
2535                 }\r
2536                 BB_AP_MODE[index] = BB_normal_AP_MODE[index];\r
2537         }                       \r
2538 \r
2539         apkbound = 6;\r
2540         \r
2541         //save BB default value\r
2542         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2543         {\r
2544                 if(index == 0)          //skip \r
2545                         continue;                               \r
2546                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
2547         }\r
2548         \r
2549         //save MAC default value                                                                                                        \r
2550 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2551         _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
2552         \r
2553         //save AFE default value\r
2554         _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2555 #else\r
2556         _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2557         \r
2558         //save AFE default value\r
2559         _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2560 #endif\r
2561 \r
2562         for(path = 0; path < pathbound; path++)\r
2563         {\r
2564 \r
2565 \r
2566                 if(path == ODM_RF_PATH_A)\r
2567                 {\r
2568                         //path A APK\r
2569                         //load APK setting\r
2570                         //path-A                \r
2571                         offset = rPdp_AntA;\r
2572                         for(index = 0; index < 11; index ++)                    \r
2573                         {\r
2574                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2575                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2576                                 \r
2577                                 offset += 0x04;\r
2578                         }\r
2579                         \r
2580                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2581                         \r
2582                         offset = rConfig_AntA;\r
2583                         for(; index < 13; index ++)             \r
2584                         {\r
2585                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2586                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2587                                 \r
2588                                 offset += 0x04;\r
2589                         }       \r
2590                         \r
2591                         //page-B1\r
2592                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
2593                 \r
2594                         //path A\r
2595                         offset = rPdp_AntA;\r
2596                         for(index = 0; index < 16; index++)\r
2597                         {\r
2598                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
2599                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2600                                 \r
2601                                 offset += 0x04;\r
2602                         }                               \r
2603                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                                                      \r
2604                 }\r
2605                 else if(path == ODM_RF_PATH_B)\r
2606                 {\r
2607                         //path B APK\r
2608                         //load APK setting\r
2609                         //path-B                \r
2610                         offset = rPdp_AntB;\r
2611                         for(index = 0; index < 10; index ++)                    \r
2612                         {\r
2613                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2614                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2615                                 \r
2616                                 offset += 0x04;\r
2617                         }\r
2618                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);                       \r
2619 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2620                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2621 #else\r
2622                         PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2623 #endif\r
2624                         \r
2625                         offset = rConfig_AntA;\r
2626                         index = 11;\r
2627                         for(; index < 13; index ++) //offset 0xb68, 0xb6c               \r
2628                         {\r
2629                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2630                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
2631                                 \r
2632                                 offset += 0x04;\r
2633                         }       \r
2634                         \r
2635                         //page-B1\r
2636                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
2637                         \r
2638                         //path B\r
2639                         offset = 0xb60;\r
2640                         for(index = 0; index < 16; index++)\r
2641                         {\r
2642                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
2643                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
2644                                 \r
2645                                 offset += 0x04;\r
2646                         }                               \r
2647                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);                                                     \r
2648                 }\r
2649         \r
2650                 //save RF default value\r
2651 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2652                 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);\r
2653 #else\r
2654                 regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord);\r
2655 #endif\r
2656                 \r
2657                 //Path A AFE all on, path B AFE All off or vise versa\r
2658                 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
2659                         ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);\r
2660                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));               \r
2661 \r
2662                 //BB to AP mode\r
2663                 if(path == 0)\r
2664                 {                               \r
2665                         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2666                         {\r
2667 \r
2668                                 if(index == 0)          //skip \r
2669                                         continue;                       \r
2670                                 else if (index < 5)\r
2671                                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);\r
2672                                 else if (BB_REG[index] == 0x870)\r
2673                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);\r
2674                                 else\r
2675                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);                                       \r
2676                         }\r
2677 \r
2678                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);                  \r
2679                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                                  \r
2680                 }\r
2681                 else            //path B\r
2682                 {\r
2683                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);                  \r
2684                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);                                  \r
2685                 \r
2686                 }\r
2687 \r
2688                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));                              \r
2689 \r
2690                 //MAC settings\r
2691 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2692                 _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);\r
2693 #else\r
2694                 _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2695 #endif\r
2696                 \r
2697                 if(path == ODM_RF_PATH_A)       //Path B to standby mode\r
2698                 {\r
2699                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);                       \r
2700                 }\r
2701                 else                    //Path A to standby mode\r
2702                 {\r
2703                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);                       \r
2704                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2705                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);                                            \r
2706                 }\r
2707 \r
2708                 delta_offset = ((delta+14)/2);\r
2709                 if(delta_offset < 0)\r
2710                         delta_offset = 0;\r
2711                 else if (delta_offset > 12)\r
2712                         delta_offset = 12;\r
2713                         \r
2714                 //AP calibration\r
2715                 for(index = 0; index < APK_BB_REG_NUM; index++)\r
2716                 {\r
2717                         if(index != 1)  //only DO PA11+PAD01001, AP RF setting\r
2718                                 continue;\r
2719                                         \r
2720                         tmpReg = APK_RF_init_value[path][index];\r
2721 #if 1                   \r
2722                         if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)\r
2723                         {\r
2724                                 BB_offset = (tmpReg & 0xF0000) >> 16;\r
2725 \r
2726                                 if(!(tmpReg & BIT15)) //sign bit 0\r
2727                                 {\r
2728                                         BB_offset = -BB_offset;\r
2729                                 }\r
2730 \r
2731                                 delta_V = APK_delta_mapping[index][delta_offset];\r
2732                                 \r
2733                                 BB_offset += delta_V;\r
2734 \r
2735                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));              \r
2736                                 \r
2737                                 if(BB_offset < 0)\r
2738                                 {\r
2739                                         tmpReg = tmpReg & (~BIT15);\r
2740                                         BB_offset = -BB_offset;\r
2741                                 }\r
2742                                 else\r
2743                                 {\r
2744                                         tmpReg = tmpReg | BIT15;\r
2745                                 }\r
2746                                 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);\r
2747                         }\r
2748 #endif\r
2749 \r
2750                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);\r
2751 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2752                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));            \r
2753                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2754                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));              \r
2755                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2756                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));                                 \r
2757 #else\r
2758                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));               \r
2759                         ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2760                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));         \r
2761                         ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2762                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));                                    \r
2763 #endif\r
2764                         \r
2765                         // PA11+PAD01111, one shot      \r
2766                         i = 0;\r
2767                         do\r
2768                         {\r
2769                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
2770                                 {\r
2771                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);              \r
2772                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2773                                         ODM_delay_ms(3);                                \r
2774                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);\r
2775                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2776 \r
2777                                         ODM_delay_ms(20);\r
2778                                 }\r
2779                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2780 \r
2781                                 if(path == ODM_RF_PATH_A)\r
2782                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);\r
2783                                 else\r
2784                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);\r
2785                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));         \r
2786                                 \r
2787 \r
2788                                 i++;\r
2789                         }\r
2790                         while(tmpReg > apkbound && i < 4);\r
2791 \r
2792                         APK_result[path][index] = tmpReg;\r
2793                 }\r
2794         }\r
2795 \r
2796         //reload MAC default value      \r
2797 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2798         _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
2799 #else\r
2800         _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2801 #endif\r
2802         \r
2803         //reload BB default value       \r
2804         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2805         {\r
2806 \r
2807                 if(index == 0)          //skip \r
2808                         continue;                                       \r
2809                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
2810         }\r
2811 \r
2812         //reload AFE default value\r
2813 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2814         _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2815 #else\r
2816         _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2817 #endif\r
2818 \r
2819         //reload RF path default value\r
2820         for(path = 0; path < pathbound; path++)\r
2821         {\r
2822                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);\r
2823                 if(path == ODM_RF_PATH_B)\r
2824                 {\r
2825                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2826                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);                                            \r
2827                 }\r
2828 \r
2829                 //note no index == 0\r
2830                 if (APK_result[path][1] > 6)\r
2831                         APK_result[path][1] = 6;\r
2832                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));                                      \r
2833         }\r
2834 \r
2835         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\n"));\r
2836         \r
2837 \r
2838         for(path = 0; path < pathbound; path++)\r
2839         {\r
2840                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, \r
2841                 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));\r
2842                 if(path == ODM_RF_PATH_A)\r
2843                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2844                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));              \r
2845                 else\r
2846                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2847                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));                                              \r
2848 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2849                 if(!IS_HARDWARE_TYPE_8723A(pAdapter))           \r
2850                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, \r
2851                         ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));                    \r
2852 #endif          \r
2853         }\r
2854 \r
2855         pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;\r
2856 \r
2857         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));\r
2858 }\r
2859 \r
2860 \r
2861 \r
2862 #define         DP_BB_REG_NUM           7\r
2863 #define         DP_RF_REG_NUM           1\r
2864 #define         DP_RETRY_LIMIT          10\r
2865 #define         DP_PATH_NUM     2\r
2866 #define         DP_DPK_NUM                      3\r
2867 #define         DP_DPK_VALUE_NUM        2\r
2868 \r
2869 \r
2870 \r
2871 //IQK version:V2.5    20140123\r
2872 //IQK is controlled by Is2ant, RF path\r
2873 VOID\r
2874 PHY_IQCalibrate_8723B(\r
2875 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2876         IN PDM_ODM_T            pDM_Odm,\r
2877 #else\r
2878         IN      PADAPTER        pAdapter,\r
2879 #endif\r
2880         IN      BOOLEAN         bReCovery,\r
2881         IN BOOLEAN      bRestore,\r
2882         IN BOOLEAN      Is2ant, //false:1ant, true:2-ant\r
2883         IN u1Byte       RF_Path //0:S1, 1:S0\r
2884         )\r
2885 {\r
2886 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2887         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
2888 \r
2889         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2890         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc; \r
2891         #else  // (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2892         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;   \r
2893         #endif\r
2894 \r
2895         #if (MP_DRIVER == 1)\r
2896         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
2897         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2898         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2899         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
2900         #endif  \r
2901         #endif//(MP_DRIVER == 1)\r
2902 #endif  \r
2903 \r
2904         s4Byte                  result[4][8];   //last is final result\r
2905         u1Byte                  i, final_candidate, Indexforchannel;\r
2906         BOOLEAN                 bPathAOK, bPathBOK;\r
2907         s4Byte                  RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;\r
2908         BOOLEAN                 is12simular, is13simular, is23simular;  \r
2909         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
2910         u4Byte                  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
2911                                         rOFDM0_XARxIQImbalance,         rOFDM0_XBRxIQImbalance, \r
2912                                         rOFDM0_ECCAThreshold,   rOFDM0_AGCRSSITable,\r
2913                                         rOFDM0_XATxIQImbalance,         rOFDM0_XBTxIQImbalance, \r
2914                                         rOFDM0_XCTxAFE,                         rOFDM0_XDTxAFE, \r
2915                                         rOFDM0_RxIQExtAnta};\r
2916 //      u4Byte                  Path_SEL_BB = 0;\r
2917         u4Byte                  GNT_BT_default;\r
2918         u4Byte                  StartTime; \r
2919         s4Byte                  ProgressingTime;\r
2920 \r
2921 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )\r
2922         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
2923                 return;\r
2924 #else\r
2925         prtl8192cd_priv priv = pDM_Odm->priv;\r
2926 \r
2927 #ifdef MP_TEST\r
2928         if(priv->pshare->rf_ft_var.mp_specific)\r
2929         {\r
2930                 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))\r
2931                         return;\r
2932         }\r
2933 #endif\r
2934 \r
2935         if(priv->pshare->IQK_88E_done)\r
2936                 bReCovery= 1;\r
2937         priv->pshare->IQK_88E_done = 1;\r
2938 \r
2939 #endif  \r
2940 \r
2941 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2942         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
2943         {\r
2944                 return;\r
2945         }\r
2946 #endif\r
2947 \r
2948 #if MP_DRIVER == 1      \r
2949         bStartContTx = pMptCtx->bStartContTx;\r
2950         bSingleTone = pMptCtx->bSingleTone;\r
2951         bCarrierSuppression = pMptCtx->bCarrierSuppression; \r
2952 #endif\r
2953         \r
2954         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
2955         if(bSingleTone || bCarrierSuppression)\r
2956                 return;\r
2957 \r
2958 #if DISABLE_BB_RF\r
2959         return;\r
2960 #endif\r
2961         if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) \r
2962                 return;\r
2963 \r
2964 \r
2965         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2966         pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;\r
2967         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2968 \r
2969         if (bRestore) {\r
2970                 u4Byte offset, data;\r
2971                 u1Byte path, bResult = SUCCESS;\r
2972                 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
2973 \r
2974                 //#define PATH_S0       1 // RF_PATH_B\r
2975                 //#define PATH_S1       0 // RF_PATH_A\r
2976 \r
2977                 path = (RF_Path==0 ? ODM_RF_PATH_A : ODM_RF_PATH_B);\r
2978 \r
2979                 // Restore TX IQK\r
2980                 for (i = 0; i < 3; ++i) {\r
2981                         offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];\r
2982                         data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];\r
2983                         if ((offset==0) || (i==1 && data==0)) { // 0xc80, 0xc88 ==> index=1\r
2984                                 DBG_871X("%s =>path:%s Restore TX IQK result failed \n",__FUNCTION__,(path==ODM_RF_PATH_A)?"A":"B");\r
2985                                 bResult = FAIL;\r
2986                                 break;\r
2987                         }\r
2988                         //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));\r
2989                         ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);\r
2990                 }\r
2991 \r
2992                 // Restore RX IQK\r
2993                 for (i = 0; i < 2; ++i) {\r
2994                         offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];\r
2995                         data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];\r
2996                         if ((offset==0) || (i==0 && data==0)) {         // 0xc14, 0xc1c ==> index=0\r
2997                                 DBG_871X("%s =>path:%s  Restore RX IQK result failed \n",__FUNCTION__,(path==ODM_RF_PATH_A)?"A":"B");\r
2998                                 bResult = FAIL;\r
2999                                 break;\r
3000                         }\r
3001                         //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));\r
3002                         ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);\r
3003                 }\r
3004 \r
3005                 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] ==0) {\r
3006                         DBG_871X("%s => Restore Path-A TxLOK result failed \n",__FUNCTION__);\r
3007                         bResult = FAIL;\r
3008                 } else {\r
3009                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]);  \r
3010                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]);  \r
3011                 }\r
3012 \r
3013                 if (bResult == SUCCESS)\r
3014                         goto out;\r
3015         }\r
3016 \r
3017 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))\r
3018         if(bReCovery)\r
3019 #else//for ODM_WIN\r
3020         if(bReCovery && (!pAdapter->bInHctTest))  //YJ,add for PowerTest,120405\r
3021 #endif  \r
3022         {\r
3023                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n"));\r
3024 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3025                 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3026 #else\r
3027                 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3028 #endif\r
3029                 goto out;\r
3030         }\r
3031 \r
3032         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
3033         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:Start!!!\n"));\r
3034 \r
3035         //save default GNT_BT\r
3036         GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord);\r
3037         // Save RF Path \r
3038 //      Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
3039 //      Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);\r
3040 \r
3041     //set GNT_BT=0, pause BT traffic\r
3042 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);\r
3043 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x1);\r
3044 \r
3045 \r
3046         for(i = 0; i < 8; i++)\r
3047         {\r
3048                 result[0][i] = 0;\r
3049                 result[1][i] = 0;\r
3050                 result[2][i] = 0;\r
3051                 result[3][i] = 0;\r
3052         }\r
3053         final_candidate = 0xff;\r
3054         bPathAOK = FALSE;\r
3055         bPathBOK = FALSE;\r
3056         is12simular = FALSE;\r
3057         is23simular = FALSE;\r
3058         is13simular = FALSE;\r
3059 \r
3060 \r
3061         for (i=0; i<3; i++)\r
3062         {\r
3063 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3064                 phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path);\r
3065 #else\r
3066                 phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path);\r
3067 #endif\r
3068 \r
3069                 if(i == 1)\r
3070                 {\r
3071 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3072                         is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1);\r
3073 #else\r
3074                         is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1);\r
3075 #endif                  \r
3076                         if(is12simular)\r
3077                         {\r
3078                                 final_candidate = 0;\r
3079                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));                         \r
3080                                 break;\r
3081                         }\r
3082                 }\r
3083                 \r
3084                 if(i == 2)\r
3085                 {\r
3086 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3087                         is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2);\r
3088 #else\r
3089                         is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2);\r
3090 #endif                  \r
3091                         if(is13simular)\r
3092                         {\r
3093                                 final_candidate = 0;                    \r
3094                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));\r
3095                                 \r
3096                                 break;\r
3097                         }\r
3098 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3099                         is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2);\r
3100 #else\r
3101                         is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2);\r
3102 #endif                  \r
3103                         if(is23simular)\r
3104                         {\r
3105                                 final_candidate = 1;\r
3106                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));                         \r
3107                         }\r
3108                         else\r
3109                         {\r
3110                                 for(i = 0; i < 8; i++)\r
3111                                         RegTmp += result[3][i];\r
3112 \r
3113                                 if(RegTmp != 0)\r
3114                                         final_candidate = 3;                    \r
3115                                 else\r
3116                                         final_candidate = 0xFF;\r
3117                         }\r
3118                 }\r
3119         }\r
3120 //      RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));\r
3121 \r
3122         for (i=0; i<4; i++)\r
3123         {\r
3124                 RegE94 = result[i][0];\r
3125                 RegE9C = result[i][1];\r
3126                 RegEA4 = result[i][2];\r
3127                 RegEAC = result[i][3];\r
3128                 RegEB4 = result[i][4];\r
3129                 RegEBC = result[i][5];\r
3130                 RegEC4 = result[i][6];\r
3131                 RegECC = result[i][7];\r
3132                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
3133         }\r
3134         \r
3135         if(final_candidate != 0xff)\r
3136         {\r
3137                 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];\r
3138                 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];\r
3139                 RegEA4 = result[final_candidate][2];\r
3140                 RegEAC = result[final_candidate][3];\r
3141                 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];\r
3142                 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];\r
3143                 RegEC4 = result[final_candidate][6];\r
3144                 RegECC = result[final_candidate][7];\r
3145                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: final_candidate is %x\n",final_candidate));\r
3146                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
3147                 bPathAOK = bPathBOK = TRUE;\r
3148         }\r
3149         else\r
3150         {\r
3151                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: FAIL use default value\n"));\r
3152         \r
3153                 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100;      //X default value\r
3154                 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0;                //Y default value\r
3155         }\r
3156 \r
3157 #if MP_DRIVER == 1\r
3158         if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))\r
3159 #endif\r
3160         {\r
3161                 if (RegE94 != 0)\r
3162                 {\r
3163 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3164                         _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
3165 #else\r
3166                         _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
3167 #endif\r
3168                 }\r
3169         }\r
3170         \r
3171 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3172 #if MP_DRIVER == 1\r
3173         if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))\r
3174 #endif\r
3175         {\r
3176                 if (RegEB4 != 0)\r
3177                 {\r
3178                         _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));\r
3179                 }\r
3180         }\r
3181 #endif\r
3182 \r
3183 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3184         Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);\r
3185 #else\r
3186         Indexforchannel = 0;    \r
3187 #endif\r
3188 \r
3189 //To Fix BSOD when final_candidate is 0xff\r
3190 //by sherry 20120321\r
3191         if(final_candidate < 4)\r
3192         {\r
3193                 for(i = 0; i < IQK_Matrix_REG_NUM; i++)\r
3194                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];\r
3195                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;          \r
3196         }\r
3197         //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
3198         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
3199 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3200 \r
3201         _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3202 #else\r
3203         _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);\r
3204 #endif  \r
3205 \r
3206         //restore GNT_BT\r
3207         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default);\r
3208         // Restore RF Path\r
3209 //      ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);\r
3210 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);\r
3211 \r
3212         //Resotr RX mode table parameter\r
3213         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
3214         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 );\r
3215         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );\r
3216         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177 );\r
3217         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );\r
3218         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd );\r
3219 \r
3220         //set GNT_BT= HW control\r
3221 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);\r
3222 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0);\r
3223 \r
3224         if (Is2ant) {\r
3225                 if (RF_Path == 0x0)     //S1\r
3226                         ODM_SetIQCbyRFpath(pDM_Odm, 0);\r
3227                 else    //S0\r
3228                         ODM_SetIQCbyRFpath(pDM_Odm, 1);\r
3229         }\r
3230 \r
3231         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));\r
3232         ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);\r
3233         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));\r
3234 \r
3235 out:\r
3236         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
3237         pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;\r
3238         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
3239 }\r
3240 \r
3241 \r
3242 VOID\r
3243 PHY_LCCalibrate_8723B(\r
3244         IN PDM_ODM_T            pDM_Odm\r
3245         )\r
3246 {\r
3247         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
3248         u4Byte                  timeout = 2000, timecount = 0;\r
3249         u4Byte                  StartTime; \r
3250         s4Byte                  ProgressingTime;\r
3251         \r
3252 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3253         PADAPTER        pAdapter = pDM_Odm->Adapter;\r
3254 \r
3255         #if (MP_DRIVER == 1)\r
3256         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
3257         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
3258         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3259         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
3260         #endif  \r
3261         #endif//(MP_DRIVER == 1)\r
3262 #endif  \r
3263 \r
3264 \r
3265 \r
3266 \r
3267 #if MP_DRIVER == 1      \r
3268         bStartContTx = pMptCtx->bStartContTx;\r
3269         bSingleTone = pMptCtx->bSingleTone;\r
3270         bCarrierSuppression = pMptCtx->bCarrierSuppression; \r
3271 #endif\r
3272 \r
3273 \r
3274 #if DISABLE_BB_RF\r
3275         return;\r
3276 #endif\r
3277 \r
3278 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3279         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
3280         {\r
3281                 return;\r
3282         }\r
3283 #endif  \r
3284         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
3285         if(bSingleTone || bCarrierSuppression)\r
3286                 return;\r
3287         \r
3288         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
3289         while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)\r
3290         {\r
3291                 ODM_delay_ms(50);\r
3292                 timecount += 50;\r
3293         }       \r
3294         \r
3295         pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;\r
3296 \r
3297         \r
3298         phy_LCCalibrate_8723B(pDM_Odm, FALSE);\r
3299 \r
3300 \r
3301         pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;\r
3302 \r
3303         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));\r
3304         ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);\r
3305         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("LCK ProgressingTime = %d\n", ProgressingTime));\r
3306 }\r
3307 \r
3308 VOID\r
3309 PHY_APCalibrate_8723B(\r
3310 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3311         IN PDM_ODM_T            pDM_Odm,\r
3312 #else\r
3313         IN      PADAPTER        pAdapter,\r
3314 #endif\r
3315         IN      s1Byte          delta   \r
3316         )\r
3317 {\r
3318 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3319         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3320         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3321         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3322         #endif\r
3323         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3324         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3325         #endif\r
3326 #endif  \r
3327 #if DISABLE_BB_RF\r
3328         return;\r
3329 #endif\r
3330 \r
3331         return;\r
3332 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3333         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
3334         {\r
3335                 return;\r
3336         }\r
3337 #endif  \r
3338 \r
3339 #if FOR_BRAZIL_PRETEST != 1\r
3340         if(pDM_Odm->RFCalibrateInfo.bAPKdone)\r
3341 #endif          \r
3342                 return;\r
3343 \r
3344 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3345         if(IS_92C_SERIAL( pHalData->VersionID)){\r
3346                 phy_APCalibrate_8723B(pAdapter, delta, TRUE);\r
3347         }\r
3348         else\r
3349 #endif\r
3350         {\r
3351                 // For 88C 1T1R\r
3352 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3353                 phy_APCalibrate_8723B(pAdapter, delta, FALSE);\r
3354 #else\r
3355                 phy_APCalibrate_8723B(pDM_Odm, delta, FALSE);\r
3356 #endif\r
3357         }\r
3358 }\r
3359 VOID phy_SetRFPathSwitch_8723B(\r
3360 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3361         IN PDM_ODM_T            pDM_Odm,\r
3362 #else\r
3363         IN      PADAPTER        pAdapter,\r
3364 #endif\r
3365         IN      BOOLEAN         bMain,\r
3366         IN      BOOLEAN         is2T\r
3367         )\r
3368 {\r
3369         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3370 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3371         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3372 #endif\r
3373 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3374         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3375 #endif\r
3376 \r
3377         if(bMain) // Left antenna       \r
3378         {\r
3379                 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1);          \r
3380         }                       \r
3381         else\r
3382         {\r
3383                 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2);          \r
3384         }               \r
3385 }\r
3386 VOID PHY_SetRFPathSwitch_8723B(\r
3387 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3388         IN PDM_ODM_T            pDM_Odm,\r
3389 #else\r
3390         IN      PADAPTER        pAdapter,\r
3391 #endif\r
3392         IN      BOOLEAN         bMain\r
3393         )\r
3394 {\r
3395 \r
3396 #if DISABLE_BB_RF\r
3397         return;\r
3398 #endif\r
3399 \r
3400 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3401                 phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE);\r
3402 #endif          \r
3403 \r
3404 }\r
3405 \r
3406 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3407 //digital predistortion\r
3408 VOID    \r
3409 phy_DigitalPredistortion8723B(\r
3410 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3411         IN      PADAPTER        pAdapter,\r
3412 #else\r
3413         IN PDM_ODM_T    pDM_Odm,\r
3414 #endif\r
3415         IN      BOOLEAN         is2T\r
3416         )\r
3417 {\r
3418 #if (RT_PLATFORM == PLATFORM_WINDOWS)\r
3419 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3420         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3421         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3422         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3423         #endif\r
3424         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3425         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3426         #endif\r
3427 #endif  \r
3428 \r
3429         u4Byte                  tmpReg, tmpReg2, index,  i;     \r
3430         u1Byte                  path, pathbound = PATH_NUM;\r
3431         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
3432         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
3433                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
3434                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
3435                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
3436                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
3437                                                 rTx_To_Tx,              rRx_CCK,        \r
3438                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
3439                                                 rRx_TO_Rx,              rStandby,       \r
3440                                                 rSleep,                         rPMPD_ANAEN };\r
3441 \r
3442         u4Byte                  BB_backup[DP_BB_REG_NUM];       \r
3443         u4Byte                  BB_REG[DP_BB_REG_NUM] = {\r
3444                                                 rOFDM0_TRxPathEnable, rFPGA0_RFMOD, \r
3445                                                 rOFDM0_TRMuxPar,        rFPGA0_XCD_RFInterfaceSW,\r
3446                                                 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, \r
3447                                                 rFPGA0_XB_RFInterfaceOE};                                               \r
3448         u4Byte                  BB_settings[DP_BB_REG_NUM] = {\r
3449                                                 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, \r
3450                                                 0x0, 0x0, 0x0}; \r
3451 \r
3452         u4Byte                  RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];\r
3453         u4Byte                  RF_REG[DP_RF_REG_NUM] = {\r
3454                                                 RF_TXBIAS_A};\r
3455 \r
3456         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
3457         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
3458                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
3459                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
3460 \r
3461         u4Byte                  Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {\r
3462                                                 {0x1e1e1e1e, 0x03901e1e},\r
3463                                                 {0x18181818, 0x03901818},\r
3464                                                 {0x0e0e0e0e, 0x03900e0e}\r
3465                                         };\r
3466 \r
3467         u4Byte                  AFE_on_off[PATH_NUM] = {\r
3468                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
3469 \r
3470         u1Byte                  RetryCount = 0;\r
3471 \r
3472 \r
3473         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n"));\r
3474         \r
3475         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R")));\r
3476 \r
3477         //save BB default value\r
3478         for(index=0; index<DP_BB_REG_NUM; index++)\r
3479                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
3480 \r
3481         //save MAC default value\r
3482 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3483         _PHY_SaveMACRegisters8723B(pAdapter, BB_REG, MAC_backup);\r
3484 #else\r
3485         _PHY_SaveMACRegisters8723B(pDM_Odm, BB_REG, MAC_backup);\r
3486 #endif  \r
3487 \r
3488         //save RF default value\r
3489         for(path=0; path<DP_PATH_NUM; path++)\r
3490         {\r
3491                 for(index=0; index<DP_RF_REG_NUM; index++)\r
3492 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3493                         RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); \r
3494 #else\r
3495                         RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);       \r
3496 #endif  \r
3497         }       \r
3498         \r
3499         //save AFE default value\r
3500 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3501         _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
3502 #else\r
3503                 _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
3504 #endif  \r
3505         \r
3506         //Path A/B AFE all on\r
3507         for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
3508                 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);\r
3509 \r
3510         //BB register setting\r
3511         for(index = 0; index < DP_BB_REG_NUM; index++)\r
3512         {\r
3513                 if(index < 4)\r
3514                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);\r
3515                 else if (index == 4)\r
3516                         ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);                  \r
3517                 else\r
3518                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);                      \r
3519         }\r
3520 \r
3521         //MAC register setting\r
3522 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3523         _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);\r
3524 #else\r
3525         _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);\r
3526 #endif  \r
3527 \r
3528         //PAGE-E IQC setting    \r
3529         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
3530         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);  \r
3531         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
3532         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
3533         \r
3534         //path_A DPK\r
3535         //Path B to standby mode\r
3536         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);\r
3537 \r
3538         // PA gain = 11 & PAD1 => tx_agc 1f ~11\r
3539         // PA gain = 11 & PAD2 => tx_agc 10~0e\r
3540         // PA gain = 01 => tx_agc 0b~0d\r
3541         // PA gain = 00 => tx_agc 0a~00\r
3542         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);      \r
3543         ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);           \r
3544         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
3545 \r
3546         //do inner loopback DPK 3 times \r
3547         for(i = 0; i < 3; i++)\r
3548         {\r
3549                 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
3550                 for(index = 0; index < 3; index++)\r
3551                         ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3552                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);                  \r
3553                 for(index = 0; index < 4; index++)\r
3554                         ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);                  \r
3555         \r
3556                 // PAGE_B for Path-A inner loopback DPK setting\r
3557                 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);\r
3558                 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
3559                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3560                 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);     \r
3561                 \r
3562                 //----send one shot signal----//\r
3563                 // Path A\r
3564                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);\r
3565                 ODM_delay_ms(1);\r
3566                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);\r
3567                 ODM_delay_ms(50);\r
3568         }\r
3569 \r
3570         //PA gain = 11 => tx_agc = 1a\r
3571         for(index = 0; index < 3; index++)              \r
3572                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);    \r
3573         ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);    \r
3574         for(index = 0; index < 4; index++)              \r
3575                 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);    \r
3576 \r
3577         //====================================\r
3578         // PAGE_B for Path-A DPK setting\r
3579         //====================================\r
3580         // open inner loopback @ b00[19]:10 od 0xb00 0x01097018\r
3581         ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);\r
3582         ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
3583         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3584         ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);     \r
3585 \r
3586         //rf_lpbk_setup\r
3587         //1.rf 00:5205a, rf 0d:0e52c\r
3588         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);\r
3589         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);        \r
3590         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );               \r
3591 \r
3592         //----send one shot signal----//\r
3593         // Path A\r
3594         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
3595         ODM_delay_ms(1);\r
3596         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);\r
3597         ODM_delay_ms(50);\r
3598 \r
3599         while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
3600         {\r
3601                 //----read back measurement results----//\r
3602                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);\r
3603                 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);\r
3604                 ODM_delay_ms(10);\r
3605                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);\r
3606                 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);\r
3607                 ODM_delay_ms(10);\r
3608 \r
3609                 tmpReg = (tmpReg & bMaskHWord) >> 16;\r
3610                 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;         \r
3611                 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )\r
3612                 {\r
3613                         ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);\r
3614                 \r
3615                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
3616                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
3617                         ODM_delay_ms(1);\r
3618                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
3619                         ODM_delay_ms(1);                        \r
3620                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);                       \r
3621                         ODM_delay_ms(50);                       \r
3622                         RetryCount++;                   \r
3623                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));                                                                          \r
3624                 }\r
3625                 else\r
3626                 {\r
3627                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));              \r
3628                         pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;\r
3629                         break;\r
3630                 }               \r
3631         }\r
3632         RetryCount = 0;\r
3633         \r
3634         //DPP path A\r
3635         if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
3636         {       \r
3637                 // DP settings\r
3638                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);\r
3639                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);\r
3640                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3641                 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);\r
3642                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
3643 \r
3644                 for(i=rPdp_AntA; i<=0xb3c; i+=4)\r
3645                 {\r
3646                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
3647                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));                \r
3648                 }\r
3649                 \r
3650                 //pwsf\r
3651                 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);   \r
3652                 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);                   \r
3653                 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);                                   \r
3654 \r
3655                 for(i=0xb4c; i<=0xb5c; i+=4)\r
3656                 {\r
3657                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
3658                 }               \r
3659 \r
3660                 //TX_AGC boundary\r
3661                 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);   \r
3662                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                                              \r
3663         }\r
3664         else\r
3665         {\r
3666                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);       \r
3667                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);             \r
3668         }\r
3669 \r
3670         //DPK path B\r
3671         if(is2T)\r
3672         {\r
3673                 //Path A to standby mode\r
3674                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);\r
3675                 \r
3676                 // LUTs => tx_agc\r
3677                 // PA gain = 11 & PAD1, => tx_agc 1f ~11\r
3678                 // PA gain = 11 & PAD2, => tx_agc 10 ~0e\r
3679                 // PA gain = 01 => tx_agc 0b ~0d\r
3680                 // PA gain = 00 => tx_agc 0a ~00\r
3681                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);      \r
3682                 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);           \r
3683                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
3684 \r
3685                 //do inner loopback DPK 3 times \r
3686                 for(i = 0; i < 3; i++)\r
3687                 {\r
3688                         //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
3689                         for(index = 0; index < 4; index++)\r
3690                                 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3691                         for(index = 0; index < 2; index++)\r
3692                                 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3693                         for(index = 0; index < 2; index++)\r
3694                                 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3695                 \r
3696                         // PAGE_B for Path-A inner loopback DPK setting\r
3697                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);\r
3698                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);\r
3699                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3700                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3701                         \r
3702                         //----send one shot signal----//\r
3703                         // Path B\r
3704                         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);\r
3705                         ODM_delay_ms(1);\r
3706                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);\r
3707                         ODM_delay_ms(50);\r
3708                 }\r
3709 \r
3710                 // PA gain = 11 => tx_agc = 1a  \r
3711                 for(index = 0; index < 4; index++)\r
3712                         ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);   \r
3713                 for(index = 0; index < 2; index++)\r
3714                         ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);   \r
3715                 for(index = 0; index < 2; index++)\r
3716                         ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);   \r
3717 \r
3718                 // PAGE_B for Path-B DPK setting\r
3719                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3720                 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);     \r
3721                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);               \r
3722                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3723 \r
3724                 // RF lpbk switches on\r
3725                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);           \r
3726                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);           \r
3727 \r
3728                 //Path-B RF lpbk\r
3729                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);\r
3730                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);\r
3731                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); \r
3732 \r
3733                 //----send one shot signal----//\r
3734                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3735                 ODM_delay_ms(1);        \r
3736                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3737                 ODM_delay_ms(50);\r
3738                 \r
3739                 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3740                 {\r
3741                         //----read back measurement results----//\r
3742                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);               \r
3743                         tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);\r
3744                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);               \r
3745                         tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);\r
3746                         \r
3747                         tmpReg = (tmpReg & bMaskHWord) >> 16;\r
3748                         tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;\r
3749                         \r
3750                         if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)\r
3751                         {\r
3752                                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3753                         \r
3754                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
3755                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
3756                                 ODM_delay_ms(1);\r
3757                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3758                                 ODM_delay_ms(1);        \r
3759                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3760                                 ODM_delay_ms(50);                       \r
3761                                 RetryCount++;                   \r
3762                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));                                                                                                               \r
3763                         }\r
3764                         else\r
3765                         {\r
3766                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));                                     \r
3767                                 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;\r
3768                                 break;\r
3769                         }                                               \r
3770                 }\r
3771         \r
3772                 //DPP path B\r
3773                 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3774                 {\r
3775                         // DP setting\r
3776                         // LUT by SRAM\r
3777                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);\r
3778                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);\r
3779                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3780                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);\r
3781                         \r
3782                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
3783                         for(i=0xb60; i<=0xb9c; i+=4)\r
3784                         {\r
3785                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
3786                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));\r
3787                         }\r
3788 \r
3789                         // PWSF\r
3790                         ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);   \r
3791                         ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);                   \r
3792                         ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);                                   \r
3793 \r
3794                         for(i=0xbac; i<=0xbbc; i+=4)\r
3795                         {\r
3796                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
3797                         }               \r
3798                         \r
3799                         // tx_agc boundary\r
3800                         ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);   \r
3801                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                              \r
3802                         \r
3803                 }\r
3804                 else\r
3805                 {\r
3806                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);       \r
3807                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);                             \r
3808                 }\r
3809         }\r
3810         \r
3811         //reload BB default value\r
3812         for(index=0; index<DP_BB_REG_NUM; index++)\r
3813                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
3814         \r
3815         //reload RF default value\r
3816         for(path = 0; path<DP_PATH_NUM; path++)\r
3817         {\r
3818                 for( i = 0 ; i < DP_RF_REG_NUM ; i++){\r
3819                         ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);\r
3820                 }\r
3821         }\r
3822         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);    //standby mode\r
3823         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);            //RF lpbk switches off\r
3824 \r
3825         //reload AFE default value\r
3826 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3827         _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); \r
3828 \r
3829         //reload MAC default value      \r
3830         _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
3831 #else\r
3832         _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);  \r
3833 \r
3834         //reload MAC default value      \r
3835         _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
3836 #endif          \r
3837 \r
3838         pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;\r
3839         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n"));\r
3840 #endif          \r
3841 }\r
3842 \r
3843 VOID\r
3844 PHY_DigitalPredistortion_8723B(\r
3845 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3846         IN      PADAPTER        pAdapter\r
3847 #else\r
3848         IN PDM_ODM_T    pDM_Odm\r
3849 #endif          \r
3850         )\r
3851 {\r
3852 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3853         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3854         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3855         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3856         #endif\r
3857         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3858         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3859         #endif\r
3860 #endif  \r
3861 #if DISABLE_BB_RF\r
3862         return;\r
3863 #endif\r
3864 \r
3865         return;\r
3866 \r
3867         if(pDM_Odm->RFCalibrateInfo.bDPdone)\r
3868                 return;\r
3869 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3870 \r
3871         if(IS_92C_SERIAL( pHalData->VersionID)){\r
3872                 phy_DigitalPredistortion8723B(pAdapter, TRUE);\r
3873         }\r
3874         else\r
3875 #endif          \r
3876         {\r
3877                 // For 88C 1T1R\r
3878                 phy_DigitalPredistortion8723B(pAdapter, FALSE);\r
3879         }\r
3880 }\r
3881         \r
3882 \r
3883 \r
3884 //return value TRUE => Main; FALSE => Aux\r
3885 \r
3886 BOOLEAN phy_QueryRFPathSwitch_8723B(\r
3887 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3888         IN PDM_ODM_T            pDM_Odm,\r
3889 #else\r
3890         IN      PADAPTER        pAdapter,\r
3891 #endif\r
3892         IN      BOOLEAN         is2T\r
3893         )\r
3894 {\r
3895 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3896         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3897         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3898         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3899         #endif\r
3900         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3901         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3902         #endif\r
3903 #endif  \r
3904 \r
3905 \r
3906         if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01)\r
3907                 return TRUE;\r
3908         else \r
3909                 return FALSE;\r
3910 \r
3911 }\r
3912 \r
3913 \r
3914 \r
3915 //return value TRUE => Main; FALSE => Aux\r
3916 BOOLEAN PHY_QueryRFPathSwitch_8723B(    \r
3917 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3918         IN PDM_ODM_T            pDM_Odm\r
3919 #else\r
3920         IN      PADAPTER        pAdapter\r
3921 #endif\r
3922         )\r
3923 {\r
3924         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3925 \r
3926 #if DISABLE_BB_RF\r
3927         return TRUE;\r
3928 #endif\r
3929 \r
3930 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3931                 return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE);\r
3932 #else\r
3933                 return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE);\r
3934 #endif\r
3935 \r
3936 }\r
3937 #endif\r