drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/rtl8723b/phydm_RegConfig8723B.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #include "Mp_Precomp.h"
  22 #include "../phydm_precomp.h"
  23
  24 #if (RTL8723B_SUPPORT == 1)
  25
  26 void
  27 odm_ConfigRFReg_8723B(
  28         IN      PDM_ODM_T                               pDM_Odm,
  29         IN      u4Byte                                  Addr,
  30         IN      u4Byte                                  Data,
  31         IN  ODM_RF_RADIO_PATH_E     RF_PATH,
  32         IN      u4Byte                              RegAddr
  33         )
  34 {
  35     if(Addr == 0xfe || Addr == 0xffe)
  36         {
  37                 #ifdef CONFIG_LONG_DELAY_ISSUE
  38                 ODM_sleep_ms(50);
  39                 #else
  40                 ODM_delay_ms(50);
  41                 #endif
  42         }
  43         else
  44         {
  45                 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  46                 // Add 1us delay between BB/RF register setting.
  47                 ODM_delay_us(1);
  48
  49                 //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25.
  50                 if(Addr == 0xb6)
  51                 {
  52                         u4Byte getvalue=0;
  53                         u1Byte  count =0;
  54                         getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
  55
  56                         ODM_delay_us(1);
  57
  58                         while((getvalue>>8)!=(Data>>8))
  59                         {
  60                                 count++;
  61                                 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  62                                 ODM_delay_us(1);
  63                                 getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
  64                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
  65                                 if(count>5)
  66                                         break;
  67                         }
  68                 }
  69
  70                 if(Addr == 0xb2)
  71                 {
  72                         u4Byte getvalue=0;
  73                         u1Byte  count =0;
  74                         getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
  75
  76                         ODM_delay_us(1);
  77
  78                         while(getvalue!=Data)
  79                         {
  80                                 count++;
  81                                 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  82                                 ODM_delay_us(1);
  83                                 //Do LCK againg
  84                                 ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
  85                                 ODM_delay_us(1);
  86                                 getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
  87                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
  88                                 if(count>5)
  89                                         break;
  90                         }
  91                 }
  92         }
  93 }
  94
  95
  96 void
  97 odm_ConfigRF_RadioA_8723B(
  98         IN      PDM_ODM_T                               pDM_Odm,
  99         IN      u4Byte                                  Addr,
 100         IN      u4Byte                                  Data
 101         )
 102 {
 103         u4Byte  content = 0x1000; // RF_Content: radioa_txt
 104         u4Byte  maskforPhySet= (u4Byte)(content&0xE000);
 105
 106     odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
 107
 108     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
 109 }
 110
 111 void
 112 odm_ConfigRF_RadioB_8723B(
 113         IN      PDM_ODM_T                               pDM_Odm,
 114         IN      u4Byte                                  Addr,
 115         IN      u4Byte                                  Data
 116         )
 117 {
 118         u4Byte  content = 0x1001; // RF_Content: radiob_txt
 119         u4Byte  maskforPhySet= (u4Byte)(content&0xE000);
 120
 121     odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
 122
 123         ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
 124
 125 }
 126
 127 void
 128 odm_ConfigMAC_8723B(
 129         IN      PDM_ODM_T       pDM_Odm,
 130         IN      u4Byte          Addr,
 131         IN      u1Byte          Data
 132         )
 133 {
 134         ODM_Write1Byte(pDM_Odm, Addr, Data);
 135     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
 136 }
 137
 138 void
 139 odm_ConfigBB_AGC_8723B(
 140     IN  PDM_ODM_T       pDM_Odm,
 141     IN  u4Byte          Addr,
 142     IN  u4Byte          Bitmask,
 143     IN  u4Byte          Data
 144     )
 145 {
 146         ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
 147         // Add 1us delay between BB/RF register setting.
 148         ODM_delay_us(1);
 149
 150     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
 151 }
 152
 153 void
 154 odm_ConfigBB_PHY_REG_PG_8723B(
 155         IN      PDM_ODM_T       pDM_Odm,
 156         IN      u4Byte          Band,
 157         IN      u4Byte          RfPath,
 158         IN      u4Byte          TxNum,
 159     IN  u4Byte          Addr,
 160     IN  u4Byte          Bitmask,
 161     IN  u4Byte          Data
 162     )
 163 {
 164         if (Addr == 0xfe || Addr == 0xffe)
 165                 #ifdef CONFIG_LONG_DELAY_ISSUE
 166                 ODM_sleep_ms(50);
 167                 #else
 168                 ODM_delay_ms(50);
 169                 #endif
 170     else
 171     {
 172 #if     !(DM_ODM_SUPPORT_TYPE&ODM_AP)
 173             PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
 174 #endif
 175     }
 176         ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
 177 }
 178
 179 void
 180 odm_ConfigBB_PHY_8723B(
 181         IN      PDM_ODM_T       pDM_Odm,
 182     IN  u4Byte          Addr,
 183     IN  u4Byte          Bitmask,
 184     IN  u4Byte          Data
 185     )
 186 {
 187         if (Addr == 0xfe)
 188                 #ifdef CONFIG_LONG_DELAY_ISSUE
 189                 ODM_sleep_ms(50);
 190                 #else
 191                 ODM_delay_ms(50);
 192                 #endif
 193         else if (Addr == 0xfd)
 194                 ODM_delay_ms(5);
 195         else if (Addr == 0xfc)
 196                 ODM_delay_ms(1);
 197         else if (Addr == 0xfb)
 198                 ODM_delay_us(50);
 199         else if (Addr == 0xfa)
 200                 ODM_delay_us(5);
 201         else if (Addr == 0xf9)
 202                 ODM_delay_us(1);
 203         else
 204         {
 205                 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
 206         }
 207
 208         // Add 1us delay between BB/RF register setting.
 209         ODM_delay_us(1);
 210     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
 211 }
 212
 213 void
 214 odm_ConfigBB_TXPWR_LMT_8723B(
 215         IN      PDM_ODM_T       pDM_Odm,
 216         IN      pu1Byte         Regulation,
 217         IN      pu1Byte         Band,
 218         IN      pu1Byte         Bandwidth,
 219         IN      pu1Byte         RateSection,
 220         IN      pu1Byte         RfPath,
 221         IN      pu1Byte         Channel,
 222         IN      pu1Byte         PowerLimit
 223         )
 224 {
 225 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 226                 PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
 227                         Bandwidth, RateSection, RfPath, Channel, PowerLimit);
 228 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 229                 PHY_SetTxPowerLimit(pDM_Odm->Adapter, Regulation, Band,
 230                         Bandwidth, RateSection, RfPath, Channel, PowerLimit);
 231 #endif
 232 }
 233
 234 #endif
 235