drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/phydm.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 \r
  22 #ifndef __HALDMOUTSRC_H__\r
  23 #define __HALDMOUTSRC_H__\r
  24 \r
  25 //============================================================\r
  26 // include files\r
  27 //============================================================\r
  28 #include "phydm_pre_define.h"\r
  29 #include "phydm_dig.h"\r
  30 #include "phydm_edcaturbocheck.h"\r
  31 #include "phydm_pathdiv.h"\r
  32 #include "phydm_antdiv.h"\r
  33 #include "phydm_antdect.h"\r
  34 #include "phydm_dynamicbbpowersaving.h"\r
  35 #include "phydm_rainfo.h"\r
  36 #include "phydm_dynamictxpower.h"\r
  37 #include "phydm_cfotracking.h"\r
  38 #include "phydm_acs.h"\r
  39 #include "phydm_adaptivity.h"\r
  40 \r
  41 \r
  42 #if (RTL8814A_SUPPORT == 1)\r
  43 #include "rtl8814a/phydm_iqk_8814a.h"\r
  44 #endif\r
  45 \r
  46 \r
  47 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
  48 #include "halphyrf_ap.h"\r
  49 #include "phydm_powertracking_ap.h"\r
  50 #endif\r
  51 \r
  52 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
  53 #include "phydm_beamforming.h"\r
  54 #include "phydm_noisemonitor.h"\r
  55 #include "halphyrf_ce.h"\r
  56 #include "phydm_powertracking_ce.h"\r
  57 #endif\r
  58 \r
  59 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
  60 #include "phydm_beamforming.h"\r
  61 #include "phydm_rxhp.h"\r
  62 #include "halphyrf_win.h"\r
  63 #include "phydm_powertracking_win.h"\r
  64 #endif\r
  65 \r
  66 //============================================================\r
  67 // Definition \r
  68 //============================================================\r
  69 //\r
  70 // 2011/09/22 MH Define all team supprt ability.\r
  71 //\r
  72 \r
  73 //\r
  74 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.\r
  75 //\r
  76 //#define               DM_ODM_SUPPORT_AP                       0\r
  77 //#define               DM_ODM_SUPPORT_ADSL                     0\r
  78 //#define               DM_ODM_SUPPORT_CE                       0\r
  79 //#define               DM_ODM_SUPPORT_MP                       1\r
  80 \r
  81 //\r
  82 // 2011/09/28 MH Define ODM SW team support flag.\r
  83 //\r
  84 \r
  85 //For SW AntDiv, PathDiv, 8192C AntDiv joint use\r
  86 #define TP_MODE         0\r
  87 #define RSSI_MODE               1\r
  88 \r
  89 #define TRAFFIC_LOW     0\r
  90 #define TRAFFIC_HIGH    1\r
  91 #define TRAFFIC_ULTRA_LOW       2\r
  92 #define TRAFFIC_MID     3\r
  93 \r
  94 \r
  95 #define NONE                    0\r
  96 \r
  97 \r
  98 \r
  99 \r
 100 //8723A High Power IGI Setting\r
 101 #define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22\r
 102 #define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28\r
 103 #define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a\r
 104 #define         DM_DIG_LOW_PWR_THRESHOLD        0x14\r
 105 \r
 106 \r
 107 //============================================================\r
 108 // structure and define\r
 109 //============================================================\r
 110 \r
 111 //\r
 112 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.\r
 113 // We need to remove to other position???\r
 114 //\r
 115 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 116 typedef         struct rtl8192cd_priv {\r
 117         u1Byte          temp;\r
 118 \r
 119 }rtl8192cd_priv, *prtl8192cd_priv;\r
 120 #endif\r
 121 \r
 122 \r
 123 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 124 typedef         struct _ADAPTER{\r
 125         u1Byte          temp;\r
 126         #ifdef AP_BUILD_WORKAROUND\r
 127         HAL_DATA_TYPE*          temp2;\r
 128         prtl8192cd_priv         priv;\r
 129         #endif\r
 130 }ADAPTER, *PADAPTER;\r
 131 #endif\r
 132 \r
 133 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 134 \r
 135 typedef         struct _WLAN_STA{\r
 136         u1Byte          temp;\r
 137 } WLAN_STA, *PRT_WLAN_STA;\r
 138 \r
 139 #endif\r
 140 \r
 141 typedef struct _Dynamic_Primary_CCA{\r
 142         u1Byte          PriCCA_flag;\r
 143         u1Byte          intf_flag;\r
 144         u1Byte          intf_type;  \r
 145         u1Byte          DupRTS_flag;\r
 146         u1Byte          Monitor_flag;\r
 147         u1Byte          CH_offset;\r
 148         u1Byte          MF_state;\r
 149 }Pri_CCA_T, *pPri_CCA_T;\r
 150 \r
 151 \r
 152 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 153 \r
 154 \r
 155 #ifdef ADSL_AP_BUILD_WORKAROUND\r
 156 #define MAX_TOLERANCE                   5\r
 157 #define IQK_DELAY_TIME                  1               //ms\r
 158 #endif\r
 159 #if 0//defined in 8192cd.h\r
 160 //\r
 161 // Indicate different AP vendor for IOT issue.\r
 162 //\r
 163 typedef enum _HT_IOT_PEER\r
 164 {\r
 165         HT_IOT_PEER_UNKNOWN                     = 0,\r
 166         HT_IOT_PEER_REALTEK                     = 1,\r
 167         HT_IOT_PEER_REALTEK_92SE                = 2,\r
 168         HT_IOT_PEER_BROADCOM            = 3,\r
 169         HT_IOT_PEER_RALINK                      = 4,\r
 170         HT_IOT_PEER_ATHEROS                     = 5,\r
 171         HT_IOT_PEER_CISCO                               = 6,\r
 172         HT_IOT_PEER_MERU                                = 7,    \r
 173         HT_IOT_PEER_MARVELL                     = 8,\r
 174         HT_IOT_PEER_REALTEK_SOFTAP      = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17\r
 175         HT_IOT_PEER_SELF_SOFTAP                 = 10, // Self is SoftAP\r
 176         HT_IOT_PEER_AIRGO                               = 11,\r
 177         HT_IOT_PEER_INTEL                               = 12, \r
 178         HT_IOT_PEER_RTK_APCLIENT                = 13, \r
 179         HT_IOT_PEER_REALTEK_81XX                = 14,   \r
 180         HT_IOT_PEER_REALTEK_WOW                 = 15,   \r
 181         HT_IOT_PEER_MAX                                 = 16\r
 182 }HT_IOT_PEER_E, *PHTIOT_PEER_E;\r
 183 #endif\r
 184 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 185 \r
 186 #define         DM_Type_ByFW                    0\r
 187 #define         DM_Type_ByDriver                1\r
 188 \r
 189 //\r
 190 // Declare for common info\r
 191 //\r
 192 \r
 193 #define IQK_THRESHOLD                   8\r
 194 #define DPK_THRESHOLD                   4\r
 195 \r
 196 \r
 197 #if (DM_ODM_SUPPORT_TYPE &  (ODM_AP))\r
 198 __PACK typedef struct _ODM_Phy_Status_Info_\r
 199 {\r
 200         u1Byte          RxPWDBAll;\r
 201         u1Byte          SignalQuality;                                  /* in 0-100 index. */\r
 202         u1Byte          RxMIMOSignalStrength[4];                /* in 0~100 index */\r
 203         s1Byte          RxMIMOSignalQuality[4];         /* EVM */\r
 204         s1Byte          RxSNR[4];                                       /* per-path's SNR */\r
 205 #if (RTL8822B_SUPPORT == 1)\r
 206         u1Byte          RxCount;                                                /* RX path counter---*/\r
 207 #endif\r
 208         u1Byte          BandWidth;\r
 209 \r
 210 } __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T;\r
 211 \r
 212 typedef struct _ODM_Phy_Status_Info_Append_\r
 213 {\r
 214         u1Byte          MAC_CRC32;      \r
 215 \r
 216 }ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T;\r
 217 \r
 218 #else\r
 219 \r
 220 typedef struct _ODM_Phy_Status_Info_\r
 221 {\r
 222         //\r
 223         // Be care, if you want to add any element please insert between \r
 224         // RxPWDBAll & SignalStrength.\r
 225         //\r
 226 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))\r
 227         u4Byte          RxPWDBAll;      \r
 228 #else\r
 229         u1Byte          RxPWDBAll;      \r
 230 #endif\r
 231         u1Byte          SignalQuality;                          /* in 0-100 index. */\r
 232         s1Byte          RxMIMOSignalQuality[4];         /* per-path's EVM */\r
 233         u1Byte          RxMIMOEVMdbm[4];                        /* per-path's EVM dbm */\r
 234         u1Byte          RxMIMOSignalStrength[4];        /* in 0~100 index */\r
 235         s2Byte          Cfo_short[4];                           /* per-path's Cfo_short */\r
 236         s2Byte          Cfo_tail[4];                                    /* per-path's Cfo_tail */\r
 237         s1Byte          RxPower;                                        /* in dBm Translate from PWdB */\r
 238         s1Byte          RecvSignalPower;                        /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */\r
 239         u1Byte          BTRxRSSIPercentage;\r
 240         u1Byte          SignalStrength;                         /* in 0-100 index. */\r
 241         s1Byte          RxPwr[4];                                       /* per-path's pwdb */\r
 242         s1Byte          RxSNR[4];                                       /* per-path's SNR       */\r
 243 #if (RTL8822B_SUPPORT == 1)\r
 244         u1Byte          RxCount:2;                                      /* RX path counter---*/\r
 245         u1Byte          BandWidth:2;\r
 246         u1Byte          rxsc:4;                                         /* sub-channel---*/\r
 247 #else\r
 248         u1Byte          BandWidth;\r
 249 #endif\r
 250         u1Byte          btCoexPwrAdjust;\r
 251 #if (RTL8822B_SUPPORT == 1)\r
 252         u1Byte          channel;                                                /* channel number---*/\r
 253         BOOLEAN         bMuPacket;                                      /* is MU packet or not---*/\r
 254         BOOLEAN         bBeamformed;                            /* BF packet---*/\r
 255 #endif\r
 256 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;\r
 257 #endif\r
 258 \r
 259 typedef struct _ODM_Per_Pkt_Info_\r
 260 {\r
 261         //u1Byte                Rate;   \r
 262         u1Byte          DataRate;\r
 263         u1Byte          StationID;\r
 264         BOOLEAN         bPacketMatchBSSID;\r
 265         BOOLEAN         bPacketToSelf;\r
 266         BOOLEAN         bPacketBeacon;\r
 267         BOOLEAN         bToSelf;\r
 268 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;\r
 269 \r
 270 \r
 271 typedef struct _ODM_Phy_Dbg_Info_\r
 272 {\r
 273         //ODM Write,debug info\r
 274         s1Byte          RxSNRdB[4];\r
 275         u4Byte          NumQryPhyStatus;\r
 276         u4Byte          NumQryPhyStatusCCK;\r
 277         u4Byte          NumQryPhyStatusOFDM;\r
 278 #if (RTL8822B_SUPPORT == 1)\r
 279         u4Byte          NumQryMuPkt;\r
 280         u4Byte          NumQryBfPkt;\r
 281 #endif\r
 282         u1Byte          NumQryBeaconPkt;\r
 283         //Others\r
 284         s4Byte          RxEVM[4];       \r
 285         \r
 286 }ODM_PHY_DBG_INFO_T;\r
 287 \r
 288 \r
 289 typedef struct _ODM_Mac_Status_Info_\r
 290 {\r
 291         u1Byte  test;\r
 292         \r
 293 }ODM_MAC_INFO;\r
 294 \r
 295 //\r
 296 // 2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T\r
 297 // Please declare below ODM relative info in your STA info structure.\r
 298 //\r
 299 #if 1\r
 300 typedef         struct _ODM_STA_INFO{\r
 301         // Driver Write\r
 302         BOOLEAN         bUsed;                          // record the sta status link or not?\r
 303         //u1Byte                WirelessMode;           // \r
 304         u1Byte          IOTPeer;                        // Enum value.  HT_IOT_PEER_E\r
 305 \r
 306         // ODM Write\r
 307         //1 PHY_STATUS_INFO\r
 308         u1Byte          RSSI_Path[4];           // \r
 309         u1Byte          RSSI_Ave;\r
 310         u1Byte          RXEVM[4];\r
 311         u1Byte          RXSNR[4];\r
 312 \r
 313         // ODM Write\r
 314         //1 TX_INFO (may changed by IC)\r
 315         //TX_INFO_T             pTxInfo;                                // Define in IC folder. Move lower layer.\r
 316 #if 0\r
 317         u1Byte          ANTSEL_A;                       //in Jagar: 4bit; others: 2bit\r
 318         u1Byte          ANTSEL_B;                       //in Jagar: 4bit; others: 2bit\r
 319         u1Byte          ANTSEL_C;                       //only in Jagar: 4bit\r
 320         u1Byte          ANTSEL_D;                       //only in Jagar: 4bit\r
 321         u1Byte          TX_ANTL;                        //not in Jagar: 2bit\r
 322         u1Byte          TX_ANT_HT;                      //not in Jagar: 2bit\r
 323         u1Byte          TX_ANT_CCK;                     //not in Jagar: 2bit\r
 324         u1Byte          TXAGC_A;                        //not in Jagar: 4bit\r
 325         u1Byte          TXAGC_B;                        //not in Jagar: 4bit\r
 326         u1Byte          TXPWR_OFFSET;           //only in Jagar: 3bit\r
 327         u1Byte          TX_ANT;                         //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK\r
 328 #endif\r
 329 \r
 330         //\r
 331         //      Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 332         //      Move To lower layer.\r
 333         //\r
 334         // ODM Write Wilson will handle this part(said by Luke.Lee)\r
 335         //TX_RPT_T              pTxRpt;                         // Define in IC folder. Move lower layer.\r
 336 #if 0   \r
 337         //1 For 88E RA (don't redefine the naming)\r
 338         u1Byte          rate_id;\r
 339         u1Byte          rate_SGI;\r
 340         u1Byte          rssi_sta_ra;\r
 341         u1Byte          SGI_enable;\r
 342         u1Byte          Decision_rate;\r
 343         u1Byte          Pre_rate;\r
 344         u1Byte          Active;\r
 345 \r
 346         // Driver write Wilson handle.\r
 347         //1 TX_RPT (don't redefine the naming)\r
 348         u2Byte          RTY[4];                         // ???\r
 349         u2Byte          TOTAL;                          // ???\r
 350         u2Byte          DROP;                           // ???\r
 351         //\r
 352         // Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 353         //\r
 354 #endif\r
 355 \r
 356 }ODM_STA_INFO_T, *PODM_STA_INFO_T;\r
 357 #endif\r
 358 \r
 359 //\r
 360 // 2011/10/20 MH Define Common info enum for all team.\r
 361 //\r
 362 typedef enum _ODM_Common_Info_Definition\r
 363 {\r
 364 //-------------REMOVED CASE-----------//\r
 365         //ODM_CMNINFO_CCK_HP,\r
 366         //ODM_CMNINFO_RFPATH_ENABLE,            // Define as ODM write???       \r
 367         //ODM_CMNINFO_BT_COEXIST,                               // ODM_BT_COEXIST_E\r
 368         //ODM_CMNINFO_OP_MODE,                          // ODM_OPERATION_MODE_E\r
 369 //-------------REMOVED CASE-----------//\r
 370 \r
 371         //\r
 372         // Fixed value:\r
 373         //\r
 374 \r
 375         //-----------HOOK BEFORE REG INIT-----------//\r
 376         ODM_CMNINFO_PLATFORM = 0,\r
 377         ODM_CMNINFO_ABILITY,                                    // ODM_ABILITY_E\r
 378         ODM_CMNINFO_INTERFACE,                          // ODM_INTERFACE_E\r
 379         ODM_CMNINFO_MP_TEST_CHIP,\r
 380         ODM_CMNINFO_IC_TYPE,                                    // ODM_IC_TYPE_E\r
 381         ODM_CMNINFO_CUT_VER,                                    // ODM_CUT_VERSION_E\r
 382         ODM_CMNINFO_FAB_VER,                                    // ODM_FAB_E\r
 383         ODM_CMNINFO_RF_TYPE,                                    // ODM_RF_PATH_E or ODM_RF_TYPE_E?\r
 384         ODM_CMNINFO_RFE_TYPE, \r
 385         ODM_CMNINFO_BOARD_TYPE,                         // ODM_BOARD_TYPE_E\r
 386         ODM_CMNINFO_PACKAGE_TYPE,\r
 387         ODM_CMNINFO_EXT_LNA,                                    // TRUE\r
 388         ODM_CMNINFO_5G_EXT_LNA, \r
 389         ODM_CMNINFO_EXT_PA,\r
 390         ODM_CMNINFO_5G_EXT_PA,\r
 391         ODM_CMNINFO_GPA,\r
 392         ODM_CMNINFO_APA,\r
 393         ODM_CMNINFO_GLNA,\r
 394         ODM_CMNINFO_ALNA,\r
 395         ODM_CMNINFO_EXT_TRSW,\r
 396         ODM_CMNINFO_EXT_LNA_GAIN,\r
 397         ODM_CMNINFO_PATCH_ID,                           //CUSTOMER ID\r
 398         ODM_CMNINFO_BINHCT_TEST,\r
 399         ODM_CMNINFO_BWIFI_TEST,\r
 400         ODM_CMNINFO_SMART_CONCURRENT,\r
 401         ODM_CMNINFO_CONFIG_BB_RF,\r
 402         ODM_CMNINFO_DOMAIN_CODE_2G,\r
 403         ODM_CMNINFO_DOMAIN_CODE_5G,\r
 404         ODM_CMNINFO_IQKFWOFFLOAD,\r
 405         ODM_CMNINFO_HUBUSBMODE,\r
 406         ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,\r
 407         ODM_CMNINFO_TX_TP,\r
 408         ODM_CMNINFO_RX_TP,\r
 409         ODM_CMNINFO_SOUNDING_SEQ,\r
 410         //-----------HOOK BEFORE REG INIT-----------//  \r
 411 \r
 412 \r
 413         //\r
 414         // Dynamic value:\r
 415         //\r
 416 //--------- POINTER REFERENCE-----------//\r
 417         ODM_CMNINFO_MAC_PHY_MODE,                       // ODM_MAC_PHY_MODE_E\r
 418         ODM_CMNINFO_TX_UNI,\r
 419         ODM_CMNINFO_RX_UNI,\r
 420         ODM_CMNINFO_WM_MODE,                            // ODM_WIRELESS_MODE_E\r
 421         ODM_CMNINFO_BAND,                                       // ODM_BAND_TYPE_E\r
 422         ODM_CMNINFO_SEC_CHNL_OFFSET,            // ODM_SEC_CHNL_OFFSET_E\r
 423         ODM_CMNINFO_SEC_MODE,                           // ODM_SECURITY_E\r
 424         ODM_CMNINFO_BW,                                         // ODM_BW_E\r
 425         ODM_CMNINFO_CHNL,\r
 426         ODM_CMNINFO_FORCED_RATE,\r
 427         \r
 428         ODM_CMNINFO_DMSP_GET_VALUE,\r
 429         ODM_CMNINFO_BUDDY_ADAPTOR,\r
 430         ODM_CMNINFO_DMSP_IS_MASTER,\r
 431         ODM_CMNINFO_SCAN,\r
 432         ODM_CMNINFO_POWER_SAVING,\r
 433         ODM_CMNINFO_ONE_PATH_CCA,                       // ODM_CCA_PATH_E\r
 434         ODM_CMNINFO_DRV_STOP,\r
 435         ODM_CMNINFO_PNP_IN,\r
 436         ODM_CMNINFO_INIT_ON,\r
 437         ODM_CMNINFO_ANT_TEST,\r
 438         ODM_CMNINFO_NET_CLOSED,\r
 439         //ODM_CMNINFO_RTSTA_AID,                                // For win driver only?\r
 440         ODM_CMNINFO_FORCED_IGI_LB,\r
 441         ODM_CMNINFO_P2P_LINK,\r
 442         ODM_CMNINFO_FCS_MODE,\r
 443         ODM_CMNINFO_IS1ANTENNA,\r
 444         ODM_CMNINFO_RFDEFAULTPATH,\r
 445 //--------- POINTER REFERENCE-----------//\r
 446 \r
 447 //------------CALL BY VALUE-------------//\r
 448         ODM_CMNINFO_WIFI_DIRECT,\r
 449         ODM_CMNINFO_WIFI_DISPLAY,\r
 450         ODM_CMNINFO_LINK_IN_PROGRESS,                   \r
 451         ODM_CMNINFO_LINK,\r
 452         ODM_CMNINFO_STATION_STATE,\r
 453         ODM_CMNINFO_RSSI_MIN,\r
 454         ODM_CMNINFO_DBG_COMP,                           // u8Byte\r
 455         ODM_CMNINFO_DBG_LEVEL,                          // u4Byte\r
 456         ODM_CMNINFO_RA_THRESHOLD_HIGH,          // u1Byte\r
 457         ODM_CMNINFO_RA_THRESHOLD_LOW,           // u1Byte\r
 458         ODM_CMNINFO_RF_ANTENNA_TYPE,            // u1Byte\r
 459         ODM_CMNINFO_BT_ENABLED,\r
 460         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,\r
 461         ODM_CMNINFO_BT_HS_RSSI,\r
 462         ODM_CMNINFO_BT_OPERATION,\r
 463         ODM_CMNINFO_BT_LIMITED_DIG,                                     //Need to Limited Dig or not\r
 464         ODM_CMNINFO_BT_DIG,\r
 465         ODM_CMNINFO_BT_BUSY,                                    //Check Bt is using or not//neil        \r
 466         ODM_CMNINFO_BT_DISABLE_EDCA,\r
 467 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)               // for repeater mode add by YuChen 2014.06.23\r
 468 #ifdef UNIVERSAL_REPEATER\r
 469         ODM_CMNINFO_VXD_LINK,\r
 470 #endif\r
 471 #endif\r
 472         ODM_CMNINFO_AP_TOTAL_NUM,\r
 473         ODM_CMNINFO_POWER_TRAINING,\r
 474 //------------CALL BY VALUE-------------//\r
 475 \r
 476         //\r
 477         // Dynamic ptr array hook itms.\r
 478         //\r
 479         ODM_CMNINFO_STA_STATUS,\r
 480         ODM_CMNINFO_PHY_STATUS,\r
 481         ODM_CMNINFO_MAC_STATUS,\r
 482         \r
 483         ODM_CMNINFO_MAX,\r
 484 \r
 485 \r
 486 }ODM_CMNINFO_E;\r
 487 \r
 488 //\r
 489 // 2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY\r
 490 //\r
 491 typedef enum _ODM_Support_Ability_Definition\r
 492 {\r
 493         //\r
 494         // BB ODM section BIT 0-19\r
 495         //\r
 496         ODM_BB_DIG                                      = BIT0,\r
 497         ODM_BB_RA_MASK                          = BIT1,\r
 498         ODM_BB_DYNAMIC_TXPWR            = BIT2,\r
 499         ODM_BB_FA_CNT                                   = BIT3,\r
 500         ODM_BB_RSSI_MONITOR                     = BIT4,\r
 501         ODM_BB_CCK_PD                           = BIT5,\r
 502         ODM_BB_ANT_DIV                          = BIT6,\r
 503         ODM_BB_PWR_SAVE                         = BIT7,\r
 504         ODM_BB_PWR_TRAIN                                = BIT8,\r
 505         ODM_BB_RATE_ADAPTIVE                    = BIT9,\r
 506         ODM_BB_PATH_DIV                         = BIT10,\r
 507         ODM_BB_PSD                                      = BIT11,\r
 508         ODM_BB_RXHP                                     = BIT12,\r
 509         ODM_BB_ADAPTIVITY                               = BIT13,\r
 510         ODM_BB_CFO_TRACKING                     = BIT14,\r
 511         ODM_BB_NHM_CNT                          = BIT15,\r
 512         ODM_BB_PRIMARY_CCA                      = BIT16,\r
 513         ODM_BB_TXBF                             = BIT17,\r
 514         \r
 515         //\r
 516         // MAC DM section BIT 20-23\r
 517         //\r
 518         ODM_MAC_EDCA_TURBO                      = BIT20,\r
 519         ODM_MAC_EARLY_MODE                      = BIT21,\r
 520         \r
 521         //\r
 522         // RF ODM section BIT 24-31\r
 523         //\r
 524         ODM_RF_TX_PWR_TRACK                     = BIT24,\r
 525         ODM_RF_RX_GAIN_TRACK                    = BIT25,\r
 526         ODM_RF_CALIBRATION                      = BIT26,\r
 527         \r
 528 }ODM_ABILITY_E;\r
 529 \r
 530 //Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino\r
 531 \r
 532 // ODM_CMNINFO_ONE_PATH_CCA\r
 533 typedef enum tag_CCA_Path\r
 534 {\r
 535         ODM_CCA_2R                      = 0,\r
 536         ODM_CCA_1R_A            = 1,\r
 537         ODM_CCA_1R_B            = 2,\r
 538 }ODM_CCA_PATH_E;\r
 539 \r
 540 //move RAInfo to Phydm_RaInfo.h\r
 541 \r
 542 //Remove struct  PATHDIV_PARA to odm_PathDiv.h \r
 543 \r
 544 //Remove struct to odm_PowerTracking.h by YuChen\r
 545 //\r
 546 // ODM Dynamic common info value definition\r
 547 //\r
 548 //Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino\r
 549 \r
 550 //move PathDiv to Phydm_PathDiv.h\r
 551 \r
 552 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{\r
 553         PHY_REG_PG_RELATIVE_VALUE = 0,\r
 554         PHY_REG_PG_EXACT_VALUE = 1\r
 555 } PHY_REG_PG_TYPE;\r
 556 \r
 557 //\r
 558 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.\r
 559 //\r
 560 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 561 #if (RT_PLATFORM != PLATFORM_LINUX)\r
 562 typedef \r
 563 #endif\r
 564         \r
 565 struct DM_Out_Source_Dynamic_Mechanism_Structure\r
 566 #else// for AP,ADSL,CE Team\r
 567 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure\r
 568 #endif\r
 569 {\r
 570         //RT_TIMER      FastAntTrainingTimer;\r
 571         //\r
 572         //      Add for different team use temporarily\r
 573         //\r
 574         PADAPTER                Adapter;                // For CE/NIC team\r
 575         prtl8192cd_priv priv;                   // For AP/ADSL team\r
 576         // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.\r
 577         BOOLEAN                 odm_ready;\r
 578 \r
 579 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 580         rtl8192cd_priv          fake_priv;\r
 581 #endif\r
 582 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 583         // ADSL_AP_BUILD_WORKAROUND\r
 584         ADAPTER                 fake_adapter;\r
 585 #endif\r
 586         \r
 587         PHY_REG_PG_TYPE         PhyRegPgValueType;\r
 588         u1Byte                          PhyRegPgVersion;\r
 589 \r
 590         u8Byte                  DebugComponents;\r
 591         u4Byte                  DebugLevel;\r
 592         \r
 593         u4Byte                  NumQryPhyStatusAll;     //CCK + OFDM\r
 594         u4Byte                  LastNumQryPhyStatusAll; \r
 595         u4Byte                  RxPWDBAve;\r
 596         BOOLEAN                 MPDIG_2G;               //off MPDIG\r
 597         u1Byte                  Times_2G;\r
 598         \r
 599 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
 600         BOOLEAN                 bCckHighPower; \r
 601         u1Byte                  RFPathRxEnable;         // ODM_CMNINFO_RFPATH_ENABLE\r
 602         u1Byte                  ControlChannel;\r
 603 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
 604 \r
 605 //--------REMOVED COMMON INFO----------//\r
 606         //u1Byte                                PseudoMacPhyMode;\r
 607         //BOOLEAN                       *BTCoexist;\r
 608         //BOOLEAN                       PseudoBtCoexist;\r
 609         //u1Byte                                OPMode;\r
 610         //BOOLEAN                       bAPMode;\r
 611         //BOOLEAN                       bClientMode;\r
 612         //BOOLEAN                       bAdHocMode;\r
 613         //BOOLEAN                       bSlaveOfDMSP;\r
 614 //--------REMOVED COMMON INFO----------//\r
 615 \r
 616 \r
 617 //1  COMMON INFORMATION\r
 618 \r
 619         //\r
 620         // Init Value\r
 621         //\r
 622 //-----------HOOK BEFORE REG INIT-----------//  \r
 623         // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4\r
 624         u1Byte                  SupportPlatform;                \r
 625         // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K\r
 626         u4Byte                  SupportAbility;\r
 627         // ODM PCIE/USB/SDIO = 1/2/3\r
 628         u1Byte                  SupportInterface;                       \r
 629         // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...\r
 630         u4Byte                  SupportICType;  \r
 631         // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...\r
 632         u1Byte                  CutVersion;\r
 633         // Fab Version TSMC/UMC = 0/1\r
 634         u1Byte                  FabVersion;\r
 635         // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...\r
 636         u1Byte                  RFType;\r
 637         u1Byte                  RFEType;        \r
 638         // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...\r
 639         u1Byte                  BoardType;\r
 640         u1Byte                  PackageType;\r
 641         u2Byte                  TypeGLNA;\r
 642         u2Byte                  TypeGPA;\r
 643         u2Byte                  TypeALNA;\r
 644         u2Byte                  TypeAPA;\r
 645         // with external LNA  NO/Yes = 0/1\r
 646         u1Byte                  ExtLNA; // 2G\r
 647         u1Byte                  ExtLNA5G; //5G\r
 648         // with external PA  NO/Yes = 0/1\r
 649         u1Byte                  ExtPA; // 2G\r
 650         u1Byte                  ExtPA5G; //5G\r
 651         // with external TRSW  NO/Yes = 0/1\r
 652         u1Byte                  ExtTRSW;\r
 653         u1Byte                  ExtLNAGain; // 2G\r
 654         u1Byte                  PatchID; //Customer ID\r
 655         BOOLEAN                 bInHctTest;\r
 656         BOOLEAN                 bWIFITest;\r
 657 \r
 658         BOOLEAN                 bDualMacSmartConcurrent;\r
 659         u4Byte                  BK_SupportAbility;\r
 660         u1Byte                  AntDivType;\r
 661         BOOLEAN                 ConfigBBRF;\r
 662         u1Byte                  odm_Regulation2_4G;\r
 663         u1Byte                  odm_Regulation5G;\r
 664         u1Byte                  IQKFWOffload;\r
 665 //-----------HOOK BEFORE REG INIT-----------//  \r
 666 \r
 667         //\r
 668         // Dynamic Value\r
 669         //      \r
 670 //--------- POINTER REFERENCE-----------//\r
 671 \r
 672         u1Byte                  u1Byte_temp;\r
 673         BOOLEAN                 BOOLEAN_temp;\r
 674         PADAPTER                PADAPTER_temp;\r
 675         \r
 676         // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2\r
 677         u1Byte                  *pMacPhyMode;\r
 678         //TX Unicast byte count\r
 679         u8Byte                  *pNumTxBytesUnicast;\r
 680         //RX Unicast byte count\r
 681         u8Byte                  *pNumRxBytesUnicast;\r
 682         // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3\r
 683         u1Byte                  *pWirelessMode; //ODM_WIRELESS_MODE_E\r
 684         // Frequence band 2.4G/5G = 0/1\r
 685         u1Byte                  *pBandType;\r
 686         // Secondary channel offset don't_care/below/above = 0/1/2\r
 687         u1Byte                  *pSecChOffset;\r
 688         // Security mode Open/WEP/AES/TKIP = 0/1/2/3\r
 689         u1Byte                  *pSecurity;\r
 690         // BW info 20M/40M/80M = 0/1/2\r
 691         u1Byte                  *pBandWidth;\r
 692         // Central channel location Ch1/Ch2/....\r
 693         u1Byte                  *pChannel;      //central channel number\r
 694         BOOLEAN                 DPK_Done;\r
 695         // Common info for 92D DMSP\r
 696         \r
 697         BOOLEAN                 *pbGetValueFromOtherMac;\r
 698         PADAPTER                *pBuddyAdapter;\r
 699         BOOLEAN                 *pbMasterOfDMSP; //MAC0: master, MAC1: slave\r
 700         // Common info for Status\r
 701         BOOLEAN                 *pbScanInProcess;\r
 702         BOOLEAN                 *pbPowerSaving;\r
 703         // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.\r
 704         u1Byte                  *pOnePathCCA;\r
 705         //pMgntInfo->AntennaTest\r
 706         u1Byte                  *pAntennaTest;\r
 707         BOOLEAN                 *pbNet_closed;\r
 708         //u1Byte                        *pAidMap;\r
 709         u1Byte                  *pu1ForcedIgiLb;\r
 710         BOOLEAN                 *pIsFcsModeEnable;\r
 711 /*--------- For 8723B IQK-----------*/\r
 712         BOOLEAN                 *pIs1Antenna;\r
 713         u1Byte                  *pRFDefaultPath;\r
 714         // 0:S1, 1:S0\r
 715         \r
 716 //--------- POINTER REFERENCE-----------//\r
 717         pu2Byte                 pForcedDataRate;\r
 718         pu1Byte                 HubUsbMode;\r
 719         BOOLEAN                 *pbFwDwRsvdPageInProgress;\r
 720         u4Byte                  *pCurrentTxTP;\r
 721         u4Byte                  *pCurrentRxTP;\r
 722         u1Byte                  *pSoundingSeq;\r
 723 //------------CALL BY VALUE-------------//\r
 724         BOOLEAN                 bLinkInProcess;\r
 725         BOOLEAN                 bWIFI_Direct;\r
 726         BOOLEAN                 bWIFI_Display;\r
 727         BOOLEAN                 bLinked;\r
 728         BOOLEAN                 bsta_state;\r
 729 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)               // for repeater mode add by YuChen 2014.06.23\r
 730 #ifdef UNIVERSAL_REPEATER\r
 731         BOOLEAN                 VXD_bLinked;\r
 732 #endif\r
 733 #endif                                                                  // for repeater mode add by YuChen 2014.06.23   \r
 734         u1Byte                  RSSI_Min;       \r
 735         u1Byte                  InterfaceIndex; /*Add for 92D  dual MAC: 0--Mac0 1--Mac1*/\r
 736         BOOLEAN                 bIsMPChip;\r
 737         BOOLEAN                 bOneEntryOnly;\r
 738         BOOLEAN                 mp_mode;\r
 739         u4Byte                  OneEntry_MACID;\r
 740         u1Byte                  pre_number_linked_client;       \r
 741         u1Byte                  number_linked_client;\r
 742         u1Byte                  pre_number_active_client;       \r
 743         u1Byte                  number_active_client;\r
 744         // Common info for BTDM\r
 745         BOOLEAN                 bBtEnabled;                     // BT is enabled\r
 746         BOOLEAN                 bBtConnectProcess;      // BT HS is under connection progress.\r
 747         u1Byte                  btHsRssi;                               // BT HS mode wifi rssi value.\r
 748         BOOLEAN                 bBtHsOperation;         // BT HS mode is under progress\r
 749         u1Byte                  btHsDigVal;                     // use BT rssi to decide the DIG value\r
 750         BOOLEAN                 bBtDisableEdcaTurbo;    // Under some condition, don't enable the EDCA Turbo\r
 751         BOOLEAN                 bBtBusy;                        // BT is busy.\r
 752         BOOLEAN                 bBtLimitedDig;                  // BT is busy.\r
 753         BOOLEAN                 bDisablePhyApi;\r
 754 //------------CALL BY VALUE-------------//\r
 755         u1Byte                  RSSI_A;\r
 756         u1Byte                  RSSI_B;\r
 757         u1Byte                  RSSI_C;\r
 758         u1Byte                  RSSI_D;\r
 759         u8Byte                  RSSI_TRSW;      \r
 760         u8Byte                  RSSI_TRSW_H;\r
 761         u8Byte                  RSSI_TRSW_L;    \r
 762         u8Byte                  RSSI_TRSW_iso;\r
 763         u1Byte                  TXAntStatus;\r
 764         u1Byte                  RXAntStatus;\r
 765         u1Byte                  cck_lna_idx;\r
 766         u1Byte                  cck_vga_idx;\r
 767         u1Byte                  ofdm_agc_idx[4];\r
 768 \r
 769         u1Byte                  RxRate;\r
 770         BOOLEAN                 bNoisyState;\r
 771         u1Byte                  TxRate;\r
 772         u1Byte                  LinkedInterval;\r
 773         u1Byte                  preChannel;\r
 774         u4Byte                  TxagcOffsetValueA;\r
 775         BOOLEAN                 IsTxagcOffsetPositiveA;\r
 776         u4Byte                  TxagcOffsetValueB;\r
 777         BOOLEAN                 IsTxagcOffsetPositiveB;\r
 778         u4Byte                  tx_tp;\r
 779         u4Byte                  rx_tp;\r
 780         u4Byte                  total_tp;\r
 781         u8Byte                  curTxOkCnt;\r
 782         u8Byte                  curRxOkCnt;     \r
 783         u8Byte                  lastTxOkCnt;\r
 784         u8Byte                  lastRxOkCnt;\r
 785         u4Byte                  BbSwingOffsetA;\r
 786         BOOLEAN                 IsBbSwingOffsetPositiveA;\r
 787         u4Byte                  BbSwingOffsetB;\r
 788         BOOLEAN                 IsBbSwingOffsetPositiveB;\r
 789         u1Byte                  antdiv_rssi;\r
 790         u1Byte                  fat_comb_a;\r
 791         u1Byte                  fat_comb_b;\r
 792         u1Byte                  antdiv_intvl;\r
 793         u1Byte                  AntType;\r
 794         u1Byte                  pre_AntType;\r
 795         u1Byte                  antdiv_period;\r
 796         u1Byte                  antdiv_select;\r
 797         u1Byte                  path_select;    \r
 798         u1Byte                  antdiv_evm_en;\r
 799         u1Byte                  bdc_holdstate;\r
 800         u1Byte                  NdpaPeriod;\r
 801         BOOLEAN                 H2C_RARpt_connect;\r
 802         BOOLEAN                 cck_agc_report_type;\r
 803         \r
 804         u1Byte                  dm_dig_max_TH;\r
 805         u1Byte                  dm_dig_min_TH;\r
 806         u1Byte                  print_agc;\r
 807         u1Byte                  TrafficLoad;\r
 808         u1Byte                  pre_TrafficLoad;\r
 809 \r
 810 \r
 811         //For Adaptivtiy\r
 812         u2Byte                  NHM_cnt_0;\r
 813         u2Byte                  NHM_cnt_1;\r
 814         s1Byte                  TH_L2H_default;\r
 815         s1Byte                  TH_EDCCA_HL_diff_default;\r
 816         s1Byte                  TH_L2H_ini;\r
 817         s1Byte                  TH_EDCCA_HL_diff;\r
 818         s1Byte                  TH_L2H_ini_mode2;\r
 819         s1Byte                  TH_EDCCA_HL_diff_mode2;\r
 820         BOOLEAN                 Carrier_Sense_enable;\r
 821         u1Byte                  Adaptivity_IGI_upper;\r
 822         BOOLEAN                 adaptivity_flag;\r
 823         u1Byte                  DCbackoff;\r
 824         BOOLEAN                 Adaptivity_enable;\r
 825         u1Byte                  APTotalNum;\r
 826         BOOLEAN                 EDCCA_enable;\r
 827         ADAPTIVITY_STATISTICS   Adaptivity;\r
 828         //For Adaptivtiy\r
 829         u1Byte                  LastUSBHub;\r
 830         u1Byte                  TxBfDataRate;\r
 831         \r
 832         u1Byte                  c2h_cmd_start;\r
 833         u1Byte                  fw_debug_trace[60]; \r
 834         u1Byte                  pre_c2h_seq;\r
 835         BOOLEAN                 fw_buff_is_enpty;\r
 836         u4Byte                  data_frame_num;\r
 837 \r
 838         /*for noise detection*/\r
 839         BOOLEAN                 NoisyDecision; /*b_noisy*/\r
 840         BOOLEAN                 pre_b_noisy;    \r
 841         u4Byte                  NoisyDecision_Smooth;\r
 842 \r
 843 #if (DM_ODM_SUPPORT_TYPE &  (ODM_CE))\r
 844         ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];\r
 845 #endif\r
 846         //\r
 847         //2 Define STA info.\r
 848         // _ODM_STA_INFO\r
 849         // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??\r
 850         PSTA_INFO_T             pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];\r
 851         u2Byte                  platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];            /* platform_macid_table[platform_macid] = phydm_macid */\r
 852 \r
 853 #if (RATE_ADAPTIVE_SUPPORT == 1)\r
 854         u2Byte                  CurrminRptTime;\r
 855         ODM_RA_INFO_T   RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119\r
 856 #endif\r
 857         //\r
 858         // 2012/02/14 MH Add to share 88E ra with other SW team.\r
 859         // We need to colelct all support abilit to a proper area.\r
 860         //\r
 861         BOOLEAN                         RaSupport88E;\r
 862 \r
 863         // Define ...........\r
 864 \r
 865         // Latest packet phy info (ODM write)\r
 866         ODM_PHY_DBG_INFO_T       PhyDbgInfo;\r
 867         //PHY_INFO_88E          PhyInfo;\r
 868 \r
 869         // Latest packet phy info (ODM write)\r
 870         ODM_MAC_INFO            *pMacInfo;\r
 871         //MAC_INFO_88E          MacInfo;\r
 872 \r
 873         // Different Team independt structure??\r
 874 \r
 875         //\r
 876         //TX_RTP_CMN            TX_retrpo;\r
 877         //TX_RTP_88E            TX_retrpo;\r
 878         //TX_RTP_8195           TX_retrpo;\r
 879 \r
 880         //\r
 881         //ODM Structure\r
 882         //\r
 883 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\r
 884         #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
 885         BDC_T                                   DM_BdcTable;\r
 886         #endif\r
 887         \r
 888         #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\r
 889         SAT_T                                           dm_sat_table;\r
 890         #endif\r
 891         \r
 892 #endif\r
 893         FAT_T                                           DM_FatTable;\r
 894         DIG_T                                           DM_DigTable;\r
 895 \r
 896         PS_T                                            DM_PSTable;\r
 897         Pri_CCA_T                                       DM_PriCCA;\r
 898 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 899         RXHP_T                                          DM_RXHP_Table;\r
 900 #endif\r
 901         RA_T                                            DM_RA_Table;  \r
 902         FALSE_ALARM_STATISTICS          FalseAlmCnt;\r
 903         FALSE_ALARM_STATISTICS          FlaseAlmCntBuddyAdapter;\r
 904         SWAT_T                                          DM_SWAT_Table;\r
 905         CFO_TRACKING                                    DM_CfoTrack;\r
 906         ACS                                                     DM_ACS;\r
 907 \r
 908 \r
 909 #if (RTL8814A_SUPPORT == 1)\r
 910         IQK_INFO        IQK_info;\r
 911 #endif /* (RTL8814A_SUPPORT==1) */\r
 912 \r
 913 \r
 914 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 915         //Path Div Struct\r
 916         PATHDIV_PARA    pathIQK;\r
 917 #endif\r
 918 #if(defined(CONFIG_PATH_DIVERSITY))\r
 919         PATHDIV_T       DM_PathDiv;\r
 920 #endif  \r
 921 \r
 922         EDCA_T          DM_EDCA_Table;\r
 923         u4Byte          WMMEDCA_BE;\r
 924 \r
 925         // Copy from SD4 structure\r
 926         //\r
 927         // ==================================================\r
 928         //\r
 929 \r
 930         //common\r
 931         //u1Byte                DM_Type;        \r
 932         //u1Byte    PSD_Report_RXHP[80];   // Add By Gary\r
 933         //u1Byte    PSD_func_flag;               // Add By Gary\r
 934         //for DIG\r
 935         //u1Byte                bDMInitialGainEnable;\r
 936         //u1Byte                binitialized; // for dm_initial_gain_Multi_STA use.\r
 937 \r
 938         BOOLEAN                 *pbDriverStopped;\r
 939         BOOLEAN                 *pbDriverIsGoingToPnpSetPowerSleep;\r
 940         BOOLEAN                 *pinit_adpt_in_progress;\r
 941 \r
 942         //PSD\r
 943         BOOLEAN                 bUserAssignLevel;\r
 944         RT_TIMER                PSDTimer;\r
 945         u1Byte                  RSSI_BT;                        //come from BT\r
 946         BOOLEAN                 bPSDinProcess;\r
 947         BOOLEAN                 bPSDactive;\r
 948         BOOLEAN                 bDMInitialGainEnable;\r
 949 \r
 950         //MPT DIG\r
 951         RT_TIMER                MPT_DIGTimer;\r
 952         \r
 953         //for rate adaptive, in fact,  88c/92c fw will handle this\r
 954         u1Byte                  bUseRAMask;\r
 955 \r
 956         ODM_RATE_ADAPTIVE       RateAdaptive;\r
 957 //#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
 958 #if(defined(CONFIG_ANT_DETECTION))\r
 959         ANT_DETECTED_INFO       AntDetectedInfo; // Antenna detected information for RSSI tool\r
 960 #endif\r
 961         ODM_RF_CAL_T    RFCalibrateInfo;\r
 962 \r
 963         \r
 964         //\r
 965         // Dynamic ATC switch\r
 966         //\r
 967 \r
 968 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN|ODM_CE))   \r
 969         //\r
 970         // Power Training\r
 971         //\r
 972         u1Byte                  ForcePowerTrainingState;\r
 973         BOOLEAN                 bChangeState;\r
 974         u4Byte                  PT_score;\r
 975         u8Byte                  OFDM_RX_Cnt;\r
 976         u8Byte                  CCK_RX_Cnt;\r
 977 #endif\r
 978         BOOLEAN                 bDisablePowerTraining;\r
 979 \r
 980         //\r
 981         // ODM system resource.\r
 982         //\r
 983 \r
 984         // ODM relative time.\r
 985         RT_TIMER                                PathDivSwitchTimer;\r
 986         //2011.09.27 add for Path Diversity\r
 987         RT_TIMER                                CCKPathDiversityTimer;\r
 988         RT_TIMER        FastAntTrainingTimer;\r
 989 #ifdef ODM_EVM_ENHANCE_ANTDIV\r
 990         RT_TIMER                        EVM_FastAntTrainingTimer;\r
 991 #endif\r
 992         RT_TIMER                sbdcnt_timer;\r
 993 \r
 994         // ODM relative workitem.\r
 995 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 996 #if USE_WORKITEM\r
 997         RT_WORK_ITEM                    PathDivSwitchWorkitem;\r
 998         RT_WORK_ITEM                    CCKPathDiversityWorkitem;\r
 999         RT_WORK_ITEM                    FastAntTrainingWorkitem;\r
1000         RT_WORK_ITEM                    MPT_DIGWorkitem;\r
1001         RT_WORK_ITEM                    RaRptWorkitem;\r
1002         RT_WORK_ITEM                    sbdcnt_workitem;\r
1003 #endif\r
1004 #endif\r
1005 \r
1006 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
1007 #if (BEAMFORMING_SUPPORT == 1)\r
1008         RT_BEAMFORMING_INFO BeamformingInfo;\r
1009 #endif \r
1010 #endif\r
1011 \r
1012 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1013         \r
1014 #if (RT_PLATFORM != PLATFORM_LINUX)\r
1015 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1016 #else\r
1017 };\r
1018 #endif  \r
1019 \r
1020 #else// for AP,ADSL,CE Team\r
1021 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1022 #endif\r
1023 \r
1024 \r
1025 typedef enum _PHYDM_STRUCTURE_TYPE{\r
1026         PHYDM_FALSEALMCNT,\r
1027         PHYDM_CFOTRACK,\r
1028         PHYDM_ADAPTIVITY,\r
1029         PHYDM_ROMINFO,\r
1030         \r
1031 }PHYDM_STRUCTURE_TYPE;\r
1032 \r
1033 \r
1034 \r
1035  typedef enum _ODM_RF_CONTENT{\r
1036         odm_radioa_txt = 0x1000,\r
1037         odm_radiob_txt = 0x1001,\r
1038         odm_radioc_txt = 0x1002,\r
1039         odm_radiod_txt = 0x1003\r
1040 } ODM_RF_CONTENT;\r
1041 \r
1042 typedef enum _ODM_BB_Config_Type{\r
1043         CONFIG_BB_PHY_REG,   \r
1044         CONFIG_BB_AGC_TAB,   \r
1045         CONFIG_BB_AGC_TAB_2G,\r
1046         CONFIG_BB_AGC_TAB_5G, \r
1047         CONFIG_BB_PHY_REG_PG,\r
1048         CONFIG_BB_PHY_REG_MP,\r
1049         CONFIG_BB_AGC_TAB_DIFF,\r
1050 } ODM_BB_Config_Type, *PODM_BB_Config_Type;\r
1051 \r
1052 typedef enum _ODM_RF_Config_Type{ \r
1053         CONFIG_RF_RADIO,\r
1054     CONFIG_RF_TXPWR_LMT,\r
1055 } ODM_RF_Config_Type, *PODM_RF_Config_Type;\r
1056 \r
1057 typedef enum _ODM_FW_Config_Type{\r
1058     CONFIG_FW_NIC,\r
1059     CONFIG_FW_NIC_2,\r
1060     CONFIG_FW_AP,\r
1061     CONFIG_FW_AP_2,\r
1062     CONFIG_FW_MP,\r
1063     CONFIG_FW_WoWLAN,\r
1064     CONFIG_FW_WoWLAN_2,\r
1065     CONFIG_FW_AP_WoWLAN,\r
1066     CONFIG_FW_BT,\r
1067 } ODM_FW_Config_Type;\r
1068 \r
1069 // Status code\r
1070 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\r
1071 typedef enum _RT_STATUS{\r
1072         RT_STATUS_SUCCESS,\r
1073         RT_STATUS_FAILURE,\r
1074         RT_STATUS_PENDING,\r
1075         RT_STATUS_RESOURCE,\r
1076         RT_STATUS_INVALID_CONTEXT,\r
1077         RT_STATUS_INVALID_PARAMETER,\r
1078         RT_STATUS_NOT_SUPPORT,\r
1079         RT_STATUS_OS_API_FAILED,\r
1080 }RT_STATUS,*PRT_STATUS;\r
1081 #endif // end of RT_STATUS definition\r
1082 \r
1083 #ifdef REMOVE_PACK\r
1084 #pragma pack()\r
1085 #endif\r
1086 \r
1087 //#include "odm_function.h"\r
1088 \r
1089 //3===========================================================\r
1090 //3 DIG\r
1091 //3===========================================================\r
1092 \r
1093 //Remove DIG by Yuchen\r
1094 \r
1095 //3===========================================================\r
1096 //3 AGC RX High Power Mode\r
1097 //3===========================================================\r
1098 #define          LNA_Low_Gain_1                      0x64\r
1099 #define          LNA_Low_Gain_2                      0x5A\r
1100 #define          LNA_Low_Gain_3                      0x58\r
1101 \r
1102 #define          FA_RXHP_TH1                           5000\r
1103 #define          FA_RXHP_TH2                           1500\r
1104 #define          FA_RXHP_TH3                             800\r
1105 #define          FA_RXHP_TH4                             600\r
1106 #define          FA_RXHP_TH5                             500\r
1107 \r
1108 //3===========================================================\r
1109 //3 EDCA\r
1110 //3===========================================================\r
1111 \r
1112 //3===========================================================\r
1113 //3 Dynamic Tx Power\r
1114 //3===========================================================\r
1115 //Dynamic Tx Power Control Threshold\r
1116 \r
1117 //Remove By YuChen\r
1118 \r
1119 //3===========================================================\r
1120 //3 Tx Power Tracking\r
1121 //3===========================================================\r
1122 \r
1123 \r
1124 \r
1125 //3===========================================================\r
1126 //3 Rate Adaptive\r
1127 //3===========================================================\r
1128 //Remove to odm_RaInfo.h by RS_James\r
1129 \r
1130 //3===========================================================\r
1131 //3 BB Power Save\r
1132 //3===========================================================\r
1133 \r
1134 typedef enum tag_1R_CCA_Type_Definition\r
1135 {\r
1136         CCA_1R =0,\r
1137         CCA_2R = 1,\r
1138         CCA_MAX = 2,\r
1139 }DM_1R_CCA_E;\r
1140 \r
1141 typedef enum tag_RF_Type_Definition\r
1142 {\r
1143         RF_Save =0,\r
1144         RF_Normal = 1,\r
1145         RF_MAX = 2,\r
1146 }DM_RF_E;\r
1147 \r
1148 \r
1149 //\r
1150 // Extern Global Variables.\r
1151 //\r
1152 //PowerTracking move to odm_powerTrakcing.h by YuChen\r
1153 //\r
1154 // check Sta pointer valid or not\r
1155 //\r
1156 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1157 #define IS_STA_VALID(pSta)              (pSta && pSta->expire_to)\r
1158 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1159 #define IS_STA_VALID(pSta)              (pSta && pSta->bUsed)\r
1160 #else\r
1161 #define IS_STA_VALID(pSta)              (pSta)\r
1162 #endif\r
1163 \r
1164 //Remove DIG by yuchen\r
1165 \r
1166 //Remove BB power saving by Yuchen\r
1167 \r
1168 //remove PT by yuchen\r
1169 \r
1170 //ODM_RAStateCheck() Remove by RS_James\r
1171 \r
1172 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))\r
1173 //============================================================\r
1174 // function prototype\r
1175 //============================================================\r
1176 //#define DM_ChangeDynamicInitGainThresh                ODM_ChangeDynamicInitGainThresh\r
1177 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
1178 //                                                                                      IN      INT32           DM_Type,\r
1179 //                                                                                      IN      INT32           DM_Value);\r
1180 \r
1181 //Remove DIG by yuchen\r
1182 \r
1183 \r
1184 BOOLEAN\r
1185 ODM_CheckPowerStatus(\r
1186         IN      PADAPTER                Adapter\r
1187         );\r
1188 \r
1189 \r
1190 //Remove ODM_RateAdaptiveStateApInit() by RS_James\r
1191 \r
1192 //Remove Edca by YuChen\r
1193 \r
1194 #endif\r
1195 \r
1196 \r
1197 \r
1198 u4Byte odm_ConvertTo_dB(u4Byte Value);\r
1199 \r
1200 u4Byte odm_ConvertTo_linear(u4Byte Value);\r
1201 \r
1202 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
1203 \r
1204 u4Byte\r
1205 GetPSDData(\r
1206         PDM_ODM_T       pDM_Odm,\r
1207         unsigned int    point,\r
1208         u1Byte initial_gain_psd);\r
1209 \r
1210 #endif\r
1211 \r
1212 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)     \r
1213 VOID\r
1214 ODM_DMWatchdog_LPS(\r
1215         IN              PDM_ODM_T               pDM_Odm\r
1216 );\r
1217 #endif\r
1218 \r
1219 \r
1220 s4Byte\r
1221 ODM_PWdB_Conversion(\r
1222     IN  s4Byte X,\r
1223     IN  u4Byte TotalBit,\r
1224     IN  u4Byte DecimalBit\r
1225     );\r
1226 \r
1227 s4Byte\r
1228 ODM_SignConversion(\r
1229     IN  s4Byte value,\r
1230     IN  u4Byte TotalBit\r
1231     );\r
1232 \r
1233 VOID \r
1234 ODM_DMInit(\r
1235  IN     PDM_ODM_T       pDM_Odm\r
1236 );\r
1237 \r
1238 VOID\r
1239 ODM_DMReset(\r
1240         IN      PDM_ODM_T       pDM_Odm\r
1241         );\r
1242 \r
1243 VOID\r
1244 phydm_support_ablity_debug(\r
1245         IN              PVOID           pDM_VOID,\r
1246         IN              u4Byte          *const dm_value,\r
1247         IN              u4Byte                  *_used,\r
1248         OUT             char                            *output,\r
1249         IN              u4Byte                  *_out_len\r
1250         );\r
1251 \r
1252 VOID\r
1253 ODM_DMWatchdog(\r
1254         IN              PDM_ODM_T                       pDM_Odm                 // For common use in the future\r
1255         );\r
1256 \r
1257 VOID\r
1258 ODM_CmnInfoInit(\r
1259         IN              PDM_ODM_T               pDM_Odm,\r
1260         IN              ODM_CMNINFO_E   CmnInfo,\r
1261         IN              u4Byte                  Value   \r
1262         );\r
1263 \r
1264 VOID\r
1265 ODM_CmnInfoHook(\r
1266         IN              PDM_ODM_T               pDM_Odm,\r
1267         IN              ODM_CMNINFO_E   CmnInfo,\r
1268         IN              PVOID                   pValue  \r
1269         );\r
1270 \r
1271 VOID\r
1272 ODM_CmnInfoPtrArrayHook(\r
1273         IN              PDM_ODM_T               pDM_Odm,\r
1274         IN              ODM_CMNINFO_E   CmnInfo,\r
1275         IN              u2Byte                  Index,\r
1276         IN              PVOID                   pValue  \r
1277         );\r
1278 \r
1279 VOID\r
1280 ODM_CmnInfoUpdate(\r
1281         IN              PDM_ODM_T               pDM_Odm,\r
1282         IN              u4Byte                  CmnInfo,\r
1283         IN              u8Byte                  Value   \r
1284         );\r
1285 \r
1286 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)\r
1287 VOID \r
1288 ODM_InitAllThreads(\r
1289     IN PDM_ODM_T        pDM_Odm \r
1290     );\r
1291 \r
1292 VOID\r
1293 ODM_StopAllThreads(\r
1294         IN PDM_ODM_T    pDM_Odm \r
1295         );\r
1296 #endif\r
1297 \r
1298 VOID \r
1299 ODM_InitAllTimers(\r
1300     IN PDM_ODM_T        pDM_Odm \r
1301     );\r
1302 \r
1303 VOID \r
1304 ODM_CancelAllTimers(\r
1305     IN PDM_ODM_T    pDM_Odm \r
1306     );\r
1307 \r
1308 VOID\r
1309 ODM_ReleaseAllTimers(\r
1310     IN PDM_ODM_T        pDM_Odm \r
1311     );\r
1312 \r
1313 \r
1314 \r
1315 \r
1316 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1317 VOID ODM_InitAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
1318 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
1319 \r
1320 \r
1321 \r
1322 u8Byte\r
1323 PlatformDivision64(\r
1324         IN u8Byte       x,\r
1325         IN u8Byte       y\r
1326 );\r
1327 \r
1328 //====================================================\r
1329 //3 PathDiV End\r
1330 //====================================================\r
1331 \r
1332 \r
1333 #define DM_ChangeDynamicInitGainThresh          ODM_ChangeDynamicInitGainThresh\r
1334 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
1335 //                                                                                      IN      INT32           DM_Type,\r
1336 //                                                                                      IN      INT32           DM_Value);\r
1337 //\r
1338 // PathDiveristy Remove by RS_James\r
1339 \r
1340 typedef enum tag_DIG_Connect_Definition\r
1341 {\r
1342         DIG_STA_DISCONNECT = 0, \r
1343         DIG_STA_CONNECT = 1,\r
1344         DIG_STA_BEFORE_CONNECT = 2,\r
1345         DIG_MultiSTA_DISCONNECT = 3,\r
1346         DIG_MultiSTA_CONNECT = 4,\r
1347         DIG_CONNECT_MAX\r
1348 }DM_DIG_CONNECT_E;\r
1349 \r
1350 \r
1351 //\r
1352 // 2012/01/12 MH Check afapter status. Temp fix BSOD.\r
1353 //\r
1354 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\\r
1355         if (pDM_Odm->Adapter == NULL)\\r
1356         {\\r
1357                 return;\\r
1358         }\\r
1359 \r
1360 \r
1361 //\r
1362 // For new definition in MP temporarily fro power tracking,\r
1363 //\r
1364 /*\r
1365 #define odm_TXPowerTrackingDirectCall(_Adapter) \\r
1366         IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \\r
1367         IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \\r
1368         IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\\r
1369         ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)\r
1370 */\r
1371 \r
1372 \r
1373 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1374 \r
1375 VOID\r
1376 ODM_AsocEntry_Init(\r
1377         IN              PDM_ODM_T               pDM_Odm\r
1378         );\r
1379 \r
1380 //Remove ODM_DynamicARFBSelect() by RS_James\r
1381 \r
1382 PVOID\r
1383 PhyDM_Get_Structure(\r
1384         IN              PDM_ODM_T               pDM_Odm,\r
1385         IN              u1Byte                  Structure_Type\r
1386 );\r
1387 \r
1388 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1389 /*===========================================================*/\r
1390 /* The following is for compile only*/\r
1391 /*===========================================================*/\r
1392 \r
1393 #define IS_HARDWARE_TYPE_8723A(_Adapter)                        FALSE\r
1394 #define IS_HARDWARE_TYPE_8723AE(_Adapter)                       FALSE\r
1395 #define IS_HARDWARE_TYPE_8192C(_Adapter)                        FALSE\r
1396 #define IS_HARDWARE_TYPE_8192D(_Adapter)                        FALSE\r
1397 #define RF_T_METER_92D                                  0x42\r
1398 \r
1399 \r
1400 #define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value)\r
1401 #define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value)\r
1402 #define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value)\r
1403 #define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value)\r
1404 \r
1405 #define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc)                              LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6)\r
1406 \r
1407 #define         RX_HAL_IS_CCK_RATE_92C(pDesc)\\r
1408                         (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\\r
1409                         GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\\r
1410                         GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\\r
1411                         GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M)\r
1412 \r
1413 #define         H2C_92C_PSD_RESULT                              16\r
1414 \r
1415 #define         rConfig_ram64x16                                0xb2c\r
1416 \r
1417 #define TARGET_CHNL_NUM_2G_5G   59\r
1418 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1419 \r
1420 VOID\r
1421 FillH2CCmd92C(  \r
1422         IN      PADAPTER                Adapter,\r
1423         IN      u1Byte  ElementID,\r
1424         IN      u4Byte  CmdLen,\r
1425         IN      pu1Byte pCmdBuffer\r
1426 );\r
1427 VOID\r
1428 PHY_SetTxPowerLevel8192C(\r
1429         IN      PADAPTER                Adapter,\r
1430         IN      u1Byte                  channel\r
1431         );\r
1432 u1Byte GetRightChnlPlaceforIQK(u1Byte chnl);\r
1433 \r
1434 #endif\r
1435 \r
1436 //===========================================================\r
1437 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1438 \r
1439 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1440 void odm_dtc(PDM_ODM_T pDM_Odm);\r
1441 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\r
1442 \r
1443 \r
1444 VOID phydm_NoisyDetection(IN    PDM_ODM_T       pDM_Odm );\r
1445 \r
1446 \r
1447 #endif\r
1448 \r