1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 #ifndef __PHYDMRAINFO_H__
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22 #define __PHYDMRAINFO_H__
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24 /*#define RAINFO_VERSION "2.0" //2014.11.04*/
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25 /*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
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26 /*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
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27 #define RAINFO_VERSION "3.2" /*2015.01.14 Dino*/
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29 #define HIGH_RSSI_THRESH 50
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30 #define LOW_RSSI_THRESH 20
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32 #define ACTIVE_TP_THRESHOLD 150
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33 #define RA_RETRY_DESCEND_NUM 2
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34 #define RA_RETRY_LIMIT_LOW 4
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35 #define RA_RETRY_LIMIT_HIGH 32
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37 #define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)
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38 #define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B)
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40 #define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
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41 #define RAINFO_STBC_STATE BIT1
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42 //#define RAINFO_LDPC_STATE BIT2
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43 #define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
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44 #define RAINFO_SHURTCUT_STATE BIT3
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45 #define RAINFO_SHURTCUT_FLAG BIT4
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46 #define RAINFO_INIT_RSSI_RATE_STATE BIT5
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47 #define RAINFO_BF_STATE BIT6
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48 #define RAINFO_BE_TX_STATE BIT7 // 1:TX
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50 #define RA_MASK_CCK 0xf
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51 #define RA_MASK_OFDM 0xff0
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52 #define RA_MASK_HT1SS 0xff000
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53 #define RA_MASK_HT2SS 0xff00000
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54 /*#define RA_MASK_MCS3SS */
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55 #define RA_MASK_HT4SS 0xff0
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56 #define RA_MASK_VHT1SS 0x3ff000
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57 #define RA_MASK_VHT2SS 0xffc00000
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59 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
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60 #define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B)
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61 #define RA_FIRST_MACID 1
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62 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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63 #define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B)
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64 #define RA_FIRST_MACID 0
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65 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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66 /*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */
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67 #define RA_FIRST_MACID 0
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71 #define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
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73 #define DM_RATR_STA_INIT 0
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74 #define DM_RATR_STA_HIGH 1
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75 #define DM_RATR_STA_MIDDLE 2
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76 #define DM_RATR_STA_LOW 3
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77 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)
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78 #define DM_RATR_STA_ULTRA_LOW 4
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81 #define DM_RA_RATE_UP 1
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82 #define DM_RA_RATE_DOWN 2
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84 typedef enum _phydm_arfr_num {
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85 ARFR_0_RATE_ID = 0x9,
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86 ARFR_1_RATE_ID = 0xa,
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87 ARFR_2_RATE_ID = 0xb,
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88 ARFR_3_RATE_ID = 0xc,
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89 ARFR_4_RATE_ID = 0xd,
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90 ARFR_5_RATE_ID = 0xe
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91 } PHYDM_RA_ARFR_NUM_E;
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93 typedef enum _Phydm_ra_dbg_para {
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94 RADBG_RTY_PENALTY = 1, //u8
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97 RADBG_TRATE_UP_TABLE = 4,
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98 RADBG_TRATE_DOWN_TABLE = 5,
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99 RADBG_TRYING_NECESSARY = 6,
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100 RADBG_TDROPING_NECESSARY = 7,
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101 RADBG_RATE_UP_RTY_RATIO = 8, //u8
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102 RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
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104 RADBG_DEBUG_MONITOR1 = 0xc,
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105 RADBG_DEBUG_MONITOR2 = 0xd,
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106 RADBG_DEBUG_MONITOR3 = 0xe,
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107 RADBG_DEBUG_MONITOR4 = 0xf,
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109 } PHYDM_RA_DBG_PARA_E;
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112 #if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
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113 typedef struct _ODM_RA_Info_ {
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119 u1Byte PreRssiStaRA;
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121 u1Byte DecisionRate;
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123 u1Byte HighestRate;
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132 u1Byte RAWaitingCounter;
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133 u1Byte RAPendingCounter;
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134 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
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135 u1Byte PTActive; // on or off
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136 u1Byte PTTryState; // 0 trying state, 1 for decision state
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137 u1Byte PTStage; // 0~6
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138 u1Byte PTStopCount; //Stop PT counter
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139 u1Byte PTPreRate; // if rate change do PT
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140 u1Byte PTPreRssi; // if RSSI change 5% do PT
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141 u1Byte PTModeSS; // decide whitch rate should do PT
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142 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
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143 u1Byte PTSmoothFactor;
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145 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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146 u1Byte RateDownCounter;
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147 u1Byte RateUpCounter;
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148 u1Byte RateDirection;
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149 u1Byte BoundingType;
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150 u1Byte BoundingCounter;
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151 u1Byte BoundingLearningTime;
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152 u1Byte RateDownStartTime;
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154 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
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158 typedef struct _Rate_Adaptive_Table_ {
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159 u1Byte firstconnect;
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160 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
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161 BOOLEAN PT_collision_pre;
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164 #if (defined(CONFIG_RA_DBG_CMD))
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165 BOOLEAN is_ra_dbg_init;
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167 u1Byte RTY_P[ODM_NUM_RATE_IDX];
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168 u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
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169 BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
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171 u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
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172 u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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173 BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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175 u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
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176 u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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177 BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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179 BOOLEAN RA_Para_feedback_req;
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185 u1Byte rate_length;
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187 u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
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189 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
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190 u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
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191 u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
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192 u1Byte retry_descend_num;
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193 u1Byte retrylimit_low;
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194 u1Byte retrylimit_high;
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200 typedef struct _ODM_RATE_ADAPTIVE {
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201 u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
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202 u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
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203 u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
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204 u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
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206 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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207 u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
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208 BOOLEAN bLowerRtsRate;
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211 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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213 #elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
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216 u1Byte UltraLowRSSIThresh;
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217 u4Byte LastRATR; // RATR Register Content
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220 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
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223 ODM_C2HRaParaReportHandler(
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230 odm_RA_ParaAdjust_Send_H2C(
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237 IN u4Byte *const dm_value
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241 odm_RA_ParaAdjust_init(
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251 phydm_ra_dynamic_retry_count(
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256 phydm_ra_dynamic_retry_limit(
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261 phydm_ra_dynamic_rate_id_on_assoc(
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263 IN u1Byte wireless_mode,
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264 IN u1Byte init_rate_id
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268 phydm_c2h_ra_report_handler(
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275 phydm_ra_info_init(
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280 odm_RSSIMonitorInit(
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285 odm_RSSIMonitorCheck(
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289 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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291 phydm_FindMinimumRSSI(
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292 IN PDM_ODM_T pDM_Odm,
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293 IN PADAPTER pAdapter,
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294 IN OUT BOOLEAN *pbLink_temp
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300 odm_RSSIMonitorCheckMP(
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305 odm_RSSIMonitorCheckCE(
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310 odm_RSSIMonitorCheckAP(
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316 odm_RateAdaptiveMaskInit(
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321 odm_RefreshRateAdaptiveMask(
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326 odm_RefreshRateAdaptiveMaskMP(
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331 odm_RefreshRateAdaptiveMaskCE(
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336 odm_RefreshRateAdaptiveMaskAPADSL(
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344 IN BOOLEAN bForceUpdate,
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345 OUT pu1Byte pRATRState
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349 odm_RefreshBasicRateMask(
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353 ODM_RAPostActionOnAssoc(
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357 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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363 IN BOOLEAN bErpProtect
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367 ODM_UpdateNoisyState(
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369 IN BOOLEAN bNoisyStateFromC2H
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373 Set_RA_DM_Ratrbitmap_by_Noisy(
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375 IN WIRELESS_MODE WirelessMode,
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376 IN u4Byte ratr_bitmap,
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377 IN u1Byte rssi_level
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381 ODM_UpdateInitRate(
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386 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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389 odm_RSSIDumpToRegister(
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394 odm_RefreshLdpcRtsMP(
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395 IN PADAPTER pAdapter,
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396 IN PDM_ODM_T pDM_Odm,
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399 IN s4Byte UndecoratedSmoothedPWDB
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403 ODM_DynamicARFBSelect(
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406 IN BOOLEAN Collision_State
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410 ODM_RateAdaptiveStateApInit(
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411 IN PVOID PADAPTER_VOID,
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412 IN PRT_WLAN_STA pEntry
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414 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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418 IN PADAPTER pAdapter
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422 PhyDM_Get_Rate_Bitmap_Ex(
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426 IN u1Byte rssi_level,
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427 OUT u8Byte *dm_RA_Mask,
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428 OUT u1Byte *dm_RteID
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431 ODM_Get_Rate_Bitmap(
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435 IN u1Byte rssi_level
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437 void phydm_ra_rssi_rpt_wk(PVOID pContext);
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439 #endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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441 #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
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443 #endif /*#ifndef __ODMRAINFO_H__*/
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