1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 //============================================================
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21 // File Name: odm_reg.h
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25 // This file is for general register definition.
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28 //============================================================
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29 #ifndef __HAL_ODM_REG_H__
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30 #define __HAL_ODM_REG_H__
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33 // Register Definition
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37 #define ODM_BB_RESET 0x002
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38 #define ODM_DUMMY 0x4fe
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39 #define RF_T_METER_OLD 0x24
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40 #define RF_T_METER_NEW 0x42
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42 #define ODM_EDCA_VO_PARAM 0x500
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43 #define ODM_EDCA_VI_PARAM 0x504
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44 #define ODM_EDCA_BE_PARAM 0x508
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45 #define ODM_EDCA_BK_PARAM 0x50C
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46 #define ODM_TXPAUSE 0x522
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49 #define ODM_FPGA_PHY0_PAGE8 0x800
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50 #define ODM_PSD_SETTING 0x808
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51 #define ODM_AFE_SETTING 0x818
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52 #define ODM_TXAGC_B_6_18 0x830
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53 #define ODM_TXAGC_B_24_54 0x834
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54 #define ODM_TXAGC_B_MCS32_5 0x838
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55 #define ODM_TXAGC_B_MCS0_MCS3 0x83c
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56 #define ODM_TXAGC_B_MCS4_MCS7 0x848
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57 #define ODM_TXAGC_B_MCS8_MCS11 0x84c
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58 #define ODM_ANALOG_REGISTER 0x85c
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59 #define ODM_RF_INTERFACE_OUTPUT 0x860
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60 #define ODM_TXAGC_B_MCS12_MCS15 0x868
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61 #define ODM_TXAGC_B_11_A_2_11 0x86c
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62 #define ODM_AD_DA_LSB_MASK 0x874
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63 #define ODM_ENABLE_3_WIRE 0x88c
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64 #define ODM_PSD_REPORT 0x8b4
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65 #define ODM_R_ANT_SELECT 0x90c
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66 #define ODM_CCK_ANT_SELECT 0xa07
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67 #define ODM_CCK_PD_THRESH 0xa0a
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68 #define ODM_CCK_RF_REG1 0xa11
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69 #define ODM_CCK_MATCH_FILTER 0xa20
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70 #define ODM_CCK_RAKE_MAC 0xa2e
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71 #define ODM_CCK_CNT_RESET 0xa2d
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72 #define ODM_CCK_TX_DIVERSITY 0xa2f
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73 #define ODM_CCK_FA_CNT_MSB 0xa5b
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74 #define ODM_CCK_FA_CNT_LSB 0xa5c
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75 #define ODM_CCK_NEW_FUNCTION 0xa75
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76 #define ODM_OFDM_PHY0_PAGE_C 0xc00
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77 #define ODM_OFDM_RX_ANT 0xc04
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78 #define ODM_R_A_RXIQI 0xc14
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79 #define ODM_R_A_AGC_CORE1 0xc50
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80 #define ODM_R_A_AGC_CORE2 0xc54
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81 #define ODM_R_B_AGC_CORE1 0xc58
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82 #define ODM_R_AGC_PAR 0xc70
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83 #define ODM_R_HTSTF_AGC_PAR 0xc7c
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84 #define ODM_TX_PWR_TRAINING_A 0xc90
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85 #define ODM_TX_PWR_TRAINING_B 0xc98
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86 #define ODM_OFDM_FA_CNT1 0xcf0
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87 #define ODM_OFDM_PHY0_PAGE_D 0xd00
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88 #define ODM_OFDM_FA_CNT2 0xda0
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89 #define ODM_OFDM_FA_CNT3 0xda4
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90 #define ODM_OFDM_FA_CNT4 0xda8
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91 #define ODM_TXAGC_A_6_18 0xe00
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92 #define ODM_TXAGC_A_24_54 0xe04
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93 #define ODM_TXAGC_A_1_MCS32 0xe08
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94 #define ODM_TXAGC_A_MCS0_MCS3 0xe10
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95 #define ODM_TXAGC_A_MCS4_MCS7 0xe14
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96 #define ODM_TXAGC_A_MCS8_MCS11 0xe18
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97 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c
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100 #define ODM_GAIN_SETTING 0x00
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101 #define ODM_CHANNEL 0x18
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102 #define ODM_RF_T_METER 0x24
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103 #define ODM_RF_T_METER_92D 0x42
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104 #define ODM_RF_T_METER_88E 0x42
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105 #define ODM_RF_T_METER_92E 0x42
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106 #define ODM_RF_T_METER_8812 0x42
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109 #define ODM_DPDT 0x300
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112 #define ODM_PSDREG 0x808
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115 #define PATHDIV_REG 0xB30
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116 #define PATHDIV_TRI 0xBA0
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120 // Bitmap Definition
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122 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
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124 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
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125 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
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126 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
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127 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
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128 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
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129 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
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130 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
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131 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
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132 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
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133 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
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134 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
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135 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
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136 #if defined(CONFIG_WLAN_HAL_8814AE)
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137 #define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8
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138 #define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc
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139 #define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0
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140 #define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4
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141 #define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8
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143 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
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144 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
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145 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
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146 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
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147 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
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148 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
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149 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
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150 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
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151 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
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152 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
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153 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
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154 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
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155 #if defined(CONFIG_WLAN_HAL_8814AE)
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156 #define rTxAGC_B_MCS19_MCS16_JAguar 0xed8
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157 #define rTxAGC_B_MCS23_MCS20_JAguar 0xedc
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158 #define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0
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159 #define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4
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160 #define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8
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161 #define rTxAGC_C_CCK11_CCK1_JAguar 0x1820
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162 #define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824
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163 #define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828
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164 #define rTxAGC_C_MCS3_MCS0_JAguar 0x182c
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165 #define rTxAGC_C_MCS7_MCS4_JAguar 0x1830
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166 #define rTxAGC_C_MCS11_MCS8_JAguar 0x1834
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167 #define rTxAGC_C_MCS15_MCS12_JAguar 0x1838
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168 #define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c
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169 #define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840
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170 #define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844
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171 #define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848
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172 #define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c
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173 #define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8
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174 #define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc
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175 #define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0
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176 #define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4
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177 #define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8
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178 #define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20
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179 #define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24
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180 #define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28
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181 #define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c
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182 #define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30
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183 #define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34
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184 #define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38
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185 #define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c
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186 #define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40
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187 #define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44
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188 #define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48
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189 #define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c
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190 #define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8
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191 #define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc
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192 #define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0
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193 #define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4
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194 #define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8
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197 #define bTxAGC_byte0_Jaguar 0xff
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198 #define bTxAGC_byte1_Jaguar 0xff00
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199 #define bTxAGC_byte2_Jaguar 0xff0000
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200 #define bTxAGC_byte3_Jaguar 0xff000000
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203 #define BIT_FA_RESET BIT0
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