drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/phydm_rxhp.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 //============================================================\r
  21 // include files\r
  22 //============================================================\r
  23 #include "mp_precomp.h"\r
  24 #include "phydm_precomp.h"\r
  25 \r
  26 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
  27 \r
  28 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD\r
  29 #define MODE_40M                0       //0:20M, 1:40M\r
  30 #define PSD_TH2         3  \r
  31 #define PSD_CHMIN               20   // Minimum channel number for BT AFH\r
  32 #define SIR_STEP_SIZE   3\r
  33 #define   Smooth_Size_1         5\r
  34 #define Smooth_TH_1     3\r
  35 #define   Smooth_Size_2         10\r
  36 #define Smooth_TH_2     4\r
  37 #define   Smooth_Size_3         20\r
  38 #define Smooth_TH_3     4\r
  39 #define   Smooth_Step_Size 5\r
  40 #define Adaptive_SIR    1\r
  41 #define SCAN_INTERVAL   1500 //ms\r
  42 #define SYN_Length              5    // for 92D\r
  43         \r
  44 #define LNA_Low_Gain_1                      0x64\r
  45 #define LNA_Low_Gain_2                      0x5A\r
  46 #define LNA_Low_Gain_3                      0x58\r
  47 \r
  48 #define pw_th_10dB                                      0x0\r
  49 #define pw_th_16dB                                      0x3\r
  50 \r
  51 #define FA_RXHP_TH1                           5000\r
  52 #define FA_RXHP_TH2                           1500\r
  53 #define FA_RXHP_TH3                             800\r
  54 #define FA_RXHP_TH4                             600\r
  55 #define FA_RXHP_TH5                             500\r
  56 \r
  57 #define Idle_Mode                                       0\r
  58 #define High_TP_Mode                            1\r
  59 #define Low_TP_Mode                             2\r
  60 \r
  61 \r
  62 VOID\r
  63 odm_PSDMonitorInit(\r
  64         IN              PVOID                   pDM_VOID\r
  65         )\r
  66 {\r
  67 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
  68         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  69 \r
  70         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);\r
  71         //PSD Monitor Setting\r
  72         //Which path in ADC/DAC is turnned on for PSD: both I/Q\r
  73         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);\r
  74         //Ageraged number: 8\r
  75         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);\r
  76         pDM_Odm->bPSDinProcess = FALSE;\r
  77         pDM_Odm->bUserAssignLevel = FALSE;\r
  78         pDM_Odm->bPSDactive = FALSE;\r
  79         //pDM_Odm->bDMInitialGainEnable=TRUE;           //change the initialization to DIGinit\r
  80         //Set Debug Port\r
  81         //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);\r
  82         //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD\r
  83         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan\r
  84         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval\r
  85 \r
  86         //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms\r
  87 #endif\r
  88 }\r
  89 \r
  90 VOID\r
  91 PatchDCTone(\r
  92         IN              PVOID                   pDM_VOID,\r
  93         pu4Byte         PSD_report,\r
  94         u1Byte          initial_gain_psd\r
  95 )\r
  96 {\r
  97         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  98         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);\r
  99         //PADAPTER      pAdapter;\r
 100         \r
 101         u4Byte  psd_report;\r
 102 \r
 103         //2 Switch to CH11 to patch CH9 and CH13 DC tone\r
 104         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11);\r
 105         \r
 106         if(pDM_Odm->SupportICType== ODM_RTL8192D)\r
 107         {\r
 108                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))\r
 109                 {\r
 110                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11);\r
 111                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);\r
 112                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);\r
 113                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A);\r
 114                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289);\r
 115                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840);\r
 116                 }\r
 117                 else\r
 118                 {\r
 119                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);\r
 120                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);\r
 121                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A);\r
 122                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289);\r
 123                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840);\r
 124                 }\r
 125         }\r
 126         \r
 127         //Ch9 DC tone patch\r
 128         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);\r
 129         PSD_report[50] = psd_report;\r
 130         //Ch13 DC tone patch\r
 131         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);\r
 132         PSD_report[70] = psd_report;\r
 133         \r
 134         //2 Switch to CH3 to patch CH1 and CH5 DC tone\r
 135         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3);\r
 136 \r
 137         \r
 138         if(pDM_Odm->SupportICType==ODM_RTL8192D)\r
 139         {\r
 140                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))\r
 141                 {\r
 142                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3);\r
 143                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);\r
 144                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);\r
 145                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A);\r
 146                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289);\r
 147                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41);\r
 148                 }\r
 149                 else\r
 150                 {\r
 151                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);\r
 152                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);\r
 153                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A);\r
 154                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289);\r
 155                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41);\r
 156                 }\r
 157         }\r
 158         \r
 159         //Ch1 DC tone patch\r
 160         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);\r
 161         PSD_report[10] = psd_report;\r
 162         //Ch5 DC tone patch\r
 163         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);\r
 164         PSD_report[30] = psd_report;\r
 165 \r
 166 }\r
 167 \r
 168 \r
 169 VOID\r
 170 GoodChannelDecision(\r
 171         IN              PVOID                   pDM_VOID,\r
 172         pu4Byte         PSD_report,\r
 173         pu1Byte         PSD_bitmap,\r
 174         u1Byte          RSSI_BT,\r
 175         pu1Byte         PSD_bitmap_memory)\r
 176 {\r
 177         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 178         pRXHP_T                 pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
 179         //s4Byte        TH1 =  SSBT-0x15;    // modify TH by Neil Chen\r
 180         s4Byte  TH1= RSSI_BT+0x14;\r
 181         s4Byte  TH2 = RSSI_BT+85;\r
 182         //u2Byte    TH3;\r
 183 //      s4Byte  RegB34;\r
 184         u1Byte  bitmap, Smooth_size[3], Smooth_TH[3];\r
 185         //u1Byte        psd_bit;\r
 186         u4Byte  i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];\r
 187         int             start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;\r
 188         \r
 189 //      RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;\r
 190 \r
 191         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))\r
 192        {\r
 193             TH1 = RSSI_BT + 0x14;  \r
 194         }\r
 195 \r
 196         Smooth_size[0]=Smooth_Size_1;\r
 197         Smooth_size[1]=Smooth_Size_2;\r
 198         Smooth_size[2]=Smooth_Size_3;\r
 199         Smooth_TH[0]=Smooth_TH_1;\r
 200         Smooth_TH[1]=Smooth_TH_2;\r
 201         Smooth_TH[2]=Smooth_TH_3;\r
 202         Smooth_Interval[0]=16;\r
 203         Smooth_Interval[1]=15;\r
 204         Smooth_Interval[2]=13;\r
 205         good_cnt = 0;\r
 206         if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 207         {\r
 208                 //2 Threshold  \r
 209 \r
 210                 if(RSSI_BT >=41)\r
 211                         TH1 = 113;      \r
 212                 else if(RSSI_BT >=38)   // >= -15dBm\r
 213                         TH1 = 105;                              //0x69\r
 214                 else if((RSSI_BT >=33)&(RSSI_BT <38))\r
 215                         TH1 = 99+(RSSI_BT-33);         //0x63\r
 216                 else if((RSSI_BT >=26)&(RSSI_BT<33))\r
 217                         TH1 = 99-(33-RSSI_BT)+2;     //0x5e\r
 218                 else if((RSSI_BT >=24)&(RSSI_BT<26))\r
 219                         TH1 = 88-((RSSI_BT-24)*3);   //0x58\r
 220                 else if((RSSI_BT >=18)&(RSSI_BT<24))\r
 221                         TH1 = 77+((RSSI_BT-18)*2);\r
 222                 else if((RSSI_BT >=14)&(RSSI_BT<18))\r
 223                         TH1 = 63+((RSSI_BT-14)*2);\r
 224                 else if((RSSI_BT >=8)&(RSSI_BT<14))\r
 225                         TH1 = 58+((RSSI_BT-8)*2);\r
 226                 else if((RSSI_BT >=3)&(RSSI_BT<8))\r
 227                         TH1 = 52+(RSSI_BT-3);\r
 228                 else\r
 229                         TH1 = 51;\r
 230         }\r
 231 \r
 232         for (i = 0; i< 10; i++)\r
 233                 PSD_bitmap[i] = 0;\r
 234         \r
 235 \r
 236          // Add By Gary\r
 237        for (i=0; i<80; i++)\r
 238                 pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;\r
 239         // End\r
 240 \r
 241 \r
 242 \r
 243         if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 244         {\r
 245                 TH1 =TH1-SIR_STEP_SIZE;\r
 246         }\r
 247         while (good_cnt < PSD_CHMIN)\r
 248         {\r
 249                 good_cnt = 0;\r
 250                 if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 251                 {\r
 252                 if(TH1 ==TH2)\r
 253                         break;\r
 254                 if((TH1+SIR_STEP_SIZE) < TH2)\r
 255                         TH1 += SIR_STEP_SIZE;\r
 256                 else\r
 257                         TH1 = TH2;\r
 258                 }\r
 259                 else\r
 260                 {\r
 261                         if(TH1==(RSSI_BT+0x1E))\r
 262                              break;    \r
 263                         if((TH1+2) < (RSSI_BT+0x1E))\r
 264                                 TH1+=3;\r
 265                         else\r
 266                                 TH1 = RSSI_BT+0x1E;     \r
 267              \r
 268                 }\r
 269                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));\r
 270                          \r
 271                 for (i = 0; i< 80; i++)\r
 272                 {\r
 273                         if((s4Byte)(PSD_report[i]) < TH1)\r
 274                         {\r
 275                                 byte_idx = i / 8;\r
 276                                 bit_idx = i -8*byte_idx;\r
 277                                 bitmap = PSD_bitmap[byte_idx];\r
 278                                 PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);\r
 279                         }\r
 280                 }\r
 281 \r
 282 #if DBG\r
 283                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));\r
 284                 for(n=0;n<10;n++)\r
 285                 {\r
 286                         //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);\r
 287                         for (i = 0; i<8; i++)\r
 288                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));\r
 289                 }\r
 290 #endif\r
 291         \r
 292                 //1 Start of smoothing function\r
 293 \r
 294                 for (j=0;j<3;j++)\r
 295                 {\r
 296                         start_byte_idx=0;\r
 297                         start_bit_idx=0;\r
 298                         for(n=0; n<Smooth_Interval[j]; n++)\r
 299                         {\r
 300                                 good_cnt_smoothing = 0;\r
 301                                 cur_bit_idx = start_bit_idx;\r
 302                                 cur_byte_idx = start_byte_idx;\r
 303                                 for ( i=0; i < Smooth_size[j]; i++)\r
 304                                 {\r
 305                                         NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;\r
 306                                         if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)\r
 307                                                 good_cnt_smoothing++;\r
 308 \r
 309                                 }\r
 310 \r
 311                                 if( good_cnt_smoothing < Smooth_TH[j] )\r
 312                                 {\r
 313                                         cur_bit_idx = start_bit_idx;\r
 314                                         cur_byte_idx = start_byte_idx;\r
 315                                         for ( i=0; i< Smooth_size[j] ; i++)\r
 316                                         {       \r
 317                                                 NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;                                \r
 318                                                 PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));\r
 319                                         }\r
 320                                 }\r
 321                                 start_bit_idx =  start_bit_idx + Smooth_Step_Size;\r
 322                                 while ( (start_bit_idx)  > 7 )\r
 323                                 {\r
 324                                         start_byte_idx= start_byte_idx+start_bit_idx/8;\r
 325                                         start_bit_idx = start_bit_idx%8;\r
 326                                 }\r
 327                         }\r
 328 \r
 329                         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));\r
 330                         for(n=0;n<10;n++)\r
 331                         {\r
 332                                 for (i = 0; i<8; i++)\r
 333                                 {\r
 334                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));\r
 335                                         \r
 336                                         if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1)  //----- Add By Gary\r
 337                                         {\r
 338                                            pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;\r
 339                                         }                                                  // ------end by Gary\r
 340                                 }\r
 341                         }\r
 342 \r
 343                 }\r
 344 \r
 345         \r
 346                 good_cnt = 0;\r
 347                 for ( i = 0; i < 10; i++)\r
 348                 {\r
 349                         for (n = 0; n < 8; n++)\r
 350                                 if((PSD_bitmap[i]& BIT(n)) != 0)\r
 351                                         good_cnt++;\r
 352                 }\r
 353                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, ODM_COMP_PSD,("PSD: good channel cnt = %u",good_cnt));\r
 354         }\r
 355 \r
 356         //RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));\r
 357         for (i = 0; i <10; i++)\r
 358                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));\r
 359 /*      \r
 360         //Update bitmap memory\r
 361         for(i = 0; i < 80; i++)\r
 362         {\r
 363                 byte_idx = i / 8;\r
 364                 bit_idx = i -8*byte_idx;\r
 365                 psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;\r
 366                 bitmap = PSD_bitmap_memory[i]; \r
 367                 PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;\r
 368         }\r
 369 */\r
 370 }\r
 371 \r
 372 \r
 373 \r
 374 VOID\r
 375 odm_PSD_Monitor(\r
 376         IN              PVOID                   pDM_VOID\r
 377 )\r
 378 {\r
 379         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 380         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
 381         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;\r
 382 \r
 383         unsigned int            pts, start_point, stop_point;\r
 384         u1Byte                  initial_gain ;\r
 385         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;\r
 386         static u1Byte           psd_cnt=0;\r
 387         static u4Byte           PSD_report[80], PSD_report_tmp;\r
 388         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;\r
 389         u1Byte                  H2C_PSD_DATA[5]={0,0,0,0,0};\r
 390         static u1Byte           H2C_PSD_DATA_last[5] ={0,0,0,0,0};\r
 391         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,\r
 392                                         0,3,6,10,13,16,19,22,26,29};\r
 393         u1Byte                  n, i, channel, BBReset,tone_idx;\r
 394         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;\r
 395         s4Byte                          PSD_skip_start, PSD_skip_stop;\r
 396         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;\r
 397         u4Byte                  ReScan, Interval, Is40MHz;\r
 398         u8Byte                  curTxOkCnt, curRxOkCnt;\r
 399         int                             cur_byte_idx, cur_bit_idx;\r
 400         PADAPTER                Adapter = pDM_Odm->Adapter;\r
 401         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;\r
 402         \r
 403 \r
 404         if(*pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep)\r
 405         {\r
 406                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("pbDriverIsGoingToPnpSetPowerSleep!!!!!!!!!!!!!!!\n"));\r
 407                 return;\r
 408         }\r
 409 \r
 410         \r
 411         if( (*(pDM_Odm->pbScanInProcess)) ||\r
 412                 pDM_Odm->bLinkInProcess)\r
 413         {\r
 414                 if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))\r
 415                 {\r
 416                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms  \r
 417                         //psd_cnt=0;\r
 418                 }\r
 419                 return;\r
 420         }\r
 421 \r
 422         if(pDM_Odm->bBtHsOperation)\r
 423         {\r
 424                 ReScan = 1;\r
 425                 Interval = SCAN_INTERVAL;\r
 426         }\r
 427         else\r
 428         {\r
 429         ReScan = PSD_RESCAN;\r
 430         Interval = SCAN_INTERVAL;\r
 431         }\r
 432 \r
 433         //1 Initialization\r
 434         if(init_memory == 0)\r
 435         {\r
 436                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));\r
 437                 for(i = 0; i < 80; i++)\r
 438                         PSD_bitmap_memory[i] = 0xFF; // channel is always good\r
 439                 init_memory = 1;\r
 440         }\r
 441         if(psd_cnt == 0)\r
 442         {\r
 443                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));\r
 444                 for(i = 0; i < 80; i++)\r
 445                         PSD_report[i] = 0;\r
 446         }\r
 447 \r
 448         //1 Backup Current Settings\r
 449         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);\r
 450 /*\r
 451         if(pDM_Odm->SupportICType==ODM_RTL8192D)\r
 452         {\r
 453                 //2 Record Current synthesizer parameters based on current channel\r
 454                 if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))\r
 455                 {\r
 456                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord);\r
 457                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord);\r
 458                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord);\r
 459                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord);\r
 460                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord);\r
 461         }\r
 462                 else     // DualMAC_DualPHY 2G\r
 463                 {\r
 464                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord);\r
 465                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord);\r
 466                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord);\r
 467                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord);\r
 468                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord);\r
 469                 }\r
 470         }\r
 471 */\r
 472         //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);\r
 473         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);\r
 474 \r
 475         //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;\r
 476         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;\r
 477 \r
 478         //2???\r
 479         if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo))\r
 480                 Is40MHz = TRUE;\r
 481         else\r
 482                 Is40MHz = FALSE;\r
 483 \r
 484         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));\r
 485         //1 Turn off CCK\r
 486         //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);\r
 487         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);\r
 488         //1 Turn off TX\r
 489         //Pause TX Queue\r
 490         //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);\r
 491         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);\r
 492         \r
 493         //Force RX to stop TX immediately\r
 494         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
 495 \r
 496         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
 497         //1 Turn off RX\r
 498         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0\r
 499         //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);\r
 500         //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);\r
 501 \r
 502         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);\r
 503         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);\r
 504 \r
 505         \r
 506         //Turn off CCA\r
 507         //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);\r
 508         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);\r
 509         \r
 510         //BB Reset\r
 511         //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);\r
 512         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);\r
 513         \r
 514         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));\r
 515         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);\r
 516         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess \r
 517         ODM_Write1Byte(pDM_Odm,  0x02, BBReset&(~BIT0));\r
 518         ODM_Write1Byte(pDM_Odm,  0x02, BBReset|BIT0);\r
 519         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);\r
 520         \r
 521         //1 Leave RX idle low power\r
 522         //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);\r
 523 \r
 524         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);\r
 525         //1 Fix initial gain\r
 526         //if (IS_HARDWARE_TYPE_8723AE(Adapter))\r
 527         //RSSI_BT = pHalData->RSSI_BT;\r
 528        //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))      // Add by Gary\r
 529        //    RSSI_BT = RSSI_BT_new;\r
 530 \r
 531         if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))\r
 532         RSSI_BT=pDM_Odm->RSSI_BT;               //need to check C2H to pDM_Odm RSSI BT\r
 533 \r
 534         if(RSSI_BT>=47)\r
 535                 RSSI_BT=47;\r
 536            \r
 537         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
 538         \r
 539         if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 540         {\r
 541                //Neil add--2011--10--12\r
 542                 //2 Initial Gain index \r
 543                 if(RSSI_BT >=35)   // >= -15dBm\r
 544                         initial_gain_psd = RSSI_BT*2;\r
 545                 else if((RSSI_BT >=33)&(RSSI_BT<35))\r
 546                         initial_gain_psd = RSSI_BT*2+6;\r
 547                 else if((RSSI_BT >=24)&(RSSI_BT<33))\r
 548                         initial_gain_psd = 70-(33-RSSI_BT);\r
 549                 else if((RSSI_BT >=19)&(RSSI_BT<24))\r
 550                         initial_gain_psd = 64-((24-RSSI_BT)*4);\r
 551                 else if((RSSI_BT >=14)&(RSSI_BT<19))\r
 552                         initial_gain_psd = 44-((18-RSSI_BT)*2);\r
 553                 else if((RSSI_BT >=8)&(RSSI_BT<14))\r
 554                         initial_gain_psd = 35-(14-RSSI_BT);\r
 555                 else\r
 556                         initial_gain_psd = 0x1B;\r
 557         }\r
 558         else\r
 559         {\r
 560         \r
 561                 //need to do    \r
 562                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI\r
 563                 //}     \r
 564         }\r
 565         //if(RSSI_BT<0x17)\r
 566         //      RSSI_BT +=3;\r
 567         //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);\r
 568         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
 569 \r
 570         //initialGainUpper = 0x5E;  //Modify by neil chen\r
 571         \r
 572         if(pDM_Odm->bUserAssignLevel)\r
 573         {\r
 574                 pDM_Odm->bUserAssignLevel = FALSE;\r
 575                 initialGainUpper = 0x7f;\r
 576         }\r
 577         else\r
 578         {\r
 579                 initialGainUpper = 0x5E;\r
 580         }\r
 581         \r
 582         /*\r
 583         if (initial_gain_psd < 0x1a)\r
 584                 initial_gain_psd = 0x1a;\r
 585         if (initial_gain_psd > initialGainUpper)\r
 586                 initial_gain_psd = initialGainUpper;\r
 587         */\r
 588 \r
 589         //if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 590         SSBT = RSSI_BT  * 2 +0x3E;\r
 591         \r
 592         \r
 593         //if(IS_HARDWARE_TYPE_8723AE(Adapter))\r
 594         //      SSBT = RSSI_BT  * 2 +0x3E;\r
 595         //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))   // Add by Gary\r
 596         //{\r
 597         //      RSSI_BT = initial_gain_psd;\r
 598         //      SSBT = RSSI_BT;\r
 599         //}\r
 600         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));\r
 601         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));\r
 602         //DbgPrint("PSD: SSBT= %d", SSBT);\r
 603         //need to do\r
 604         pDM_Odm->bDMInitialGainEnable = FALSE;\r
 605         initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F);\r
 606         \r
 607         // make sure the initial gain is under the correct range.\r
 608         //initial_gain_psd &= 0x7f;\r
 609         ODM_Write_DIG(pDM_Odm, initial_gain_psd);\r
 610         //1 Turn off 3-wire\r
 611         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);\r
 612 \r
 613         //pts value = 128, 256, 512, 1024\r
 614         pts = 128;\r
 615 \r
 616         if(pts == 128)\r
 617         {\r
 618                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);\r
 619                 start_point = 64;\r
 620                 stop_point = 192;\r
 621         }\r
 622         else if(pts == 256)\r
 623         {\r
 624                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);\r
 625                 start_point = 128;\r
 626                 stop_point = 384;\r
 627         }\r
 628         else if(pts == 512)\r
 629         {\r
 630                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);\r
 631                 start_point = 256;\r
 632                 stop_point = 768;\r
 633         }\r
 634         else\r
 635         {\r
 636                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);\r
 637                 start_point = 512;\r
 638                 stop_point = 1536;\r
 639         }\r
 640         \r
 641 \r
 642 //3 Skip WLAN channels if WLAN busy\r
 643 \r
 644         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;\r
 645         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;\r
 646         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
 647         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);   \r
 648 \r
 649         PSD_skip_start=80;\r
 650         PSD_skip_stop = 0;\r
 651         wlan_channel = CurrentChannel & 0x0f;\r
 652 \r
 653         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));\r
 654         if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 655         {\r
 656                 if(pDM_Odm->bBtHsOperation)\r
 657                 {\r
 658                         if(pDM_Odm->bLinked)\r
 659                         {\r
 660                                 if(Is40MHz)\r
 661                                 {\r
 662                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask\r
 663                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
 664                                 }\r
 665                                 else\r
 666                                 {\r
 667                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask\r
 668                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; \r
 669                                 }\r
 670                         }\r
 671                         else\r
 672                         {\r
 673                                 // mask for 40MHz\r
 674                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask\r
 675                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
 676                         }\r
 677                         if(PSD_skip_start < 0)\r
 678                                 PSD_skip_start = 0;\r
 679                         if(PSD_skip_stop >80)\r
 680                                 PSD_skip_stop = 80;\r
 681                 }\r
 682                 else\r
 683                 {\r
 684                         if((curRxOkCnt+curTxOkCnt) > 5)\r
 685                         {\r
 686                                 if(Is40MHz)\r
 687                                 {\r
 688                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask\r
 689                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;\r
 690                                 }\r
 691                                 else\r
 692                                 {\r
 693                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask\r
 694                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; \r
 695                                 }\r
 696                                 \r
 697                                 if(PSD_skip_start < 0)\r
 698                                         PSD_skip_start = 0;\r
 699                                 if(PSD_skip_stop >80)\r
 700                                         PSD_skip_stop = 80;\r
 701                         }\r
 702                 }\r
 703         }\r
 704 #if 0   \r
 705         else\r
 706         {\r
 707                 if((curRxOkCnt+curTxOkCnt) > 1000)\r
 708                 {\r
 709                         PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;\r
 710                         PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;\r
 711                 }\r
 712         }   \r
 713 #endif  //Reove RXHP Issue\r
 714         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));\r
 715 \r
 716         for (n=0;n<80;n++)\r
 717         {\r
 718                 if((n%20)==0)\r
 719                 {\r
 720                         channel = (n/20)*4 + 1;\r
 721                                         \r
 722                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
 723                                 }\r
 724                 tone_idx = n%20;\r
 725                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))\r
 726                 {       \r
 727                         PSD_report[n] = SSBT;\r
 728                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));\r
 729                 }\r
 730                 else\r
 731                 {\r
 732                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);\r
 733 \r
 734                         if ( PSD_report_tmp > PSD_report[n])\r
 735                                 PSD_report[n] = PSD_report_tmp;\r
 736                                 \r
 737                 }\r
 738         }\r
 739 \r
 740         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);\r
 741       \r
 742        //----end\r
 743         //1 Turn on RX\r
 744         //Rx AGC on\r
 745         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);\r
 746         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);\r
 747         //CCK on\r
 748         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);\r
 749         //1 Turn on TX\r
 750         //Resume TX Queue\r
 751         \r
 752         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);\r
 753         //Turn on 3-wire\r
 754         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);\r
 755         //1 Restore Current Settings\r
 756         //Resume DIG\r
 757         pDM_Odm->bDMInitialGainEnable = TRUE;\r
 758         \r
 759         ODM_Write_DIG(pDM_Odm, initial_gain);\r
 760 \r
 761         // restore originl center frequency\r
 762         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);\r
 763 \r
 764         //Turn on CCA\r
 765         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);\r
 766         //Restore RX idle low power\r
 767         if(RxIdleLowPwr == TRUE)\r
 768                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);\r
 769         \r
 770         psd_cnt++;\r
 771         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));\r
 772         if (psd_cnt < ReScan)\r
 773                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval);            \r
 774         else\r
 775         {\r
 776                 psd_cnt = 0;\r
 777                 for(i=0;i<80;i++)\r
 778                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);\r
 779                         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));\r
 780 \r
 781 \r
 782                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);\r
 783 \r
 784                 if(pDM_Odm->SupportICType==ODM_RTL8723A)\r
 785                 {\r
 786                         cur_byte_idx=0;\r
 787                         cur_bit_idx=0;\r
 788 \r
 789                         //2 Restore H2C PSD Data to Last Data\r
 790                         H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];\r
 791                         H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];\r
 792                         H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];\r
 793                         H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];\r
 794                         H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];\r
 795 \r
 796         \r
 797                         //2 Translate 80bit channel map to 40bit channel        \r
 798                         for ( i=0;i<5;i++)\r
 799                         {\r
 800                                 for(n=0;n<8;n++)\r
 801                                 {\r
 802                                         cur_byte_idx = i*2 + n/4;\r
 803                                         cur_bit_idx = (n%4)*2;\r
 804                                         if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))\r
 805                                                 H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);\r
 806                                 }\r
 807                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));\r
 808                         }\r
 809         \r
 810                         //3 To Compare the difference\r
 811                         for ( i=0;i<5;i++)\r
 812                         {\r
 813                                 if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])\r
 814                                 {\r
 815                                         FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);\r
 816                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n"));\r
 817                                         break;\r
 818                                 }\r
 819                                 else\r
 820                                 {\r
 821                                         if(i==5)\r
 822                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n"));  \r
 823                                 }\r
 824                         }\r
 825                         if(pDM_Odm->bBtHsOperation)\r
 826                         {\r
 827                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000);\r
 828                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));             \r
 829                         }\r
 830                         else\r
 831                         {\r
 832                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500);\r
 833                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));             \r
 834                 }\r
 835         }\r
 836     }\r
 837 }\r
 838 /*\r
 839 //Neil for Get BT RSSI\r
 840 // Be Triggered by BT C2H CMD\r
 841 VOID\r
 842 ODM_PSDGetRSSI(\r
 843         IN      u1Byte  RSSI_BT)\r
 844 {\r
 845 \r
 846 \r
 847 }\r
 848 \r
 849 */\r
 850 \r
 851 VOID\r
 852 ODM_PSDMonitor(\r
 853         IN              PVOID                   pDM_VOID\r
 854         )\r
 855 {\r
 856         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 857         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\r
 858         \r
 859         //if(IS_HARDWARE_TYPE_8723AE(Adapter))\r
 860         \r
 861         if(pDM_Odm->SupportICType == ODM_RTL8723A)   //may need to add other IC type\r
 862         {\r
 863                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)\r
 864                 {\r
 865                         if(!pDM_Odm->bBtEnabled) //need to check upper layer connection\r
 866                         {\r
 867                                 pDM_Odm->bPSDactive=FALSE;\r
 868                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));\r
 869                                 return; \r
 870                         }\r
 871 \r
 872                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));\r
 873                 //{\r
 874                         pDM_Odm->bPSDinProcess = TRUE;\r
 875                         pDM_Odm->bPSDactive=TRUE;\r
 876                         odm_PSD_Monitor(pDM_Odm);\r
 877                         pDM_Odm->bPSDinProcess = FALSE;\r
 878                 }       \r
 879         }       \r
 880 \r
 881 }\r
 882 VOID\r
 883 odm_PSDMonitorCallback(\r
 884         PRT_TIMER               pTimer\r
 885 )\r
 886 {\r
 887         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;\r
 888        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);\r
 889 \r
 890         PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);\r
 891 }\r
 892 \r
 893 VOID\r
 894 odm_PSDMonitorWorkItemCallback(\r
 895     IN PVOID            pContext\r
 896     )\r
 897 {\r
 898         PADAPTER        Adapter = (PADAPTER)pContext;\r
 899         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 900         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 901 \r
 902         ODM_PSDMonitor(pDM_Odm);\r
 903 }\r
 904 \r
 905 \r
 906  //cosa debug tool need to modify\r
 907 \r
 908 VOID\r
 909 ODM_PSDDbgControl(\r
 910         IN      PADAPTER        Adapter,\r
 911         IN      u4Byte          mode,\r
 912         IN      u4Byte          btRssi\r
 913         )\r
 914 {\r
 915 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\r
 916         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 917         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 918 \r
 919         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));\r
 920         if(mode)\r
 921         {\r
 922                 pDM_Odm->RSSI_BT = (u1Byte)btRssi;\r
 923                 pDM_Odm->bUserAssignLevel = TRUE;\r
 924                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms             \r
 925         }\r
 926         else\r
 927         {\r
 928                 ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);\r
 929         }\r
 930 #endif\r
 931 }\r
 932 \r
 933 \r
 934 //#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
 935 \r
 936 void    odm_RXHPInit(\r
 937         IN              PVOID                   pDM_VOID)\r
 938 {\r
 939 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
 940         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 941         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;\r
 942         u1Byte                  index;\r
 943 \r
 944         pRX_HP_Table->RXHP_enable = TRUE;\r
 945         pRX_HP_Table->RXHP_flag = 0;\r
 946         pRX_HP_Table->PSD_func_trigger = 0;\r
 947         pRX_HP_Table->Pre_IGI = 0x20;\r
 948         pRX_HP_Table->Cur_IGI = 0x20;\r
 949         pRX_HP_Table->Cur_pw_th = pw_th_10dB;\r
 950         pRX_HP_Table->Pre_pw_th = pw_th_10dB;\r
 951         for(index=0; index<80; index++)\r
 952                 pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;\r
 953 \r
 954 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
 955         pRX_HP_Table->TP_Mode = Idle_Mode;\r
 956 #endif\r
 957 #endif\r
 958 }\r
 959 \r
 960 VOID\r
 961 odm_PSD_RXHP(\r
 962         IN              PVOID                   pDM_VOID\r
 963 )\r
 964 {\r
 965         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 966         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;\r
 967         PADAPTER                Adapter =  pDM_Odm->Adapter;\r
 968         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);\r
 969         unsigned int            pts, start_point, stop_point, initial_gain ;\r
 970         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;\r
 971         static u1Byte           psd_cnt=0;\r
 972         static u4Byte           PSD_report[80], PSD_report_tmp;\r
 973         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;\r
 974         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,\r
 975                                         0,3,6,10,13,16,19,22,26,29};\r
 976         u1Byte                  n, i, channel, BBReset,tone_idx;\r
 977         u1Byte                  PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;\r
 978         s4Byte                          PSD_skip_start, PSD_skip_stop;\r
 979         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;\r
 980         u4Byte                  ReScan, Interval, Is40MHz;\r
 981         u8Byte                  curTxOkCnt, curRxOkCnt;\r
 982         //--------------2G band synthesizer for 92D switch RF channel using----------------- \r
 983         u1Byte                  group_idx=0;\r
 984         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;\r
 985         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel\r
 986         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}\r
 987                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14\r
 988                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8\r
 989        //--------------------- Add by Gary for Debug setting ----------------------\r
 990         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);\r
 991        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);\r
 992        //---------------------------------------------------------------------\r
 993         \r
 994         if(pMgntInfo->bScanInProgress)\r
 995         {\r
 996                 return;\r
 997         }\r
 998 \r
 999         ReScan = PSD_RESCAN;\r
1000         Interval = SCAN_INTERVAL;\r
1001 \r
1002 \r
1003         //1 Initialization\r
1004         if(init_memory == 0)\r
1005         {\r
1006                 RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));\r
1007                 for(i = 0; i < 80; i++)\r
1008                         PSD_bitmap_memory[i] = 0xFF; // channel is always good\r
1009                 init_memory = 1;\r
1010         }\r
1011         if(psd_cnt == 0)\r
1012         {\r
1013                 RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));\r
1014                 for(i = 0; i < 80; i++)\r
1015                         PSD_report[i] = 0;\r
1016         }\r
1017 \r
1018         //1 Backup Current Settings\r
1019         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);\r
1020         if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
1021         {\r
1022                 //2 Record Current synthesizer parameters based on current channel\r
1023                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))\r
1024                 {\r
1025                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord);\r
1026                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord);\r
1027                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord);\r
1028                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord);\r
1029                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord);\r
1030         }\r
1031                 else     // DualMAC_DualPHY 2G\r
1032                 {\r
1033                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord);\r
1034                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord);\r
1035                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord);\r
1036                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord);\r
1037                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord);\r
1038                 }\r
1039         }\r
1040         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);\r
1041         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;\r
1042         Is40MHz = *(pDM_Odm->pBandWidth);\r
1043         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));\r
1044         //1 Turn off CCK\r
1045         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);\r
1046         //1 Turn off TX\r
1047         //Pause TX Queue\r
1048         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);\r
1049         //Force RX to stop TX immediately\r
1050         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);\r
1051         //1 Turn off RX\r
1052         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0\r
1053         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);\r
1054         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);\r
1055         //Turn off CCA\r
1056         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);\r
1057         //BB Reset\r
1058         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess \r
1059         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);\r
1060         ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));\r
1061         ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);\r
1062         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);\r
1063         //1 Leave RX idle low power\r
1064         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);\r
1065         //1 Fix initial gain\r
1066         RSSI_BT = RSSI_BT_new;\r
1067         RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
1068         \r
1069         if(rssi_ctrl == 1)        // just for debug!!\r
1070                 initial_gain_psd = RSSI_BT_new; \r
1071         else\r
1072                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI\r
1073         \r
1074         RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));\r
1075         \r
1076         initialGainUpper = 0x54;\r
1077         \r
1078         RSSI_BT = initial_gain_psd;\r
1079         //SSBT = RSSI_BT;\r
1080         \r
1081         //RT_TRACE(     ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));\r
1082         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));\r
1083         \r
1084         pDM_Odm->bDMInitialGainEnable = FALSE;          \r
1085         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;\r
1086         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); \r
1087         ODM_Write_DIG(pDM_Odm, initial_gain_psd);\r
1088         //1 Turn off 3-wire\r
1089         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);\r
1090 \r
1091         //pts value = 128, 256, 512, 1024\r
1092         pts = 128;\r
1093 \r
1094         if(pts == 128)\r
1095         {\r
1096                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);\r
1097                 start_point = 64;\r
1098                 stop_point = 192;\r
1099         }\r
1100         else if(pts == 256)\r
1101         {\r
1102                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);\r
1103                 start_point = 128;\r
1104                 stop_point = 384;\r
1105         }\r
1106         else if(pts == 512)\r
1107         {\r
1108                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);\r
1109                 start_point = 256;\r
1110                 stop_point = 768;\r
1111         }\r
1112         else\r
1113         {\r
1114                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);\r
1115                 start_point = 512;\r
1116                 stop_point = 1536;\r
1117         }\r
1118         \r
1119 \r
1120 //3 Skip WLAN channels if WLAN busy\r
1121         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;\r
1122         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;\r
1123         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
1124         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);\r
1125         \r
1126         PSD_skip_start=80;\r
1127         PSD_skip_stop = 0;\r
1128         wlan_channel = CurrentChannel & 0x0f;\r
1129 \r
1130         RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));\r
1131         \r
1132         if((curRxOkCnt+curTxOkCnt) > 1000)\r
1133         {\r
1134                 PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;\r
1135                 PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;\r
1136         }\r
1137 \r
1138         RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));\r
1139 \r
1140         for (n=0;n<80;n++)\r
1141         {\r
1142                 if((n%20)==0)\r
1143                 {\r
1144                         channel = (n/20)*4 + 1;\r
1145                         if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
1146                         {\r
1147                                 switch(channel)\r
1148                                 {\r
1149                                         case 1: \r
1150                                         case 9:\r
1151                                                 group_idx = 0;\r
1152                                                 break;\r
1153                                         case 5:\r
1154                                                 group_idx = 2;\r
1155                                                 break;\r
1156                                         case 13:\r
1157                                                 group_idx = 1;\r
1158                                                 break;\r
1159                                 }\r
1160                                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))   \r
1161                 {\r
1162                                         for(i = 0; i < SYN_Length; i++)\r
1163                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);\r
1164 \r
1165                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
1166                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel);\r
1167                                 }\r
1168                                 else  // DualMAC_DualPHY 2G\r
1169                         {\r
1170                                         for(i = 0; i < SYN_Length; i++)\r
1171                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);   \r
1172                                         \r
1173                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
1174                                 }\r
1175                         }\r
1176                         else\r
1177                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);\r
1178                         }       \r
1179                 tone_idx = n%20;\r
1180                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))\r
1181                 {       \r
1182                         PSD_report[n] = initial_gain_psd;//SSBT;\r
1183                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));\r
1184                 }\r
1185                 else\r
1186                 {\r
1187                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);\r
1188 \r
1189                         if ( PSD_report_tmp > PSD_report[n])\r
1190                                 PSD_report[n] = PSD_report_tmp;\r
1191                                 \r
1192                 }\r
1193         }\r
1194 \r
1195         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);\r
1196       \r
1197        //----end\r
1198         //1 Turn on RX\r
1199         //Rx AGC on\r
1200         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);\r
1201         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);\r
1202         //CCK on\r
1203         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);\r
1204         //1 Turn on TX\r
1205         //Resume TX Queue\r
1206         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);\r
1207         //Turn on 3-wire\r
1208         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);\r
1209         //1 Restore Current Settings\r
1210         //Resume DIG\r
1211         pDM_Odm->bDMInitialGainEnable= TRUE;\r
1212         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);\r
1213         ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain);\r
1214         // restore originl center frequency\r
1215         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);\r
1216         if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
1217         {\r
1218                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))\r
1219                 {\r
1220                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);\r
1221                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);\r
1222                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);\r
1223                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);\r
1224                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);\r
1225                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);\r
1226                 }\r
1227                 else     // DualMAC_DualPHY\r
1228                 {\r
1229                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);\r
1230                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);\r
1231                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);\r
1232                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);\r
1233                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);\r
1234                 }\r
1235         }\r
1236         //Turn on CCA\r
1237         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);\r
1238         //Restore RX idle low power\r
1239         if(RxIdleLowPwr == TRUE)\r
1240                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);\r
1241         \r
1242         psd_cnt++;\r
1243         //gPrint("psd cnt=%d\n", psd_cnt);\r
1244         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));\r
1245         if (psd_cnt < ReScan)\r
1246         {\r
1247                 ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval);  //ms\r
1248         }\r
1249         else\r
1250         {       \r
1251                 psd_cnt = 0;\r
1252                 for(i=0;i<80;i++)\r
1253                         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));\r
1254                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);\r
1255 \r
1256                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);\r
1257 \r
1258         }\r
1259 }\r
1260 \r
1261 void odm_Write_RXHP(\r
1262         IN              PVOID                   pDM_VOID)\r
1263 {\r
1264         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1265         pRXHP_T         pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;\r
1266         u4Byte          currentIGI;\r
1267 \r
1268         if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)\r
1269         {\r
1270                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);\r
1271                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);    \r
1272         }\r
1273         \r
1274         if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)\r
1275 {\r
1276                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th);  // RegC54[9:8]=2'b11:  AGC Flow 3\r
1277         }\r
1278 \r
1279         if(pRX_HP_Table->RXHP_flag == 0)\r
1280         {\r
1281                 pRX_HP_Table->Cur_IGI = 0x20;\r
1282         }\r
1283         else\r
1284         {\r
1285                 currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
1286                 if(currentIGI<0x50)\r
1287                 {\r
1288                         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);\r
1289                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);    \r
1290                 }\r
1291         }\r
1292         pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;\r
1293         pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;\r
1294 \r
1295 }\r
1296 \r
1297 \r
1298 void odm_RXHP(\r
1299         IN              PVOID                   pDM_VOID)\r
1300 {\r
1301 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
1302 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1303         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1304         PADAPTER        Adapter =  pDM_Odm->Adapter;\r
1305         PMGNT_INFO      pMgntInfo = &(Adapter->MgntInfo);\r
1306         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;\r
1307         pRXHP_T         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;\r
1308         PFALSE_ALARM_STATISTICS         FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT);\r
1309         \r
1310         u1Byte                  i, j, sum;\r
1311         u1Byte                  Is40MHz;\r
1312         s1Byte                  Intf_diff_idx, MIN_Intf_diff_idx = 16;   \r
1313        s4Byte                   cur_channel;    \r
1314        u1Byte                   ch_map_intf_5M[17] = {0};     \r
1315        static u4Byte            FA_TH = 0;      \r
1316         static u1Byte           psd_intf_flag = 0;\r
1317         static s4Byte           curRssi = 0;                \r
1318        static s4Byte            preRssi = 0;                                                                \r
1319         static u1Byte           PSDTriggerCnt = 1;\r
1320         \r
1321         u1Byte                  RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31);   // for debug!!\r
1322 \r
1323 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)   \r
1324         static s8Byte           lastTxOkCnt = 0, lastRxOkCnt = 0;  \r
1325        s8Byte                   curTxOkCnt, curRxOkCnt;\r
1326         s8Byte                  curTPOkCnt;\r
1327         s8Byte                  TP_Acc3, TP_Acc5;\r
1328         static s8Byte           TP_Buff[5] = {0};\r
1329         static u1Byte           pre_state = 0, pre_state_flag = 0;\r
1330         static u1Byte           Intf_HighTP_flag = 0, De_counter = 16; \r
1331         static u1Byte           TP_Degrade_flag = 0;\r
1332 #endif     \r
1333         static u1Byte           LatchCnt = 0;\r
1334         \r
1335         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E))\r
1336                 return;\r
1337         //AGC RX High Power Mode is only applied on 2G band in 92D!!!\r
1338         if(pDM_Odm->SupportICType == ODM_RTL8192D)\r
1339         {\r
1340                 if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G)\r
1341                         return;\r
1342         }\r
1343 \r
1344         if(!(pDM_Odm->SupportAbility & ODM_BB_RXHP))\r
1345                 return;\r
1346 \r
1347 \r
1348         //RX HP ON/OFF\r
1349         if(RX_HP_enable == 1)\r
1350                 pRX_HP_Table->RXHP_enable = FALSE;\r
1351         else\r
1352                 pRX_HP_Table->RXHP_enable = TRUE;\r
1353 \r
1354         if(pRX_HP_Table->RXHP_enable == FALSE)\r
1355         {\r
1356                 if(pRX_HP_Table->RXHP_flag == 1)\r
1357                 {\r
1358                         pRX_HP_Table->RXHP_flag = 0;\r
1359                         psd_intf_flag = 0;\r
1360                 }\r
1361                 return;\r
1362         }\r
1363 \r
1364 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)   \r
1365         //2 Record current TP for USB interface\r
1366         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;\r
1367         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;\r
1368         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
1369         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);\r
1370 \r
1371         curTPOkCnt = curTxOkCnt+curRxOkCnt;\r
1372         TP_Buff[0] = curTPOkCnt;    // current TP  \r
1373         TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);\r
1374         TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);\r
1375         \r
1376         if(TP_Acc5 < 1000)\r
1377                 pRX_HP_Table->TP_Mode = Idle_Mode;\r
1378         else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))\r
1379                 pRX_HP_Table->TP_Mode = Low_TP_Mode;\r
1380         else\r
1381                 pRX_HP_Table->TP_Mode = High_TP_Mode;\r
1382 \r
1383         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));\r
1384         // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.\r
1385         // When LatchCnt = 0, we would Get PSD result.\r
1386         if(TP_Degrade_flag == 1)\r
1387         {\r
1388                 LatchCnt--;\r
1389                 if(LatchCnt == 0)\r
1390                 {\r
1391                         TP_Degrade_flag = 0;\r
1392                 }\r
1393         }\r
1394         // When PSD function triggered by TP degrade 20%, and Interference Flag = 1\r
1395         // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.\r
1396         if(Intf_HighTP_flag == 1)\r
1397         {\r
1398                 De_counter--;\r
1399                 if(De_counter == 0)\r
1400                 {\r
1401                         Intf_HighTP_flag = 0;\r
1402                         psd_intf_flag = 0;\r
1403                 }\r
1404         }\r
1405 #endif\r
1406 \r
1407         //2 AGC RX High Power Mode by PSD only applied to STA Mode\r
1408         //3 NOT applied 1. Ad Hoc Mode.\r
1409         //3 NOT applied 2. AP Mode\r
1410         if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))\r
1411         {    \r
1412                 Is40MHz = *(pDM_Odm->pBandWidth);\r
1413                 curRssi = pDM_Odm->RSSI_Min;\r
1414                 cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;\r
1415 \r
1416                 /* check illegal channel and bandwidth */\r
1417                 if (Is40MHz && ((cur_channel < 3) || (cur_channel > 12))) {\r
1418                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("illegal channel setting, 40MHz channel = %d\n", cur_channel));\r
1419                         return;\r
1420                 }\r
1421                 \r
1422                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));\r
1423                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));\r
1424                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));\r
1425                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));\r
1426                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));\r
1427         //2 PSD function would be triggered \r
1428         //3 1. Every 4 sec for PCIE\r
1429         //3 2. Before TP Mode (Idle TP<4kbps) for USB\r
1430         //3 3. After TP Mode (High TP) for USB \r
1431                 if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0))    // Only RSSI>TH and RX_HP_flag=0 will Do PSD process \r
1432                 {\r
1433 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1434                         //2 Before TP Mode ==> PSD would be trigger every 4 sec\r
1435                         if(pRX_HP_Table->TP_Mode == Idle_Mode)          //2.1 less wlan traffic <4kbps\r
1436                         {\r
1437 #endif\r
1438                                 if(PSDTriggerCnt == 1)       \r
1439                                 {       \r
1440                                         odm_PSD_RXHP(pDM_Odm);\r
1441                                         pRX_HP_Table->PSD_func_trigger = 1;\r
1442                                         PSDTriggerCnt = 0;\r
1443                                 }\r
1444                                 else\r
1445                                 {\r
1446                                         PSDTriggerCnt++;\r
1447                                 }\r
1448 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1449                         }       \r
1450                         //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function\r
1451                         if(pRX_HP_Table->TP_Mode == High_TP_Mode)\r
1452                         {\r
1453                                 if((pre_state_flag == 0)&&(LatchCnt == 0)) \r
1454                                 {\r
1455                                         // TP var < 5%\r
1456                                         if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))\r
1457                                         {\r
1458                                                 pre_state++;\r
1459                                                 if(pre_state == 3)      // hit pre_state condition => consecutive 3 times\r
1460                                                 {\r
1461                                                         pre_state_flag = 1;\r
1462                                                         pre_state = 0;\r
1463                                                 }\r
1464 \r
1465                                         }\r
1466                                         else\r
1467                                         {\r
1468                                                 pre_state = 0;\r
1469                                         }\r
1470                                 }\r
1471                                 //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%\r
1472                                 if(pre_state_flag == 1)         \r
1473                                 {\r
1474                                         if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3))      // degrade 20%\r
1475                                         {\r
1476                                                 odm_PSD_RXHP(pDM_Odm);\r
1477                                                 pRX_HP_Table->PSD_func_trigger = 1;\r
1478                                                 TP_Degrade_flag = 1;\r
1479                                                 LatchCnt = 2;\r
1480                                                 pre_state_flag = 0;\r
1481                                         }\r
1482                                         else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])\r
1483                                         {\r
1484                                                 odm_PSD_RXHP(pDM_Odm);\r
1485                                                 pRX_HP_Table->PSD_func_trigger = 1;\r
1486                                                 TP_Degrade_flag = 1;\r
1487                                                 LatchCnt = 2;\r
1488                                                 pre_state_flag = 0;\r
1489                                         }\r
1490                                         else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])\r
1491                                         {\r
1492                                                 odm_PSD_RXHP(pDM_Odm);\r
1493                                                 pRX_HP_Table->PSD_func_trigger = 1;\r
1494                                                 TP_Degrade_flag = 1;\r
1495                                                 LatchCnt = 2;\r
1496                                                 pre_state_flag = 0;\r
1497                                         }\r
1498                                 }\r
1499                         }\r
1500 #endif\r
1501 }\r
1502 \r
1503 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1504                 for (i=0;i<4;i++)\r
1505                 {\r
1506                         TP_Buff[4-i] = TP_Buff[3-i];\r
1507                 }\r
1508 #endif\r
1509                 //2 Update PSD bitmap according to PSD report \r
1510                 if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))\r
1511                 {       \r
1512                         //2 Separate 80M bandwidth into 16 group with smaller 5M BW.\r
1513                         for (i = 0 ; i < 16 ; i++)\r
1514                         {\r
1515                                 sum = 0;\r
1516                                 for(j = 0; j < 5 ; j++)\r
1517                                         sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];\r
1518             \r
1519                                 if(sum < 5)\r
1520                                 {\r
1521                                         ch_map_intf_5M[i] = 1;  // interference flag\r
1522                                 }\r
1523                         }\r
1524                         //=============just for debug=========================\r
1525                         //for(i=0;i<16;i++)\r
1526                                 //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);\r
1527                         //===============================================\r
1528                         //2 Mask target channel 5M index\r
1529                         for(i = 0; i < (4+4*Is40MHz) ; i++)\r
1530                         {\r
1531                                 ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0;  \r
1532                         }\r
1533                                 \r
1534                         psd_intf_flag = 0;\r
1535                         for(i = 0; i < 16; i++)\r
1536                         {\r
1537                                 if(ch_map_intf_5M[i] == 1)\r
1538                         {\r
1539                                 psd_intf_flag = 1;            // interference is detected!!!    \r
1540                                 break;\r
1541                                 }\r
1542                         }\r
1543                                 \r
1544 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1545                         if(pRX_HP_Table->TP_Mode!=Idle_Mode)\r
1546                         {\r
1547                                 if(psd_intf_flag == 1)     // to avoid psd_intf_flag always 1\r
1548                                 {\r
1549                                         Intf_HighTP_flag = 1;\r
1550                                         De_counter = 32;     // 0x1E -> 0x3E needs 32 times by each IGI step =1\r
1551                                 }\r
1552                         }\r
1553 #endif\r
1554                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));\r
1555                         //2 Distance between target channel and interference\r
1556                         for(i = 0; i < 16; i++)\r
1557                         {\r
1558                                 if(ch_map_intf_5M[i] == 1)\r
1559                                 {\r
1560                                         Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz));  \r
1561                                 if(Intf_diff_idx < MIN_Intf_diff_idx)\r
1562                                                 MIN_Intf_diff_idx = Intf_diff_idx;    // the min difference index between interference and target\r
1563                                 }\r
1564                         }\r
1565                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx)); \r
1566                         //2 Choose False Alarm Threshold\r
1567                         switch (MIN_Intf_diff_idx){\r
1568                                 case 0: \r
1569                                 case 1:\r
1570                                 case 2:\r
1571                                 case 3:          \r
1572                                         FA_TH = FA_RXHP_TH1;  \r
1573                                 break;\r
1574                                 case 4:                         // CH5\r
1575                                 case 5:                         // CH6\r
1576                                         FA_TH = FA_RXHP_TH2;    \r
1577                                 break;\r
1578                                 case 6:                         // CH7\r
1579                                 case 7:                         // CH8\r
1580                                         FA_TH = FA_RXHP_TH3;\r
1581                                         break; \r
1582                         case 8:                         // CH9\r
1583                                 case 9:                         //CH10\r
1584                                         FA_TH = FA_RXHP_TH4;\r
1585                                         break;  \r
1586                                 case 10:\r
1587                                 case 11:\r
1588                                 case 12:\r
1589                                 case 13:         \r
1590                                 case 14:\r
1591                                 case 15:                \r
1592                                         FA_TH = FA_RXHP_TH5;\r
1593                                         break;                  \r
1594                 }       \r
1595                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));\r
1596                         pRX_HP_Table->PSD_func_trigger = 0;\r
1597                 }\r
1598                 //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode\r
1599                 if(pRX_HP_Table->RXHP_flag == 1)\r
1600                 {\r
1601                 if ((curRssi > 80)&&(preRssi < 80))\r
1602                 { \r
1603                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;\r
1604                 }\r
1605                 else if ((curRssi < 80)&&(preRssi > 80))\r
1606                 {\r
1607                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
1608                         }\r
1609                 else if ((curRssi > 72)&&(preRssi < 72))\r
1610                         {\r
1611                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
1612                 }\r
1613                 else if ((curRssi < 72)&&( preRssi > 72))\r
1614                         {\r
1615                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;\r
1616                 }\r
1617                 else if (curRssi < 68)           //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode\r
1618                 {\r
1619                                 pRX_HP_Table->Cur_pw_th = pw_th_10dB;\r
1620                                 pRX_HP_Table->RXHP_flag = 0;    // Back to Normal DIG Mode                \r
1621                                 psd_intf_flag = 0;\r
1622                         }\r
1623                 }\r
1624                 else    // pRX_HP_Table->RXHP_flag == 0\r
1625                 {\r
1626                         //1 Decide whether to enter AGC RX High Power Mode\r
1627                         if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) &&  \r
1628                                 (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))\r
1629                         {\r
1630                                 if (curRssi > 80)\r
1631                                 {\r
1632                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;\r
1633                                 }\r
1634                                 else if (curRssi > 72) \r
1635                         {\r
1636                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;\r
1637                                 }\r
1638                                 else\r
1639                                 {\r
1640                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;\r
1641                                 }\r
1642                                 pRX_HP_Table->Cur_pw_th = pw_th_16dB;           //RegC54[9:8]=2'b11: to enter AGC Flow 3\r
1643                                 pRX_HP_Table->First_time_enter = TRUE;\r
1644                                 pRX_HP_Table->RXHP_flag = 1;    //      RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode\r
1645                         }\r
1646                 }\r
1647                 preRssi = curRssi; \r
1648                 odm_Write_RXHP(pDM_Odm);        \r
1649         }\r
1650 #endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
1651 #endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)\r
1652 }\r
1653 \r
1654 \r
1655 VOID\r
1656 odm_PSD_RXHPCallback(\r
1657         PRT_TIMER               pTimer\r
1658 )\r
1659 {\r
1660         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;\r
1661         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1662         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1663         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;\r
1664         \r
1665 #if DEV_BUS_TYPE==RT_PCI_INTERFACE\r
1666         #if USE_WORKITEM\r
1667         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);\r
1668         #else\r
1669         odm_PSD_RXHP(pDM_Odm);\r
1670         #endif\r
1671 #else\r
1672         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);\r
1673 #endif\r
1674         \r
1675         }\r
1676 \r
1677 VOID\r
1678 odm_PSD_RXHPWorkitemCallback(\r
1679     IN PVOID            pContext\r
1680     )\r
1681 {\r
1682         PADAPTER        pAdapter = (PADAPTER)pContext;\r
1683         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1684         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1685         \r
1686         odm_PSD_RXHP(pDM_Odm);\r
1687 }\r
1688 \r
1689 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1690 \r
1691 \r
1692  \r