drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/rtl8723b/halphyrf_8723b_ce.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 #include "mp_precomp.h"\r
  22 #include "../phydm_precomp.h"\r
  23 \r
  24 \r
  25 \r
  26 /*---------------------------Define Local Constant---------------------------*/\r
  27 // 2010/04/25 MH Define the max tx power tracking tx agc power.\r
  28 #define         ODM_TXPWRTRACK_MAX_IDX8723B     6\r
  29 \r
  30 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0]\r
  31 #define         PATH_S0                                                 1 // RF_PATH_B\r
  32 #define         IDX_0xC94                                               0\r
  33 #define         IDX_0xC80                                               1\r
  34 #define         IDX_0xC4C                                               2\r
  35 #define         IDX_0xC14                                               0\r
  36 #define         IDX_0xCA0                                               1\r
  37 #define         KEY                                                     0\r
  38 #define         VAL                                                     1\r
  39 \r
  40 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1]\r
  41 #define         PATH_S1                                                 0 // RF_PATH_A\r
  42 #define         IDX_0xC9C                                               0\r
  43 #define         IDX_0xC88                                               1\r
  44 #define         IDX_0xC4C                                               2\r
  45 #define         IDX_0xC1C                                               0\r
  46 #define         IDX_0xC78                                               1\r
  47 \r
  48 \r
  49 /*---------------------------Define Local Constant---------------------------*/\r
  50 \r
  51 \r
  52 //3============================================================\r
  53 //3 Tx Power Tracking\r
  54 //3============================================================\r
  55 \r
  56 \r
  57 void setIqkMatrix_8723B(\r
  58         PDM_ODM_T       pDM_Odm,\r
  59         u1Byte          OFDM_index,\r
  60         u1Byte          RFPath,\r
  61         s4Byte          IqkResult_X,\r
  62         s4Byte          IqkResult_Y\r
  63         )\r
  64 {\r
  65         s4Byte                  ele_A=0, ele_D, ele_C=0, value32;\r
  66 \r
  67         if (OFDM_index >= OFDM_TABLE_SIZE)\r
  68                 OFDM_index = OFDM_TABLE_SIZE-1;\r
  69 \r
  70         ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;              \r
  71         \r
  72         //new element A = element D x X\r
  73         if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))\r
  74         {\r
  75                 if ((IqkResult_X & 0x00000200) != 0)    //consider minus\r
  76                         IqkResult_X = IqkResult_X | 0xFFFFFC00;\r
  77                 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;\r
  78                         \r
  79                 //new element C = element D x Y\r
  80                 if ((IqkResult_Y & 0x00000200) != 0)\r
  81                         IqkResult_Y = IqkResult_Y | 0xFFFFFC00;\r
  82                 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;\r
  83 \r
  84                 //if (RFPath == ODM_RF_PATH_A)\r
  85                 switch (RFPath)\r
  86                 {\r
  87                 case ODM_RF_PATH_A:\r
  88                         //wirte new elements A, C, D to regC80 and regC94, element B is always 0\r
  89                         value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;\r
  90                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);\r
  91 \r
  92                         value32 = (ele_C&0x000003C0)>>6;\r
  93                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);\r
  94 \r
  95                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
  96                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);                    \r
  97                         break;\r
  98                 case ODM_RF_PATH_B:\r
  99                         //wirte new elements A, C, D to regC88 and regC9C, element B is always 0\r
 100                         value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;\r
 101                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);\r
 102 \r
 103                         value32 = (ele_C&0x000003C0)>>6;\r
 104                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);    \r
 105                         \r
 106                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
 107                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);\r
 108                         \r
 109                         break;                  \r
 110                 default:\r
 111                         break;\r
 112                 }       \r
 113         }\r
 114         else\r
 115         {\r
 116                 switch (RFPath)\r
 117                 {\r
 118                 case ODM_RF_PATH_A:\r
 119                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                              \r
 120                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);\r
 121                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);                       \r
 122                         break;\r
 123 \r
 124                 case ODM_RF_PATH_B:\r
 125                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                                                                              \r
 126                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);       \r
 127                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);                               \r
 128                         break;                  \r
 129 \r
 130                 default:\r
 131                         break;\r
 132                 }               \r
 133         }\r
 134 \r
 135         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", \r
 136         (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));                              \r
 137 }\r
 138 \r
 139 \r
 140 VOID\r
 141 setCCKFilterCoefficient(\r
 142         PDM_ODM_T       pDM_Odm,\r
 143         u1Byte          CCKSwingIndex\r
 144 )\r
 145 {\r
 146         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 147         {\r
 148                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);\r
 149                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);\r
 150                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);\r
 151                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);\r
 152                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);\r
 153                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);\r
 154                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);\r
 155                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);           \r
 156         }\r
 157         else\r
 158         {\r
 159                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);\r
 160                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);\r
 161                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);\r
 162                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);\r
 163                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);\r
 164                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);\r
 165                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);\r
 166                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);       \r
 167         }               \r
 168 }\r
 169 \r
 170 void DoIQK_8723B(\r
 171         PVOID           pDM_VOID,\r
 172         u1Byte          DeltaThermalIndex,\r
 173         u1Byte          ThermalValue,   \r
 174         u1Byte          Threshold\r
 175         )\r
 176 {\r
 177 #if 0 // mark by Lucas@SD4 20140128, suggested by Allen@SD3\r
 178         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 179 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 180         PADAPTER                Adapter = pDM_Odm->Adapter;\r
 181         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 182 #endif\r
 183 \r
 184         ODM_ResetIQKResult(pDM_Odm);            \r
 185 \r
 186 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 187 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 188 #if USE_WORKITEM\r
 189         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 190 #else\r
 191         PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 192 #endif\r
 193 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 194         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 195 #endif\r
 196 #endif                  \r
 197 \r
 198 \r
 199         pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;\r
 200 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 201         PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE);\r
 202 #else\r
 203         PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE);\r
 204 #endif\r
 205         \r
 206 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 207 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 208 #if USE_WORKITEM\r
 209         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 210 #else\r
 211         PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 212 #endif\r
 213 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 214         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 215 #endif\r
 216 #endif\r
 217 #endif // #if 0\r
 218 }\r
 219 \r
 220 /*-----------------------------------------------------------------------------\r
 221  * Function:    odm_TxPwrTrackSetPwr88E()\r
 222  *\r
 223  * Overview:    88E change all channel tx power accordign to flag.\r
 224  *                              OFDM & CCK are all different.\r
 225  *\r
 226  * Input:               NONE\r
 227  *\r
 228  * Output:              NONE\r
 229  *\r
 230  * Return:              NONE\r
 231  *\r
 232  * Revised History:\r
 233  *      When            Who     Remark\r
 234  *      04/23/2012      MHC     Create Version 0.  \r
 235  *\r
 236  *---------------------------------------------------------------------------*/\r
 237 VOID\r
 238 ODM_TxPwrTrackSetPwr_8723B(\r
 239         IN      PVOID           pDM_VOID,\r
 240         PWRTRACK_METHOD         Method,\r
 241         u1Byte                          RFPath,\r
 242         u1Byte                          ChannelMappedIndex\r
 243         )\r
 244 {\r
 245         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 246         PADAPTER        Adapter = pDM_Odm->Adapter;\r
 247         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
 248         u1Byte          PwrTrackingLimit_OFDM = 34; //+0dB\r
 249         u1Byte          PwrTrackingLimit_CCK= 28;       //-2dB\r
 250         u1Byte          TxRate = 0xFF;\r
 251         u1Byte          Final_OFDM_Swing_Index = 0; \r
 252         u1Byte          Final_CCK_Swing_Index = 0; \r
 253         u1Byte          i = 0;\r
 254         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
 255 \r
 256         if (pDM_Odm->mp_mode == TRUE) {\r
 257         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
 258                 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 259                         #if (MP_DRIVER == 1)\r
 260                                         PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);\r
 261                                         \r
 262                                         TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 263                         #endif\r
 264                 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\r
 265                                 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);\r
 266                                 \r
 267                                 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 268                 #endif  \r
 269         #endif\r
 270         } else {\r
 271                 u2Byte  rate     = *(pDM_Odm->pForcedDataRate);\r
 272                 \r
 273                 if (!rate) { /*auto rate*/\r
 274                         if (rate != 0xFF) {\r
 275                         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 276                                                 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);\r
 277                         #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\r
 278                                                 TxRate = HwRateToMRate(pDM_Odm->TxRate);\r
 279                         #endif\r
 280                         }\r
 281                 } else { /*force rate*/\r
 282                         TxRate = (u1Byte)rate;\r
 283                 }\r
 284         }\r
 285                 \r
 286         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));\r
 287         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));\r
 288 \r
 289         if(TxRate != 0xFF)\r
 290         {\r
 291                 //2 CCK\r
 292                 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))\r
 293                         PwrTrackingLimit_CCK = 28;      //-2dB\r
 294                 //2 OFDM\r
 295                 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))\r
 296                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 297                 else if(TxRate == MGN_54M)\r
 298                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 299 \r
 300                 //2 HT\r
 301                 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK\r
 302                         PwrTrackingLimit_OFDM= 38; //+4dB\r
 303                 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM\r
 304                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 305                 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM\r
 306                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 307 \r
 308                 else\r
 309                         PwrTrackingLimit_OFDM =  pRFCalibrateInfo->DefaultOfdmIndex;   /*Default OFDM index = 30*/\r
 310         }\r
 311         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));\r
 312 \r
 313         if (Method == TXAGC) \r
 314         {\r
 315                 u1Byte  rf = 0;\r
 316                 u4Byte  pwr = 0, TxAGC = 0;\r
 317                 PADAPTER Adapter = pDM_Odm->Adapter;\r
 318 \r
 319                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel)));\r
 320 \r
 321                 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];\r
 322 \r
 323 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))\r
 324                 if (pDM_Odm->mp_mode == TRUE)\r
 325                 {\r
 326                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 327                         pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath];\r
 328                         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);\r
 329                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 330                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);\r
 331                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));\r
 332 \r
 333                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 334                         pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]);\r
 335                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 336                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 337                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 338                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 339                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 340                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 341                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 342                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));\r
 343                 }\r
 344                 else            \r
 345                 {\r
 346                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;\r
 347                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 348 \r
 349                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);\r
 350                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);\r
 351                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);\r
 352                 }\r
 353 #endif\r
 354         }\r
 355         else if (Method == BBSWING)\r
 356         {\r
 357                 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];\r
 358                 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; \r
 359 \r
 360                 // Adjust BB swing by OFDM IQ matrix\r
 361                 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)\r
 362                         Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;\r
 363                 else if (Final_OFDM_Swing_Index <= 0)\r
 364                         Final_OFDM_Swing_Index = 0;\r
 365 \r
 366                 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)\r
 367                         Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;\r
 368                 else if (pRFCalibrateInfo->BbSwingIdxCck <= 0)\r
 369                         Final_CCK_Swing_Index = 0;\r
 370 \r
 371                 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, \r
 372                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 373                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);  \r
 374 \r
 375                 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);\r
 376 \r
 377         }\r
 378         else if (Method == MIX_MODE)\r
 379         {\r
 380                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 381                         ("pRFCalibrateInfo->DefaultOfdmIndex=%d,  pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",\r
 382                         pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath));\r
 383 \r
 384                 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];\r
 385                 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];\r
 386 \r
 387                 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM )     //BBSwing higher then Limit\r
 388                 {\r
 389                         pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;\r
 390 \r
 391                         setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, \r
 392                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 393                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 394 \r
 395                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;\r
 396                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 397                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 398 \r
 399                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 400                                 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", \r
 401                                 PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));\r
 402                 }\r
 403                 else if (Final_OFDM_Swing_Index <= 0)\r
 404                 {\r
 405                         pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;\r
 406 \r
 407                         setIqkMatrix_8723B(pDM_Odm, 0, RFPath, \r
 408                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 409                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 410 \r
 411                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;\r
 412                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 413                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 414 \r
 415                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 416                                 ("******Path_A Lower then BBSwing lower bound  0 , Remnant TxAGC Value = %d\n", \r
 417                                 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));\r
 418                 }\r
 419                 else\r
 420                 {\r
 421                         setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, \r
 422                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 423                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);\r
 424 \r
 425                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 426                                 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index));\r
 427 \r
 428                         if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA)  /*If TxAGC has changed, reset TxAGC again*/\r
 429                         {\r
 430                                 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0;\r
 431                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );\r
 432                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 433                                 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE;\r
 434 \r
 435                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 436                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n"));\r
 437                         }\r
 438                 }\r
 439 \r
 440                 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)\r
 441                 {\r
 442                         pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;\r
 443                         setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);\r
 444                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 445                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 446 \r
 447                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 448                                 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx  = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx));\r
 449                 }\r
 450                 else if(Final_CCK_Swing_Index <= 0)       // Lowest CCK Index = 0\r
 451                 {\r
 452                         pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;\r
 453                         setCCKFilterCoefficient(pDM_Odm, 0);\r
 454                         pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 455                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 456 \r
 457                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 458                                 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx  = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx));\r
 459                 }\r
 460                 else\r
 461                 {\r
 462                         setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);\r
 463 \r
 464                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 465                                 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index));\r
 466 \r
 467                         if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK)  /*If TxAGC has changed, reset TxAGC again*/\r
 468                         {\r
 469                                 pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;\r
 470                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );\r
 471                                 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE;\r
 472 \r
 473                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,\r
 474                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n"));\r
 475                         }\r
 476                 }\r
 477         }\r
 478         else\r
 479         {\r
 480                 return; // This method is not supported.\r
 481         }\r
 482 }\r
 483 \r
 484 VOID\r
 485 GetDeltaSwingTable_8723B(\r
 486         IN      PVOID           pDM_VOID,\r
 487         OUT pu1Byte                     *TemperatureUP_A,\r
 488         OUT pu1Byte                     *TemperatureDOWN_A,\r
 489         OUT pu1Byte                     *TemperatureUP_B,\r
 490         OUT pu1Byte                     *TemperatureDOWN_B      \r
 491         )\r
 492 {\r
 493         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 494         PADAPTER                Adapter                  = pDM_Odm->Adapter;\r
 495         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
 496         HAL_DATA_TYPE   *pHalData                = GET_HAL_DATA(Adapter);\r
 497         u1Byte                  TxRate                  = 0xFF;\r
 498         u1Byte                  channel                  = pHalData->CurrentChannel;\r
 499 \r
 500         if (pDM_Odm->mp_mode == TRUE) {\r
 501         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
 502                 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 503                         #if (MP_DRIVER == 1)\r
 504                                         PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);\r
 505                                         \r
 506                                         TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 507                         #endif\r
 508                 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\r
 509                                 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);\r
 510                                 \r
 511                                 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 512                 #endif  \r
 513         #endif\r
 514         } else {\r
 515                 u2Byte  rate     = *(pDM_Odm->pForcedDataRate);\r
 516                 \r
 517                 if (!rate) { /*auto rate*/\r
 518                         if (rate != 0xFF) {\r
 519                         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
 520                                                 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);\r
 521                         #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\r
 522                                                 TxRate = HwRateToMRate(pDM_Odm->TxRate);\r
 523                         #endif\r
 524                         }\r
 525                 } else { /*force rate*/\r
 526                         TxRate = (u1Byte)rate;\r
 527                 }\r
 528         }\r
 529                 \r
 530         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));\r
 531 \r
 532         if ( 1 <= channel && channel <= 14) {\r
 533                 if (IS_CCK_RATE(TxRate)) {\r
 534                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;\r
 535                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;\r
 536                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;\r
 537                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;     \r
 538                 } else {\r
 539                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;\r
 540                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;\r
 541                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;\r
 542                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;                        \r
 543                 }\r
 544         } else {\r
 545                 *TemperatureUP_A   = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 546                 *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;   \r
 547                 *TemperatureUP_B   = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 548                 *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;           \r
 549         }\r
 550         \r
 551         return;\r
 552 }\r
 553 \r
 554 \r
 555 void ConfigureTxpowerTrack_8723B(\r
 556         PTXPWRTRACK_CFG pConfig\r
 557         )\r
 558 {\r
 559         pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;\r
 560         pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;\r
 561         pConfig->Threshold_IQK = IQK_THRESHOLD;\r
 562         pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;\r
 563         pConfig->RfPathCount = MAX_PATH_NUM_8723B;\r
 564         pConfig->ThermalRegAddr = RF_T_METER_8723B;\r
 565                 \r
 566         pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;\r
 567         pConfig->DoIQK = DoIQK_8723B;\r
 568         pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;\r
 569         pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;\r
 570 }\r
 571 \r
 572 //1 7.  IQK\r
 573 #define MAX_TOLERANCE           5\r
 574 #define IQK_DELAY_TIME          1               //ms\r
 575 \r
 576 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 577 phy_PathA_IQK_8723B(\r
 578 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 579         IN PDM_ODM_T            pDM_Odm,\r
 580 #else\r
 581         IN      PADAPTER        pAdapter,\r
 582 #endif\r
 583         IN      BOOLEAN         configPathB,\r
 584         IN      u1Byte          RF_Path\r
 585         )\r
 586 {\r
 587         u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;\r
 588         u1Byte result = 0x00;\r
 589 \r
 590 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 591         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
 592         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 593         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 594         #endif\r
 595         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 596         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 597         #endif\r
 598 #endif  \r
 599 \r
 600 \r
 601         // Save RF Path \r
 602         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
 603 \r
 604         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));\r
 605 \r
 606         //leave IQK mode\r
 607         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 608 \r
 609         //      enable path A PA in TXIQK mode\r
 610         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
 611         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );\r
 612         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );\r
 613         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );\r
 614         //      disable path B PA in TXIQK mode\r
 615 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 );\r
 616 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 );\r
 617 \r
 618         //1 Tx IQK\r
 619         //IQK setting\r
 620         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 621         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 622         //path-A IQK setting\r
 623 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));\r
 624         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 625         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 626         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 627         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 628 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);\r
 629         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);\r
 630         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);\r
 631         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 632         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 633 \r
 634         //LO calibration setting\r
 635 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 636         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);\r
 637 \r
 638         //enter IQK mode\r
 639         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 640 \r
 641         //Ant switch\r
 642         if (configPathB || (RF_Path == 0))\r
 643                 // wifi switch to S1\r
 644                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 645         else\r
 646                 // wifi switch to S0\r
 647                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 648 \r
 649         //GNT_BT = 0\r
 650         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 651 \r
 652         //One shot, path A LOK & IQK\r
 653 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 654         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 655         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 656         \r
 657         // delay x ms\r
 658 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));\r
 659         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 660         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 661 \r
 662         //restore Ant Path\r
 663         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 664         //GNT_BT = 1\r
 665         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 666 \r
 667         //leave IQK mode\r
 668         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 669 \r
 670 \r
 671         // Check failed\r
 672         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 673         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 674         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 675         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));\r
 676         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
 677         //monitor image power before & after IQK\r
 678         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
 679         ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
 680 \r
 681 \r
 682         if(!(regEAC & BIT28) &&         \r
 683                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 684                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
 685                 result |= 0x01;\r
 686 \r
 687         return result;  \r
 688 \r
 689 #if 0\r
 690         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 691                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 692                 (((regEAC & 0x03FF0000)>>16) != 0x36))\r
 693                 result |= 0x02;\r
 694         else\r
 695                 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));\r
 696 #endif  \r
 697         }\r
 698 \r
 699 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 700 phy_PathA_RxIQK8723B(\r
 701 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 702         IN PDM_ODM_T            pDM_Odm,\r
 703 #else\r
 704         IN      PADAPTER        pAdapter,\r
 705 #endif\r
 706         IN      BOOLEAN         configPathB,\r
 707         IN      u1Byte          RF_Path\r
 708         )\r
 709 {\r
 710         u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp, Path_SEL_BB;\r
 711         u1Byte result = 0x00;\r
 712 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 713         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 714         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 715         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 716         #endif\r
 717         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 718         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 719         #endif\r
 720 #endif  \r
 721 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));\r
 722 \r
 723         // Save RF Path \r
 724         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); \r
 725 \r
 726         //leave IQK mode\r
 727         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 728 \r
 729         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n"));\r
 730         //1 Get TXIMR setting\r
 731         //modify RXIQK mode table\r
 732 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));\r
 733         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
 734         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
 735         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);\r
 736         //LNA2 off, PA on for Dcut\r
 737         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);\r
 738 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);  \r
 739         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 740         \r
 741         //IQK setting\r
 742         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 743         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 744 \r
 745         //path-A IQK setting\r
 746         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 747         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 748         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 749         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 750 \r
 751 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);\r
 752         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);\r
 753         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);    \r
 754         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 755         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 756 \r
 757         //LO calibration setting\r
 758 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 759         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
 760 \r
 761         //enter IQK mode\r
 762         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 763 \r
 764         //Ant switch\r
 765         if (configPathB || (RF_Path == 0))\r
 766                 // wifi switch to S1\r
 767                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 768         else\r
 769                 // wifi switch to S0\r
 770                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 771 \r
 772         //GNT_BT = 0\r
 773         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 774 \r
 775         //One shot, path A LOK & IQK\r
 776 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 777         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 778         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 779         \r
 780         // delay x ms\r
 781 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));\r
 782         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 783         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 784 \r
 785         //restore Ant Path\r
 786         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 787         //GNT_BT = 1\r
 788         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 789 \r
 790         //leave IQK mode\r
 791         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 792 \r
 793         // Check failed\r
 794         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 795         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 796         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 797         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));   \r
 798         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
 799         //monitor image power before & after IQK\r
 800         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
 801                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
 802 \r
 803                 if(!(regEAC & BIT28) &&         \r
 804                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 805                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
 806 \r
 807                         result |= 0x01;\r
 808                 else                                                    //if Tx not OK, ignore Rx\r
 809                         return result;  \r
 810 \r
 811 \r
 812         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);  \r
 813         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);\r
 814         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));  \r
 815         \r
 816 \r
 817         //1 RX IQK\r
 818         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n"));\r
 819 \r
 820         //modify RXIQK mode table\r
 821 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));\r
 822         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                      \r
 823         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);                            \r
 824         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
 825         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); \r
 826         //LAN2 on, PA off for Dcut\r
 827         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); \r
 828 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);                             \r
 829         \r
 830         //PA, PAD setting\r
 831         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 );  \r
 832         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f ); \r
 833 \r
 834 \r
 835         //IQK setting\r
 836         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 837 \r
 838         //path-A IQK setting\r
 839         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 840         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 841         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 842         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 843 \r
 844         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);\r
 845 //      ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);\r
 846         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);\r
 847         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 848         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 849 \r
 850         //LO calibration setting\r
 851 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 852         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);\r
 853 \r
 854         //enter IQK mode\r
 855         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
 856 \r
 857         //Ant switch\r
 858         if (configPathB || (RF_Path == 0))\r
 859                 // wifi switch to S1\r
 860                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);\r
 861         else\r
 862                 // wifi switch to S0\r
 863                 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 864 \r
 865         //GNT_BT = 0\r
 866         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 867 \r
 868         //One shot, path A LOK & IQK\r
 869 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 870         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 871         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 872         \r
 873         // delay x ms\r
 874 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 875         //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);\r
 876         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
 877 \r
 878         //restore Ant Path\r
 879         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
 880         //GNT_BT = 1\r
 881         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
 882 \r
 883     //leave IQK mode\r
 884         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 885 \r
 886         // Check failed\r
 887         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 888         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);\r
 889         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
 890         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));\r
 891         //monitor image power before & after IQK\r
 892         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", \r
 893         ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));\r
 894 \r
 895         //      PA/PAD controlled by 0x0\r
 896         //leave IQK mode\r
 897         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
 898         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 );\r
 899 \r
 900         /* Allen 20141201 */\r
 901                 tmp=(regEAC & 0x03FF0000)>>16;\r
 902                 if ((tmp & 0x200)> 0)\r
 903                         tmp = 0x400 - tmp;\r
 904                         \r
 905         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 906                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 907                 (((regEAC & 0x03FF0000)>>16) != 0x36)&&         \r
 908                         (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&\r
 909                         (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&\r
 910                         (tmp < 0x1a))\r
 911                 result |= 0x02;\r
 912         else                                                    //if Tx not OK, ignore Rx\r
 913                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK fail!!\n"));\r
 914         \r
 915 \r
 916         return result;\r
 917 \r
 918 \r
 919 }\r
 920 \r
 921 u1Byte                          //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 922 phy_PathB_IQK_8723B(\r
 923 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 924         IN PDM_ODM_T            pDM_Odm\r
 925 #else\r
 926         IN      PADAPTER        pAdapter\r
 927 #endif\r
 928         )\r
 929 {\r
 930         u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;\r
 931         u1Byte  result = 0x00;\r
 932 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 933         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 934         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 935         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 936         #endif\r
 937         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 938         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 939         #endif\r
 940 #endif  \r
 941         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B IQK!\n"));\r
 942 \r
 943         // Save RF Path\r
 944         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
 945 \r
 946     //leave IQK mode\r
 947         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
 948 \r
 949         //      in TXIQK mode\r
 950 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
 951 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );\r
 952 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );\r
 953 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );\r
 954         //      enable path B PA in TXIQK mode\r
 955         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1);\r
 956         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1);\r
 957 \r
 958 \r
 959 \r
 960         //1 Tx IQK\r
 961         //IQK setting\r
 962         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 963         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 964         //path-A IQK setting\r
 965 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n"));\r
 966         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
 967         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
 968         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 969         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
 970         \r
 971 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114);\r
 972         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);\r
 973         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);\r
 974         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
 975         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
 976 \r
 977         //LO calibration setting\r
 978 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 979         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);\r
 980 \r
 981         //enter IQK mode\r
 982         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);      \r
 983 \r
 984         //switch to path B\r
 985         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
 986 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
 987 \r
 988         //GNT_BT = 0\r
 989         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
 990 \r
 991         //One shot, path B LOK & IQK\r
 992 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
 993         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 994         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 995 \r
 996         // delay x ms\r
 997 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 998         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 999         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
1000 \r
1001         //restore Ant Path\r
1002         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
1003         //GNT_BT = 1\r
1004         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
1005 \r
1006     //leave IQK mode\r
1007         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1008 \r
1009 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord)));\r
1010         \r
1011         \r
1012         // Check failed\r
1013         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
1014         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
1015         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
1016         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
1017         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
1018         //monitor image power before & after IQK\r
1019         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
1020                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
1021 \r
1022         if(!(regEAC & BIT28) &&         \r
1023                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
1024                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
1025                 result |= 0x01;\r
1026 \r
1027         return result;\r
1028 \r
1029 #if 0\r
1030         if(!(regEAC & BIT30) &&\r
1031                 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&\r
1032                 (((regECC & 0x03FF0000)>>16) != 0x36))\r
1033                 result |= 0x02;\r
1034         else\r
1035                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));\r
1036         \r
1037 #endif\r
1038 }\r
1039 \r
1040 \r
1041 \r
1042 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
1043 phy_PathB_RxIQK8723B(\r
1044 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1045         IN PDM_ODM_T            pDM_Odm,\r
1046 #else\r
1047         IN      PADAPTER        pAdapter,\r
1048 #endif\r
1049         IN      BOOLEAN         configPathB\r
1050         )\r
1051 {\r
1052         u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;\r
1053         u1Byte result = 0x00;\r
1054 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1055         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1056         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1057         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1058         #endif\r
1059         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1060         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1061         #endif\r
1062 #endif  \r
1063 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n"));\r
1064 \r
1065         // Save RF Path\r
1066         Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
1067     //leave IQK mode\r
1068         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
1069 \r
1070         //switch to path B\r
1071         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1072 \r
1073         //1 Get TXIMR setting\r
1074         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n"));\r
1075         //modify RXIQK mode table\r
1076 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));\r
1077         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
1078         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
1079         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );\r
1080         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 );\r
1081         //open PA S1 & SMIXER\r
1082         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );\r
1083         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd );\r
1084         \r
1085 \r
1086         //IQK setting\r
1087         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
1088         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
1089 \r
1090 \r
1091         //path-B IQK setting\r
1092         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
1093         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
1094         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1095         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1096 \r
1097 //      ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f );\r
1098         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);\r
1099         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);    \r
1100         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
1101         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
1102 \r
1103         //LO calibration setting\r
1104 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
1105         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
1106 \r
1107     //enter IQK mode\r
1108         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1109 \r
1110         //switch to path B\r
1111         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1112 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
1113 \r
1114         //GNT_BT = 0\r
1115         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
1116 \r
1117         //One shot, path B TXIQK @ RXIQK\r
1118 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
1119         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
1120         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
1121 \r
1122         \r
1123         // delay x ms\r
1124 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
1125         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
1126         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
1127 \r
1128         //restore Ant Path\r
1129         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
1130         //GNT_BT = 1\r
1131         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
1132 \r
1133     //leave IQK mode\r
1134         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1135 \r
1136         // Check failed\r
1137         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
1138         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
1139         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
1140         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
1141         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));\r
1142         //monitor image power before & after IQK\r
1143         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", \r
1144                 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));\r
1145 \r
1146 \r
1147                 if(!(regEAC & BIT28) &&         \r
1148                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
1149                 (((regE9C & 0x03FF0000)>>16) != 0x42))\r
1150                         result |= 0x01;\r
1151                 else                                                    //if Tx not OK, ignore Rx\r
1152                         return result;  \r
1153 \r
1154 \r
1155 \r
1156         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);  \r
1157         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);\r
1158         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));  \r
1159         \r
1160 \r
1161         //1 RX IQK\r
1162         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n"));\r
1163 \r
1164         //modify RXIQK mode table\r
1165         //<20121009, Kordan> RF Mode = 3\r
1166         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1167         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);                             \r
1168         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
1169         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); \r
1170         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); \r
1171 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);   \r
1172 \r
1173         //open PA S1 & close SMIXER\r
1174         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); \r
1175         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd);\r
1176 \r
1177         //PA, PAD setting\r
1178 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);\r
1179 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); \r
1180 \r
1181 \r
1182 \r
1183         //IQK setting\r
1184         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
1185 \r
1186         //path-B IQK setting\r
1187         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);\r
1188         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);\r
1189         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1190         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);\r
1191 \r
1192         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);\r
1193 //      ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);    \r
1194         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);\r
1195         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);\r
1196         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);\r
1197 \r
1198         //LO calibration setting\r
1199 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
1200         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);\r
1201 \r
1202     //enter IQK mode\r
1203         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1204 \r
1205         //switch to path B\r
1206         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);\r
1207 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);\r
1208 \r
1209         //GNT_BT = 0\r
1210         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);\r
1211 \r
1212         //One shot, path B LOK & IQK\r
1213 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));\r
1214         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
1215         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
1216         \r
1217         // delay x ms\r
1218 //      ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
1219         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
1220         ODM_delay_ms(IQK_DELAY_TIME_8723B);\r
1221 \r
1222         //restore Ant Path\r
1223         ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);\r
1224         //GNT_BT = 1\r
1225         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);\r
1226 \r
1227     //leave IQK mode\r
1228         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
1229 \r
1230         // Check failed\r
1231         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
1232         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);;\r
1233 \r
1234         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
1235         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));\r
1236         //monitor image power before & after IQK\r
1237         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", \r
1238                 ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));\r
1239 \r
1240         //      PA/PAD controlled by 0x0\r
1241         //leave IQK mode\r
1242 //      ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x00000000);\r
1243 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 );\r
1244 \r
1245 \r
1246 \r
1247 #if 0   \r
1248         if(!(regEAC & BIT31) &&         \r
1249                 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&\r
1250                 (((regEBC & 0x03FF0000)>>16) != 0x42) )\r
1251                 result |= 0x01;\r
1252         else                                                    //if Tx not OK, ignore Rx\r
1253                 return result;\r
1254 #endif  \r
1255 \r
1256 \r
1257         /* Allen 20141201 */\r
1258                 tmp=(regEAC & 0x03FF0000)>>16;\r
1259                 if ((tmp & 0x200)> 0)\r
1260                         tmp = 0x400 - tmp;\r
1261 \r
1262         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
1263                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
1264                 (((regEAC & 0x03FF0000)>>16) != 0x36) &&        \r
1265                         (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&\r
1266                         (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&\r
1267                         (tmp < 0x1a))\r
1268                         \r
1269                 result |= 0x02;\r
1270         else\r
1271                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));\r
1272         \r
1273 \r
1274         return result;\r
1275 \r
1276 \r
1277 }\r
1278 \r
1279 \r
1280 VOID\r
1281 _PHY_PathAFillIQKMatrix8723B(\r
1282 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1283         IN PDM_ODM_T            pDM_Odm,\r
1284 #else\r
1285         IN      PADAPTER        pAdapter,\r
1286 #endif\r
1287         IN      BOOLEAN         bIQKOK,\r
1288         IN      s4Byte          result[][8],\r
1289         IN      u1Byte          final_candidate,\r
1290         IN      BOOLEAN         bTxOnly\r
1291         )\r
1292 {\r
1293         u4Byte  Oldval_0, X, TX0_A, reg;\r
1294         s4Byte  Y, TX0_C;\r
1295 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1296         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1297         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1298         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1299         #endif\r
1300         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1301         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1302         #endif\r
1303 #endif  \r
1304         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1305 \r
1306         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
1307 \r
1308         if(final_candidate == 0xFF)\r
1309                 return;\r
1310 \r
1311         else if(bIQKOK)\r
1312         {\r
1313                 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
1314 \r
1315                 X = result[final_candidate][0];\r
1316                 if ((X & 0x00000200) != 0)\r
1317                         X = X | 0xFFFFFC00;                     \r
1318                 TX0_A = (X * Oldval_0) >> 8;\r
1319                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));\r
1320                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);\r
1321 \r
1322                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));\r
1323          \r
1324                 Y = result[final_candidate][1];\r
1325                 if ((Y & 0x00000200) != 0)\r
1326                         Y = Y | 0xFFFFFC00;     \r
1327 \r
1328                 //2 Tx IQC\r
1329                 TX0_C = (Y * Oldval_0) >> 8;\r
1330                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));\r
1331                 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));\r
1332                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;\r
1333                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord);\r
1334                 \r
1335                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));\r
1336                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;\r
1337                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord);\r
1338 \r
1339                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));\r
1340                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;\r
1341                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);\r
1342 \r
1343                 if(bTxOnly)\r
1344                 {\r
1345                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n"));\r
1346 \r
1347                         // <20130226, Kordan> Saving RxIQC, otherwise not initialized.\r
1348                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1349                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1350                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1351 //                      pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);\r
1352                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;\r
1353                         return;\r
1354                 }\r
1355 \r
1356                 reg = result[final_candidate][2];\r
1357 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)               \r
1358                 if( RTL_ABS(reg ,0x100) >= 16) \r
1359                         reg = 0x100;\r
1360 #endif\r
1361 \r
1362                 //2 Rx IQC\r
1363                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);\r
1364                 reg = result[final_candidate][3] & 0x3F;\r
1365                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);\r
1366                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1367                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);\r
1368 \r
1369                 reg = (result[final_candidate][3] >> 6) & 0xF;\r
1370                 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);\r
1371                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1372                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1373                 \r
1374         }\r
1375 }\r
1376 \r
1377 VOID\r
1378 _PHY_PathBFillIQKMatrix8723B(\r
1379 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1380         IN PDM_ODM_T            pDM_Odm,\r
1381 #else\r
1382         IN      PADAPTER        pAdapter,\r
1383 #endif\r
1384         IN      BOOLEAN         bIQKOK,\r
1385         IN      s4Byte          result[][8],\r
1386         IN      u1Byte          final_candidate,\r
1387         IN      BOOLEAN         bTxOnly                 //do Tx only\r
1388         )\r
1389 {\r
1390         u4Byte  Oldval_1, X, TX1_A, reg;\r
1391         s4Byte  Y, TX1_C;\r
1392 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1393         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1394         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1395         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1396         #endif\r
1397         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1398         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1399         #endif\r
1400 #endif  \r
1401         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1402 \r
1403         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
1404 \r
1405         if(final_candidate == 0xFF)\r
1406                 return;\r
1407 \r
1408         else if(bIQKOK)\r
1409         {\r
1410                 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
1411 \r
1412                 X = result[final_candidate][4];\r
1413                 if ((X & 0x00000200) != 0)\r
1414                         X = X | 0xFFFFFC00;     \r
1415                 TX1_A = (X * Oldval_1) >> 8;\r
1416                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));\r
1417 \r
1418                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);\r
1419                 \r
1420                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));\r
1421 \r
1422                 Y = result[final_candidate][5];\r
1423                 if ((Y & 0x00000200) != 0)\r
1424                         Y = Y | 0xFFFFFC00;     \r
1425 \r
1426                 TX1_C = (Y * Oldval_1) >> 8;\r
1427                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));\r
1428                 \r
1429                 //2 Tx IQC              \r
1430                 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));\r
1431 //              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE;\r
1432 //              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);\r
1433                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;\r
1434                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);\r
1435 \r
1436                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));\r
1437                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;\r
1438                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord);\r
1439 \r
1440                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));\r
1441                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;\r
1442                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);\r
1443                 \r
1444                 if(bTxOnly) {\r
1445                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n"));\r
1446                         \r
1447                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1448 //                      pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);             \r
1449                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;    \r
1450                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1451                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);\r
1452                         return;\r
1453                 }\r
1454 \r
1455                 //2 Rx IQC\r
1456                 reg = result[final_candidate][6];\r
1457                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);\r
1458                 reg = result[final_candidate][7] & 0x3F;\r
1459                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);\r
1460                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;\r
1461                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord);\r
1462 \r
1463                 reg = (result[final_candidate][7] >> 6) & 0xF;\r
1464 //              ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);\r
1465                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;\r
1466                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(ODM_GetBBReg(pDM_Odm,rOFDM0_RxIQExtAnta, bMaskDWord)& 0x0fffffff);                \r
1467         }\r
1468 }\r
1469 \r
1470 //\r
1471 // 2011/07/26 MH Add an API for testing IQK fail case.\r
1472 //\r
1473 // MP Already declare in odm.c \r
1474 \r
1475 VOID\r
1476 ODM_SetIQCbyRFpath(\r
1477         IN PDM_ODM_T            pDM_Odm,\r
1478     IN u4Byte RFpath\r
1479         )\r
1480 {\r
1481 \r
1482   PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
1483 \r
1484   if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)&&\r
1485         (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0))\r
1486   {\r
1487         if(RFpath) //S1: RFpath = 0, S0:RFpath = 1\r
1488         {\r
1489           //S0 TX IQC\r
1490       ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);\r
1491           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);\r
1492           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);\r
1493       //S0 RX IQC\r
1494           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);\r
1495           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);\r
1496     }\r
1497     else\r
1498     {\r
1499           //S1 TX IQC\r
1500           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);\r
1501           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);\r
1502           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);\r
1503           //S1 RX IQC\r
1504           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);\r
1505           ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);\r
1506     }\r
1507   }     \r
1508 }\r
1509 \r
1510 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) \r
1511 BOOLEAN\r
1512 ODM_CheckPowerStatus(\r
1513         IN      PADAPTER                Adapter)\r
1514 {\r
1515 /*\r
1516         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
1517         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;\r
1518         RT_RF_POWER_STATE       rtState;\r
1519         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);\r
1520 \r
1521         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.\r
1522         if (pMgntInfo->init_adpt_in_progress == TRUE)\r
1523         {\r
1524                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));\r
1525                 return  TRUE;\r
1526         }\r
1527         \r
1528         //\r
1529         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.\r
1530         //\r
1531         rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));\r
1532         if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)\r
1533         {\r
1534                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s/%d/%d\n", \r
1535                 rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));\r
1536                 return  FALSE;\r
1537         }\r
1538 */\r
1539         return  TRUE;\r
1540 }\r
1541 #endif\r
1542 \r
1543 VOID\r
1544 _PHY_SaveADDARegisters8723B(\r
1545 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1546         IN PDM_ODM_T            pDM_Odm,\r
1547 #else\r
1548         IN      PADAPTER        pAdapter,\r
1549 #endif\r
1550         IN      pu4Byte         ADDAReg,\r
1551         IN      pu4Byte         ADDABackup,\r
1552         IN      u4Byte          RegisterNum\r
1553         )\r
1554 {\r
1555         u4Byte  i;\r
1556 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1557         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1558         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1559         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1560         #endif\r
1561         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1562         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1563         #endif\r
1564         \r
1565         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
1566                 return;\r
1567 #endif\r
1568         \r
1569         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));\r
1570         for( i = 0 ; i < RegisterNum ; i++){\r
1571                 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);\r
1572         }\r
1573 }\r
1574 \r
1575 \r
1576 VOID\r
1577 _PHY_SaveMACRegisters8723B(\r
1578 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1579         IN PDM_ODM_T            pDM_Odm,\r
1580 #else\r
1581         IN      PADAPTER        pAdapter,\r
1582 #endif\r
1583         IN      pu4Byte         MACReg,\r
1584         IN      pu4Byte         MACBackup\r
1585         )\r
1586 {\r
1587         u4Byte  i;\r
1588 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1589         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1590         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1591         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1592         #endif\r
1593         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1594         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1595         #endif\r
1596 #endif  \r
1597         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));\r
1598         for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1599                 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);               \r
1600         }\r
1601         MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);               \r
1602 \r
1603 }\r
1604 \r
1605 \r
1606 VOID\r
1607 _PHY_ReloadADDARegisters8723B(\r
1608 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1609         IN PDM_ODM_T            pDM_Odm,\r
1610 #else\r
1611         IN      PADAPTER        pAdapter,\r
1612 #endif\r
1613         IN      pu4Byte         ADDAReg,\r
1614         IN      pu4Byte         ADDABackup,\r
1615         IN      u4Byte          RegiesterNum\r
1616         )\r
1617 {\r
1618         u4Byte  i;\r
1619 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1620         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1621         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1622         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1623         #endif\r
1624         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1625         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1626         #endif\r
1627 #endif\r
1628         \r
1629         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));\r
1630         for(i = 0 ; i < RegiesterNum; i++)\r
1631         {\r
1632                 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);\r
1633         }\r
1634 }\r
1635 \r
1636 VOID\r
1637 _PHY_ReloadMACRegisters8723B(\r
1638 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1639         IN PDM_ODM_T            pDM_Odm,\r
1640 #else\r
1641         IN      PADAPTER        pAdapter,\r
1642 #endif\r
1643         IN      pu4Byte         MACReg,\r
1644         IN      pu4Byte         MACBackup\r
1645         )\r
1646 {\r
1647         u4Byte  i;\r
1648 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1649         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1650         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1651         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1652         #endif\r
1653         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1654         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1655         #endif\r
1656 #endif\r
1657         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Reload MAC parameters !\n"));\r
1658         for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1659                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);\r
1660         }\r
1661         ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);       \r
1662 }\r
1663 \r
1664 \r
1665 VOID\r
1666 _PHY_PathADDAOn8723B(\r
1667 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1668         IN PDM_ODM_T            pDM_Odm,\r
1669 #else\r
1670         IN      PADAPTER        pAdapter,\r
1671 #endif\r
1672         IN      pu4Byte         ADDAReg,\r
1673         IN      BOOLEAN         isPathAOn,\r
1674         IN      BOOLEAN         is2T\r
1675         )\r
1676 {\r
1677         u4Byte  pathOn;\r
1678         u4Byte  i;\r
1679 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1680         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1681         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1682         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1683         #endif\r
1684         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1685         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1686         #endif\r
1687 #endif\r
1688         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));\r
1689 \r
1690         pathOn = isPathAOn ? 0x01c00014 : 0x01c00014;\r
1691         if(FALSE == is2T){\r
1692                 pathOn = 0x01c00014;\r
1693                 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014);\r
1694         }\r
1695         else{\r
1696                 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);\r
1697         }\r
1698         \r
1699         for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){\r
1700                 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);\r
1701         }\r
1702         \r
1703 }\r
1704 \r
1705 VOID\r
1706 _PHY_MACSettingCalibration8723B(\r
1707 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1708         IN PDM_ODM_T            pDM_Odm,\r
1709 #else\r
1710         IN      PADAPTER        pAdapter,\r
1711 #endif\r
1712         IN      pu4Byte         MACReg,\r
1713         IN      pu4Byte         MACBackup       \r
1714         )\r
1715 {\r
1716         u4Byte  i = 0;\r
1717 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1718         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1719         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1720         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1721         #endif\r
1722         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1723         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1724         #endif\r
1725 #endif  \r
1726         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));\r
1727 \r
1728         ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);\r
1729 \r
1730         for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1731                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));\r
1732         }\r
1733         ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); \r
1734 \r
1735 }\r
1736 \r
1737 VOID\r
1738 _PHY_PathAStandBy8723B(\r
1739 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1740         IN PDM_ODM_T            pDM_Odm\r
1741 #else\r
1742         IN PADAPTER pAdapter\r
1743 #endif\r
1744         )\r
1745 {\r
1746 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1747         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1748         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1749         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1750         #endif\r
1751         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1752         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1753         #endif\r
1754 #endif  \r
1755         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path-A standby mode!\n"));\r
1756 \r
1757         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0);\r
1758 //Allen\r
1759         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);\r
1760         //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);\r
1761 //\r
1762         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);\r
1763 }\r
1764 \r
1765 VOID\r
1766 _PHY_PIModeSwitch8723B(\r
1767 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1768         IN PDM_ODM_T            pDM_Odm,\r
1769 #else\r
1770         IN      PADAPTER        pAdapter,\r
1771 #endif\r
1772         IN      BOOLEAN         PIMode\r
1773         )\r
1774 {\r
1775         u4Byte  mode;\r
1776 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1777         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1778         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1779         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1780         #endif\r
1781         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1782         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1783         #endif\r
1784 #endif  \r
1785         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));\r
1786 \r
1787         mode = PIMode ? 0x01000100 : 0x01000000;\r
1788         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);\r
1789         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);\r
1790 }\r
1791 \r
1792 BOOLEAN                                                 \r
1793 phy_SimularityCompare_8723B(\r
1794 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1795         IN PDM_ODM_T            pDM_Odm,\r
1796 #else\r
1797         IN      PADAPTER        pAdapter,\r
1798 #endif\r
1799         IN      s4Byte          result[][8],\r
1800         IN      u1Byte           c1,\r
1801         IN      u1Byte           c2\r
1802         )\r
1803 {\r
1804         u4Byte          i, j, diff, SimularityBitMap, bound = 0;\r
1805 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1806         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
1807         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1808         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1809         #endif\r
1810         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1811         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1812         #endif\r
1813 #endif  \r
1814         u1Byte          final_candidate[2] = {0xFF, 0xFF};      //for path A and path B\r
1815         BOOLEAN         bResult = TRUE;\r
1816 //#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1817 //      BOOLEAN         is2T = IS_92C_SERIAL( pHalData->VersionID);\r
1818 //#else\r
1819         BOOLEAN         is2T = TRUE;\r
1820 //#endif\r
1821 \r
1822         s4Byte tmp1 = 0,tmp2 = 0;\r
1823         \r
1824         if(is2T)\r
1825                 bound = 8;\r
1826         else\r
1827                 bound = 4;\r
1828 \r
1829         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2));\r
1830 \r
1831 \r
1832         SimularityBitMap = 0;\r
1833         \r
1834         for( i = 0; i < bound; i++ )\r
1835         {\r
1836                 \r
1837                 if((i==1) || (i==3) || (i==5) || (i==7))\r
1838                 {\r
1839                         if((result[c1][i]& 0x00000200) != 0)\r
1840                                 tmp1 = result[c1][i] | 0xFFFFFC00; \r
1841                         else\r
1842                                 tmp1 = result[c1][i];\r
1843 \r
1844                         if((result[c2][i]& 0x00000200) != 0)\r
1845                                 tmp2 = result[c2][i] | 0xFFFFFC00; \r
1846                         else\r
1847                                 tmp2 = result[c2][i];\r
1848                 }\r
1849                 else\r
1850                 {\r
1851                         tmp1 = result[c1][i];   \r
1852                         tmp2 = result[c2][i];\r
1853                 }\r
1854                 \r
1855                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);\r
1856                 \r
1857                 if (diff > MAX_TOLERANCE)\r
1858                 {\r
1859                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",      diff, i, result[c1][i], result[c2][i]));\r
1860                 \r
1861                         if((i == 2 || i == 6) && !SimularityBitMap)\r
1862                         {\r
1863                                 if(result[c1][i]+result[c1][i+1] == 0)\r
1864                                         final_candidate[(i/4)] = c2;\r
1865                                 else if (result[c2][i]+result[c2][i+1] == 0)\r
1866                                         final_candidate[(i/4)] = c1;\r
1867                                 else\r
1868                                         SimularityBitMap = SimularityBitMap|(1<<i);                             \r
1869                         }\r
1870                         else\r
1871                                 SimularityBitMap = SimularityBitMap|(1<<i);\r
1872                 }\r
1873         }\r
1874         \r
1875         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap   %x !!!\n", SimularityBitMap));\r
1876         \r
1877         if ( SimularityBitMap == 0)\r
1878         {\r
1879                 for( i = 0; i < (bound/4); i++ )\r
1880                 {\r
1881                         if(final_candidate[i] != 0xFF)\r
1882                         {\r
1883                                 for( j = i*4; j < (i+1)*4-2; j++)\r
1884                                         result[3][j] = result[final_candidate[i]][j];\r
1885                                 bResult = FALSE;\r
1886                         }\r
1887                 }\r
1888                 return bResult;\r
1889         }\r
1890         else \r
1891         {\r
1892 \r
1893         if (!(SimularityBitMap & 0x03))                 //path A TX OK\r
1894         {\r
1895                 for(i = 0; i < 2; i++)\r
1896                         result[3][i] = result[c1][i];\r
1897         }\r
1898 \r
1899         if (!(SimularityBitMap & 0x0c))                 //path A RX OK\r
1900         {\r
1901                 for(i = 2; i < 4; i++)\r
1902                         result[3][i] = result[c1][i];\r
1903         }\r
1904 \r
1905         if (!(SimularityBitMap & 0x30)) //path B TX OK\r
1906         {\r
1907                 for(i = 4; i < 6; i++)\r
1908                         result[3][i] = result[c1][i];\r
1909 \r
1910         }\r
1911 \r
1912         if (!(SimularityBitMap & 0xc0)) //path B RX OK\r
1913         {\r
1914                 for(i = 6; i < 8; i++)\r
1915                         result[3][i] = result[c1][i];\r
1916         }\r
1917                         return FALSE;\r
1918         }       \r
1919 }\r
1920 \r
1921 \r
1922 \r
1923 VOID    \r
1924 phy_IQCalibrate_8723B(\r
1925 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1926         IN PDM_ODM_T            pDM_Odm,\r
1927 #else\r
1928         IN      PADAPTER        pAdapter,\r
1929 #endif\r
1930         IN      s4Byte          result[][8],\r
1931         IN      u1Byte          t,\r
1932         IN      BOOLEAN         is2T,\r
1933         IN      u1Byte          RF_Path\r
1934         )\r
1935 {\r
1936 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1937         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
1938         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1939         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1940         #endif\r
1941         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1942         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1943         #endif\r
1944 #endif  \r
1945         u4Byte                  i;\r
1946         u1Byte                  PathAOK, PathBOK;\r
1947         u1Byte                  tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0);\r
1948         u1Byte                  tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0);    \r
1949         u4Byte                  ADDA_REG[IQK_ADDA_REG_NUM] = {  \r
1950                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
1951                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
1952                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
1953                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
1954                                                 rTx_To_Tx,              rRx_CCK,        \r
1955                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
1956                                                 rRx_TO_Rx,              rStandby,       \r
1957                                                 rSleep,                         rPMPD_ANAEN };\r
1958         u4Byte                  IQK_MAC_REG[IQK_MAC_REG_NUM] = {\r
1959                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
1960                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
1961                                         \r
1962         //since 92C & 92D have the different define in IQK_BB_REG       \r
1963         u4Byte  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
1964                                                         rOFDM0_TRxPathEnable,           rOFDM0_TRMuxPar,        \r
1965                                                         rFPGA0_XCD_RFInterfaceSW,       rConfig_AntA,   rConfig_AntB,\r
1966                                                         rFPGA0_XAB_RFInterfaceSW,       rFPGA0_XA_RFInterfaceOE,        \r
1967                                                         rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting       \r
1968                                                         };      \r
1969 \r
1970         u4Byte Path_SEL_BB;\r
1971 //        u4Byte Path_SEL_BB, Path_SEL_RF;\r
1972 \r
1973 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
1974         u4Byte  retryCount = 2;\r
1975 #else\r
1976 #if MP_DRIVER\r
1977         const u4Byte    retryCount = 1;\r
1978 #else\r
1979         const u4Byte    retryCount = 2;\r
1980 #endif\r
1981 #endif\r
1982 \r
1983 if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )\r
1984 {\r
1985                 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);\r
1986                 return;\r
1987 }\r
1988 \r
1989         // Note: IQ calibration must be performed after loading \r
1990         //              PHY_REG.txt , and radio_a, radio_b.txt  \r
1991         \r
1992         //u4Byte bbvalue;\r
1993 \r
1994 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
1995 #ifdef MP_TEST\r
1996                 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)\r
1997                         retryCount = 9; \r
1998 #endif\r
1999 #endif\r
2000 \r
2001 \r
2002         if(t==0)\r
2003         {\r
2004 //               bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);\r
2005 //                      RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));\r
2006 \r
2007                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
2008         \r
2009                 // Save ADDA parameters, turn Path A ADDA on\r
2010 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2011                 _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2012                 _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2013                 _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);                          \r
2014 #else\r
2015                 _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2016                 _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2017                 _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);           \r
2018 #endif\r
2019         }\r
2020         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
2021         \r
2022 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2023         \r
2024         _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T);\r
2025 #else\r
2026         _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T);\r
2027 #endif\r
2028                 \r
2029 //no serial mode\r
2030 #if 0   \r
2031         if(t==0)\r
2032         {\r
2033                 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));\r
2034         }\r
2035         \r
2036         if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
2037                 // Switch BB to PI mode to do IQ Calibration.\r
2038 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2039                 _PHY_PIModeSwitch8723B(pAdapter, TRUE);\r
2040 #else\r
2041                 _PHY_PIModeSwitch8723B(pDM_Odm, TRUE);\r
2042 #endif\r
2043         }\r
2044 #endif\r
2045 \r
2046         //save RF path for 8723B\r
2047 //      Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
2048 //      Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);\r
2049         \r
2050         //MAC settings\r
2051 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2052         _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2053 #else\r
2054         _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2055 #endif\r
2056         \r
2057         //BB setting\r
2058         //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);     \r
2059         ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);       \r
2060         ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);\r
2061         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);\r
2062         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);\r
2063 \r
2064         \r
2065 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);\r
2066 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);   \r
2067 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);\r
2068 //      ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);    \r
2069         \r
2070 \r
2071 //for 8723B\r
2072 #if 0\r
2073         if(is2T)\r
2074         {\r
2075 \r
2076                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);\r
2077         }\r
2078 #endif\r
2079 \r
2080         \r
2081 //no APK\r
2082 #if 0\r
2083         //Page B init\r
2084         //AP or IQK\r
2085         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);\r
2086         \r
2087         if(is2T)\r
2088         {\r
2089                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);\r
2090         }\r
2091 #endif\r
2092 \r
2093 //RX IQ calibration setting for 8723B D cut large current issue when leaving IPS\r
2094 \r
2095         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);       \r
2096         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);\r
2097     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);\r
2098     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);\r
2099     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);\r
2100     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); \r
2101     ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); \r
2102 /*\r
2103 //LOK RF setting\r
2104         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1);\r
2105         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1);\r
2106         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032);\r
2107         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); \r
2108 */\r
2109 \r
2110 \r
2111 //path A TX IQK\r
2112 #if 1\r
2113 \r
2114         for(i = 0 ; i < retryCount ; i++){\r
2115 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2116                 PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path);\r
2117 #else\r
2118                 PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path);\r
2119 #endif\r
2120 //              if(PathAOK == 0x03){\r
2121                 if(PathAOK == 0x01){\r
2122                         // Path A Tx IQK Success\r
2123                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2124                         pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask);\r
2125 \r
2126                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));\r
2127                                 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2128                                 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2129                         break;\r
2130                 }\r
2131 #if 0           \r
2132                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK\r
2133                 {\r
2134                         RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only      Tx Success!!\n"));\r
2135                         \r
2136                         result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2137                         result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;                        \r
2138                 }\r
2139 #endif          \r
2140         }\r
2141 #endif\r
2142 \r
2143 //path A RXIQK\r
2144 #if 1\r
2145 \r
2146         for(i = 0 ; i < retryCount ; i++){\r
2147 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2148                 PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path);\r
2149 #else\r
2150                 PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path);\r
2151 #endif\r
2152                 if(PathAOK == 0x03){\r
2153                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK Success!!\n"));\r
2154 //                              result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2155 //                              result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2156                                 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2157                                 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2158                         break;\r
2159                 }\r
2160                 else\r
2161                 {\r
2162                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));           \r
2163                 }\r
2164         }\r
2165 \r
2166         if(0x00 == PathAOK){            \r
2167                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));            \r
2168         }\r
2169 #endif\r
2170 \r
2171 //path B IQK\r
2172 #if 1\r
2173 \r
2174         if(is2T){\r
2175 \r
2176 /*\r
2177 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2178 //              _PHY_PathAStandBy8723B(pAdapter);\r
2179 \r
2180                 // Turn Path B ADDA on\r
2181                 _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T);\r
2182 #else\r
2183 //              _PHY_PathAStandBy8723B(pDM_Odm);\r
2184 \r
2185                 // Turn Path B ADDA on\r
2186                 _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T);\r
2187 #endif\r
2188 */\r
2189 \r
2190 //path B TX IQK\r
2191 #if 1\r
2192                 for(i = 0 ; i < retryCount ; i++){\r
2193 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2194                         PathBOK = phy_PathB_IQK_8723B(pAdapter);\r
2195 #else\r
2196                         PathBOK = phy_PathB_IQK_8723B(pDM_Odm);\r
2197 #endif\r
2198 //              if(PathBOK == 0x03){\r
2199                 if(PathBOK == 0x01){\r
2200                         // Path B Tx IQK Success\r
2201                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2202                         pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask);\r
2203 \r
2204                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n"));\r
2205                                 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2206                                 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2207                         break;\r
2208                 }\r
2209 #if 0           \r
2210                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK\r
2211                 {\r
2212                         RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only      Tx Success!!\n"));\r
2213                         \r
2214                         result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;\r
2215                         result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;                        \r
2216                 }\r
2217 #endif          \r
2218         }\r
2219 #endif\r
2220 \r
2221 //path B RX IQK\r
2222 #if 1\r
2223 \r
2224 for(i = 0 ; i < retryCount ; i++){\r
2225 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2226                 PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T);\r
2227 #else\r
2228                 PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T);\r
2229 #endif\r
2230                 if(PathBOK == 0x03){\r
2231                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK Success!!\n"));\r
2232 //                              result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2233 //                              result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
2234                                 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2235                                 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
2236                         break;\r
2237                 }\r
2238                 else\r
2239                 {\r
2240                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n"));           \r
2241                 }\r
2242         }\r
2243 \r
2244 #endif\r
2245 \r
2246 ////////Allen end ///////// \r
2247                 if(0x00 == PathBOK){            \r
2248                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));            \r
2249                 }\r
2250         }\r
2251 #endif  //pathB IQK\r
2252 \r
2253         //Back to BB mode, load original value\r
2254         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));\r
2255         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);\r
2256 \r
2257         if(t!=0)\r
2258         {\r
2259                 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
2260                         // Switch back BB to SI mode after finish IQ Calibration.\r
2261 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2262 //                      _PHY_PIModeSwitch8723B(pAdapter, FALSE);\r
2263 #else\r
2264 //                      _PHY_PIModeSwitch8723B(pDM_Odm, FALSE);\r
2265 #endif\r
2266                 }\r
2267 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2268 \r
2269                 // Reload ADDA power saving parameters\r
2270                 _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2271 \r
2272                 // Reload MAC parameters\r
2273                 _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2274                 \r
2275                 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
2276 #else\r
2277                 // Reload ADDA power saving parameters\r
2278                 _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
2279 \r
2280                 // Reload MAC parameters\r
2281                 _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
2282                 \r
2283                 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
2284 #endif\r
2285 \r
2286 \r
2287                 //Reload RF path\r
2288 //              ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);\r
2289 //              ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);\r
2290         \r
2291                 //Allen initial gain 0xc50\r
2292                 // Restore RX initial gain\r
2293                 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50);\r
2294                 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50);\r
2295                 if(is2T){\r
2296                         ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50);\r
2297                         ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58);\r
2298                 }\r
2299         \r
2300                 //load 0xe30 IQC default value\r
2301                 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
2302                 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                          \r
2303                 \r
2304         }\r
2305         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n"));\r
2306         \r
2307 }\r
2308 \r
2309 \r
2310 VOID    \r
2311 phy_LCCalibrate_8723B(\r
2312         IN PDM_ODM_T            pDM_Odm,\r
2313         IN      BOOLEAN         is2T\r
2314         )\r
2315 {\r
2316         u1Byte  tmpReg;\r
2317         u4Byte  RF_Amode=0, RF_Bmode=0, LC_Cal;\r
2318 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2319                 PADAPTER pAdapter = pDM_Odm->Adapter;\r
2320 #endif  \r
2321         if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )\r
2322         {\r
2323                 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);\r
2324                 return;\r
2325         }\r
2326 \r
2327         //Check continuous TX and Packet TX\r
2328         tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);\r
2329 \r
2330         if((tmpReg&0x70) != 0)                  //Deal with contisuous TX case\r
2331                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F);    //disable all continuous TX\r
2332         else                                                    // Deal with Packet TX case\r
2333                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);             // block all queues\r
2334 \r
2335         if((tmpReg&0x70) != 0)\r
2336         {\r
2337                 //1. Read original RF mode\r
2338                 //Path-A\r
2339 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2340                 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
2341 \r
2342                 //Path-B\r
2343                 if(is2T)\r
2344                         RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); \r
2345 #else\r
2346                 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
2347 \r
2348                 //Path-B\r
2349                 if(is2T)\r
2350                         RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);    \r
2351 #endif  \r
2352 \r
2353                 //2. Set RF mode = standby mode\r
2354                 //Path-A\r
2355                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);\r
2356 \r
2357                 //Path-B\r
2358                 if(is2T)\r
2359                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);                   \r
2360         }\r
2361         \r
2362         //3. Read RF reg18\r
2363 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2364         LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
2365 #else\r
2366         LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
2367 #endif  \r
2368         \r
2369         //4. Set LC calibration begin   bit15\r
2370         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON\r
2371         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);\r
2372 \r
2373         ODM_delay_ms(100);              \r
2374 \r
2375         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF\r
2376 \r
2377         // Channel 10 LC calibration issue for 8723bs with 26M xtal\r
2378         if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2)\r
2379         {\r
2380                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);\r
2381         }\r
2382 \r
2383         //Restore original situation\r
2384         if((tmpReg&0x70) != 0)  //Deal with contisuous TX case \r
2385         {  \r
2386                 //Path-A\r
2387                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);\r
2388                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);\r
2389                 \r
2390                 //Path-B\r
2391                 if(is2T)\r
2392                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);\r
2393         }\r
2394         else // Deal with Packet TX case\r
2395         {\r
2396                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); \r
2397         }\r
2398 }\r
2399 \r
2400 //Analog Pre-distortion calibration\r
2401 #define         APK_BB_REG_NUM  8\r
2402 #define         APK_CURVE_REG_NUM 4\r
2403 #define         PATH_NUM                2\r
2404 \r
2405 VOID    \r
2406 phy_APCalibrate_8723B(\r
2407 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2408         IN PDM_ODM_T            pDM_Odm,\r
2409 #else\r
2410         IN      PADAPTER        pAdapter,\r
2411 #endif\r
2412         IN      s1Byte          delta,\r
2413         IN      BOOLEAN         is2T\r
2414         )\r
2415 {\r
2416 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2417         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2418         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2419         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
2420         #endif\r
2421         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2422         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
2423         #endif\r
2424 #endif\r
2425         u4Byte                  regD[PATH_NUM];\r
2426         u4Byte                  tmpReg, index, offset,  apkbound;\r
2427         u1Byte                  path, i, pathbound = PATH_NUM;          \r
2428         u4Byte                  BB_backup[APK_BB_REG_NUM];\r
2429         u4Byte                  BB_REG[APK_BB_REG_NUM] = {      \r
2430                                                 rFPGA1_TxBlock,         rOFDM0_TRxPathEnable, \r
2431                                                 rFPGA0_RFMOD,   rOFDM0_TRMuxPar, \r
2432                                                 rFPGA0_XCD_RFInterfaceSW,       rFPGA0_XAB_RFInterfaceSW, \r
2433                                                 rFPGA0_XA_RFInterfaceOE,        rFPGA0_XB_RFInterfaceOE };\r
2434         u4Byte                  BB_AP_MODE[APK_BB_REG_NUM] = {  \r
2435                                                 0x00000020, 0x00a05430, 0x02040000, \r
2436                                                 0x000800e4, 0x00204000 };\r
2437         u4Byte                  BB_normal_AP_MODE[APK_BB_REG_NUM] = {   \r
2438                                                 0x00000020, 0x00a05430, 0x02040000, \r
2439                                                 0x000800e4, 0x22204000 };                                               \r
2440 \r
2441         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
2442         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
2443                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
2444                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
2445                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
2446                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
2447                                                 rTx_To_Tx,              rRx_CCK,        \r
2448                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
2449                                                 rRx_TO_Rx,              rStandby,       \r
2450                                                 rSleep,                         rPMPD_ANAEN };\r
2451 \r
2452         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
2453         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
2454                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
2455                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
2456 \r
2457         u4Byte                  APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
2458                                         {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},\r
2459                                         {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}\r
2460                                         };      \r
2461 \r
2462         u4Byte                  APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
2463                                         {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},  //path settings equal to path b settings\r
2464                                         {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}\r
2465                                         };\r
2466         \r
2467         u4Byte                  APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
2468                                         {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},\r
2469                                         {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}\r
2470                                         };\r
2471 \r
2472         u4Byte                  APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
2473                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},  //path settings equal to path b settings\r
2474                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}\r
2475                                         };\r
2476 \r
2477         u4Byte                  AFE_on_off[PATH_NUM] = {\r
2478                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
2479 \r
2480         u4Byte                  APK_offset[PATH_NUM] = {\r
2481                                         rConfig_AntA, rConfig_AntB};\r
2482 \r
2483         u4Byte                  APK_normal_offset[PATH_NUM] = {\r
2484                                         rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};\r
2485                                         \r
2486         u4Byte                  APK_value[PATH_NUM] = {\r
2487                                         0x92fc0000, 0x12fc0000};                                        \r
2488 \r
2489         u4Byte                  APK_normal_value[PATH_NUM] = {\r
2490                                         0x92680000, 0x12680000};                                        \r
2491 \r
2492         s1Byte                  APK_delta_mapping[APK_BB_REG_NUM][13] = {\r
2493                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2494                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},                                                                                  \r
2495                                         {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2496                                         {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
2497                                         {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}\r
2498                                         };\r
2499         \r
2500         u4Byte                  APK_normal_setting_value_1[13] = {\r
2501                                         0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,\r
2502                                         0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,\r
2503                                         0x12680000, 0x00880000, 0x00880000\r
2504                                         };\r
2505 \r
2506         u4Byte                  APK_normal_setting_value_2[16] = {\r
2507                                         0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,\r
2508                                         0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,\r
2509                                         0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,\r
2510                                         0x00050006\r
2511                                         };\r
2512         \r
2513         u4Byte                  APK_result[PATH_NUM][APK_BB_REG_NUM];   //val_1_1a, val_1_2a, val_2a, val_3a, val_4a\r
2514 //      u4Byte                  AP_curve[PATH_NUM][APK_CURVE_REG_NUM];\r
2515 \r
2516         s4Byte                  BB_offset, delta_V, delta_offset;\r
2517 \r
2518 #if MP_DRIVER == 1\r
2519 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2520         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);   \r
2521 #else\r
2522         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2523 #endif\r
2524         pMptCtx->APK_bound[0] = 45;\r
2525         pMptCtx->APK_bound[1] = 52;     \r
2526 \r
2527 #endif\r
2528 \r
2529         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));\r
2530         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));\r
2531         if(!is2T)\r
2532                 pathbound = 1;\r
2533 \r
2534         //2 FOR NORMAL CHIP SETTINGS\r
2535 \r
2536 // Temporarily do not allow normal driver to do the following settings because these offset\r
2537 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal\r
2538 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the\r
2539 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.\r
2540 #if MP_DRIVER != 1\r
2541         return;\r
2542 #endif\r
2543         //settings adjust for normal chip\r
2544         for(index = 0; index < PATH_NUM; index ++)\r
2545         {\r
2546                 APK_offset[index] = APK_normal_offset[index];\r
2547                 APK_value[index] = APK_normal_value[index];\r
2548                 AFE_on_off[index] = 0x6fdb25a4;\r
2549         }\r
2550 \r
2551         for(index = 0; index < APK_BB_REG_NUM; index ++)\r
2552         {\r
2553                 for(path = 0; path < pathbound; path++)\r
2554                 {\r
2555                         APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];\r
2556                         APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];\r
2557                 }\r
2558                 BB_AP_MODE[index] = BB_normal_AP_MODE[index];\r
2559         }                       \r
2560 \r
2561         apkbound = 6;\r
2562         \r
2563         //save BB default value\r
2564         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2565         {\r
2566                 if(index == 0)          //skip \r
2567                         continue;                               \r
2568                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
2569         }\r
2570         \r
2571         //save MAC default value                                                                                                        \r
2572 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2573         _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
2574         \r
2575         //save AFE default value\r
2576         _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2577 #else\r
2578         _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2579         \r
2580         //save AFE default value\r
2581         _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2582 #endif\r
2583 \r
2584         for(path = 0; path < pathbound; path++)\r
2585         {\r
2586 \r
2587 \r
2588                 if(path == ODM_RF_PATH_A)\r
2589                 {\r
2590                         //path A APK\r
2591                         //load APK setting\r
2592                         //path-A                \r
2593                         offset = rPdp_AntA;\r
2594                         for(index = 0; index < 11; index ++)                    \r
2595                         {\r
2596                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2597                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2598                                 \r
2599                                 offset += 0x04;\r
2600                         }\r
2601                         \r
2602                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2603                         \r
2604                         offset = rConfig_AntA;\r
2605                         for(; index < 13; index ++)             \r
2606                         {\r
2607                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2608                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2609                                 \r
2610                                 offset += 0x04;\r
2611                         }       \r
2612                         \r
2613                         //page-B1\r
2614                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
2615                 \r
2616                         //path A\r
2617                         offset = rPdp_AntA;\r
2618                         for(index = 0; index < 16; index++)\r
2619                         {\r
2620                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
2621                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2622                                 \r
2623                                 offset += 0x04;\r
2624                         }                               \r
2625                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                                                      \r
2626                 }\r
2627                 else if(path == ODM_RF_PATH_B)\r
2628                 {\r
2629                         //path B APK\r
2630                         //load APK setting\r
2631                         //path-B                \r
2632                         offset = rPdp_AntB;\r
2633                         for(index = 0; index < 10; index ++)                    \r
2634                         {\r
2635                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2636                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
2637                                 \r
2638                                 offset += 0x04;\r
2639                         }\r
2640                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);                       \r
2641 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2642                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2643 #else\r
2644                         PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
2645 #endif\r
2646                         \r
2647                         offset = rConfig_AntA;\r
2648                         index = 11;\r
2649                         for(; index < 13; index ++) //offset 0xb68, 0xb6c               \r
2650                         {\r
2651                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
2652                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
2653                                 \r
2654                                 offset += 0x04;\r
2655                         }       \r
2656                         \r
2657                         //page-B1\r
2658                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
2659                         \r
2660                         //path B\r
2661                         offset = 0xb60;\r
2662                         for(index = 0; index < 16; index++)\r
2663                         {\r
2664                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
2665                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
2666                                 \r
2667                                 offset += 0x04;\r
2668                         }                               \r
2669                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);                                                     \r
2670                 }\r
2671         \r
2672                 //save RF default value\r
2673 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2674                 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);\r
2675 #else\r
2676                 regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord);\r
2677 #endif\r
2678                 \r
2679                 //Path A AFE all on, path B AFE All off or vise versa\r
2680                 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
2681                         ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);\r
2682                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));               \r
2683 \r
2684                 //BB to AP mode\r
2685                 if(path == 0)\r
2686                 {                               \r
2687                         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2688                         {\r
2689 \r
2690                                 if(index == 0)          //skip \r
2691                                         continue;                       \r
2692                                 else if (index < 5)\r
2693                                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);\r
2694                                 else if (BB_REG[index] == 0x870)\r
2695                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);\r
2696                                 else\r
2697                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);                                       \r
2698                         }\r
2699 \r
2700                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);                  \r
2701                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                                  \r
2702                 }\r
2703                 else            //path B\r
2704                 {\r
2705                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);                  \r
2706                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);                                  \r
2707                 \r
2708                 }\r
2709 \r
2710                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));                              \r
2711 \r
2712                 //MAC settings\r
2713 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2714                 _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);\r
2715 #else\r
2716                 _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2717 #endif\r
2718                 \r
2719                 if(path == ODM_RF_PATH_A)       //Path B to standby mode\r
2720                 {\r
2721                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);                       \r
2722                 }\r
2723                 else                    //Path A to standby mode\r
2724                 {\r
2725                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);                       \r
2726                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2727                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);                                            \r
2728                 }\r
2729 \r
2730                 delta_offset = ((delta+14)/2);\r
2731                 if(delta_offset < 0)\r
2732                         delta_offset = 0;\r
2733                 else if (delta_offset > 12)\r
2734                         delta_offset = 12;\r
2735                         \r
2736                 //AP calibration\r
2737                 for(index = 0; index < APK_BB_REG_NUM; index++)\r
2738                 {\r
2739                         if(index != 1)  //only DO PA11+PAD01001, AP RF setting\r
2740                                 continue;\r
2741                                         \r
2742                         tmpReg = APK_RF_init_value[path][index];\r
2743 #if 1                   \r
2744                         if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)\r
2745                         {\r
2746                                 BB_offset = (tmpReg & 0xF0000) >> 16;\r
2747 \r
2748                                 if(!(tmpReg & BIT15)) //sign bit 0\r
2749                                 {\r
2750                                         BB_offset = -BB_offset;\r
2751                                 }\r
2752 \r
2753                                 delta_V = APK_delta_mapping[index][delta_offset];\r
2754                                 \r
2755                                 BB_offset += delta_V;\r
2756 \r
2757                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));              \r
2758                                 \r
2759                                 if(BB_offset < 0)\r
2760                                 {\r
2761                                         tmpReg = tmpReg & (~BIT15);\r
2762                                         BB_offset = -BB_offset;\r
2763                                 }\r
2764                                 else\r
2765                                 {\r
2766                                         tmpReg = tmpReg | BIT15;\r
2767                                 }\r
2768                                 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);\r
2769                         }\r
2770 #endif\r
2771 \r
2772                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);\r
2773 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2774                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));            \r
2775                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2776                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));              \r
2777                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2778                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));                                 \r
2779 #else\r
2780                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));               \r
2781                         ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2782                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));         \r
2783                         ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2784                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));                                    \r
2785 #endif\r
2786                         \r
2787                         // PA11+PAD01111, one shot      \r
2788                         i = 0;\r
2789                         do\r
2790                         {\r
2791                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
2792                                 {\r
2793                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);              \r
2794                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2795                                         ODM_delay_ms(3);                                \r
2796                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);\r
2797                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2798 \r
2799                                         ODM_delay_ms(20);\r
2800                                 }\r
2801                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
2802 \r
2803                                 if(path == ODM_RF_PATH_A)\r
2804                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);\r
2805                                 else\r
2806                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);\r
2807                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));         \r
2808                                 \r
2809 \r
2810                                 i++;\r
2811                         }\r
2812                         while(tmpReg > apkbound && i < 4);\r
2813 \r
2814                         APK_result[path][index] = tmpReg;\r
2815                 }\r
2816         }\r
2817 \r
2818         //reload MAC default value      \r
2819 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2820         _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
2821 #else\r
2822         _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
2823 #endif\r
2824         \r
2825         //reload BB default value       \r
2826         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2827         {\r
2828 \r
2829                 if(index == 0)          //skip \r
2830                         continue;                                       \r
2831                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
2832         }\r
2833 \r
2834         //reload AFE default value\r
2835 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2836         _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2837 #else\r
2838         _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2839 #endif\r
2840 \r
2841         //reload RF path default value\r
2842         for(path = 0; path < pathbound; path++)\r
2843         {\r
2844                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);\r
2845                 if(path == ODM_RF_PATH_B)\r
2846                 {\r
2847                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2848                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);                                            \r
2849                 }\r
2850 \r
2851                 //note no index == 0\r
2852                 if (APK_result[path][1] > 6)\r
2853                         APK_result[path][1] = 6;\r
2854                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));                                      \r
2855         }\r
2856 \r
2857         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\n"));\r
2858         \r
2859 \r
2860         for(path = 0; path < pathbound; path++)\r
2861         {\r
2862                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, \r
2863                 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));\r
2864                 if(path == ODM_RF_PATH_A)\r
2865                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2866                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));              \r
2867                 else\r
2868                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2869                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));                                              \r
2870 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2871                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, \r
2872                         ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));                    \r
2873 #endif          \r
2874         }\r
2875 \r
2876         pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;\r
2877 \r
2878         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));\r
2879 }\r
2880 \r
2881 \r
2882 \r
2883 #define         DP_BB_REG_NUM           7\r
2884 #define         DP_RF_REG_NUM           1\r
2885 #define         DP_RETRY_LIMIT          10\r
2886 #define         DP_PATH_NUM     2\r
2887 #define         DP_DPK_NUM                      3\r
2888 #define         DP_DPK_VALUE_NUM        2\r
2889 \r
2890 \r
2891 \r
2892 //IQK version:V2.5    20140123\r
2893 //IQK is controlled by Is2ant, RF path\r
2894 VOID\r
2895 PHY_IQCalibrate_8723B(\r
2896 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2897         IN PDM_ODM_T            pDM_Odm,\r
2898 #else\r
2899         IN      PADAPTER        pAdapter,\r
2900 #endif\r
2901         IN      BOOLEAN         bReCovery,\r
2902         IN BOOLEAN      bRestore,\r
2903         IN BOOLEAN      Is2ant, //false:1ant, true:2-ant\r
2904         IN u1Byte       RF_Path //0:S1, 1:S0\r
2905         )\r
2906 {\r
2907 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2908         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter); \r
2909 \r
2910         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2911         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc; \r
2912         #else  // (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2913         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;   \r
2914         #endif\r
2915 \r
2916         #if (MP_DRIVER == 1)\r
2917         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
2918         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2919         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2920         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
2921         #endif  \r
2922         #endif//(MP_DRIVER == 1)\r
2923 #endif  \r
2924 \r
2925         s4Byte                  result[4][8];   //last is final result\r
2926         u1Byte                  i, final_candidate, Indexforchannel;\r
2927         BOOLEAN                 bPathAOK, bPathBOK;\r
2928         s4Byte                  RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;\r
2929         BOOLEAN                 is12simular, is13simular, is23simular;  \r
2930         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
2931         u4Byte                  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
2932                                         rOFDM0_XARxIQImbalance,         rOFDM0_XBRxIQImbalance, \r
2933                                         rOFDM0_ECCAThreshold,   rOFDM0_AGCRSSITable,\r
2934                                         rOFDM0_XATxIQImbalance,         rOFDM0_XBTxIQImbalance, \r
2935                                         rOFDM0_XCTxAFE,                         rOFDM0_XDTxAFE, \r
2936                                         rOFDM0_RxIQExtAnta};\r
2937 //      u4Byte                  Path_SEL_BB = 0;\r
2938         u4Byte                  GNT_BT_default;\r
2939         u4Byte                  StartTime; \r
2940         s4Byte                  ProgressingTime;\r
2941 \r
2942 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )\r
2943         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
2944                 return;\r
2945 #else\r
2946         prtl8192cd_priv priv = pDM_Odm->priv;\r
2947 \r
2948 #ifdef MP_TEST\r
2949         if(priv->pshare->rf_ft_var.mp_specific)\r
2950         {\r
2951                 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))\r
2952                         return;\r
2953         }\r
2954 #endif\r
2955 \r
2956         if(priv->pshare->IQK_88E_done)\r
2957                 bReCovery= 1;\r
2958         priv->pshare->IQK_88E_done = 1;\r
2959 \r
2960 #endif  \r
2961 \r
2962 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2963         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
2964         {\r
2965                 return;\r
2966         }\r
2967 #endif\r
2968 \r
2969 #if MP_DRIVER == 1      \r
2970         bStartContTx = pMptCtx->bStartContTx;\r
2971         bSingleTone = pMptCtx->bSingleTone;\r
2972         bCarrierSuppression = pMptCtx->bCarrierSuppression; \r
2973 #endif\r
2974         \r
2975         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
2976         if(bSingleTone || bCarrierSuppression)\r
2977                 return;\r
2978 \r
2979 #if DISABLE_BB_RF\r
2980         return;\r
2981 #endif\r
2982         if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) \r
2983                 return;\r
2984 \r
2985 \r
2986         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2987         pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;\r
2988         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2989 \r
2990         if (bRestore) {\r
2991                 u4Byte offset, data;\r
2992                 u1Byte path, bResult = SUCCESS;\r
2993                 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
2994 \r
2995                 //#define PATH_S0       1 // RF_PATH_B\r
2996                 //#define PATH_S1       0 // RF_PATH_A\r
2997 \r
2998                 path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B);\r
2999 \r
3000                 // Restore TX IQK\r
3001                 for (i = 0; i < 3; ++i) {\r
3002                         offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];\r
3003                         data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];\r
3004                         if ((offset == 0) || (i == 1 && data == 0)) {   /* 0xc80, 0xc88 ==> index=1 */\r
3005                                 DBG_871X("%s =>path:%s Restore TX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B");\r
3006                                 bResult = FAIL;\r
3007                                 break;\r
3008                         }\r
3009                         //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));\r
3010                         ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);\r
3011                 }\r
3012 \r
3013                 // Restore RX IQK\r
3014                 for (i = 0; i < 2; ++i) {\r
3015                         offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];\r
3016                         data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];\r
3017                         if ((offset == 0) || (i == 0 && data == 0)) {   /* 0xc14, 0xc1c ==> index=0 */\r
3018                                 DBG_871X("%s =>path:%s  Restore RX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B");\r
3019                                 bResult = FAIL;\r
3020                                 break;\r
3021                         }\r
3022                         //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));\r
3023                         ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);\r
3024                 }\r
3025 \r
3026                 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] ==0) {\r
3027                         DBG_871X("%s => Restore Path-A TxLOK result failed \n",__FUNCTION__);\r
3028                         bResult = FAIL;\r
3029                 } else {\r
3030                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]);  \r
3031                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]);  \r
3032                 }\r
3033 \r
3034                 if (bResult == SUCCESS)\r
3035                         goto out;\r
3036         }\r
3037 \r
3038 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))\r
3039         if(bReCovery)\r
3040 #else//for ODM_WIN\r
3041         if(bReCovery && (!pAdapter->bInHctTest))  //YJ,add for PowerTest,120405\r
3042 #endif  \r
3043         {\r
3044                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n"));\r
3045 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3046                 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3047 #else\r
3048                 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3049 #endif\r
3050                 goto out;\r
3051         }\r
3052         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
3053         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:Start!!!\n"));\r
3054 \r
3055         //save default GNT_BT\r
3056         GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord);\r
3057         // Save RF Path \r
3058 //      Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);\r
3059 //      Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);\r
3060 \r
3061     //set GNT_BT=0, pause BT traffic\r
3062 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);\r
3063 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x1);\r
3064 \r
3065 \r
3066         for(i = 0; i < 8; i++)\r
3067         {\r
3068                 result[0][i] = 0;\r
3069                 result[1][i] = 0;\r
3070                 result[2][i] = 0;\r
3071                 result[3][i] = 0;\r
3072         }\r
3073         final_candidate = 0xff;\r
3074         bPathAOK = FALSE;\r
3075         bPathBOK = FALSE;\r
3076         is12simular = FALSE;\r
3077         is23simular = FALSE;\r
3078         is13simular = FALSE;\r
3079 \r
3080 \r
3081         for (i=0; i<3; i++)\r
3082         {\r
3083 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3084                 phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path);\r
3085 #else\r
3086                 phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path);\r
3087 #endif\r
3088 \r
3089                 if(i == 1)\r
3090                 {\r
3091 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3092                         is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1);\r
3093 #else\r
3094                         is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1);\r
3095 #endif                  \r
3096                         if(is12simular)\r
3097                         {\r
3098                                 final_candidate = 0;\r
3099                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));                         \r
3100                                 break;\r
3101                         }\r
3102                 }\r
3103                 \r
3104                 if(i == 2)\r
3105                 {\r
3106 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3107                         is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2);\r
3108 #else\r
3109                         is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2);\r
3110 #endif                  \r
3111                         if(is13simular)\r
3112                         {\r
3113                                 final_candidate = 0;                    \r
3114                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));\r
3115                                 \r
3116                                 break;\r
3117                         }\r
3118 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3119                         is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2);\r
3120 #else\r
3121                         is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2);\r
3122 #endif                  \r
3123                         if(is23simular)\r
3124                         {\r
3125                                 final_candidate = 1;\r
3126                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));                         \r
3127                         }\r
3128                         else\r
3129                         {\r
3130                                 for(i = 0; i < 8; i++)\r
3131                                         RegTmp += result[3][i];\r
3132 \r
3133                                 if(RegTmp != 0)\r
3134                                         final_candidate = 3;                    \r
3135                                 else\r
3136                                         final_candidate = 0xFF;\r
3137                         }\r
3138                 }\r
3139         }\r
3140 //      RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));\r
3141 \r
3142         for (i=0; i<4; i++)\r
3143         {\r
3144                 RegE94 = result[i][0];\r
3145                 RegE9C = result[i][1];\r
3146                 RegEA4 = result[i][2];\r
3147                 RegEAC = result[i][3];\r
3148                 RegEB4 = result[i][4];\r
3149                 RegEBC = result[i][5];\r
3150                 RegEC4 = result[i][6];\r
3151                 RegECC = result[i][7];\r
3152                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
3153         }\r
3154         \r
3155         if(final_candidate != 0xff)\r
3156         {\r
3157                 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];\r
3158                 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];\r
3159                 RegEA4 = result[final_candidate][2];\r
3160                 RegEAC = result[final_candidate][3];\r
3161                 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];\r
3162                 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];\r
3163                 RegEC4 = result[final_candidate][6];\r
3164                 RegECC = result[final_candidate][7];\r
3165                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: final_candidate is %x\n",final_candidate));\r
3166                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
3167                 bPathAOK = bPathBOK = TRUE;\r
3168         }\r
3169         else\r
3170         {\r
3171                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: FAIL use default value\n"));\r
3172         \r
3173                 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100;      //X default value\r
3174                 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0;                //Y default value\r
3175         }\r
3176 \r
3177 #if MP_DRIVER == 1\r
3178         if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))\r
3179 #endif\r
3180         {\r
3181                 if (RegE94 != 0)\r
3182                 {\r
3183 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3184                         _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
3185 #else\r
3186                         _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
3187 #endif\r
3188                 }\r
3189         }\r
3190         \r
3191 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3192 #if MP_DRIVER == 1\r
3193         if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))\r
3194 #endif\r
3195         {\r
3196                 if (RegEB4 != 0)\r
3197                 {\r
3198                         _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));\r
3199                 }\r
3200         }\r
3201 #endif\r
3202 \r
3203 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3204         Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);\r
3205 #else\r
3206         Indexforchannel = 0;    \r
3207 #endif\r
3208 \r
3209 //To Fix BSOD when final_candidate is 0xff\r
3210 //by sherry 20120321\r
3211         if(final_candidate < 4)\r
3212         {\r
3213                 for(i = 0; i < IQK_Matrix_REG_NUM; i++)\r
3214                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];\r
3215                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;          \r
3216         }\r
3217         //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
3218         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
3219 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3220 \r
3221         _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
3222 #else\r
3223         _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);\r
3224 #endif  \r
3225 \r
3226         //restore GNT_BT\r
3227         ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default);\r
3228         // Restore RF Path\r
3229 //      ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);\r
3230 //      ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);\r
3231 \r
3232         //Resotr RX mode table parameter\r
3233         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );\r
3234         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 );\r
3235         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );\r
3236         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177 );\r
3237         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );\r
3238         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd );\r
3239 \r
3240         //set GNT_BT= HW control\r
3241 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);\r
3242 //      ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0);\r
3243 \r
3244         if (Is2ant) {\r
3245                 if (RF_Path == 0x0)     //S1\r
3246                         ODM_SetIQCbyRFpath(pDM_Odm, 0);\r
3247                 else    //S0\r
3248                         ODM_SetIQCbyRFpath(pDM_Odm, 1);\r
3249         }\r
3250 \r
3251         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));\r
3252         ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime);\r
3253         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));\r
3254 \r
3255 out:\r
3256         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
3257         pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;\r
3258         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
3259 }\r
3260 \r
3261 \r
3262 VOID\r
3263 PHY_LCCalibrate_8723B(\r
3264         PVOID           pDM_VOID\r
3265         )\r
3266 {\r
3267         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
3268         u4Byte                  timeout = 2000, timecount = 0;\r
3269         u4Byte                  StartTime; \r
3270         s4Byte                  ProgressingTime;\r
3271         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
3272 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3273         PADAPTER        pAdapter = pDM_Odm->Adapter;\r
3274 \r
3275         #if (MP_DRIVER == 1)\r
3276         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
3277         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
3278         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3279         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
3280         #endif  \r
3281         #endif//(MP_DRIVER == 1)\r
3282 #endif  \r
3283 \r
3284 \r
3285 \r
3286 \r
3287 #if MP_DRIVER == 1      \r
3288         bStartContTx = pMptCtx->bStartContTx;\r
3289         bSingleTone = pMptCtx->bSingleTone;\r
3290         bCarrierSuppression = pMptCtx->bCarrierSuppression; \r
3291 #endif\r
3292 \r
3293 \r
3294 #if DISABLE_BB_RF\r
3295         return;\r
3296 #endif\r
3297 \r
3298 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3299         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
3300         {\r
3301                 return;\r
3302         }\r
3303 #endif  \r
3304         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
3305         if(bSingleTone || bCarrierSuppression)\r
3306                 return;\r
3307         \r
3308         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
3309         while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)\r
3310         {\r
3311                 ODM_delay_ms(50);\r
3312                 timecount += 50;\r
3313         }       \r
3314         \r
3315         pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;\r
3316 \r
3317         \r
3318         phy_LCCalibrate_8723B(pDM_Odm, FALSE);\r
3319 \r
3320 \r
3321         pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;\r
3322 \r
3323         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));\r
3324         ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);\r
3325         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("LCK ProgressingTime = %d\n", ProgressingTime));\r
3326 }\r
3327 \r
3328 VOID\r
3329 PHY_APCalibrate_8723B(\r
3330 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3331         IN PDM_ODM_T            pDM_Odm,\r
3332 #else\r
3333         IN      PADAPTER        pAdapter,\r
3334 #endif\r
3335         IN      s1Byte          delta   \r
3336         )\r
3337 {\r
3338 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3339         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3340         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3341         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3342         #endif\r
3343         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3344         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3345         #endif\r
3346 #endif  \r
3347 #if DISABLE_BB_RF\r
3348         return;\r
3349 #endif\r
3350 \r
3351         return;\r
3352 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3353         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
3354         {\r
3355                 return;\r
3356         }\r
3357 #endif  \r
3358 \r
3359 #if FOR_BRAZIL_PRETEST != 1\r
3360         if(pDM_Odm->RFCalibrateInfo.bAPKdone)\r
3361 #endif          \r
3362                 return;\r
3363 \r
3364 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3365         if(IS_2T2R( pHalData->VersionID)){\r
3366                 phy_APCalibrate_8723B(pAdapter, delta, TRUE);\r
3367         }\r
3368         else\r
3369 #endif\r
3370         {\r
3371                 // For 88C 1T1R\r
3372 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3373                 phy_APCalibrate_8723B(pAdapter, delta, FALSE);\r
3374 #else\r
3375                 phy_APCalibrate_8723B(pDM_Odm, delta, FALSE);\r
3376 #endif\r
3377         }\r
3378 }\r
3379 VOID phy_SetRFPathSwitch_8723B(\r
3380 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3381         IN PDM_ODM_T            pDM_Odm,\r
3382 #else\r
3383         IN      PADAPTER        pAdapter,\r
3384 #endif\r
3385         IN      BOOLEAN         bMain,\r
3386         IN      BOOLEAN         is2T\r
3387         )\r
3388 {\r
3389         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3390 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3391         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3392 #endif\r
3393 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3394         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3395 #endif\r
3396 \r
3397         if(bMain) // Left antenna       \r
3398         {\r
3399                 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1);          \r
3400         }                       \r
3401         else\r
3402         {\r
3403                 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2);          \r
3404         }               \r
3405 }\r
3406 VOID PHY_SetRFPathSwitch_8723B(\r
3407 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3408         IN PDM_ODM_T            pDM_Odm,\r
3409 #else\r
3410         IN      PADAPTER        pAdapter,\r
3411 #endif\r
3412         IN      BOOLEAN         bMain\r
3413         )\r
3414 {\r
3415 \r
3416 #if DISABLE_BB_RF\r
3417         return;\r
3418 #endif\r
3419 \r
3420 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3421                 phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE);\r
3422 #endif          \r
3423 \r
3424 }\r
3425 \r
3426 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3427 //digital predistortion\r
3428 VOID    \r
3429 phy_DigitalPredistortion8723B(\r
3430 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3431         IN      PADAPTER        pAdapter,\r
3432 #else\r
3433         IN PDM_ODM_T    pDM_Odm,\r
3434 #endif\r
3435         IN      BOOLEAN         is2T\r
3436         )\r
3437 {\r
3438 #if (RT_PLATFORM == PLATFORM_WINDOWS)\r
3439 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3440         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3441         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3442         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3443         #endif\r
3444         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3445         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3446         #endif\r
3447 #endif  \r
3448 \r
3449         u4Byte                  tmpReg, tmpReg2, index,  i;     \r
3450         u1Byte                  path, pathbound = PATH_NUM;\r
3451         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
3452         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
3453                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
3454                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
3455                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
3456                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
3457                                                 rTx_To_Tx,              rRx_CCK,        \r
3458                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
3459                                                 rRx_TO_Rx,              rStandby,       \r
3460                                                 rSleep,                         rPMPD_ANAEN };\r
3461 \r
3462         u4Byte                  BB_backup[DP_BB_REG_NUM];       \r
3463         u4Byte                  BB_REG[DP_BB_REG_NUM] = {\r
3464                                                 rOFDM0_TRxPathEnable, rFPGA0_RFMOD, \r
3465                                                 rOFDM0_TRMuxPar,        rFPGA0_XCD_RFInterfaceSW,\r
3466                                                 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, \r
3467                                                 rFPGA0_XB_RFInterfaceOE};                                               \r
3468         u4Byte                  BB_settings[DP_BB_REG_NUM] = {\r
3469                                                 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, \r
3470                                                 0x0, 0x0, 0x0}; \r
3471 \r
3472         u4Byte                  RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];\r
3473         u4Byte                  RF_REG[DP_RF_REG_NUM] = {\r
3474                                                 RF_TXBIAS_A};\r
3475 \r
3476         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
3477         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
3478                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
3479                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
3480 \r
3481         u4Byte                  Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {\r
3482                                                 {0x1e1e1e1e, 0x03901e1e},\r
3483                                                 {0x18181818, 0x03901818},\r
3484                                                 {0x0e0e0e0e, 0x03900e0e}\r
3485                                         };\r
3486 \r
3487         u4Byte                  AFE_on_off[PATH_NUM] = {\r
3488                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
3489 \r
3490         u1Byte                  RetryCount = 0;\r
3491 \r
3492 \r
3493         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n"));\r
3494         \r
3495         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R")));\r
3496 \r
3497         //save BB default value\r
3498         for(index=0; index<DP_BB_REG_NUM; index++)\r
3499                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
3500 \r
3501         //save MAC default value\r
3502 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3503         _PHY_SaveMACRegisters8723B(pAdapter, BB_REG, MAC_backup);\r
3504 #else\r
3505         _PHY_SaveMACRegisters8723B(pDM_Odm, BB_REG, MAC_backup);\r
3506 #endif  \r
3507 \r
3508         //save RF default value\r
3509         for(path=0; path<DP_PATH_NUM; path++)\r
3510         {\r
3511                 for(index=0; index<DP_RF_REG_NUM; index++)\r
3512 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3513                         RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); \r
3514 #else\r
3515                         RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);       \r
3516 #endif  \r
3517         }       \r
3518         \r
3519         //save AFE default value\r
3520 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3521         _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
3522 #else\r
3523                 _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
3524 #endif  \r
3525         \r
3526         //Path A/B AFE all on\r
3527         for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
3528                 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);\r
3529 \r
3530         //BB register setting\r
3531         for(index = 0; index < DP_BB_REG_NUM; index++)\r
3532         {\r
3533                 if(index < 4)\r
3534                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);\r
3535                 else if (index == 4)\r
3536                         ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);                  \r
3537                 else\r
3538                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);                      \r
3539         }\r
3540 \r
3541         //MAC register setting\r
3542 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3543         _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);\r
3544 #else\r
3545         _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);\r
3546 #endif  \r
3547 \r
3548         //PAGE-E IQC setting    \r
3549         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
3550         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);  \r
3551         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
3552         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
3553         \r
3554         //path_A DPK\r
3555         //Path B to standby mode\r
3556         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);\r
3557 \r
3558         // PA gain = 11 & PAD1 => tx_agc 1f ~11\r
3559         // PA gain = 11 & PAD2 => tx_agc 10~0e\r
3560         // PA gain = 01 => tx_agc 0b~0d\r
3561         // PA gain = 00 => tx_agc 0a~00\r
3562         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);      \r
3563         ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);           \r
3564         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
3565 \r
3566         //do inner loopback DPK 3 times \r
3567         for(i = 0; i < 3; i++)\r
3568         {\r
3569                 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
3570                 for(index = 0; index < 3; index++)\r
3571                         ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3572                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);                  \r
3573                 for(index = 0; index < 4; index++)\r
3574                         ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);                  \r
3575         \r
3576                 // PAGE_B for Path-A inner loopback DPK setting\r
3577                 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);\r
3578                 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
3579                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3580                 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);     \r
3581                 \r
3582                 //----send one shot signal----//\r
3583                 // Path A\r
3584                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);\r
3585                 ODM_delay_ms(1);\r
3586                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);\r
3587                 ODM_delay_ms(50);\r
3588         }\r
3589 \r
3590         //PA gain = 11 => tx_agc = 1a\r
3591         for(index = 0; index < 3; index++)              \r
3592                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);    \r
3593         ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);    \r
3594         for(index = 0; index < 4; index++)              \r
3595                 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);    \r
3596 \r
3597         //====================================\r
3598         // PAGE_B for Path-A DPK setting\r
3599         //====================================\r
3600         // open inner loopback @ b00[19]:10 od 0xb00 0x01097018\r
3601         ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);\r
3602         ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
3603         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3604         ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);     \r
3605 \r
3606         //rf_lpbk_setup\r
3607         //1.rf 00:5205a, rf 0d:0e52c\r
3608         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);\r
3609         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);        \r
3610         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );               \r
3611 \r
3612         //----send one shot signal----//\r
3613         // Path A\r
3614         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
3615         ODM_delay_ms(1);\r
3616         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);\r
3617         ODM_delay_ms(50);\r
3618 \r
3619         while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
3620         {\r
3621                 //----read back measurement results----//\r
3622                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);\r
3623                 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);\r
3624                 ODM_delay_ms(10);\r
3625                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);\r
3626                 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);\r
3627                 ODM_delay_ms(10);\r
3628 \r
3629                 tmpReg = (tmpReg & bMaskHWord) >> 16;\r
3630                 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;         \r
3631                 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )\r
3632                 {\r
3633                         ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);\r
3634                 \r
3635                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
3636                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
3637                         ODM_delay_ms(1);\r
3638                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
3639                         ODM_delay_ms(1);                        \r
3640                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);                       \r
3641                         ODM_delay_ms(50);                       \r
3642                         RetryCount++;                   \r
3643                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));                                                                          \r
3644                 }\r
3645                 else\r
3646                 {\r
3647                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));              \r
3648                         pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;\r
3649                         break;\r
3650                 }               \r
3651         }\r
3652         RetryCount = 0;\r
3653         \r
3654         //DPP path A\r
3655         if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
3656         {       \r
3657                 // DP settings\r
3658                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);\r
3659                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);\r
3660                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
3661                 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);\r
3662                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
3663 \r
3664                 for(i=rPdp_AntA; i<=0xb3c; i+=4)\r
3665                 {\r
3666                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
3667                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));                \r
3668                 }\r
3669                 \r
3670                 //pwsf\r
3671                 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);   \r
3672                 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);                   \r
3673                 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);                                   \r
3674 \r
3675                 for(i=0xb4c; i<=0xb5c; i+=4)\r
3676                 {\r
3677                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
3678                 }               \r
3679 \r
3680                 //TX_AGC boundary\r
3681                 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);   \r
3682                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                                              \r
3683         }\r
3684         else\r
3685         {\r
3686                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);       \r
3687                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);             \r
3688         }\r
3689 \r
3690         //DPK path B\r
3691         if(is2T)\r
3692         {\r
3693                 //Path A to standby mode\r
3694                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);\r
3695                 \r
3696                 // LUTs => tx_agc\r
3697                 // PA gain = 11 & PAD1, => tx_agc 1f ~11\r
3698                 // PA gain = 11 & PAD2, => tx_agc 10 ~0e\r
3699                 // PA gain = 01 => tx_agc 0b ~0d\r
3700                 // PA gain = 00 => tx_agc 0a ~00\r
3701                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);      \r
3702                 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);           \r
3703                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);              \r
3704 \r
3705                 //do inner loopback DPK 3 times \r
3706                 for(i = 0; i < 3; i++)\r
3707                 {\r
3708                         //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
3709                         for(index = 0; index < 4; index++)\r
3710                                 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3711                         for(index = 0; index < 2; index++)\r
3712                                 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3713                         for(index = 0; index < 2; index++)\r
3714                                 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3715                 \r
3716                         // PAGE_B for Path-A inner loopback DPK setting\r
3717                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);\r
3718                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);\r
3719                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3720                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3721                         \r
3722                         //----send one shot signal----//\r
3723                         // Path B\r
3724                         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);\r
3725                         ODM_delay_ms(1);\r
3726                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);\r
3727                         ODM_delay_ms(50);\r
3728                 }\r
3729 \r
3730                 // PA gain = 11 => tx_agc = 1a  \r
3731                 for(index = 0; index < 4; index++)\r
3732                         ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);   \r
3733                 for(index = 0; index < 2; index++)\r
3734                         ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);   \r
3735                 for(index = 0; index < 2; index++)\r
3736                         ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);   \r
3737 \r
3738                 // PAGE_B for Path-B DPK setting\r
3739                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3740                 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);     \r
3741                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);               \r
3742                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3743 \r
3744                 // RF lpbk switches on\r
3745                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);           \r
3746                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);           \r
3747 \r
3748                 //Path-B RF lpbk\r
3749                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);\r
3750                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);\r
3751                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); \r
3752 \r
3753                 //----send one shot signal----//\r
3754                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3755                 ODM_delay_ms(1);        \r
3756                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3757                 ODM_delay_ms(50);\r
3758                 \r
3759                 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3760                 {\r
3761                         //----read back measurement results----//\r
3762                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);               \r
3763                         tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);\r
3764                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);               \r
3765                         tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);\r
3766                         \r
3767                         tmpReg = (tmpReg & bMaskHWord) >> 16;\r
3768                         tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;\r
3769                         \r
3770                         if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)\r
3771                         {\r
3772                                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3773                         \r
3774                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);\r
3775                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);      \r
3776                                 ODM_delay_ms(1);\r
3777                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3778                                 ODM_delay_ms(1);        \r
3779                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3780                                 ODM_delay_ms(50);                       \r
3781                                 RetryCount++;                   \r
3782                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));                                                                                                               \r
3783                         }\r
3784                         else\r
3785                         {\r
3786                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));                                     \r
3787                                 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;\r
3788                                 break;\r
3789                         }                                               \r
3790                 }\r
3791         \r
3792                 //DPP path B\r
3793                 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3794                 {\r
3795                         // DP setting\r
3796                         // LUT by SRAM\r
3797                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);\r
3798                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);\r
3799                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3800                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);\r
3801                         \r
3802                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);\r
3803                         for(i=0xb60; i<=0xb9c; i+=4)\r
3804                         {\r
3805                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
3806                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));\r
3807                         }\r
3808 \r
3809                         // PWSF\r
3810                         ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);   \r
3811                         ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);                   \r
3812                         ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);                                   \r
3813 \r
3814                         for(i=0xbac; i<=0xbbc; i+=4)\r
3815                         {\r
3816                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
3817                         }               \r
3818                         \r
3819                         // tx_agc boundary\r
3820                         ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);   \r
3821                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);                              \r
3822                         \r
3823                 }\r
3824                 else\r
3825                 {\r
3826                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);       \r
3827                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);                             \r
3828                 }\r
3829         }\r
3830         \r
3831         //reload BB default value\r
3832         for(index=0; index<DP_BB_REG_NUM; index++)\r
3833                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
3834         \r
3835         //reload RF default value\r
3836         for(path = 0; path<DP_PATH_NUM; path++)\r
3837         {\r
3838                 for( i = 0 ; i < DP_RF_REG_NUM ; i++){\r
3839                         ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);\r
3840                 }\r
3841         }\r
3842         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);    //standby mode\r
3843         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);            //RF lpbk switches off\r
3844 \r
3845         //reload AFE default value\r
3846 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3847         _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); \r
3848 \r
3849         //reload MAC default value      \r
3850         _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);\r
3851 #else\r
3852         _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);  \r
3853 \r
3854         //reload MAC default value      \r
3855         _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);\r
3856 #endif          \r
3857 \r
3858         pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;\r
3859         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n"));\r
3860 #endif          \r
3861 }\r
3862 \r
3863 VOID\r
3864 PHY_DigitalPredistortion_8723B(\r
3865 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3866         IN      PADAPTER        pAdapter\r
3867 #else\r
3868         IN PDM_ODM_T    pDM_Odm\r
3869 #endif          \r
3870         )\r
3871 {\r
3872 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3873         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3874         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3875         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3876         #endif\r
3877         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3878         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3879         #endif\r
3880 #endif  \r
3881 #if DISABLE_BB_RF\r
3882         return;\r
3883 #endif\r
3884 \r
3885         return;\r
3886 \r
3887         if(pDM_Odm->RFCalibrateInfo.bDPdone)\r
3888                 return;\r
3889 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3890 \r
3891         if(IS_2T2R( pHalData->VersionID)){\r
3892                 phy_DigitalPredistortion8723B(pAdapter, TRUE);\r
3893         }\r
3894         else\r
3895 #endif          \r
3896         {\r
3897                 // For 88C 1T1R\r
3898                 phy_DigitalPredistortion8723B(pAdapter, FALSE);\r
3899         }\r
3900 }\r
3901         \r
3902 \r
3903 \r
3904 //return value TRUE => Main; FALSE => Aux\r
3905 \r
3906 BOOLEAN phy_QueryRFPathSwitch_8723B(\r
3907 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3908         IN PDM_ODM_T            pDM_Odm,\r
3909 #else\r
3910         IN      PADAPTER        pAdapter,\r
3911 #endif\r
3912         IN      BOOLEAN         is2T\r
3913         )\r
3914 {\r
3915 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3916         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3917         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3918         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3919         #endif\r
3920         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3921         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3922         #endif\r
3923 #endif  \r
3924 \r
3925 \r
3926         if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01)\r
3927                 return TRUE;\r
3928         else \r
3929                 return FALSE;\r
3930 \r
3931 }\r
3932 \r
3933 \r
3934 \r
3935 //return value TRUE => Main; FALSE => Aux\r
3936 BOOLEAN PHY_QueryRFPathSwitch_8723B(    \r
3937 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3938         IN PDM_ODM_T            pDM_Odm\r
3939 #else\r
3940         IN      PADAPTER        pAdapter\r
3941 #endif\r
3942         )\r
3943 {\r
3944         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3945 \r
3946 #if DISABLE_BB_RF\r
3947         return TRUE;\r
3948 #endif\r
3949 \r
3950 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3951                 return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE);\r
3952 #else\r
3953                 return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE);\r
3954 #endif\r
3955 \r
3956 }\r
3957 #endif\r